commit 6e7df1d151a7a127caf3b62ff6dfc003fc2aefcd
author Tom Rini <trini@konsulko.com> Tue Jan 10 11:19:45 2023 -0500
committer Tom Rini <trini@konsulko.com> Fri Jan 20 12:27:24 2023 -0500
tree ae38e9dcf468b2e4e58293561fae87895d9b549f
parent ad242344681f6a0076a6bf100aa83ac9ecbea355

global: Finish CONFIG -> CFG migration

At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks.  Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

drivers/ram/aspeed/sdram_ast2600.c

diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c
index a2d7ca8..1876755 100644
--- a/drivers/ram/aspeed/sdram_ast2600.c
+++ b/drivers/ram/aspeed/sdram_ast2600.c
@@ -104,10 +104,10 @@
  * -> WL = AL + CWL + PL = CWL
  * -> RL = AL + CL + PL = CL
  */
-#define CONFIG_WL			9
-#define CONFIG_RL			12
-#define T_RDDATA_EN			((CONFIG_RL - 2) << 8)
-#define T_PHY_WRLAT			(CONFIG_WL - 2)
+#define CFG_WL			9
+#define CFG_RL			12
+#define T_RDDATA_EN			((CFG_RL - 2) << 8)
+#define T_PHY_WRLAT			(CFG_WL - 2)
 
 /* MR0 */
 #define MR0_CL_12			(BIT(4) | BIT(2))
@@ -974,8 +974,8 @@
 	/* update CL and WL */
 	reg = readl(&regs->ac_timing[1]);
 	reg &= ~(SDRAM_WL_SETTING | SDRAM_CL_SETTING);
-	reg |= FIELD_PREP(SDRAM_WL_SETTING, CONFIG_WL - 5) |
-	       FIELD_PREP(SDRAM_CL_SETTING, CONFIG_RL - 5);
+	reg |= FIELD_PREP(SDRAM_WL_SETTING, CFG_WL - 5) |
+	       FIELD_PREP(SDRAM_CL_SETTING, CFG_RL - 5);
 	writel(reg, &regs->ac_timing[1]);
 
 	writel(DDR4_MR01_MODE, &regs->mr01_mode_setting);

drivers/ram/octeon/octeon_ddr.c

diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c
index bb21078..ff2899d 100644
--- a/drivers/ram/octeon/octeon_ddr.c
+++ b/drivers/ram/octeon/octeon_ddr.c
@@ -17,7 +17,7 @@
 
 #include <mach/octeon_ddr.h>
 
-#define CONFIG_REF_HERTZ	50000000
+#define CFG_REF_HERTZ	50000000
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -152,7 +152,7 @@
 static u32 octeon3_refclock(u32 alt_refclk, u32 ddr_hertz,
 			    struct dimm_config *dimm_config)
 {
-	u32 ddr_ref_hertz = CONFIG_REF_HERTZ;
+	u32 ddr_ref_hertz = CFG_REF_HERTZ;
 	int ddr_type;
 	int spd_dimm_type;
 
@@ -2453,7 +2453,7 @@
 		} else {
 			if (ddr_ref_hertz == 100000000) {
 				debug("N0: DRAM init: requested 100 MHz refclk NOT SUPPORTED\n");
-				ddr_ref_hertz = CONFIG_REF_HERTZ;
+				ddr_ref_hertz = CFG_REF_HERTZ;
 			}
 		}
 
@@ -2486,7 +2486,7 @@
 				if (hertz_diff > ((int)ddr_hertz * 5 / 100)) {
 					// nope, diff is greater than than 5%
 					debug("N0: DRAM init: requested 100 MHz refclk NOT FOUND\n");
-					ddr_ref_hertz = CONFIG_REF_HERTZ;
+					ddr_ref_hertz = CFG_REF_HERTZ;
 					// clear the flag before trying again!!
 					set_ddr_clock_initialized(priv, 0, 0);
 					goto try_again;

drivers/ram/rockchip/dmc-rk3368.c

diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
index 6929a7e..dd5b191 100644
--- a/drivers/ram/rockchip/dmc-rk3368.c
+++ b/drivers/ram/rockchip/dmc-rk3368.c
@@ -109,7 +109,7 @@
 	PCTL_STAT_MSK = 7,
 	INIT_MEM = 0,
 	CONFIG,
-	CONFIG_REQ,
+	CFG_REQ,
 	ACCESS,
 	ACCESS_REQ,
 	LOW_POWER,