rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index 41a2a15..6921759 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -36,66 +36,66 @@
#define CONFIG_ENV_OVERWRITE 1
/* SDRAM */
-#define CFG_SDRAM_BASE (0x8C000000)
-#define CFG_SDRAM_SIZE (0x04000000)
+#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
+#define CONFIG_SYS_SDRAM_SIZE (0x04000000)
-#define CFG_LONGHELP
-#define CFG_PROMPT "=> "
-#define CFG_CBSIZE 256
-#define CFG_PBSIZE 256
-#define CFG_MAXARGS 16
-#define CFG_BARGSIZE 512
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE 512
/* List of legal baudrate settings for this board */
-#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
-#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
-#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END (TEXT_BASE - 0x100000)
-#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
/* Address of u-boot image in Flash */
-#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
-#define CFG_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */
-#define CFG_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_SIZE (256)
-#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE (256)
+#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/*
* NOR Flash ( Spantion S29GL256P )
*/
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_BASE (0xA0000000)
-#define CFG_MAX_FLASH_BANKS (1)
-#define CFG_MAX_FLASH_SECT 256
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_BASE (0xA0000000)
+#define CONFIG_SYS_MAX_FLASH_BANKS (1)
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x40000
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
/*
* SuperH Clock setting
*/
#define CONFIG_SYS_CLK_FREQ 60000000
#define TMU_CLK_DIVIDER 4
-#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
-#define CFG_PLL_SETTLING_TIME 100/* in us */
+#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
/*
* IDE support
*/
#define CONFIG_IDE_RESET 1
-#define CFG_PIO_MODE 1
-#define CFG_IDE_MAXBUS 1 /* IDE bus */
-#define CFG_IDE_MAXDEVICE 1
-#define CFG_ATA_BASE_ADDR 0xb4000000
-#define CFG_ATA_STRIDE 2 /* 1bit shift */
-#define CFG_ATA_DATA_OFFSET 0x1000 /* data reg offset */
-#define CFG_ATA_REG_OFFSET 0x1000 /* reg offset */
-#define CFG_ATA_ALT_OFFSET 0x800 /* alternate register offset */
+#define CONFIG_SYS_PIO_MODE 1
+#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE 1
+#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
+#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
/*
* SuperH PCI Bridge Configration