rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index 5ab76c6..70bae60 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -125,7 +125,7 @@
/* ------------------------------------------------------------------------- */
/* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
/* Unfortunately, we cant change it while we are in flash, so we initialize it
* to the "final" value. This means that any debug_led calls before
@@ -134,7 +134,7 @@
*/
void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
int display_mem_map (void);
/* ------------------------------------------------------------------------- */
@@ -197,7 +197,7 @@
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CFG_PCI_IDSEL);
+ (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
@@ -206,7 +206,7 @@
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CFG_PCI_IDSEL);
+ (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
/* Enable master */
@@ -224,21 +224,21 @@
/* ronen- add write to pci remap registers for 64460.
in 64360 when writing to pci base go and overide remap automaticaly,
in 64460 it doesn't */
- GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16);
- GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16);
- GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
+ GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
+ GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
- GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
- GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16);
- GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16);
- GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
+ GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
+ GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
- GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
/* PCI interface settings */
/* Timeout set to retry forever */
@@ -254,7 +254,7 @@
for (stat = 0; stat <= PCI_HOST1; stat++)
pciWriteConfigReg (stat,
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
- SELF, CFG_GT_REGS);
+ SELF, CONFIG_SYS_GT_REGS);
#endif
}
@@ -270,7 +270,7 @@
tmp = GTREGREAD (CPU_CONFIGURATION);
/* set the SINGLE_CPU bit see MV64360 P.399 */
-#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
+#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
tmp |= CPU_CONF_SINGLE_CPU;
#endif
@@ -320,7 +320,7 @@
* it last time. (huber)
*/
- my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+ my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
/* No PCI in first release of Port To_do: enable it. */
#ifdef CONFIG_PCI
@@ -364,45 +364,45 @@
* registers to boot from the sram. (device0)
*/
- memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
- memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
- memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
- memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+ memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+ memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
+ memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
+ memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
/* configure device timing */
- GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
- GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
- GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
- GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_DEV3_PAR);
+ GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
+ GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
+ GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
+ GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR);
-#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
/* detect if we are booting from the 32 bit flash */
if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
/* 32 bit boot flash */
- GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+ GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
- CFG_32BIT_BOOT_PAR);
+ CONFIG_SYS_32BIT_BOOT_PAR);
} else {
/* 8 bit boot flash */
- GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
- GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+ GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+ GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
}
#else
/* 8 bit boot flash only */
-/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
#endif
gt_cpu_config ();
/* MPP setup */
- GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
- GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
- GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
- GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+ GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+ GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+ GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+ GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
- GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+ GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
DEBUG_LED0_ON ();
DEBUG_LED1_ON ();
DEBUG_LED2_ON ();
@@ -415,7 +415,7 @@
int misc_init_r ()
{
icache_enable ();
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
l2cache_enable ();
#endif
#ifdef CONFIG_MPSC
@@ -428,19 +428,19 @@
/* disable the dcache and MMU */
dcache_lock ();
#endif
- if (flash_info[3].size < CFG_FLASH_INCREMENT) {
+ if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) {
unsigned int flash_offset;
unsigned int l;
- flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size;
- for (l = 0; l < CFG_MAX_FLASH_SECT; l++) {
+ flash_offset = CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size;
+ for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) {
if (flash_info[3].start[l] != 0) {
flash_info[3].start[l] += flash_offset;
}
}
flash_protect (FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE + monitor_flash_len - 1,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[3]);
}
return 0;
@@ -449,7 +449,7 @@
void after_reloc (ulong dest_addr, gd_t * gd)
{
- memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE);
+ memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE);
display_mem_map ();
/* now, jump to the main ppcboot board init code */
@@ -469,7 +469,7 @@
{
int l_type = 0;
- printf ("BOARD: %s\n", CFG_BOARD_NAME);
+ printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
return (l_type);
}
@@ -540,7 +540,7 @@
/* DRAM check routines copied from gw8260 */
-#if defined (CFG_DRAM_TEST)
+#if defined (CONFIG_SYS_DRAM_TEST)
/*********************************************************************/
/* NAME: move64() - moves a double word (64-bit) */
@@ -571,7 +571,7 @@
}
-#if defined (CFG_DRAM_TEST_DATA)
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
unsigned long long pattern[] = {
0xaaaaaaaaaaaaaaaaLL,
@@ -634,7 +634,7 @@
/*********************************************************************/
int mem_test_data (void)
{
- unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+ unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
@@ -661,9 +661,9 @@
return 0;
}
-#endif /* CFG_DRAM_TEST_DATA */
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
-#if defined (CFG_DRAM_TEST_ADDRESS)
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
/*********************************************************************/
/* NAME: mem_test_address() - test address lines */
/* */
@@ -688,8 +688,8 @@
int mem_test_address (void)
{
volatile unsigned int *pmem =
- (volatile unsigned int *) CFG_MEMTEST_START;
- const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+ (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+ const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
unsigned int i;
/* write address to each location */
@@ -706,9 +706,9 @@
}
return 0;
}
-#endif /* CFG_DRAM_TEST_ADDRESS */
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
-#if defined (CFG_DRAM_TEST_WALK)
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
/*********************************************************************/
/* NAME: mem_march() - memory march */
/* */
@@ -766,7 +766,7 @@
}
return 0;
}
-#endif /* CFG_DRAM_TEST_WALK */
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
/*********************************************************************/
/* NAME: mem_test_walk() - a simple walking ones test */
@@ -798,8 +798,8 @@
{
unsigned long long mask;
volatile unsigned long long *pmem =
- (volatile unsigned long long *) CFG_MEMTEST_START;
- const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+ (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+ const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
unsigned int i;
@@ -865,23 +865,23 @@
int runaddress = 0;
int runwalk = 0;
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
s = getenv ("testdramdata");
rundata = (s && (*s == 'y')) ? 1 : 0;
#endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
s = getenv ("testdramaddress");
runaddress = (s && (*s == 'y')) ? 1 : 0;
#endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
s = getenv ("testdramwalk");
runwalk = (s && (*s == 'y')) ? 1 : 0;
#endif
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
- printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+ printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
}
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
if (rundata == 1) {
printf ("Test DATA ... ");
if (mem_test_data () == 1) {
@@ -891,7 +891,7 @@
printf ("ok \n");
}
#endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
if (runaddress == 1) {
printf ("Test ADDRESS ... ");
if (mem_test_address () == 1) {
@@ -901,7 +901,7 @@
printf ("ok \n");
}
#endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
if (runwalk == 1) {
printf ("Test WALKING ONEs ... ");
if (mem_test_walk () == 1) {
@@ -917,7 +917,7 @@
return 0;
}
-#endif /* CFG_DRAM_TEST */
+#endif /* CONFIG_SYS_DRAM_TEST */
/* ronen - the below functions are used by the bootm function */
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
@@ -956,7 +956,7 @@
/* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
/* Relocate MV64360 internal regs */
- my_remap_gt_regs_bootm (CFG_GT_REGS, CFG_DFL_GT_REGS);
+ my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS);
icache_disable ();
dcache_disable ();
diff --git a/board/esd/cpci750/i2c.c b/board/esd/cpci750/i2c.c
index 5b1bc01..d95567f 100644
--- a/board/esd/cpci750/i2c.c
+++ b/board/esd/cpci750/i2c.c
@@ -46,7 +46,7 @@
unsigned int n, m, freq, margin, power;
unsigned int actualN = 0, actualM = 0;
unsigned int minMargin = 0xffffffff;
- unsigned int tclk = CFG_TCLK;
+ unsigned int tclk = CONFIG_SYS_TCLK;
unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */
DP (puts ("i2c_init\n"));
@@ -380,7 +380,7 @@
int len)
{
uchar status = 0;
- unsigned int i2cFreq = CFG_I2C_SPEED;
+ unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_read\n"));
@@ -428,7 +428,7 @@
int len)
{
uchar status = 0;
- unsigned int i2cFreq = CFG_I2C_SPEED;
+ unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_write\n"));
@@ -464,7 +464,7 @@
unsigned int i2c_status;
#endif
uchar status = 0;
- unsigned int i2cFreq = CFG_I2C_SPEED;
+ unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_probe\n"));
diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c
index 0adafe2..9bdc523 100644
--- a/board/esd/cpci750/ide.c
+++ b/board/esd/cpci750/ide.c
@@ -30,7 +30,7 @@
#include <ide.h>
#include <pci.h>
-extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
+extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
int ide_preinit (void)
{
@@ -39,7 +39,7 @@
int l;
status = 1;
- for (l = 0; l < CFG_IDE_MAXBUS; l++) {
+ for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
ide_bus_offset[l] = -ATA_STATUS;
}
devbusfn = pci_find_device (0x1103, 0x0004, 0);
@@ -51,11 +51,11 @@
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
(u32 *) & ide_bus_offset[0]);
ide_bus_offset[0] &= 0xfffffffe;
- ide_bus_offset[0] += CFG_PCI0_IO_SPACE;
+ ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE;
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
(u32 *) & ide_bus_offset[1]);
ide_bus_offset[1] &= 0xfffffffe;
- ide_bus_offset[1] += CFG_PCI0_IO_SPACE;
+ ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
}
return (status);
}
diff --git a/board/esd/cpci750/local.h b/board/esd/cpci750/local.h
index bca0e1f..de3758a 100644
--- a/board/esd/cpci750/local.h
+++ b/board/esd/cpci750/local.h
@@ -48,7 +48,7 @@
/* #define CONFIG_BOOTCOMMAND */
/* #define CONFIG_RAMBOOTCOMMAND */
/* #define CONFIG_NFSBOOTCOMMAND */
-/* #define CFG_AUTOLOAD */
+/* #define CONFIG_SYS_AUTOLOAD */
/* #define CONFIG_PREBOOT */
/* These don't */
diff --git a/board/esd/cpci750/misc.S b/board/esd/cpci750/misc.S
index 160b1d3..233fd83 100644
--- a/board/esd/cpci750/misc.S
+++ b/board/esd/cpci750/misc.S
@@ -16,7 +16,7 @@
board_relocate_rom:
mflr r7
/* update the location of the GT registers */
- lis r11, CFG_GT_REGS@h
+ lis r11, CONFIG_SYS_GT_REGS@h
/* if we're using ECC, we must use the DMA engine to copy ourselves */
bl start_idma_transfer_0
bl wait_for_idma_0
@@ -29,12 +29,12 @@
board_init_ecc:
mflr r7
/* NOTE: r10 still contains the location we've been relocated to
- * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+ * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
/* now that we're running from ram, init the rest of main memory
* for ECC use */
- lis r8, CFG_MONITOR_LEN@h
- ori r8, r8, CFG_MONITOR_LEN@l
+ lis r8, CONFIG_SYS_MONITOR_LEN@h
+ ori r8, r8, CONFIG_SYS_MONITOR_LEN@l
divw r3, r10, r8
@@ -120,15 +120,15 @@
blr
#endif
-#ifdef CFG_BOARD_ASM_INIT
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
/* NOTE: trashes r3-r7 */
.globl board_asm_init
board_asm_init:
/* just move the GT registers to where they belong */
- lis r3, CFG_DFL_GT_REGS@h
- ori r3, r3, CFG_DFL_GT_REGS@l
- lis r4, CFG_GT_REGS@h
- ori r4, r4, CFG_GT_REGS@l
+ lis r3, CONFIG_SYS_DFL_GT_REGS@h
+ ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l
+ lis r4, CONFIG_SYS_GT_REGS@h
+ ori r4, r4, CONFIG_SYS_GT_REGS@l
li r5, INTERNAL_SPACE_DECODE
/* test to see if we've already moved */
@@ -153,11 +153,11 @@
cmp cr0, r7, r6
bne 1b
- lis r3, CFG_INT_SRAM_BASE@h
- ori r3, r3, CFG_INT_SRAM_BASE@l
+ lis r3, CONFIG_SYS_INT_SRAM_BASE@h
+ ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
rlwinm r3, r3, 16, 16, 31
- lis r4, CFG_GT_REGS@h
- ori r4, r4, CFG_GT_REGS@l
+ lis r4, CONFIG_SYS_GT_REGS@h
+ ori r4, r4, CONFIG_SYS_GT_REGS@l
li r5, INTEGRATED_SRAM_BASE_ADDR
stwbrx r3, r5, r4
diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c
index fa8d3bd..c89426d 100644
--- a/board/esd/cpci750/mpsc.c
+++ b/board/esd/cpci750/mpsc.c
@@ -427,7 +427,7 @@
(MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
/* Setup MPSC internal address space base address */
- GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+ GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
/* no high address remap*/
GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
@@ -517,9 +517,9 @@
#ifdef ZUMA_NTL
/* from tclk */
- clock = (CFG_TCLK / (16 * rate)) - 1;
+ clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
#else
- clock = (CFG_TCLK / (16 * rate)) - 1;
+ clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
#endif
galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */
diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c
index c335ebf..cbe766f 100644
--- a/board/esd/cpci750/pci.c
+++ b/board/esd/cpci750/pci.c
@@ -932,14 +932,14 @@
/* PCI memory space */
pci_set_region (pci0_hose.regions + 0,
- CFG_PCI0_0_MEM_SPACE,
- CFG_PCI0_0_MEM_SPACE,
- CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+ CONFIG_SYS_PCI0_0_MEM_SPACE,
+ CONFIG_SYS_PCI0_0_MEM_SPACE,
+ CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci0_hose.regions + 1,
- CFG_PCI0_IO_SPACE_PCI,
- CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+ CONFIG_SYS_PCI0_IO_SPACE_PCI,
+ CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci0_hose,
pci_hose_read_config_byte_via_dword,
@@ -981,14 +981,14 @@
/* PCI memory space */
pci_set_region (pci1_hose.regions + 0,
- CFG_PCI1_0_MEM_SPACE,
- CFG_PCI1_0_MEM_SPACE,
- CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+ CONFIG_SYS_PCI1_0_MEM_SPACE,
+ CONFIG_SYS_PCI1_0_MEM_SPACE,
+ CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci1_hose.regions + 1,
- CFG_PCI1_IO_SPACE_PCI,
- CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+ CONFIG_SYS_PCI1_IO_SPACE_PCI,
+ CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci1_hose,
pci_hose_read_config_byte_via_dword,
diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c
index 0291937..4c03630 100644
--- a/board/esd/cpci750/sdram_init.c
+++ b/board/esd/cpci750/sdram_init.c
@@ -350,7 +350,7 @@
} else
dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
-#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
+#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
for (i = 0; i <= 127; i++) {
printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
@@ -1656,13 +1656,13 @@
if (dimmInfo2.numOfModuleBanks > 2)
printf("Error, SPD claims DIMM2 has >2 banks\n");
- for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+ for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
/* skip over banks that are not populated */
if (! checkbank[bank_no])
continue;
- if ((total + check) > CFG_GT_REGS)
- check = CFG_GT_REGS - total;
+ if ((total + check) > CONFIG_SYS_GT_REGS)
+ check = CONFIG_SYS_GT_REGS - total;
memory_map_bank(bank_no, total, check);
realsize = dram_size((long int *)total, check);