rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/README b/README
index c63c720..ebee20f 100644
--- a/README
+++ b/README
@@ -210,7 +210,7 @@
* Configuration _SETTINGS_:
These depend on the hardware etc. and should not be meddled with if
you don't know what you're doing; they have names beginning with
- "CFG_".
+ "CONFIG_SYS_".
Later we will add a configuration tool - probably similar to or even
identical to what's used for the Linux kernel. Right now, we have to
@@ -284,10 +284,10 @@
- Board flavour: (if CONFIG_MPC8260ADS is defined)
CONFIG_ADSTYPE
Possible values are:
- CFG_8260ADS - original MPC8260ADS
- CFG_8266ADS - MPC8266ADS
- CFG_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR
- CFG_8272ADS - MPC8272ADS
+ CONFIG_SYS_8260ADS - original MPC8260ADS
+ CONFIG_SYS_8266ADS - MPC8266ADS
+ CONFIG_SYS_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR
+ CONFIG_SYS_8272ADS - MPC8272ADS
- MPC824X Family Member (if CONFIG_MPC824X is defined)
Define exactly one of
@@ -302,28 +302,28 @@
or XTAL/EXTAL)
- 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU):
- CFG_8xx_CPUCLK_MIN
- CFG_8xx_CPUCLK_MAX
+ CONFIG_SYS_8xx_CPUCLK_MIN
+ CONFIG_SYS_8xx_CPUCLK_MAX
CONFIG_8xx_CPUCLK_DEFAULT
See doc/README.MPC866
- CFG_MEASURE_CPUCLK
+ CONFIG_SYS_MEASURE_CPUCLK
Define this to measure the actual CPU clock instead
of relying on the correctness of the configured
values. Mostly useful for board bringup to make sure
the PLL is locked at the intended frequency. Note
that this requires a (stable) reference clock (32 kHz
- RTC clock or CFG_8XX_XIN)
+ RTC clock or CONFIG_SYS_8XX_XIN)
- Intel Monahans options:
- CFG_MONAHANS_RUN_MODE_OSC_RATIO
+ CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
Defines the Monahans run mode to oscillator
ratio. Valid values are 8, 16, 24, 31. The core
frequency is this value multiplied by 13 MHz.
- CFG_MONAHANS_TURBO_RUN_MODE_RATIO
+ CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
Defines the Monahans turbo mode to oscillator
ratio. Valid values are 1 (default if undefined) and
@@ -436,7 +436,7 @@
CONFIG_CONSOLE_CURSOR cursor drawing on/off
(requires blink timer
cf. i8042.c)
- CFG_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c)
+ CONFIG_SYS_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c)
CONFIG_CONSOLE_TIME display time/date info in
upper right corner
(requires CONFIG_CMD_DATE)
@@ -461,8 +461,8 @@
- Console Baudrate:
CONFIG_BAUDRATE - in bps
Select one of the baudrates listed in
- CFG_BAUDRATE_TABLE, see below.
- CFG_BRGCLK_PRESCALE, baudrate prescale
+ CONFIG_SYS_BAUDRATE_TABLE, see below.
+ CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale
- Interrupt driven serial port input:
CONFIG_SERIAL_SOFTWARE_FIFO
@@ -546,7 +546,7 @@
- Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined)
CONFIG_KGDB_BAUDRATE
Select one of the baudrates listed in
- CFG_BAUDRATE_TABLE, see below.
+ CONFIG_SYS_BAUDRATE_TABLE, see below.
- Monitor Functions:
Monitor commands can be included or excluded
@@ -673,7 +673,7 @@
CONFIG_RTC_DS164x - use Dallas DS164x RTC
CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC
CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC
- CFG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337
+ CONFIG_SYS_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337
Note that if the RTC uses I2C, then the I2C interface
must also be configured. See I2C Support, below.
@@ -711,11 +711,11 @@
CONFIG_LBA48
Set this to enable support for disks larger than 137GB
- Also look at CFG_64BIT_LBA ,CFG_64BIT_VSPRINTF and CFG_64BIT_STRTOUL
+ Also look at CONFIG_SYS_64BIT_LBA ,CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
Whithout these , LBA48 support uses 32bit variables and will 'only'
support disks up to 2.1TB.
- CFG_64BIT_LBA:
+ CONFIG_SYS_64BIT_LBA:
When enabled, makes the IDE subsystem use 64bit sector addresses.
Default is 32bit.
@@ -724,12 +724,12 @@
SYM53C8XX SCSI controller; define
CONFIG_SCSI_SYM53C8XX to enable it.
- CFG_SCSI_MAX_LUN [8], CFG_SCSI_MAX_SCSI_ID [7] and
- CFG_SCSI_MAX_DEVICE [CFG_SCSI_MAX_SCSI_ID *
- CFG_SCSI_MAX_LUN] can be adjusted to define the
+ CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
+ CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
+ CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
maximum numbers of LUNs, SCSI ID's and target
devices.
- CFG_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
+ CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
- NETWORK Support (PCI):
CONFIG_E1000
@@ -811,7 +811,7 @@
CONFIG_USB_CONFIG
for differential drivers: 0x00001000
for single ended drivers: 0x00005000
- CFG_USB_EVENT_POLL
+ CONFIG_SYS_USB_EVENT_POLL
May be defined to allow interrupt polling
instead of using asynchronous interrupts
@@ -838,18 +838,18 @@
Define this to have a tty type of device available to
talk to the UDC device
- CFG_CONSOLE_IS_IN_ENV
+ CONFIG_SYS_CONSOLE_IS_IN_ENV
Define this if you want stdin, stdout &/or stderr to
be set to usbtty.
mpc8xx:
- CFG_USB_EXTC_CLK 0xBLAH
+ CONFIG_SYS_USB_EXTC_CLK 0xBLAH
Derive USB clock from external clock "blah"
- - CFG_USB_EXTC_CLK 0x02
+ - CONFIG_SYS_USB_EXTC_CLK 0x02
- CFG_USB_BRG_CLK 0xBLAH
+ CONFIG_SYS_USB_BRG_CLK 0xBLAH
Derive USB clock from brgclk
- - CFG_USB_BRG_CLK 0x04
+ - CONFIG_SYS_USB_BRG_CLK 0x04
If you have a USB-IF assigned VendorID then you may wish to
define your own vendor specific values either in BoardName.h
@@ -891,16 +891,16 @@
CONFIG_JFFS2_NAND_DEV
Define these for a default partition on a NAND device
- CFG_JFFS2_FIRST_SECTOR,
- CFG_JFFS2_FIRST_BANK, CFG_JFFS2_NUM_BANKS
+ CONFIG_SYS_JFFS2_FIRST_SECTOR,
+ CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
Define these for a default partition on a NOR device
- CFG_JFFS_CUSTOM_PART
+ CONFIG_SYS_JFFS_CUSTOM_PART
Define this to create an own partition. You have to provide a
function struct part_info* jffs2_part_info(int part_num)
If you define only one JFFS2 partition you may also want to
- #define CFG_JFFS_SINGLE_PART 1
+ #define CONFIG_SYS_JFFS_SINGLE_PART 1
to disable the command chpart. This is the default when you
have not defined a custom partition
@@ -1014,7 +1014,7 @@
320x240. Black & white.
Normally display is black on white background; define
- CFG_WHITE_ON_BLACK to get it inverted.
+ CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
- Splash Screen Support: CONFIG_SPLASH_SCREEN
@@ -1041,7 +1041,7 @@
compressed images are supported.
NOTE: the bzip2 algorithm requires a lot of RAM, so
- the malloc area (as defined by CFG_MALLOC_LEN) should
+ the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
be at least 4MB.
CONFIG_LZMA
@@ -1065,7 +1065,7 @@
Use the lzmainfo tool to determinate the lc and lp values and
then calculate the amount of needed dynamic memory (ensuring
- the appropriate CFG_MALLOC_LEN value).
+ the appropriate CONFIG_SYS_MALLOC_LEN value).
- MII/PHY support:
CONFIG_PHY_ADDR
@@ -1282,15 +1282,15 @@
There are several other quantities that must also be
defined when you define CONFIG_HARD_I2C or CONFIG_SOFT_I2C.
- In both cases you will need to define CFG_I2C_SPEED
+ In both cases you will need to define CONFIG_SYS_I2C_SPEED
to be the frequency (in Hz) at which you wish your i2c bus
- to run and CFG_I2C_SLAVE to be the address of this node (ie
+ to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
the CPU's i2c node address).
Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c)
sets the CPU up as a master node and so its address should
therefore be cleared to 0 (See, eg, MPC823e User's Manual
- p.16-473). So, set CFG_I2C_SLAVE to 0.
+ p.16-473). So, set CONFIG_SYS_I2C_SLAVE to 0.
That's all that's required for CONFIG_HARD_I2C.
@@ -1361,7 +1361,7 @@
#define I2C_DELAY udelay(2)
- CFG_I2C_INIT_BOARD
+ CONFIG_SYS_I2C_INIT_BOARD
When a board is reset during an i2c bus transfer
chips might think that the current transfer is still
@@ -1385,7 +1385,7 @@
active. To switch to a different bus, use the 'i2c dev' command.
Note that bus numbering is zero-based.
- CFG_I2C_NOPROBES
+ CONFIG_SYS_I2C_NOPROBES
This option specifies a list of I2C devices that will be skipped
when the 'i2c probe' command is issued (or 'iprobe' using the legacy
@@ -1394,31 +1394,31 @@
e.g.
#undef CONFIG_I2C_MULTI_BUS
- #define CFG_I2C_NOPROBES {0x50,0x68}
+ #define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
will skip addresses 0x50 and 0x68 on a board with one I2C bus
#define CONFIG_I2C_MULTI_BUS
- #define CFG_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
+ #define CONFIG_SYS_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
- CFG_SPD_BUS_NUM
+ CONFIG_SYS_SPD_BUS_NUM
If defined, then this indicates the I2C bus number for DDR SPD.
If not defined, then U-Boot assumes that SPD is on I2C bus 0.
- CFG_RTC_BUS_NUM
+ CONFIG_SYS_RTC_BUS_NUM
If defined, then this indicates the I2C bus number for the RTC.
If not defined, then U-Boot assumes that RTC is on I2C bus 0.
- CFG_DTT_BUS_NUM
+ CONFIG_SYS_DTT_BUS_NUM
If defined, then this indicates the I2C bus number for the DTT.
If not defined, then U-Boot assumes that DTT is on I2C bus 0.
- CFG_I2C_DTT_ADDR:
+ CONFIG_SYS_I2C_DTT_ADDR:
If defined, specifies the I2C address of the DTT device.
If not defined, then U-Boot uses predefined value for
@@ -1529,11 +1529,11 @@
Specify the number of FPGA devices to support.
- CFG_FPGA_PROG_FEEDBACK
+ CONFIG_SYS_FPGA_PROG_FEEDBACK
Enable printing of hash marks during FPGA configuration.
- CFG_FPGA_CHECK_BUSY
+ CONFIG_SYS_FPGA_CHECK_BUSY
Enable checks on FPGA configuration interface busy
status by the configuration function. This option
@@ -1545,29 +1545,29 @@
If defined, a function that provides delays in the FPGA
configuration driver.
- CFG_FPGA_CHECK_CTRLC
+ CONFIG_SYS_FPGA_CHECK_CTRLC
Allow Control-C to interrupt FPGA configuration
- CFG_FPGA_CHECK_ERROR
+ CONFIG_SYS_FPGA_CHECK_ERROR
Check for configuration errors during FPGA bitfile
loading. For example, abort during Virtex II
configuration if the INIT_B line goes low (which
indicated a CRC error).
- CFG_FPGA_WAIT_INIT
+ CONFIG_SYS_FPGA_WAIT_INIT
Maximum time to wait for the INIT_B line to deassert
after PROB_B has been deasserted during a Virtex II
FPGA configuration sequence. The default time is 500
ms.
- CFG_FPGA_WAIT_BUSY
+ CONFIG_SYS_FPGA_WAIT_BUSY
Maximum time to wait for BUSY to deassert during
Virtex II FPGA configuration. The default is 5 ms.
- CFG_FPGA_WAIT_CONFIG
+ CONFIG_SYS_FPGA_WAIT_CONFIG
Time to wait after FPGA configuration. The default is
200 ms.
@@ -1665,7 +1665,7 @@
for the "hush" shell.
- CFG_HUSH_PARSER
+ CONFIG_SYS_HUSH_PARSER
Define this variable to enable the "hush" shell (from
Busybox) as command line interpreter, thus enabling
@@ -1677,7 +1677,7 @@
with a somewhat smaller memory footprint.
- CFG_PROMPT_HUSH_PS2
+ CONFIG_SYS_PROMPT_HUSH_PS2
This defines the secondary prompt string, which is
printed when the command interpreter needs more input
@@ -1749,10 +1749,10 @@
Adding this option adds support for Xilinx SystemACE
chips attached via some sort of local bus. The address
of the chip must also be defined in the
- CFG_SYSTEMACE_BASE macro. For example:
+ CONFIG_SYS_SYSTEMACE_BASE macro. For example:
#define CONFIG_SYSTEMACE
- #define CFG_SYSTEMACE_BASE 0xf0000000
+ #define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
When SystemACE support is added, the "ace" device type
becomes available to the fat commands, i.e. fatls.
@@ -2000,53 +2000,53 @@
Configuration Settings:
-----------------------
-- CFG_LONGHELP: Defined when you want long help messages included;
+- CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
undefine this when you're short of memory.
-- CFG_PROMPT: This is what U-Boot prints on the console to
+- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
prompt for user input.
-- CFG_CBSIZE: Buffer size for input from the Console
+- CONFIG_SYS_CBSIZE: Buffer size for input from the Console
-- CFG_PBSIZE: Buffer size for Console output
+- CONFIG_SYS_PBSIZE: Buffer size for Console output
-- CFG_MAXARGS: max. Number of arguments accepted for monitor commands
+- CONFIG_SYS_MAXARGS: max. Number of arguments accepted for monitor commands
-- CFG_BARGSIZE: Buffer size for Boot Arguments which are passed to
+- CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to
the application (usually a Linux kernel) when it is
booted
-- CFG_BAUDRATE_TABLE:
+- CONFIG_SYS_BAUDRATE_TABLE:
List of legal baudrate settings for this board.
-- CFG_CONSOLE_INFO_QUIET
+- CONFIG_SYS_CONSOLE_INFO_QUIET
Suppress display of console information at boot.
-- CFG_CONSOLE_IS_IN_ENV
+- CONFIG_SYS_CONSOLE_IS_IN_ENV
If the board specific function
extern int overwrite_console (void);
returns 1, the stdin, stderr and stdout are switched to the
serial port, else the settings in the environment are used.
-- CFG_CONSOLE_OVERWRITE_ROUTINE
+- CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
Enable the call to overwrite_console().
-- CFG_CONSOLE_ENV_OVERWRITE
+- CONFIG_SYS_CONSOLE_ENV_OVERWRITE
Enable overwrite of previous console environment settings.
-- CFG_MEMTEST_START, CFG_MEMTEST_END:
+- CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END:
Begin and End addresses of the area used by the
simple memory test.
-- CFG_ALT_MEMTEST:
+- CONFIG_SYS_ALT_MEMTEST:
Enable an alternate, more extensive memory test.
-- CFG_MEMTEST_SCRATCH:
+- CONFIG_SYS_MEMTEST_SCRATCH:
Scratch address used by the alternate memory test
You only need to set this if address zero isn't writeable
-- CFG_MEM_TOP_HIDE (PPC only):
- If CFG_MEM_TOP_HIDE is defined in the board config header,
+- CONFIG_SYS_MEM_TOP_HIDE (PPC only):
+ If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header,
this specified memory area will get subtracted from the top
(end) of RAM and won't get "touched" at all by U-Boot. By
fixing up gd->ram_size the Linux kernel should gets passed
@@ -2066,75 +2066,75 @@
non page size aligned address and this could cause major
problems.
-- CFG_TFTP_LOADADDR:
+- CONFIG_SYS_TFTP_LOADADDR:
Default load address for network file downloads
-- CFG_LOADS_BAUD_CHANGE:
+- CONFIG_SYS_LOADS_BAUD_CHANGE:
Enable temporary baudrate change while serial download
-- CFG_SDRAM_BASE:
+- CONFIG_SYS_SDRAM_BASE:
Physical start address of SDRAM. _Must_ be 0 here.
-- CFG_MBIO_BASE:
+- CONFIG_SYS_MBIO_BASE:
Physical start address of Motherboard I/O (if using a
Cogent motherboard)
-- CFG_FLASH_BASE:
+- CONFIG_SYS_FLASH_BASE:
Physical start address of Flash memory.
-- CFG_MONITOR_BASE:
+- CONFIG_SYS_MONITOR_BASE:
Physical start address of boot monitor code (set by
make config files to be same as the text base address
(TEXT_BASE) used when linking) - same as
- CFG_FLASH_BASE when booting from flash.
+ CONFIG_SYS_FLASH_BASE when booting from flash.
-- CFG_MONITOR_LEN:
+- CONFIG_SYS_MONITOR_LEN:
Size of memory reserved for monitor code, used to
determine _at_compile_time_ (!) if the environment is
embedded within the U-Boot image, or in a separate
flash sector.
-- CFG_MALLOC_LEN:
+- CONFIG_SYS_MALLOC_LEN:
Size of DRAM reserved for malloc() use.
-- CFG_BOOTM_LEN:
+- CONFIG_SYS_BOOTM_LEN:
Normally compressed uImages are limited to an
uncompressed size of 8 MBytes. If this is not enough,
- you can define CFG_BOOTM_LEN in your board config file
+ you can define CONFIG_SYS_BOOTM_LEN in your board config file
to adjust this setting to your needs.
-- CFG_BOOTMAPSZ:
+- CONFIG_SYS_BOOTMAPSZ:
Maximum size of memory mapped by the startup code of
the Linux kernel; all data that must be processed by
the Linux kernel (bd_info, boot arguments, FDT blob if
used) must be put below this limit, unless "bootm_low"
enviroment variable is defined and non-zero. In such case
all data for the Linux kernel must be between "bootm_low"
- and "bootm_low" + CFG_BOOTMAPSZ.
+ and "bootm_low" + CONFIG_SYS_BOOTMAPSZ.
-- CFG_MAX_FLASH_BANKS:
+- CONFIG_SYS_MAX_FLASH_BANKS:
Max number of Flash memory banks
-- CFG_MAX_FLASH_SECT:
+- CONFIG_SYS_MAX_FLASH_SECT:
Max number of sectors on a Flash chip
-- CFG_FLASH_ERASE_TOUT:
+- CONFIG_SYS_FLASH_ERASE_TOUT:
Timeout for Flash erase operations (in ms)
-- CFG_FLASH_WRITE_TOUT:
+- CONFIG_SYS_FLASH_WRITE_TOUT:
Timeout for Flash write operations (in ms)
-- CFG_FLASH_LOCK_TOUT
+- CONFIG_SYS_FLASH_LOCK_TOUT
Timeout for Flash set sector lock bit operation (in ms)
-- CFG_FLASH_UNLOCK_TOUT
+- CONFIG_SYS_FLASH_UNLOCK_TOUT
Timeout for Flash clear lock bits operation (in ms)
-- CFG_FLASH_PROTECTION
+- CONFIG_SYS_FLASH_PROTECTION
If defined, hardware flash sectors protection is used
instead of U-Boot software protection.
-- CFG_DIRECT_FLASH_TFTP:
+- CONFIG_SYS_DIRECT_FLASH_TFTP:
Enable TFTP transfers directly to flash memory;
without this option such a download has to be
@@ -2147,7 +2147,7 @@
too limited to allow for a temporary copy of the
downloaded image) this option may be very useful.
-- CFG_FLASH_CFI:
+- CONFIG_SYS_FLASH_CFI:
Define if the flash driver uses extra elements in the
common flash structure for storing flash geometry.
@@ -2155,14 +2155,14 @@
This option also enables the building of the cfi_flash driver
in the drivers directory
-- CFG_FLASH_USE_BUFFER_WRITE
+- CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Use buffered writes to flash.
- CONFIG_FLASH_SPANSION_S29WS_N
s29ws-n MirrorBit flash has non-standard addresses for buffered
write commands.
-- CFG_FLASH_QUIET_TEST
+- CONFIG_SYS_FLASH_QUIET_TEST
If this option is defined, the common CFI flash doesn't
print it's warning upon not recognized FLASH banks. This
is useful, if some of the configured banks are only
@@ -2173,7 +2173,7 @@
digits and dots. Recommended value: 45 (9..1) for 80
column displays, 15 (3..1) for 40 column displays.
-- CFG_RX_ETH_BUFFER:
+- CONFIG_SYS_RX_ETH_BUFFER:
Defines the number of Ethernet receive buffers. On some
Ethernet controllers it is recommended to set this value
to 8 or even higher (EEPRO100 or 405 EMAC), since all
@@ -2208,7 +2208,7 @@
type flash chips the second sector can be used: the offset
for this sector is given here.
- CONFIG_ENV_OFFSET is used relative to CFG_FLASH_BASE.
+ CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE.
- CONFIG_ENV_ADDR:
@@ -2291,24 +2291,24 @@
These two #defines specify the offset and size of the
environment area within the total memory of your EEPROM.
- - CFG_I2C_EEPROM_ADDR:
+ - CONFIG_SYS_I2C_EEPROM_ADDR:
If defined, specified the chip address of the EEPROM device.
The default address is zero.
- - CFG_EEPROM_PAGE_WRITE_BITS:
+ - CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
If defined, the number of bits used to address bytes in a
single page in the EEPROM device. A 64 byte page, for example
would require six bits.
- - CFG_EEPROM_PAGE_WRITE_DELAY_MS:
+ - CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS:
If defined, the number of milliseconds to delay between
page writes. The default is zero milliseconds.
- - CFG_I2C_EEPROM_ADDR_LEN:
+ - CONFIG_SYS_I2C_EEPROM_ADDR_LEN:
The length in bytes of the EEPROM memory array address. Note
that this is NOT the chip address length!
- - CFG_I2C_EEPROM_ADDR_OVERFLOW:
+ - CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW:
EEPROM chips that implement "address overflow" are ones
like Catalyst 24WC04/08/16 which has 9/10/11 bits of
address and the extra bits end up in the "chip address" bit
@@ -2319,7 +2319,7 @@
still be one byte because the extra address bits are hidden
in the chip address.
- - CFG_EEPROM_SIZE:
+ - CONFIG_SYS_EEPROM_SIZE:
The size in bytes of the EEPROM device.
@@ -2358,7 +2358,7 @@
to a block boundary, and CONFIG_ENV_SIZE must be a multiple of
the NAND devices block size.
-- CFG_SPI_INIT_OFFSET
+- CONFIG_SYS_SPI_INIT_OFFSET
Defines offset to the initial SPI buffer area in DPRAM. The
area is used at an early stage (ROM part) if the environment
@@ -2384,29 +2384,29 @@
the default environment is used; a new CRC is computed as soon as you
use the "saveenv" command to store a valid environment.
-- CFG_FAULT_ECHO_LINK_DOWN:
+- CONFIG_SYS_FAULT_ECHO_LINK_DOWN:
Echo the inverted Ethernet link state to the fault LED.
- Note: If this option is active, then CFG_FAULT_MII_ADDR
+ Note: If this option is active, then CONFIG_SYS_FAULT_MII_ADDR
also needs to be defined.
-- CFG_FAULT_MII_ADDR:
+- CONFIG_SYS_FAULT_MII_ADDR:
MII address of the PHY to check for the Ethernet link state.
-- CFG_64BIT_VSPRINTF:
+- CONFIG_SYS_64BIT_VSPRINTF:
Makes vsprintf (and all *printf functions) support printing
of 64bit values by using the L quantifier
-- CFG_64BIT_STRTOUL:
+- CONFIG_SYS_64BIT_STRTOUL:
Adds simple_strtoull that returns a 64bit value
Low Level (hardware related) configuration options:
---------------------------------------------------
-- CFG_CACHELINE_SIZE:
+- CONFIG_SYS_CACHELINE_SIZE:
Cache Line Size of the CPU.
-- CFG_DEFAULT_IMMR:
+- CONFIG_SYS_DEFAULT_IMMR:
Default address of the IMMR after system reset.
Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
@@ -2414,36 +2414,36 @@
the IMMR register after a reset.
- Floppy Disk Support:
- CFG_FDC_DRIVE_NUMBER
+ CONFIG_SYS_FDC_DRIVE_NUMBER
the default drive number (default value 0)
- CFG_ISA_IO_STRIDE
+ CONFIG_SYS_ISA_IO_STRIDE
defines the spacing between FDC chipset registers
(default value 1)
- CFG_ISA_IO_OFFSET
+ CONFIG_SYS_ISA_IO_OFFSET
defines the offset of register from address. It
depends on which part of the data bus is connected to
the FDC chipset. (default value 0)
- If CFG_ISA_IO_STRIDE CFG_ISA_IO_OFFSET and
- CFG_FDC_DRIVE_NUMBER are undefined, they take their
+ If CONFIG_SYS_ISA_IO_STRIDE CONFIG_SYS_ISA_IO_OFFSET and
+ CONFIG_SYS_FDC_DRIVE_NUMBER are undefined, they take their
default value.
- if CFG_FDC_HW_INIT is defined, then the function
+ if CONFIG_SYS_FDC_HW_INIT is defined, then the function
fdc_hw_init() is called at the beginning of the FDC
setup. fdc_hw_init() must be provided by the board
source code. It is used to make hardware dependant
initializations.
-- CFG_IMMR: Physical address of the Internal Memory.
+- CONFIG_SYS_IMMR: Physical address of the Internal Memory.
DO NOT CHANGE unless you know exactly what you're
doing! (11-4) [MPC8xx/82xx systems only]
-- CFG_INIT_RAM_ADDR:
+- CONFIG_SYS_INIT_RAM_ADDR:
Start address of memory area that can be used for
initial data and stack; please note that this must be
@@ -2458,91 +2458,91 @@
- MPC824X: data cache
- PPC4xx: data cache
-- CFG_GBL_DATA_OFFSET:
+- CONFIG_SYS_GBL_DATA_OFFSET:
Offset of the initial data structure in the memory
- area defined by CFG_INIT_RAM_ADDR. Usually
- CFG_GBL_DATA_OFFSET is chosen such that the initial
+ area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
+ CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
data is located at the end of the available space
- (sometimes written as (CFG_INIT_RAM_END -
- CFG_INIT_DATA_SIZE), and the initial stack is just
- below that area (growing from (CFG_INIT_RAM_ADDR +
- CFG_GBL_DATA_OFFSET) downward.
+ (sometimes written as (CONFIG_SYS_INIT_RAM_END -
+ CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
+ below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
+ CONFIG_SYS_GBL_DATA_OFFSET) downward.
Note:
On the MPC824X (or other systems that use the data
cache for initial memory) the address chosen for
- CFG_INIT_RAM_ADDR is basically arbitrary - it must
+ CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
point to an otherwise UNUSED address space between
the top of RAM and the start of the PCI space.
-- CFG_SIUMCR: SIU Module Configuration (11-6)
+- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6)
-- CFG_SYPCR: System Protection Control (11-9)
+- CONFIG_SYS_SYPCR: System Protection Control (11-9)
-- CFG_TBSCR: Time Base Status and Control (11-26)
+- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26)
-- CFG_PISCR: Periodic Interrupt Status and Control (11-31)
+- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31)
-- CFG_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30)
+- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30)
-- CFG_SCCR: System Clock and reset Control Register (15-27)
+- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
-- CFG_OR_TIMING_SDRAM:
+- CONFIG_SYS_OR_TIMING_SDRAM:
SDRAM timing
-- CFG_MAMR_PTA:
+- CONFIG_SYS_MAMR_PTA:
periodic timer for refresh
-- CFG_DER: Debug Event Register (37-47)
+- CONFIG_SYS_DER: Debug Event Register (37-47)
-- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CFG_REMAP_OR_AM,
- CFG_PRELIM_OR_AM, CFG_OR_TIMING_FLASH, CFG_OR0_REMAP,
- CFG_OR0_PRELIM, CFG_BR0_PRELIM, CFG_OR1_REMAP, CFG_OR1_PRELIM,
- CFG_BR1_PRELIM:
+- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
+ CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
+ CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
+ CONFIG_SYS_BR1_PRELIM:
Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)
- SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE,
- CFG_OR_TIMING_SDRAM, CFG_OR2_PRELIM, CFG_BR2_PRELIM,
- CFG_OR3_PRELIM, CFG_BR3_PRELIM:
+ CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM,
+ CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
-- CFG_MAMR_PTA, CFG_MPTPR_2BK_4K, CFG_MPTPR_1BK_4K, CFG_MPTPR_2BK_8K,
- CFG_MPTPR_1BK_8K, CFG_MAMR_8COL, CFG_MAMR_9COL:
+- CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K,
+ CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL:
Machine Mode Register and Memory Periodic Timer
Prescaler definitions (SDRAM timing)
-- CFG_I2C_UCODE_PATCH, CFG_I2C_DPMEM_OFFSET [0x1FC0]:
+- CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_I2C_DPMEM_OFFSET [0x1FC0]:
enable I2C microcode relocation patch (MPC8xx);
define relocation offset in DPRAM [DSP2]
-- CFG_SMC_UCODE_PATCH, CFG_SMC_DPMEM_OFFSET [0x1FC0]:
+- CONFIG_SYS_SMC_UCODE_PATCH, CONFIG_SYS_SMC_DPMEM_OFFSET [0x1FC0]:
enable SMC microcode relocation patch (MPC8xx);
define relocation offset in DPRAM [SMC1]
-- CFG_SPI_UCODE_PATCH, CFG_SPI_DPMEM_OFFSET [0x1FC0]:
+- CONFIG_SYS_SPI_UCODE_PATCH, CONFIG_SYS_SPI_DPMEM_OFFSET [0x1FC0]:
enable SPI microcode relocation patch (MPC8xx);
define relocation offset in DPRAM [SCC4]
-- CFG_USE_OSCCLK:
+- CONFIG_SYS_USE_OSCCLK:
Use OSCM clock mode on MBX8xx board. Be careful,
wrong setting might damage your board. Read
doc/README.MBX before setting this variable!
-- CFG_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
+- CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
Offset of the bootmode word in DPRAM used by post
(Power On Self Tests). This definition overrides
#define'd default value in commproc.h resp.
cpm_8260.h.
-- CFG_PCI_SLV_MEM_LOCAL, CFG_PCI_SLV_MEM_BUS, CFG_PICMR0_MASK_ATTRIB,
- CFG_PCI_MSTR0_LOCAL, CFG_PCIMSK0_MASK, CFG_PCI_MSTR1_LOCAL,
- CFG_PCIMSK1_MASK, CFG_PCI_MSTR_MEM_LOCAL, CFG_PCI_MSTR_MEM_BUS,
- CFG_CPU_PCI_MEM_START, CFG_PCI_MSTR_MEM_SIZE, CFG_POCMR0_MASK_ATTRIB,
- CFG_PCI_MSTR_MEMIO_LOCAL, CFG_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START,
- CFG_PCI_MSTR_MEMIO_SIZE, CFG_POCMR1_MASK_ATTRIB, CFG_PCI_MSTR_IO_LOCAL,
- CFG_PCI_MSTR_IO_BUS, CFG_CPU_PCI_IO_START, CFG_PCI_MSTR_IO_SIZE,
- CFG_POCMR2_MASK_ATTRIB: (MPC826x only)
+- CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB,
+ CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL,
+ CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS,
+ CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB,
+ CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START,
+ CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
+ CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
+ CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
- CONFIG_SPD_EEPROM
@@ -2552,16 +2552,16 @@
SPD_EEPROM_ADDRESS
I2C address of the SPD EEPROM
-- CFG_SPD_BUS_NUM
+- CONFIG_SYS_SPD_BUS_NUM
If SPD EEPROM is on an I2C bus other than the first
one, specify here. Note that the value must resolve
to something your driver can deal with.
-- CFG_83XX_DDR_USES_CS0
+- CONFIG_SYS_83XX_DDR_USES_CS0
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.
-- CFG_83XX_DDR_USES_CS0
+- CONFIG_SYS_83XX_DDR_USES_CS0
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.
@@ -2861,7 +2861,7 @@
for use by the bootm command. See also "bootm_size"
environment variable. Address defined by "bootm_low" is
also the base of the initial memory mapping for the Linux
- kernel -- see the description of CFG_BOOTMAPSZ.
+ kernel -- see the description of CONFIG_SYS_BOOTMAPSZ.
bootm_size - Memory range available for image processing in the bootm
command can be restricted. This variable is given as
@@ -2909,7 +2909,7 @@
is usually what you want since it allows for
maximum initrd size. If for some reason you want to
make sure that the initrd image is loaded below the
- CFG_BOOTMAPSZ limit, you can set this environment
+ CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
variable to a value of "no" or "off" or "0".
Alternatively, you can set it to a maximum upper
address to use (U-Boot will still check that it
@@ -3183,7 +3183,7 @@
include/asm-ppc/tqm8xx.h) includes the same definition of the Board
Information structure as we define in include/asm-<arch>/u-boot.h,
and make sure that your definition of IMAP_ADDR uses the same value
-as your U-Boot configuration in CFG_IMMR.
+as your U-Boot configuration in CONFIG_SYS_IMMR.
Configuring the Linux kernel:
@@ -3730,7 +3730,7 @@
cause you grief during the initial boot! It is frequently not
used.
- CFG_INIT_RAM_ADDR should be somewhere that won't interfere
+ CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
with your processor/board/system design. The default value
you will find in any recent u-boot distribution in
walnut.h should work for you. I'd set it to a value larger
@@ -3827,7 +3827,7 @@
TQM8xxL modules this is the range 0x40000000 ... 0x4001FFFF). After
booting and sizing and initializing DRAM, the code relocates itself
to the upper end of DRAM. Immediately below the U-Boot code some
-memory is reserved for use by malloc() [see CFG_MALLOC_LEN
+memory is reserved for use by malloc() [see CONFIG_SYS_MALLOC_LEN
configuration setting]. Below that, a structure with global Board
Info data is placed, followed by the stack (growing downward).