| commit | 6cd7134e7309a53f015a402e52e5863f29e366fd | [log] [tgz] |
|---|---|---|
| author | Ley Foon Tan <ley.foon.tan@intel.com> | Fri Mar 22 01:24:01 2019 +0800 |
| committer | Marek Vasut <marex@denx.de> | Wed Apr 17 22:20:17 2019 +0200 |
| tree | 826c653c4a9efe0076dca4f88fc5217ad8413afc | |
| parent | b6f7ee5d1f980ffa63e22749e2deae6caa57227e [diff] |
ddr: altera: Stratix10: Add multi-banks DRAM size check Stratix 10 maps dram from 0 to 128GB. There is a 2GB hole in the memory for peripherals and other IO from 2GB to 4GB. However the dram controller ignores upper address bits for smaller dram configurations. Example: a 4GB dram maps to multiple locations, every 4GB on the address. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>