tree 4fd174441b93ae79f561109b68f714bfa7d6227d
parent 2a9cf320afb051f40a4bbb98aa9a6b1a94332d27
author Michael Walle <michael@walle.cc> 1653944527 +0200
committer Peng Fan <peng.fan@nxp.com> 1655711565 +0800

board: sl28: set CPO value

With a 8GiB memory board, it seems that the "very unlikely event" of a
DDR initialization with non-optimal values are not really that unlikely.
It happens in about every other reboot. As described in erratum
A-009942, preset the DEBUG_28 register with an optimal value. The value
iself depends on the memory configuration of the board, but the used
value seems to work well for all variants.

Signed-off-by: Michael Walle <michael@walle.cc>