tree 95d3a04d591215ed8bcb92e5e765d4ff411c9cce
parent 94f0003f654fb490ee4be2e2aef1811835f1fb8d
author Fabio Estevam <festevam@gmail.com> 1332308565 +0000
committer Stefano Babic <sbabic@denx.de> 1332834077 +0200

mx53: Make PLL2 to be the parent of UART clock

Change the parent UART clock to be PLL2, so that U-boot can also boot
a Freescale 2.6.35 kernel for mx53.

FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid
conflicts with IPU clocks, so that the video resolution can be changed
without affecting the UART clock.

On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded
and this patch fixes this problem.

Tested on a mx53loco board booting a FSL kernel and also a mainline kernel.

Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>