tree 669eca4ca7d0e4d6d62ce480455d346f2b192f2f
parent f8cb101e1e3f5ee2007b78b6b12e24120385aeac
author York Sun <yorksun@freescale.com> 1426782626 -0700
committer York Sun <yorksun@freescale.com> 1429804553 -0700

drivers/ddr/fsl: Update DDR driver for DDR4

Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.

Signed-off-by: York Sun <yorksun@freescale.com>