diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index b75d4cc..d84622f 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -22,27 +22,27 @@
  * IFC Definitions
  */
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CFG_SYS_NOR0_CSPR_EXT	(0x0)
 #define CFG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
 #define CFG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
 
-#define CONFIG_SYS_NOR0_CSPR					\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+#define CFG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS)		| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY				\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+#define CFG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY)	| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR					\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)		| \
+#define CFG_SYS_NOR1_CSPR					\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS)		| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EARLY				\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
+#define CFG_SYS_NOR1_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
@@ -59,13 +59,13 @@
 				FTIM2_NOR_TWPH(0xe) | \
 				FTIM2_NOR_TWP(0x1c))
 #define CFG_SYS_NOR_FTIM3	0x04000000
-#define CONFIG_SYS_IFC_CCR	0x01000000
+#define CFG_SYS_IFC_CCR	0x01000000
 
 #ifndef SYS_NO_FLASH
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
-					 CONFIG_SYS_FLASH_BASE + 0x40000000}
+#define CFG_SYS_FLASH_BANKS_LIST	{ CFG_SYS_FLASH_BASE,\
+					 CFG_SYS_FLASH_BASE + 0x40000000}
 #endif
 #endif
 
@@ -101,7 +101,7 @@
 #define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
-#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define CFG_SYS_I2C_FPGA_ADDR	0x66
 #define QIXIS_LBMAP_SWITCH		6
 #define QIXIS_QMAP_MASK			0xe0
 #define QIXIS_QMAP_SHIFT		5
@@ -127,8 +127,8 @@
 #define QIXIS_SDID_MASK			0x07
 #define QIXIS_ESDHC_NO_ADAPTER		0x7
 
-#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
-#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+#define CFG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CFG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 					| CSPR_PORT_SIZE_8 \
 					| CSPR_MSEL_GPCM \
 					| CSPR_V)
@@ -139,9 +139,9 @@
 
 #define SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(0)
+#define CFG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(0)
 #else
-#define CONFIG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(12)
+#define CFG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(12)
 #endif
 /* QIXIS Timing parameters*/
 #define SYS_FPGA_CS_FTIM0	(FTIM0_GPCM_TACSE(0x0e) | \
@@ -155,102 +155,102 @@
 #define SYS_FPGA_CS_FTIM3	0x0
 
 #ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CFG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK1_FINAL		CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK3		SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0		SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS3_FTIM1		SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS3_FTIM2		SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR1_CSPR_EARLY
+#define CFG_SYS_CSPR1_FINAL		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK_EARLY
+#define CFG_SYS_AMASK1_FINAL		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK3		SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0		SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS3_FTIM1		SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS3_FTIM2		SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
 #else
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR2_FINAL		SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK2		SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS2_FTIM0		SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR2_FINAL		SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK2		SYS_FPGA_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS2_FTIM0		SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS2_FTIM1		SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS2_FTIM2		SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS2_FTIM3		SYS_FPGA_CS_FTIM3
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CFG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK1_FINAL		CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK3		SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0		SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS3_FTIM1		SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS3_FTIM2		SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR1_CSPR_EARLY
+#define CFG_SYS_CSPR1_FINAL		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK_EARLY
+#define CFG_SYS_AMASK1_FINAL		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK3		SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0		SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS3_FTIM1		SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS3_FTIM2		SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
 #endif
 #endif
 
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
 /*
  * I2C bus multiplexer
@@ -281,7 +281,7 @@
 * RTC configuration
 */
 #define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
+#define CFG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 
 #ifdef CONFIG_FSL_DSPI
 #if !defined(CONFIG_TFABOOT) && \