| commit | 64e8482f1c94ab6e1fb4837a8744ca8a156c507e | [log] [tgz] |
|---|---|---|
| author | Zong Li <zong.li@sifive.com> | Thu Dec 14 14:09:36 2023 +0000 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Wed Dec 27 17:28:57 2023 +0800 |
| tree | 6a9e59f3b1672adb4266a19a8520cede20921cbb | |
| parent | 4b151562bb8e54160adedbc6a1c0c749c00a2f84 [diff] |
cache: add sifive private L2 cache driver This driver is currently responsible for enabling the clock gating feature of SiFive pre core's private L2 cache. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>