| commit | 639200f6a0dcfe67e4c923b6108703e192946388 | [log] [tgz] |
|---|---|---|
| author | Paul Burton <paul.burton@imgtec.com> | Wed Sep 21 11:18:59 2016 +0100 |
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | Wed Sep 21 15:04:04 2016 +0200 |
| tree | 2c086874eab5ecabfe7b0aac920d8608d5fbbc72 | |
| parent | d608254b0aa23607df1dcb5a7ca07de9a8ec9bb0 [diff] |
MIPS: Ensure cache ops complete in mips_cache_reset Ensure that cache operations complete before returning from mips_cache_reset by placing a completion barrier (sync instruction) before the return. Without this there is no guarantee that the cache ops will complete before any subsequent memory accesses, since they are indexed cache ops & thus not implicitly ordered with memory accesses. Signed-off-by: Paul Burton <paul.burton@imgtec.com>