commit 625ab11fdae3daf346647aaba59abee804e34589
author David Wu <david.wu@rock-chips.com> Tue Apr 16 21:55:26 2019 +0800
committer Kever Yang <kever.yang@rock-chips.com> Wed May 08 17:34:12 2019 +0800
tree 59fe14af76986ea4cb065b90c88127d626b7c982
parent cd8f00ce08102d2dbb350c76bbb53f7b0f804b7d

pinctrl: rockchip: Split the common set_drive() func into per Soc

As the common set_mux func(), implement the feature at the own file
for each Soc.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

drivers/pinctrl/rockchip/pinctrl-rk3328.c

diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c
index de21fba..0ad5669 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c
@@ -191,6 +191,30 @@
 	*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
 }
 
+static int rk3328_set_drive(struct rockchip_pin_bank *bank,
+			    int pin_num, int strength)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u32 data;
+	u8 bit;
+	int type = bank->drv[pin_num / 8].drv_type;
+
+	rk3328_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	ret = rockchip_translate_drive_value(type, strength);
+	if (ret < 0) {
+		debug("unsupported driver strength %d\n", strength);
+		return ret;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
 #define RK3328_SCHMITT_BITS_PER_PIN		1
 #define RK3328_SCHMITT_PINS_PER_REG		16
 #define RK3328_SCHMITT_BANK_STRIDE		8
@@ -239,7 +263,7 @@
 	.niomux_routes		= ARRAY_SIZE(rk3328_mux_route_data),
 	.set_mux		= rk3328_set_mux,
 	.pull_calc_reg		= rk3328_calc_pull_reg_and_bit,
-	.drv_calc_reg		= rk3328_calc_drv_reg_and_bit,
+	.set_drive		= rk3328_set_drive,
 	.schmitt_calc_reg	= rk3328_calc_schmitt_reg_and_bit,
 };