Fix coding style issues; update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
diff --git a/board/ms7722se/Makefile b/board/ms7722se/Makefile
index 94469f7..6dec013 100644
--- a/board/ms7722se/Makefile
+++ b/board/ms7722se/Makefile
@@ -1,7 +1,7 @@
#
# Copyright (C) 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
+#
# Copyright (C) 2007
# Kenati Technologies, Inc.
#
diff --git a/board/ms7722se/config.mk b/board/ms7722se/config.mk
index e4ca55a..4797d6f 100644
--- a/board/ms7722se/config.mk
+++ b/board/ms7722se/config.mk
@@ -29,4 +29,3 @@
#
TEXT_BASE = 0x8FFC0000
-
diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S
index e0d519c..2024e27 100644
--- a/board/ms7722se/lowlevel_init.S
+++ b/board/ms7722se/lowlevel_init.S
@@ -1,7 +1,7 @@
/*
* Copyright (C) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
+ *
* Copyright (C) 2007
* Kenati Technologies, Inc.
*
@@ -52,19 +52,19 @@
mov.l r0, @r1
mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
- mov.l MSTPCR0_D, r0 !
+ mov.l MSTPCR0_D, r0 !
mov.l r0, @r1
mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
- mov.l MSTPCR2_D, r0 !
+ mov.l MSTPCR2_D, r0 !
mov.l r0, @r1
- mov.l SBSCR_A, r1 !
- mov.w SBSCR_D, r0 !
+ mov.l SBSCR_A, r1 !
+ mov.w SBSCR_D, r0 !
mov.w r0, @r1
- mov.l PSCR_A, r1 !
- mov.w PSCR_D, r0 !
+ mov.l PSCR_A, r1 !
+ mov.w PSCR_D, r0 !
mov.w r0, @r1
! mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
@@ -80,7 +80,7 @@
mov.w r0, @r1
mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
- mov.l FRQCR_D, r0 !
+ mov.l FRQCR_D, r0 !
mov.l r0, @r1
mov.l CCR_A, r1 ! Address of Cache Control Register
@@ -200,11 +200,9 @@
rts
mov #0, r0
-
-
.align 2
-CCR_A: .long CCR
+CCR_A: .long CCR
MMUCR_A: .long MMUCR
MSTPCR0_A: .long MSTPCR0
MSTPCR2_A: .long MSTPCR2
@@ -223,7 +221,7 @@
PSELA_A: .long 0xa405014E
PSELA_D: .word 0x0A10
- .align 2
+ .align 2
DRVCR_A: .long 0xa405018A
DRVCR_D: .word 0x0554
diff --git a/board/ms7722se/ms7722se.c b/board/ms7722se/ms7722se.c
index 3eeb1b7..0d3d55c 100644
--- a/board/ms7722se/ms7722se.c
+++ b/board/ms7722se/ms7722se.c
@@ -4,7 +4,7 @@
*
* Copyright (C) 2007
* Kenati Technologies, Inc.
- *
+ *
* board/ms7722se/ms7722se.c
*
* This program is free software; you can redistribute it and/or
@@ -57,4 +57,3 @@
{
*((volatile unsigned short *) LED_BASE) = (value & 0xFF);
}
-
diff --git a/board/ms7722se/u-boot.lds b/board/ms7722se/u-boot.lds
index 24c2184..692bc62 100644
--- a/board/ms7722se/u-boot.lds
+++ b/board/ms7722se/u-boot.lds
@@ -32,19 +32,19 @@
Although size of SDRAM can be either 16 or 32 MBytes,
we assume 16 MBytes (ie ignore upper half if the full
32 MBytes is present).
-
+
NOTE: This address must match with the definition of
TEXT_BASE in config.mk (in this directory).
-
+
*/
. = 0x8C000000 + (64*1024*1024) - (256*1024);
-
+
PROVIDE (reloc_dst = .);
PROVIDE (_ftext = .);
PROVIDE (_fcode = .);
PROVIDE (_start = .);
-
+
.text :
{
cpu/sh4/start.o (.text)
@@ -89,7 +89,7 @@
}
PROVIDE (__u_boot_cmd_end = .);
- PROVIDE (reloc_dst_end = .);
+ PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
PROVIDE (bss_start = .);
@@ -103,4 +103,3 @@
PROVIDE (_end = .);
}
-
diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S
index 360c9fa..d3e3cd5 100644
--- a/board/ms7750se/lowlevel_init.S
+++ b/board/ms7750se/lowlevel_init.S
@@ -2,8 +2,8 @@
modified from SH-IPL+g
Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
- Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
-
+ Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
+
Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
* See file CREDITS for list of people who contributed to this
@@ -102,7 +102,7 @@
mov #0,r0
mov.b r0,@r1
- ! Do you need PCMCIA setting?
+ ! Do you need PCMCIA setting?
! If so, please add the lines here...
mov.l RTCNT_A,r1 /* RTCNT Address */
@@ -165,7 +165,7 @@
WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
WCR3_A: .long WCR3
WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
-RTCSR_A: .long RTCSR
+RTCSR_A: .long RTCSR
RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */
RTCNT_A: .long RTCNT
RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
@@ -177,4 +177,3 @@
MCR_D2: .long MCR_D2_VALUE
RFCR_A: .long RFCR
RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
-
diff --git a/board/ms7750se/ms7750se.c b/board/ms7750se/ms7750se.c
index 1ae9dd1..d2d824c 100644
--- a/board/ms7750se/ms7750se.c
+++ b/board/ms7750se/ms7750se.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2007
+ * Copyright (C) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* See file CREDITS for list of people who contributed to this
diff --git a/board/ms7750se/u-boot.lds b/board/ms7750se/u-boot.lds
index 24c2184..692bc62 100644
--- a/board/ms7750se/u-boot.lds
+++ b/board/ms7750se/u-boot.lds
@@ -32,19 +32,19 @@
Although size of SDRAM can be either 16 or 32 MBytes,
we assume 16 MBytes (ie ignore upper half if the full
32 MBytes is present).
-
+
NOTE: This address must match with the definition of
TEXT_BASE in config.mk (in this directory).
-
+
*/
. = 0x8C000000 + (64*1024*1024) - (256*1024);
-
+
PROVIDE (reloc_dst = .);
PROVIDE (_ftext = .);
PROVIDE (_fcode = .);
PROVIDE (_start = .);
-
+
.text :
{
cpu/sh4/start.o (.text)
@@ -89,7 +89,7 @@
}
PROVIDE (__u_boot_cmd_end = .);
- PROVIDE (reloc_dst_end = .);
+ PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
PROVIDE (bss_start = .);
@@ -103,4 +103,3 @@
PROVIDE (_end = .);
}
-