keystone2: use EFUSE_BOOTROM information to configure PLLs
This patch reads EFUSE_BOOTROM register to see the maximum supported
clock for CORE and TETRIS PLLs and configure them accordingly.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index a369d6b..6fb3d21 100644
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emac_defs.h>
@@ -28,12 +29,23 @@
[rp1_clk] = 123456789
};
-static struct pll_init_data pll_config[] = {
- CORE_PLL_1228,
- PASS_PLL_983,
- TETRIS_PLL_1200,
+static struct pll_init_data core_pll_config[] = {
+ CORE_PLL_799,
+ CORE_PLL_999,
+ CORE_PLL_1200,
};
+static struct pll_init_data tetris_pll_config[] = {
+ TETRIS_PLL_800,
+ TETRIS_PLL_1000,
+ TETRIS_PLL_1200,
+ TETRIS_PLL_1350,
+ TETRIS_PLL_1400,
+};
+
+static struct pll_init_data pa_pll_config =
+ PASS_PLL_983;
+
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
{
@@ -75,7 +87,16 @@
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
- init_plls(ARRAY_SIZE(pll_config), pll_config);
+ int speed;
+
+ speed = get_max_dev_speed();
+ init_pll(&core_pll_config[speed]);
+
+ init_pll(&pa_pll_config);
+
+ speed = get_max_arm_speed();
+ init_pll(&tetris_pll_config[speed]);
+
return 0;
}
#endif