tree f9207d7c9eec2b8916d2146bce78da7d0dfd1729
parent f69b0653acf5482a94fa1ec9542165914e30e50c
author Michael Langer <michael.langer@de.bosch.com> 1339645473 +0000
committer Albert ARIBAUD <albert.u.boot@aribaud.net> 1341662849 +0200

i.MX6 USDHC: Use the ESDHC clock

The commit "i.mx: fsl_esdhc: add the i.mx6q support" (4692708d) introduces
support for the i.MX6Q MMC host controller USDHC.

MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock
of the ESDHC IP found in < i.MX6 silicon. However, the default clock for the USDHC
IP found in i.MX6 is 200MHz (MXC_ESDHC_CLK). This difference will cause a 3 times
higher clock on SD_CLK than expected (see fsl_esdh.c -> set_sysctl()).

Signed-off-by: Michael Langer <michael.langer@de.bosch.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <r64343@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>