mpc8323erdb: Improve the system performance
The following changes are based on kernel UCC ethernet performance:
1. Make the CSB bus pipeline depth as 4, and enable the repeat mode
2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT
switch to enable this setting.
The following changes are based on the App Note AN3369 and
verified to improve memory latency using LMbench:
3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting
previously.
5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on
Twr=15ns, and this was already the setting in DDR_MODE)
6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
Trp=15ns)
7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
Tras=40ns)
8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
Trcd=15ns)
9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on
Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based
on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
on CL=3 and WL=2).
Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index e643037..fba5b02 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -79,6 +79,12 @@
(CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
#endif
+#ifdef CFG_SPCR_OPT
+ /* Optimize transactions between CSB and other devices */
+ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
+ (CFG_SPCR_OPT << SPCR_OPT_SHIFT);
+#endif
+
#ifdef CFG_SPCR_TSECEP
/* all eTSEC's Emergency priority */
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |