arm: am33xx: Fix MPU opp selection
Update MPU frequencies and voltages as per the latest
DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4.
Below is the consolidated data:
MPU values for PG 2.0 and later(Package ZCZ and ZCE):
-------------------------------------------------------
| | ZCZ | ZCE |
|-------------------------------------------------------|
| | VDD[V] | ARM [MHz] | VDD[V] | ARM [MHz] |
|-------|----------|------------|----------|------------|
| NITRO | 1.325 | 1000 | NA | NA |
|-------|----------|------------|----------|------------|
| TURBO | 1.26 | 800 | NA | NA |
|-------|----------|------------|----------|------------|
|OPP120 | 1.20 | 720 | NA | NA |
|-------|----------|------------|----------|------------|
|OPP100 | 1.10 | 600 | 1.10 | 600 |
|-------|----------|------------|----------|------------|
| OPP50 | 0.95 | 300 | 0.95 | 300 |
-------------------------------------------------------
There is no eFuse blown on PG1.0 Silicons due to which there is
no way to detect the maximum frequencies supported. So default
to OPP100 for which both frequency and voltages are common on both
the packages.
[1] http://www.ti.com/lit/ds/symlink/am3356.pdf
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c
index e4fc461..58bfa5c 100644
--- a/arch/arm/mach-omap2/am33xx/sys_info.c
+++ b/arch/arm/mach-omap2/am33xx/sys_info.c
@@ -132,13 +132,21 @@
sil_rev = readl(&cdev->deviceid) >> 28;
- if (sil_rev == 1)
- /* PG 2.0, efuse may not be set. */
- return MPUPLL_M_800;
- else if (sil_rev >= 2) {
+ if (sil_rev == 0) {
+ /* No efuse in PG 1.0. Use max speed */
+ return MPUPLL_M_720;
+ } else if (sil_rev >= 1) {
/* Check what the efuse says our max speed is. */
- int efuse_arm_mpu_max_freq;
+ int efuse_arm_mpu_max_freq, package_type;
efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
+ package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
+ PACKAGE_TYPE_SHIFT;
+
+ /* PG 2.0, efuse may not be set. */
+ if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
+ PACKAGE_TYPE_RESERVED)
+ return MPUPLL_M_800;
+
switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
case AM335X_ZCZ_1000:
return MPUPLL_M_1000;
@@ -155,14 +163,14 @@
}
}
- /* PG 1.0 or otherwise unknown, use the PG1.0 max */
+ /* unknown, use the PG1.0 max */
return MPUPLL_M_720;
}
int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
{
- /* For PG2.1 and later, we have one set of values. */
- if (sil_rev >= 2) {
+ /* For PG2.0 and later, we have one set of values. */
+ if (sil_rev >= 1) {
switch (frequency) {
case MPUPLL_M_1000:
return TPS65910_OP_REG_SEL_1_3_2_5;
@@ -171,12 +179,13 @@
case MPUPLL_M_720:
return TPS65910_OP_REG_SEL_1_2_0;
case MPUPLL_M_600:
+ case MPUPLL_M_500:
case MPUPLL_M_300:
- return TPS65910_OP_REG_SEL_1_1_3;
+ return TPS65910_OP_REG_SEL_1_1_0;
}
}
- /* Default to PG1.0/PG2.0 values. */
- return TPS65910_OP_REG_SEL_1_1_3;
+ /* Default to PG1.0 values. */
+ return TPS65910_OP_REG_SEL_1_2_6;
}
#endif