commit 56db948b85aa7c03c79b2c796500de4523924a9d
author York Sun <york.sun@nxp.com> Mon Nov 05 18:02:09 2018 +0000
committer York Sun <york.sun@nxp.com> Thu Dec 06 14:37:19 2018 -0800
tree 66a4244e1f6382be7584687574284be3b92cb71b
parent 5a73ec6169d1db85eacc4ad2fc74dad92a846c9e

armv8: fsl-layerscape: Update parsing boot source

Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erratum workaround A010539 is enabled and RCW source is
cleared.

Signed-off-by: York Sun <york.sun@nxp.com>

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index ca632eb..36189f7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -693,23 +693,41 @@
 		}
 	}
 #endif
+
+	if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
+		src = BOOT_SOURCE_QSPI_NOR;
+
 	debug("%s: src 0x%x\n", __func__, src);
 	return src;
 }
 
 enum boot_src get_boot_src(void)
 {
-	u32 porsr1;
+	struct pt_regs regs;
+	u32 porsr1 = 0;
 
 #if defined(CONFIG_FSL_LSCH3)
 	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
-
-	porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 #elif defined(CONFIG_FSL_LSCH2)
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-
-	porsr1 = in_be32(&gur->porsr1);
 #endif
+
+	if (current_el() == 2) {
+		regs.regs[0] = SIP_SVC_RCW;
+
+		smc_call(&regs);
+		if (!regs.regs[0])
+			porsr1 = regs.regs[1];
+	}
+
+	if (current_el() == 3 || !porsr1) {
+#ifdef CONFIG_FSL_LSCH3
+		porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+#elif defined(CONFIG_FSL_LSCH2)
+		porsr1 = in_be32(&gur->porsr1);
+#endif
+	}
+
 	debug("%s: porsr1 0x%x\n", __func__, porsr1);
 
 	return __get_boot_src(porsr1);