commit 552ff8f1d9fccf57243a01afe6dbebb982867e20
author John Rigby <jcrigby@gmail.com> Mon Jan 25 23:12:56 2010 -0700
committer Tom Rix <Tom.Rix@windriver.com> Sun Mar 07 12:36:36 2010 -0600
tree 3f19fa8792bf08b97b26cdcd051dbb015ee95dad
parent e911c983f4a8d588f831806af37eb56c95512d5d

Add support for Freescale MX25 SOC

ARM926EJS core with MX31 peripherals.

Signed-off-by: John Rigby <jcrigby@gmail.com>
Earlier Version Signed-off-by: Wolfgang Denk <wd@denx.de>
CC: Fred Fan <fanyefeng@gmail.com>
CC: Tom <Tom.Rix@windriver.com>

cpu/arm926ejs/mx25/reset.c

diff --git a/cpu/arm926ejs/mx25/reset.c b/cpu/arm926ejs/mx25/reset.c
new file mode 100644
index 0000000..1e33150
--- /dev/null
+++ b/cpu/arm926ejs/mx25/reset.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let it time out
+ */
+void reset_cpu (ulong ignored)
+{
+	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
+	/* Disable watchdog and set Time-Out field to 0 */
+	writel (0x00000000, &regs->wcr);
+
+	/* Write Service Sequence */
+	writel (0x00005555, &regs->wsr);
+	writel (0x0000AAAA, &regs->wsr);
+
+	/* Enable watchdog */
+	writel (WCR_WDE, &regs->wcr);
+
+	while (1) ;
+}