Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 21fc03b..e6249f1 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -12,7 +12,7 @@
obj-y += cpu.o cp15.o
obj-y += syslib.o
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_SOCFPGA),)
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
index 8b6e108..7524ef9 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -7,7 +7,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
fpga_manager.o
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
deleted file mode 100644
index b4d0627..0000000
--- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-/* Set up the platform, once the cpu has been initialized */
-.globl lowlevel_init
-lowlevel_init:
-
- /* Remap */
-#ifdef CONFIG_SPL_BUILD
- /*
- * SPL : configure the remap (L3 NIC-301 GPV)
- * so the on-chip RAM at lower memory instead ROM.
- */
- ldr r0, =SOCFPGA_L3REGS_ADDRESS
- mov r1, #0x19
- str r1, [r0]
-#else
- /*
- * U-Boot : configure the remap (L3 NIC-301 GPV)
- * so the SDRAM at lower memory instead on-chip RAM.
- */
- ldr r0, =SOCFPGA_L3REGS_ADDRESS
- mov r1, #0x2
- str r1, [r0]
-
- /* Private components security */
-
- /*
- * U-Boot : configure private timer, global timer and cpu
- * component access as non secure for kernel stage (as required
- * by kernel)
- */
- mrc p15,4,r0,c15,c0,0
- add r1, r0, #0x54
- ldr r2, [r1]
- orr r2, r2, #0xff
- orr r2, r2, #0xf00
- str r2, [r1]
-#endif /* #ifdef CONFIG_SPL_BUILD */
- mov pc, lr
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index 25921e7..45b352b 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -113,3 +113,27 @@
clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) |
(1 << RSTMGR_PERMODRST_SPIM1_LSB));
}
+
+/* Bring UART0 out of reset. */
+void socfpga_uart0_enable(void)
+{
+ const void *reset = &reset_manager_base->per_mod_reset;
+
+ clrbits_le32(reset, 1 << RSTMGR_PERMODRST_UART0_LSB);
+}
+
+/* Bring SDRAM controller out of reset. */
+void socfpga_sdram_enable(void)
+{
+ const void *reset = &reset_manager_base->per_mod_reset;
+
+ clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SDR_LSB);
+}
+
+/* Bring OSC1 timer out of reset. */
+void socfpga_osc1timer_enable(void)
+{
+ const void *reset = &reset_manager_base->per_mod_reset;
+
+ clrbits_le32(reset, 1 << RSTMGR_PERMODRST_OSC1TIMER0_LSB);
+}
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 6a8c15d..f994658 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/io.h>
+#include <asm/pl310.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
#include <image.h>
@@ -15,9 +16,13 @@
#include <asm/arch/freeze_controller.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/scan_manager.h>
+#include <asm/arch/sdram.h>
DECLARE_GLOBAL_DATA_PTR;
+static struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
#define MAIN_VCO_BASE ( \
(CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
@@ -43,6 +48,31 @@
CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
)
+void board_init_f(ulong dummy)
+{
+ struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+ unsigned long reg;
+ /*
+ * First C code to run. Clear fake OCRAM ECC first as SBE
+ * and DBE might triggered during power on
+ */
+ reg = readl(&sysmgr_regs->eccgrp_ocram);
+ if (reg & SYSMGR_ECC_OCRAM_SERR)
+ writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
+ &sysmgr_regs->eccgrp_ocram);
+ if (reg & SYSMGR_ECC_OCRAM_DERR)
+ writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
+ &sysmgr_regs->eccgrp_ocram);
+
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* Remap SDRAM to 0x0 */
+ writel(0x1, &pl310->pl310_addr_filter_start);
+
+ board_init_r(NULL, 0);
+}
+
u32 spl_boot_device(void)
{
return BOOT_DEVICE_RAM;
@@ -53,6 +83,7 @@
*/
void spl_board_init(void)
{
+ unsigned long sdram_size;
#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
cm_config_t cm_default_cfg = {
/* main group */
@@ -144,10 +175,19 @@
/* freeze all IO banks */
sys_mgr_frzctrl_freeze_req();
+ socfpga_sdram_enable();
+ socfpga_uart0_enable();
+ socfpga_osc1timer_enable();
+
+ timer_init();
+
debug("Reconfigure Clock Manager\n");
/* reconfigure the PLLs */
cm_basic_init(&cm_default_cfg);
+ /* Enable bootrom to configure IOs. */
+ sysmgr_enable_warmrstcfgio();
+
/* configure the IOCSR / IO buffer settings */
if (scan_mgr_configure_iocsr())
hang();
@@ -165,4 +205,25 @@
/* enable console uart printing */
preloader_console_init();
+
+ if (sdram_mmr_init_full(0xffffffff) != 0) {
+ puts("SDRAM init failed.\n");
+ hang();
+ }
+
+ debug("SDRAM: Calibrating PHY\n");
+ /* SDRAM calibration */
+ if (sdram_calibration_full() == 0) {
+ puts("SDRAM calibration failed.\n");
+ hang();
+ }
+
+ sdram_size = sdram_calculate_size();
+ debug("SDRAM: %ld MiB\n", sdram_size >> 20);
+
+ /* Sanity check ensure correct SDRAM size specified */
+ if (get_ram_size(0, sdram_size) != sdram_size) {
+ puts("SDRAM size check failed!\n");
+ hang();
+ }
}
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c
index 11f7bad..8126e0d 100644
--- a/arch/arm/cpu/armv7/socfpga/system_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -66,3 +66,12 @@
populate_sysmgr_fpgaintf_module();
}
+
+/*
+ * This bit allows the bootrom to configure the IOs after a warm reset.
+ */
+void sysmgr_enable_warmrstcfgio(void)
+{
+ setbits_le32(&sysmgr_regs->romcodegrp_ctrl,
+ SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
+}
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts
index 4e529a1..1b86897 100644
--- a/arch/arm/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -25,6 +25,10 @@
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
+
+ spi0 = "/spi@ff705000"; /* QSPI */
+ spi1 = "/spi@fff00000";
+ spi2 = "/spi@fff01000";
};
regulator_3_3v: 3-3-v-regulator {
@@ -72,3 +76,23 @@
&usb1 {
status = "okay";
};
+
+&qspi {
+ status = "okay";
+
+ flash0: n25q00@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00";
+ reg = <0>; /* chip select */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ page-size = <256>;
+ block-size = <16>; /* 2^16, 64KB */
+ read-delay = <4>; /* delay value in read data capture register */
+ tshsl-ns = <50>;
+ tsd2d-ns = <50>;
+ tchsh-ns = <4>;
+ tslch-ns = <4>;
+ };
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 8e1f88c..0b300b9 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -25,6 +25,10 @@
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
+
+ spi0 = "/spi@ff705000"; /* QSPI */
+ spi1 = "/spi@fff00000";
+ spi2 = "/spi@fff01000";
};
regulator_3_3v: 3-3-v-regulator {
@@ -77,3 +81,23 @@
&usb1 {
status = "okay";
};
+
+&qspi {
+ status = "okay";
+
+ flash0: n25q00@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00";
+ reg = <0>; /* chip select */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ page-size = <256>;
+ block-size = <16>; /* 2^16, 64KB */
+ read-delay = <4>; /* delay value in read data capture register */
+ tshsl-ns = <50>;
+ tsd2d-ns = <50>;
+ tchsh-ns = <4>;
+ tslch-ns = <4>;
+ };
+};
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 034135b..d63a285 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -15,6 +15,9 @@
void socfpga_emac_reset(int enable);
void socfpga_watchdog_reset(void);
void socfpga_spim_enable(void);
+void socfpga_uart0_enable(void);
+void socfpga_sdram_enable(void);
+void socfpga_osc1timer_enable(void);
struct socfpga_reset_manager {
u32 status;
@@ -36,7 +39,10 @@
#define RSTMGR_PERMODRST_EMAC0_LSB 0
#define RSTMGR_PERMODRST_EMAC1_LSB 1
#define RSTMGR_PERMODRST_L4WD0_LSB 6
+#define RSTMGR_PERMODRST_OSC1TIMER0_LSB 8
+#define RSTMGR_PERMODRST_UART0_LSB 16
#define RSTMGR_PERMODRST_SPIM0_LSB 18
#define RSTMGR_PERMODRST_SPIM1_LSB 19
+#define RSTMGR_PERMODRST_SDR_LSB 29
#endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/sdram.h b/arch/arm/include/asm/arch-socfpga/sdram.h
new file mode 100644
index 0000000..4f6489d
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/sdram.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * FIXME: This file contains temporary stub functions and is here
+ * only until these functions are properly merged into
+ * mainline.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_SDRAM_H__
+#define __ARCH_SDRAM_H__
+
+/* function declaration */
+inline unsigned long sdram_calculate_size(void) { return 0; }
+inline unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) { return 0; }
+inline int sdram_calibration_full(void) { return 0; }
+
+#endif /* __ARCH_SDRAM_H__ */
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h
index 071ec4f..51d9815 100644
--- a/arch/arm/include/asm/arch-socfpga/system_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -10,6 +10,7 @@
#ifndef __ASSEMBLY__
void sysmgr_pinmux_init(void);
+void sysmgr_enable_warmrstcfgio(void);
/* declaration for handoff table type */
extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
diff --git a/board/altera/socfpga/pinmux_config.c b/board/altera/socfpga/pinmux_config.c
index 61cdc73..7e7a184 100644
--- a/board/altera/socfpga/pinmux_config.c
+++ b/board/altera/socfpga/pinmux_config.c
@@ -54,8 +54,8 @@
2, /* GENERALIO14 */
0, /* GENERALIO15 */
0, /* GENERALIO16 */
- 0, /* GENERALIO17 */
- 0, /* GENERALIO18 */
+ 2, /* GENERALIO17 */
+ 2, /* GENERALIO18 */
0, /* GENERALIO19 */
0, /* GENERALIO20 */
0, /* GENERALIO21 */
diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h
index 8130fa4..7cd25df 100644
--- a/board/altera/socfpga/pll_config.h
+++ b/board/altera/socfpga/pll_config.h
@@ -36,7 +36,7 @@
/* Peripheral PLL */
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)
/*
* To tell where is the VCOs source:
* 0 = EOSC1
diff --git a/board/altera/socfpga/socfpga.c b/board/altera/socfpga/socfpga.c
index 20d2216..a1dbc49 100644
--- a/board/altera/socfpga/socfpga.c
+++ b/board/altera/socfpga/socfpga.c
@@ -18,6 +18,8 @@
DECLARE_GLOBAL_DATA_PTR;
+void s_init(void) {}
+
/*
* Miscellaneous platform dependent initialisations
*/
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index c4c112c..357a335 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -35,3 +35,19 @@
sandbox,filename = "spi.bin";
};
};
+
+config DESIGNWARE_SPI
+ bool "Designware SPI driver"
+ depends on DM_SPI
+ help
+ Enable the Designware SPI driver. This driver can be used to
+ access the SPI NOR flash on platforms embedding this Designware
+ IP core.
+
+config CADENCE_QSPI
+ bool "Cadence QSPI driver"
+ depends on DM_SPI
+ help
+ Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
+ used to access the SPI NOR flash on platforms embedding this
+ Cadence IP core.
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 1ecd56f..41bb52b 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -40,7 +40,7 @@
#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
+#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
@@ -292,6 +292,7 @@
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024)
+#define CONFIG_SPL_MAX_SIZE (64 * 1024)
#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
#define CONFIG_CRC32_VERIFY
@@ -304,6 +305,11 @@
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
+/*
+ * Stack setup
+ */
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_PARTITIONS
#endif