x86: Move common CPU code to its own place
Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index f96dc2b..e72ff2a 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -332,8 +332,6 @@
#define SPI_FREQ_SWSEQ 0x3893
#define SPI_DESC_COMP0 0x38b0
#define SPI_FREQ_WR_ERA 0x38b4
-#define SOFT_RESET_CTRL 0x38f4
-#define SOFT_RESET_DATA 0x38f8
#define DIR_ROUTE(a, b, c, d) \
(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h
new file mode 100644
index 0000000..562de3e
--- /dev/null
+++ b/arch/x86/include/asm/cpu_common.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_CPU_COMMON_H
+#define __ASM_CPU_COMMON_H
+
+#define IA32_PERF_CTL 0x199
+
+/**
+ * cpu_common_init() - Set up common CPU init
+ *
+ * This reports BIST failure, enables the LAPIC, updates microcode, enables
+ * the upper 128-bytes of CROM RAM, probes the northbridge, PCH, LPC and SATA.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int cpu_common_init(void);
+
+/**
+ * cpu_set_flex_ratio_to_tdp_nominal() - Set up the maximum non-turbo rate
+ *
+ * If a change is needed, this function will do a soft reset so it takes
+ * effect.
+ *
+ * Some details are available here:
+ * http://forum.hwbot.org/showthread.php?t=76092
+ *
+ * @return 0 if OK, -ve on error
+ */
+int cpu_set_flex_ratio_to_tdp_nominal(void);
+
+#endif
diff --git a/arch/x86/include/asm/intel_regs.h b/arch/x86/include/asm/intel_regs.h
index 961d2bd..d2a6d26 100644
--- a/arch/x86/include/asm/intel_regs.h
+++ b/arch/x86/include/asm/intel_regs.h
@@ -12,8 +12,17 @@
#define MCH_BASE_SIZE 0x8000
#define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg))
+#define MCHBAR_PEI_VERSION 0x5034
+#define MCH_PKG_POWER_LIMIT_LO 0x59a0
+#define MCH_PKG_POWER_LIMIT_HI 0x59a4
+#define MCH_DDR_POWER_LIMIT_LO 0x58e0
+#define MCH_DDR_POWER_LIMIT_HI 0x58e4
+
/* Access the Root Complex Register Block */
#define RCB_BASE_ADDRESS 0xfed1c000
#define RCB_REG(reg) (RCB_BASE_ADDRESS + (reg))
+#define SOFT_RESET_CTRL 0x38f4
+#define SOFT_RESET_DATA 0x38f8
+
#endif