powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option
Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing
macros.
Signed-off-by: York Sun <york.sun@nxp.com>
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 80b3b74..77e3f83 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -914,7 +914,7 @@
#define CONFIG_SYS_FSL_SFP_VER_3_0
-#elif defined(CONFIG_PPC_C29X)
+#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_MAX_CPUS 1
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
@@ -955,7 +955,7 @@
#define CONFIG_SYS_FSL_DDRC_GEN3
#endif
-#if !defined(CONFIG_PPC_C29X)
+#if !defined(CONFIG_ARCH_C29X)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 74c2959..cef9da0 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2123,7 +2123,7 @@
#ifdef CONFIG_MPC8536
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
-#elif defined(CONFIG_PPC_C29X)
+#elif defined(CONFIG_ARCH_C29X)
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
& MPC85xx_PORDEVSR2_DDR_SPD_0) \
@@ -2175,7 +2175,7 @@
#elif defined(CONFIG_ARCH_BSC9132)
#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
-#elif defined(CONFIG_PPC_C29X)
+#elif defined(CONFIG_ARCH_C29X)
#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
#else
@@ -2193,7 +2193,7 @@
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
u32 pordbgmsr; /* POR debug mode status */
u32 pordevsr2; /* POR I/O device status 2 */
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
#endif
@@ -2344,7 +2344,7 @@
#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
#endif
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
#define MPC85xx_PMUXCR_SPI_MASK 0x00000300
#define MPC85xx_PMUXCR_SPI 0x00000000
#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
@@ -2964,7 +2964,7 @@
#endif
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
#else