diff --git a/board/atum8548/Makefile b/board/atum8548/Makefile
index e198062..bf0830c 100644
--- a/board/atum8548/Makefile
+++ b/board/atum8548/Makefile
@@ -29,7 +29,7 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o
+COBJS	:= $(BOARD).o law.o
 
 SOBJS	:= init.o
 
diff --git a/board/atum8548/init.S b/board/atum8548/init.S
index 654a569..7e161c1 100644
--- a/board/atum8548/init.S
+++ b/board/atum8548/init.S
@@ -30,11 +30,6 @@
 #include <config.h>
 #include <mpc85xx.h>
 
-#define LAWAR_TRGT_PCI1		0x00000000
-#define LAWAR_TRGT_PCI2		0x00100000
-#define LAWAR_TRGT_PCIE		0x00200000
-#define LAWAR_TRGT_DDR		0x00f00000
-
 /*
  * TLB0 and TLB1 Entries
  *
@@ -178,58 +173,3 @@
 
 2:
 	entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
- * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
- * 0xa000_0000	   0xbfff_ffff	   PCIe MEM		   512M
- * 0xc000_0000	   0xdfff_ffff	   PCI2 MEM		   512M
- * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
- * 0xe200_0000	   0xe10f_ffff	   PCI1 IO		   1M
- * 0xe280_0000	   0xe20f_ffff	   PCI2 IO		   1M
- * 0xe300_0000	   0xe30f_ffff	   PCIe IO		   1M
- * 0xf800_0000	   0xffff_ffff	   FLASH (boot bank)	   128M
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- *
- * LAW 0 is reserved for boot mapping
- */
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-law_entry:
-	entry_start
-
-	.long (4f-3f)/8
-3:
-	.long  0
-	.long  (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_1G)) & ~LAWAR_EN
-
-	.long	(CFG_PCI1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
-	.long	(CFG_PCI1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
-
-	.long	(CFG_PCI2_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
-	.long	(CFG_PCI2_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
-
-	.long	(CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
-	.long	(CFG_PCIE1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
-
-	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-	.long	(CFG_LBC_CACHE_BASE>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
-
-4:
-	entry_end
diff --git a/board/atum8548/law.c b/board/atum8548/law.c
new file mode 100644
index 0000000..3606cbb
--- /dev/null
+++ b/board/atum8548/law.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
+ * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
+ * 0xa000_0000	   0xbfff_ffff	   PCIe MEM		   512M
+ * 0xc000_0000	   0xdfff_ffff	   PCI2 MEM		   512M
+ * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
+ * 0xe200_0000	   0xe10f_ffff	   PCI1 IO		   1M
+ * 0xe280_0000	   0xe20f_ffff	   PCI2 IO		   1M
+ * 0xe300_0000	   0xe30f_ffff	   PCIe IO		   1M
+ * 0xf800_0000	   0xffff_ffff	   FLASH (boot bank)	   128M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+	SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1),
+	SET_LAW_ENTRY(4, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+	SET_LAW_ENTRY(6, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW_ENTRY(7, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW_ENTRY(8, CFG_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile
index 643fbc0..ef78942 100644
--- a/board/freescale/mpc8568mds/Makefile
+++ b/board/freescale/mpc8568mds/Makefile
@@ -29,7 +29,7 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o bcsr.o
+COBJS	:= $(BOARD).o bcsr.o law.o
 
 SOBJS	:= init.o
 
diff --git a/board/freescale/mpc8568mds/init.S b/board/freescale/mpc8568mds/init.S
index 2748c51..39819ab 100644
--- a/board/freescale/mpc8568mds/init.S
+++ b/board/freescale/mpc8568mds/init.S
@@ -176,61 +176,3 @@
 
 2:
 	entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- *0)   0x0000_0000   0x7fff_ffff     DDR                     2G
- *1)   0x8000_0000   0x9fff_ffff     PCI1 MEM                512MB
- *2)   0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
- *-)   0xe000_0000   0xe00f_ffff     CCSR                    1M
- *3)   0xe200_0000   0xe27f_ffff     PCI1 I/O                8M
- *4)   0xe280_0000   0xe2ff_ffff     PCIe I/O                8M
- *5)   0xc000_0000   0xdfff_ffff     SRIO                    512MB
- *6.a) 0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
- *6.b) 0xf800_0000   0xf800_7fff     BCSR                    32KB
- *6.c) 0xf800_8000   0xf800_ffff     PIB (CS4)		     32KB
- *6.d) 0xf801_0000   0xf801_7fff     PIB (CS5)		     32KB
- *6.e) 0xfe00_0000   0xffff_ffff     Flash                   32MB
- *
- *Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- *
- * The defines below are 1-off of the actual LAWAR0 usage.
- * So LAWAR3 define uses the LAWAR4 register in the ECM.
- */
-
-#define LAWBAR0 0
-#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
-
-#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
-
-#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR5	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
-#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR6	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-
-law_entry:
-	entry_start
-	.long (4f-3f)/8
-3:
-	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
-	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6
-4:
-	entry_end
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
new file mode 100644
index 0000000..b35bbcd
--- /dev/null
+++ b/board/freescale/mpc8568mds/law.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *0)   0x0000_0000   0x7fff_ffff     DDR                     2G
+ *1)   0x8000_0000   0x9fff_ffff     PCI1 MEM                512MB
+ *2)   0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
+ *-)   0xe000_0000   0xe00f_ffff     CCSR                    1M
+ *3)   0xe200_0000   0xe27f_ffff     PCI1 I/O                8M
+ *4)   0xe280_0000   0xe2ff_ffff     PCIe I/O                8M
+ *5)   0xc000_0000   0xdfff_ffff     SRIO                    512MB
+ *6.a) 0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
+ *6.b) 0xf800_0000   0xf800_7fff     BCSR                    32KB
+ *6.c) 0xf800_8000   0xf800_ffff     PIB (CS4)		     32KB
+ *6.d) 0xf801_0000   0xf801_7fff     PIB (CS5)		     32KB
+ *6.e) 0xfe00_0000   0xffff_ffff     Flash                   32MB
+ *
+ *Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(3, CFG_PCIE1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW_ENTRY(6, CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+	/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
+	SET_LAW_ENTRY(7, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/mpc8540eval/Makefile b/board/mpc8540eval/Makefile
index d649c60..c892247 100644
--- a/board/mpc8540eval/Makefile
+++ b/board/mpc8540eval/Makefile
@@ -25,10 +25,8 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o flash.o
-#COBJS	:= $(BOARD).o flash.o $(BOARD)_slave.o
+COBJS	:= $(BOARD).o flash.o law.o
 SOBJS	:= init.o
-#SOBJS	:=
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/mpc8540eval/init.S b/board/mpc8540eval/init.S
index a8ac3fb..adc5115 100644
--- a/board/mpc8540eval/init.S
+++ b/board/mpc8540eval/init.S
@@ -135,44 +135,3 @@
 	.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
   #endif
 	entry_end
-
-/* LAW(Local Access Window) configuration:
- * 0000_0000-0800_0000: DDR(128M) -or- larger
- * f000_0000-f3ff_ffff: PCI(256M)
- * f400_0000-f7ff_ffff: RapidIO(128M)
- * f800_0000-ffff_ffff: localbus(128M)
- *   f800_0000-fbff_ffff: LBC SDRAM(64M)
- *   fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
- *   fdf0_0000-fdff_ffff: CCSRBAR(1M)
- *   fe00_0000-ffff_ffff: Flash(32M)
- * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
- *       Window.
- * Note: If flash is 8M at default position(last 8M),no LAW needed.
- */
-
-#if !defined(CONFIG_SPD_EEPROM)
-#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR0 	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
-#else
-#define LAWBAR0 0
-#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-#endif
-
-#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#if !defined(CONFIG_RAM_AS_FLASH)
-#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
-#else
-#define LAWBAR2 0
-#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-#endif
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-law_entry:
-	entry_start
-	.long 0x03
-	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
-	entry_end
diff --git a/board/mpc8540eval/law.c b/board/mpc8540eval/law.c
new file mode 100644
index 0000000..4d603f0
--- /dev/null
+++ b/board/mpc8540eval/law.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(128M) -or- larger
+ * f000_0000-f3ff_ffff: PCI(256M)
+ * f400_0000-f7ff_ffff: RapidIO(128M)
+ * f800_0000-ffff_ffff: localbus(128M)
+ *   f800_0000-fbff_ffff: LBC SDRAM(64M)
+ *   fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
+ *   fdf0_0000-fdff_ffff: CCSRBAR(1M)
+ *   fe00_0000-ffff_ffff: Flash(32M)
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ *       Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+	SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#endif
+	SET_LAW_ENTRY(2, CFG_PCI_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
+#ifndef CONFIG_RAM_AS_FLASH
+	SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/tqm85xx/Makefile b/board/tqm85xx/Makefile
index cad7e1e..66f2830 100644
--- a/board/tqm85xx/Makefile
+++ b/board/tqm85xx/Makefile
@@ -25,9 +25,8 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o sdram.o
+COBJS	:= $(BOARD).o sdram.o law.o
 SOBJS	:= init.o
-#SOBJS	:=
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/tqm85xx/init.S b/board/tqm85xx/init.S
index dcb9386..1b25deb 100644
--- a/board/tqm85xx/init.S
+++ b/board/tqm85xx/init.S
@@ -176,47 +176,3 @@
 	.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 	entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
- * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
- * 0xc000_0000	   0xdfff_ffff	   RapidIO		   512M
- * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
- * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
- * 0xf800_0000	   0xf80f_ffff	   BCSR			   1M
- * 0xfe00_0000	   0xffff_ffff	   FLASH (boot bank)	   32M
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
-#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
-
-/*
- * Rapid IO at 0xc000_0000 for 512 M
- */
-#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-law_entry:
-	entry_start
-	.long 0x05
-	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
-	.long LAWBAR4,LAWAR4
-	entry_end
diff --git a/board/tqm85xx/law.c b/board/tqm85xx/law.c
new file mode 100644
index 0000000..1573e58
--- /dev/null
+++ b/board/tqm85xx/law.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
+ * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
+ * 0xc000_0000	   0xdfff_ffff	   RapidIO		   512M
+ * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
+ * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
+ * 0xf800_0000	   0xf80f_ffff	   BCSR			   1M
+ * 0xfe00_0000	   0xffff_ffff	   FLASH (boot bank)	   32M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+	SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index f7020b4..c14376e 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -63,6 +63,8 @@
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
 #define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
 
 #define CONFIG_SYS_CLK_FREQ	33000000
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 2868dcb..bf64f27 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -43,6 +43,8 @@
 #undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
 #define CONFIG_DDR_DLL                      /* possible DLL fix needed */
 
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
 /* Using Localbus SDRAM to emulate flash before we can program the flash,
  * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
  * Not availabe for EVAL board
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 2b089d9..a12d193 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -49,6 +49,7 @@
 /*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index f3b1a53..dd0654b 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -50,6 +50,8 @@
 #define CONFIG_CPM2		1	/* has CPM2			*/
 #endif
 
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
 /*
  * sysclk for MPC85xx
  *