pci: pci-uclass: Add multi entry support for memory regions
Enable PCI memory regions in ranges property to be of multiple entry.
This helps to add support for SoC's like OcteonTX/TX2 where every
peripheral is on PCI bus.
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 5e0a393..1c47a21 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -43,6 +43,16 @@
help
Enable PCI memory and I/O space resource allocation and assignment.
+config PCI_REGION_MULTI_ENTRY
+ bool "Enable Multiple entries of region type MEMORY in ranges for PCI"
+ depends on PCI || DM_PCI
+ default n
+ help
+ Enable PCI memory regions to be of multiple entry. Multiple entry
+ here refers to allow more than one count of address ranges for MEMORY
+ region type. This helps to add support for SoC's like OcteonTX/TX2
+ where every peripheral is on the PCI bus.
+
config PCIE_ECAM_GENERIC
bool "Generic ECAM-based PCI host controller support"
default n
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index cf1bbcc..19ea3ae 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -936,10 +936,13 @@
}
pos = -1;
- for (i = 0; i < hose->region_count; i++) {
- if (hose->regions[i].flags == type)
- pos = i;
+ if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
+ for (i = 0; i < hose->region_count; i++) {
+ if (hose->regions[i].flags == type)
+ pos = i;
+ }
}
+
if (pos == -1)
pos = hose->region_count++;
debug(" - type=%d, pos=%d\n", type, pos);