tree 2ac2373905fe23b18d4c4eddc897de6664bc842b
parent f0aa26f006339969d5e712c50fdb6838333be3b8
author Vladimir Zapolskiy <vz@mleia.com> 1443997125 +0100
committer Tom Rini <trini@konsulko.com> 1444597933 -0400

lpc32xx: fix calculation of HCLK PLL output clock

Execution branches on feedback mode are swapped, this has no effect
if default direct mode is on (then p_div is equal to 1 and Fout equals
to Fcco), that's why the problem remained unnoticed for a long time.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>