Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next
diff --git a/MAINTAINERS b/MAINTAINERS
index a4637fd..b667c8e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14,261 +14,260 @@
# PowerPC Systems: #
# #
# Maintainer Name, Email Address #
-# Board CPU #
+# Board CPU #
#########################################################################
Greg Allen <gallen@arlut.utexas.edu>
- UTX8245 MPC8245
+ UTX8245 MPC8245
Pantelis Antoniou <panto@intracom.gr>
- NETVIA MPC8xx
+ NETVIA MPC8xx
Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- cpci5200 MPC5200
- mecp5200 MPC5200
- pf5200 MPC5200
+ cpci5200 MPC5200
+ mecp5200 MPC5200
+ pf5200 MPC5200
- CPCI750 PPC750FX/GX
+ CPCI750 PPC750FX/GX
Yuli Barcohen <yuli@arabellasw.com>
- Adder MPC87x/MPC852T
- ep8248 MPC8248
- ISPAN MPC8260
- MPC8260ADS MPC826x/MPC827x/MPC8280
- Rattler MPC8248
- ZPC1900 MPC8265
+ Adder MPC87x/MPC852T
+ ep8248 MPC8248
+ ISPAN MPC8260
+ MPC8260ADS MPC826x/MPC827x/MPC8280
+ Rattler MPC8248
+ ZPC1900 MPC8265
Michael Barkowski <michael.barkowski@freescale.com>
- MPC8323ERDB MPC8323
+ MPC8323ERDB MPC8323
Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
- sacsng MPC8260
+ sacsng MPC8260
Oliver Brown <obrown@adventnetworks.com>
- gw8260 MPC8260
+ gw8260 MPC8260
Conn Clark <clark@esteem.com>
- ESTEEM192E MPC8xx
+ ESTEEM192E MPC8xx
Joe D'Abbraccio <ljd015@freescale.com>
- MPC837xERDB MPC837x
+ MPC837xERDB MPC837x
Kári Davíðsson <kd@flaga.is>
- FLAGADM MPC823
+ FLAGADM MPC823
Torsten Demke <torsten.demke@fci.com>
- eXalion MPC824x
+ eXalion MPC824x
Wolfgang Denk <wd@denx.de>
- IceCube_5100 MGT5100
- IceCube_5200 MPC5200
+ IceCube_5100 MGT5100
+ IceCube_5200 MPC5200
- AMX860 MPC860
- ETX094 MPC850
- FPS850L MPC850
- FPS860L MPC860
- ICU862 MPC862
- IP860 MPC860
- IVML24 MPC860
- IVML24_128 MPC860
- IVML24_256 MPC860
- IVMS8 MPC860
- IVMS8_128 MPC860
- IVMS8_256 MPC860
- LANTEC MPC850
- LWMON MPC823
- NC650 MPC852
- R360MPI MPC823
- RMU MPC850
- RRvision MPC823
- SM850 MPC850
- SPD823TS MPC823
- TQM823L MPC823
- TQM823L_LCD MPC823
- TQM850L MPC850
- TQM855L MPC855
- TQM860L MPC860
- TQM860L_FEC MPC860
- c2mon MPC855
- hermes MPC860
- lwmon MPC823
- pcu_e MPC855
+ AMX860 MPC860
+ ETX094 MPC850
+ FPS850L MPC850
+ FPS860L MPC860
+ ICU862 MPC862
+ IP860 MPC860
+ IVML24 MPC860
+ IVML24_128 MPC860
+ IVML24_256 MPC860
+ IVMS8 MPC860
+ IVMS8_128 MPC860
+ IVMS8_256 MPC860
+ LANTEC MPC850
+ LWMON MPC823
+ NC650 MPC852
+ R360MPI MPC823
+ RMU MPC850
+ RRvision MPC823
+ SM850 MPC850
+ SPD823TS MPC823
+ TQM823L MPC823
+ TQM823L_LCD MPC823
+ TQM850L MPC850
+ TQM855L MPC855
+ TQM860L MPC860
+ TQM860L_FEC MPC860
+ c2mon MPC855
+ hermes MPC860
+ lwmon MPC823
+ pcu_e MPC855
- CU824 MPC8240
- Sandpoint8240 MPC8240
- SL8245 MPC8245
+ CU824 MPC8240
+ Sandpoint8240 MPC8240
+ SL8245 MPC8245
- ATC MPC8250
- PM825 MPC8250
+ ATC MPC8250
+ PM825 MPC8250
- TQM8255 MPC8255
+ TQM8255 MPC8255
- CPU86 MPC8260
- PM826 MPC8260
- TQM8260 MPC8260
+ CPU86 MPC8260
+ PM826 MPC8260
+ TQM8260 MPC8260
- P3G4 MPC7410
+ P3G4 MPC7410
- PCIPPC2 MPC750
- PCIPPC6 MPC750
+ PCIPPC2 MPC750
+ PCIPPC6 MPC750
- EXBITGEN PPC405GP
+ EXBITGEN PPC405GP
Jon Diekema <jon.diekema@smiths-aerospace.com>
- sbc8260 MPC8260
+ sbc8260 MPC8260
Dave Ellis <DGE@sixnetio.com>
- SXNI855T MPC8xx
+ SXNI855T MPC8xx
Thomas Frieden <ThomasF@hyperion-entertainment.com>
- AmigaOneG3SE MPC7xx
+ AmigaOneG3SE MPC7xx
Matthias Fuchs <matthias.fuchs@esd-electronics.com>
- ADCIOP IOP480 (PPC401)
- APC405 PPC405GP
- AR405 PPC405GP
- ASH405 PPC405EP
- CANBT PPC405CR
- CPCI2DP PPC405GP
- CPCI405 PPC405GP
- CPCI4052 PPC405GP
- CPCI405AB PPC405GP
- CPCI405DT PPC405GP
- CPCIISER4 PPC405GP
- DASA_SIM IOP480 (PPC401)
- DP405 PPC405EP
- DU405 PPC405GP
- DU440 PPC440EPx
- G2000 PPC405EP
- HH405 PPC405EP
- HUB405 PPC405EP
- OCRTC PPC405GP
- ORSG PPC405GP
- PCI405 PPC405GP
- PLU405 PPC405EP
- PMC405 PPC405GP
- PMC440 PPC440EPx
- VOH405 PPC405EP
- VOM405 PPC405EP
- WUH405 PPC405EP
- CMS700 PPC405EP
+ ADCIOP IOP480 (PPC401)
+ APC405 PPC405GP
+ AR405 PPC405GP
+ ASH405 PPC405EP
+ CANBT PPC405CR
+ CPCI2DP PPC405GP
+ CPCI405 PPC405GP
+ CPCI4052 PPC405GP
+ CPCI405AB PPC405GP
+ CPCI405DT PPC405GP
+ CPCIISER4 PPC405GP
+ DASA_SIM IOP480 (PPC401)
+ DP405 PPC405EP
+ DU405 PPC405GP
+ DU440 PPC440EPx
+ G2000 PPC405EP
+ HH405 PPC405EP
+ HUB405 PPC405EP
+ OCRTC PPC405GP
+ ORSG PPC405GP
+ PCI405 PPC405GP
+ PLU405 PPC405EP
+ PMC405 PPC405GP
+ PMC440 PPC440EPx
+ VOH405 PPC405EP
+ VOM405 PPC405EP
+ WUH405 PPC405EP
+ CMS700 PPC405EP
Niklaus Giger <niklaus.giger@netstal.com>
- HCU4 PPC405GPr
- MCU25 PPC405GPr
- HCU5 PPC440EPx
+ HCU4 PPC405GPr
+ MCU25 PPC405GPr
+ HCU5 PPC440EPx
Frank Gottschling <fgottschling@eltec.de>
- MHPC MPC8xx
+ MHPC MPC8xx
- BAB7xx MPC740/MPC750
+ BAB7xx MPC740/MPC750
Wolfgang Grandegger <wg@denx.de>
- CCM MPC855
+ CCM MPC855
- PN62 MPC8240
-
- IPHASE4539 MPC8260
- SCM MPC8260
+ PN62 MPC8240
+ IPHASE4539 MPC8260
+ SCM MPC8260
Howard Gray <mvsensor@matrix-vision.de>
- MVS1 MPC823
+ MVS1 MPC823
Joe Hamman <joe.hamman@embeddedspecialties.com>
- sbc8548 MPC8548
- sbc8641d MPC8641D
+ sbc8548 MPC8548
+ sbc8641d MPC8641D
Klaus Heydeck <heydeck@kieback-peter.de>
- KUP4K MPC855
- KUP4X MPC859
+ KUP4K MPC855
+ KUP4X MPC859
Gary Jennejohn <garyj@denx.de>
- quad100hd PPC405EP
+ quad100hd PPC405EP
Murray Jensen <Murray.Jensen@csiro.au>
- cogent_mpc8xx MPC8xx
+ cogent_mpc8xx MPC8xx
- cogent_mpc8260 MPC8260
- hymod MPC8260
+ cogent_mpc8260 MPC8260
+ hymod MPC8260
Larry Johnson <lrj@acm.org>
- korat PPC440EPx
+ korat PPC440EPx
Brad Kemp <Brad.Kemp@seranoa.com>
- ppmc8260 MPC8260
+ ppmc8260 MPC8260
Sangmoon Kim <dogoil@etinsys.com>
- debris MPC8245
- KVME080 MPC8245
+ debris MPC8245
+ KVME080 MPC8245
Thomas Lange <thomas@corelatus.se>
- GTH MPC860
+ GTH MPC860
Robert Lazarski <robertlazarski@gmail.com>
- ATUM8548 MPC8548
+ ATUM8548 MPC8548
The LEOX team <team@leox.org>
- ELPT860 MPC860T
+ ELPT860 MPC860T
Dave Liu <daveliu@freescale.com>
- MPC8315ERDB MPC8315
- MPC832XEMDS MPC832x
- MPC8360EMDS MPC8360
- MPC837XEMDS MPC837x
+ MPC8315ERDB MPC8315
+ MPC832XEMDS MPC832x
+ MPC8360EMDS MPC8360
+ MPC837XEMDS MPC837x
Nye Liu <nyet@zumanetworks.com>
- ZUMA MPC7xx_74xx
+ ZUMA MPC7xx_74xx
Jon Loeliger <jdl@freescale.com>
- MPC8540ADS MPC8540
- MPC8560ADS MPC8560
- MPC8541CDS MPC8541
- MPC8555CDS MPC8555
+ MPC8540ADS MPC8540
+ MPC8560ADS MPC8560
+ MPC8541CDS MPC8541
+ MPC8555CDS MPC8555
- MPC8641HPCN MPC8641D
+ MPC8641HPCN MPC8641D
Dan Malek <dan@embeddedalley.com>
- stxgp3 MPC85xx
- stxssa MPC85xx
- stxxtc MPC8xx
+ stxgp3 MPC85xx
+ stxssa MPC85xx
+ stxxtc MPC8xx
Eran Man <eran@nbase.co.il>
- EVB64260_750CX MPC750CX
+ EVB64260_750CX MPC750CX
Andrea "llandre" Marson <andrea.marson@dave-tech.it>
@@ -276,75 +275,75 @@
Reinhard Meyer <r.meyer@emk-elektronik.de>
- TOP860 MPC860T
- TOP5200 MPC5200
+ TOP860 MPC860T
+ TOP5200 MPC5200
Tolunay Orkun <torkun@nextio.com>
- csb272 PPC405GP
- csb472 PPC405GP
+ csb272 PPC405GP
+ csb472 PPC405GP
John Otken <jotken@softadvances.com>
- luan PPC440SP
- taihu PPC405EP
+ luan PPC440SP
+ taihu PPC405EP
Keith Outwater <Keith_Outwater@mvis.com>
- GEN860T MPC860T
- GEN860T_SC MPC860T
+ GEN860T MPC860T
+ GEN860T_SC MPC860T
Frank Panno <fpanno@delphintech.com>
- ep8260 MPC8260
+ ep8260 MPC8260
Denis Peter <d.peter@mpl.ch>
- MIP405 PPC4xx
- PIP405 PPC4xx
+ MIP405 PPC4xx
+ PIP405 PPC4xx
Kim Phillips <kim.phillips@freescale.com>
- MPC8349EMDS MPC8349
+ MPC8349EMDS MPC8349
Daniel Poirot <dan.poirot@windriver.com>
- sbc8240 MPC8240
- sbc405 PPC405GP
+ sbc8240 MPC8240
+ sbc405 PPC405GP
Stefan Roese <sr@denx.de>
- P3M7448 MPC7448
+ P3M7448 MPC7448
- uc100 MPC857
+ uc100 MPC857
- TQM85xx MPC8540/8541/8555/8560
+ TQM85xx MPC8540/8541/8555/8560
- acadia PPC405EZ
- alpr PPC440GX
- bamboo PPC440EP
- bunbinga PPC405EP
- canyonlands PPC460EX
- ebony PPC440GP
- glacier PPC460GT
- haleakala PPC405EXr
- katmai PPC440SPe
- kilauea PPC405EX
- lwmon5 PPC440EPx
- makalu PPC405EX
- ocotea PPC440GX
- p3p440 PPC440GP
- pcs440ep PPC440EP
- rainier PPC440GRx
- sequoia PPC440EPx
- sycamore PPC405GPr
- taishan PPC440GX
- walnut PPC405GP
- yellowstone PPC440GR
- yosemite PPC440EP
- zeus PPC405EP
+ acadia PPC405EZ
+ alpr PPC440GX
+ bamboo PPC440EP
+ bunbinga PPC405EP
+ canyonlands PPC460EX
+ ebony PPC440GP
+ glacier PPC460GT
+ haleakala PPC405EXr
+ katmai PPC440SPe
+ kilauea PPC405EX
+ lwmon5 PPC440EPx
+ makalu PPC405EX
+ ocotea PPC440GX
+ p3p440 PPC440GP
+ pcs440ep PPC440EP
+ rainier PPC440GRx
+ sequoia PPC440EPx
+ sycamore PPC405GPr
+ taishan PPC440GX
+ walnut PPC405GP
+ yellowstone PPC440GR
+ yosemite PPC440EP
+ zeus PPC405EP
- P3M750 PPC750FX/GX/GL
+ P3M750 PPC750FX/GX/GL
Yusdi Santoso <yusdi_santoso@adaptec.com>
@@ -352,73 +351,73 @@
Travis Sawyer (travis.sawyer@sandburst.com>
- KAREF PPC440GX
- METROBOX PPC440GX
- XPEDITE1K PPC440GX
+ KAREF PPC440GX
+ METROBOX PPC440GX
+ XPEDITE1K PPC440GX
Heiko Schocher <hs@denx.de>
- ids8247 MPC8247
- jupiter MPC5200
- mgcoge MPC8247
- mgsuvd MPC852
- municse MPC5200
- sc3 PPC405GP
- uc101 MPC5200
+ ids8247 MPC8247
+ jupiter MPC5200
+ mgcoge MPC8247
+ mgsuvd MPC852
+ municse MPC5200
+ sc3 PPC405GP
+ uc101 MPC5200
Peter De Schrijver <p2@mind.be>
- ML2 PPC4xx
+ ML2 PPC4xx
Andre Schwarz <andre.schwarz@matrix-vision.de>
- mvblm7 MPC8343
+ mvblm7 MPC8343
Timur Tabi <timur@freescale.com>
- MPC8349E-mITX MPC8349
- MPC8349E-mITX-GP MPC8349
+ MPC8349E-mITX MPC8349
+ MPC8349E-mITX-GP MPC8349
Erik Theisen <etheisen@mindspring.com>
- W7OLMC PPC4xx
- W7OLMG PPC4xx
+ W7OLMC PPC4xx
+ W7OLMG PPC4xx
Jim Thompson <jim@musenki.com>
- MUSENKI MPC8245/8241
- Sandpoint8245 MPC8245
+ MUSENKI MPC8245/8241
+ Sandpoint8245 MPC8245
Rune Torgersen <runet@innovsys.com>
- MPC8266ADS MPC8266
+ MPC8266ADS MPC8266
David Updegraff <dave@cray.com>
- CRAYL1 PPC4xx
+ CRAYL1 PPC4xx
Anton Vorontsov <avorontsov@ru.mvista.com>
- MPC8360ERDK MPC8360
+ MPC8360ERDK MPC8360
Josef Wagner <Wagner@Microsys.de>
- CPC45 MPC8245
- PM520 MPC5200
+ CPC45 MPC8245
+ PM520 MPC5200
Stephen Williams <steve@icarus.com>
- JSE PPC405GPr
+ JSE PPC405GPr
John Zhan <zhanz@sinovee.com>
- svm_sc8xx MPC8xx
+ svm_sc8xx MPC8xx
Guennadi Liakhovetski <g.liakhovetski@gmx.de>
- linkstation MPC8241
+ linkstation MPC8241
Feng Kan <fkan@amcc.com>
@@ -427,332 +426,332 @@
Unknown / orphaned boards:
- ADS860 MPC8xx
- FADS823 MPC8xx
- FADS850SAR MPC8xx
- FADS860T MPC8xx
- GENIETV MPC8xx
- IAD210 MPC8xx
- MBX MPC8xx
- MBX860T MPC8xx
- NX823 MPC8xx
- RPXClassic MPC8xx
- RPXlite MPC8xx
+ ADS860 MPC8xx
+ FADS823 MPC8xx
+ FADS850SAR MPC8xx
+ FADS860T MPC8xx
+ GENIETV MPC8xx
+ IAD210 MPC8xx
+ MBX MPC8xx
+ MBX860T MPC8xx
+ NX823 MPC8xx
+ RPXClassic MPC8xx
+ RPXlite MPC8xx
- ERIC PPC4xx
+ ERIC PPC4xx
- MOUSSE MPC824x
+ MOUSSE MPC824x
- RPXsuper MPC8260
- rsdproto MPC8260
+ RPXsuper MPC8260
+ rsdproto MPC8260
- EVB64260 MPC7xx_74xx
+ EVB64260 MPC7xx_74xx
#########################################################################
# ARM Systems: #
# #
# Maintainer Name, Email Address #
-# Board CPU #
+# Board CPU #
#########################################################################
Rowel Atienza <rowel@diwalabs.com>
- armadillo ARM720T
+ armadillo ARM720T
Rishi Bhattacharya <rishi@ti.com>
- omap5912osk ARM926EJS
+ omap5912osk ARM926EJS
Cliff Brake <cliff.brake@gmail.com>
- pxa255_idp xscale
+ pxa255_idp xscale
Rick Bronson <rick@efn.org>
- AT91RM9200DK at91rm9200
+ AT91RM9200DK at91rm9200
George G. Davis <gdavis@mvista.com>
- assabet SA1100
- gcplus SA1100
+ assabet SA1100
+ gcplus SA1100
Thomas Elste <info@elste.org>
- modnet50 ARM720T (NET+50)
+ modnet50 ARM720T (NET+50)
Peter Figuli <peposh@etc.sk>
- wepep250 xscale
+ wepep250 xscale
Marius Gröger <mag@sysgo.de>
- impa7 ARM720T (EP7211)
- ep7312 ARM720T (EP7312)
+ impa7 ARM720T (EP7211)
+ ep7312 ARM720T (EP7312)
Kshitij Gupta <kshitij@ti.com>
- omap1510inn ARM925T
- omap1610inn ARM926EJS
-
-Kyle Harris <kharris@nexus-tech.net>
-
- lubbock xscale
- cradle xscale
- ixdp425 xscale
+ omap1510inn ARM925T
+ omap1610inn ARM926EJS
Gary Jennejohn <gj@denx.de>
- smdk2400 ARM920T
- trab ARM920T
+ smdk2400 ARM920T
+ trab ARM920T
Konstantin Kletschke <kletschke@synertronixx.de>
- scb9328 ARM920T
+ scb9328 ARM920T
Nishant Kamat <nskamat@ti.com>
- omap1610h2 ARM926EJS
+ omap1610h2 ARM926EJS
Sergey Kubushyn <ksi@koi8.net>
- DV-EVM ARM926EJS
- SONATA ARM926EJS
- SCHMOOGIE ARM926EJS
+ DV-EVM ARM926EJS
+ SONATA ARM926EJS
+ SCHMOOGIE ARM926EJS
Prakash Kumar <prakash@embedx.com>
- cerf250 xscale
+ cerf250 xscale
David Müller <d.mueller@elsoft.ch>
- smdk2410 ARM920T
- VCMA9 ARM920T
+ smdk2410 ARM920T
+ VCMA9 ARM920T
Rolf Offermanns <rof@sysgo.de>
- shannon SA1100
+ shannon SA1100
Peter Pearse <peter.pearse@arm.com>
- integratorcp All current ARM supplied &
- supported core modules
- -see http://www.arm.com
- /products/DevTools
- /Hardware_Platforms.html
- versatile ARM926EJ-S
- versatile ARM926EJ-S
+ integratorcp All current ARM supplied & supported core modules
+ -see http://www.arm.com/products/DevTools/Hardware_Platforms.html
+ versatile ARM926EJ-S
+ versatile ARM926EJ-S
Dave Peverley <dpeverley@mpc-data.co.uk>
- omap730p2 ARM926EJS
+ omap730p2 ARM926EJS
Stelian Pop <stelian.pop@leadtechdesign.com>
- at91cap9adk ARM926EJS (AT91CAP9 SoC)
- at91sam9260ek ARM926EJS (AT91SAM9260 SoC)
- at91sam9261ek ARM926EJS (AT91SAM9261 SoC)
- at91sam9263ek ARM926EJS (AT91SAM9263 SoC)
- at91sam9rlek ARM926EJS (AT91SAM9RL SoC)
+ at91cap9adk ARM926EJS (AT91CAP9 SoC)
+ at91sam9260ek ARM926EJS (AT91SAM9260 SoC)
+ at91sam9261ek ARM926EJS (AT91SAM9261 SoC)
+ at91sam9263ek ARM926EJS (AT91SAM9263 SoC)
+ at91sam9rlek ARM926EJS (AT91SAM9RL SoC)
Stefan Roese <sr@denx.de>
- ixdpg425 xscale
- pdnb3 xscale
- scpu xscale
+ ixdpg425 xscale
+ pdnb3 xscale
+ scpu xscale
Robert Schwebel <r.schwebel@pengutronix.de>
- csb226 xscale
- innokom xscale
+ csb226 xscale
+ innokom xscale
Andrea Scian <andrea.scian@dave-tech.it>
- B2 ARM7TDMI (S3C44B0X)
+ B2 ARM7TDMI (S3C44B0X)
Greg Ungerer <greg.ungerer@opengear.com>
- cm4008 ks8695p
- cm4116 ks8695p
- cm4148 ks8695p
+ cm4008 ks8695p
+ cm4116 ks8695p
+ cm4148 ks8695p
Richard Woodruff <r-woodruff2@ti.com>
- omap2420h4 ARM1136EJS
+ omap2420h4 ARM1136EJS
Kyungmin Park <kyungmin.park@samsung.com>
- apollon ARM1136EJS
+ apollon ARM1136EJS
Alex Züpke <azu@sysgo.de>
- lart SA1100
- dnp1110 SA1110
+ lart SA1100
+ dnp1110 SA1110
Michael Schwingen <michael@schwingen.org>
- actux1 xscale
- actux2 xscale
- actux3 xscale
- actux4 xscale
+ actux1 xscale
+ actux2 xscale
+ actux3 xscale
+ actux4 xscale
+
+-------------------------------------------------------------------------
+
+Unknown / orphaned boards:
+ Board CPU Last known maintainer / Comment
+.........................................................................
+ cradle xscale Kyle Harris <kharris@nexus-tech.net> / dead address
+ ixdp425 xscale Kyle Harris <kharris@nexus-tech.net> / dead address
+ lubbock xscale Kyle Harris <kharris@nexus-tech.net> / dead address
#########################################################################
# x86 Systems: #
# #
# Maintainer Name, Email Address #
-# Board CPU #
+# Board CPU #
#########################################################################
Daniel Engström <daniel@omicron.se>
- sc520_cdp x86
+ sc520_cdp x86
#########################################################################
# MIPS Systems: #
# #
# Maintainer Name, Email Address #
-# Board CPU #
+# Board CPU #
#########################################################################
Wolfgang Denk <wd@denx.de>
- incaip MIPS32 4Kc
- purple MIPS64 5Kc
+ incaip MIPS32 4Kc
+ purple MIPS64 5Kc
Thomas Lange <thomas@corelatus.se>
- dbau1x00 MIPS32 Au1000
- gth2 MIPS32 Au1000
+ dbau1x00 MIPS32 Au1000
+ gth2 MIPS32 Au1000
Vlad Lungu <vlad.lungu@windriver.com>
- qemu_mips MIPS32
+ qemu_mips MIPS32
#########################################################################
# Nios-32 Systems: #
# #
# Maintainer Name, Email Address #
-# Board CPU #
+# Board CPU #
#########################################################################
Stephan Linz <linz@li-pro.net>
- DK1S10 Nios-32
- ADNPESC1 Nios-32
+ DK1S10 Nios-32
+ ADNPESC1 Nios-32
Scott McNutt <smcnutt@psyent.com>
- DK1C20 Nios-32
+ DK1C20 Nios-32
#########################################################################
# Nios-II Systems: #
# #
# Maintainer Name, Email Address #
-# Board CPU #
+# Board CPU #
#########################################################################
Scott McNutt <smcnutt@psyent.com>
- PCI5441 Nios-II
- PK1C20 Nios-II
- EP1C20 Nios-II
- EP1S10 Nios-II
- EP1S40 Nios-II
+ PCI5441 Nios-II
+ PK1C20 Nios-II
+ EP1C20 Nios-II
+ EP1S10 Nios-II
+ EP1S40 Nios-II
#########################################################################
# MicroBlaze Systems: #
# #
# Maintainer Name, Email Address #
-# Board CPU #
+# Board CPU #
#########################################################################
Yasushi Shoji <yashi@atmark-techno.com>
- SUZAKU MicroBlaze
+ SUZAKU MicroBlaze
Michal Simek <monstr@monstr.eu>
- ML401 MicroBlaze
- XUPV2P MicroBlaze
+ ML401 MicroBlaze
+ XUPV2P MicroBlaze
#########################################################################
# Coldfire Systems: #
# #
# Maintainer Name, Email Address #
-# Board CPU #
+# Board CPU #
#########################################################################
Matthias Fuchs <matthias.fuchs@esd-electronics.com>
- TASREG MCF5249
+ TASREG MCF5249
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
- M52277EVB mcf5227x
- M5235EVB mcf52x2
- M5329EVB mcf532x
- M5373EVB mcf532x
- M54455EVB mcf5445x
- M5475EVB mcf547x_8x
- M5485EVB mcf547x_8x
+ M52277EVB mcf5227x
+ M5235EVB mcf52x2
+ M5329EVB mcf532x
+ M5373EVB mcf532x
+ M54455EVB mcf5445x
+ M5475EVB mcf547x_8x
+ M5485EVB mcf547x_8x
Hayden Fraser <Hayden.Fraser@freescale.com>
- M5253EVBE mcf52x2
+ M5253EVBE mcf52x2
#########################################################################
# AVR32 Systems: #
# #
# Maintainer Name, Email Address #
-# Board CPU #
+# Board CPU #
#########################################################################
Haavard Skinnemoen <hskinnemoen@atmel.com>
- ATSTK1000 AT32AP7xxx
- ATSTK1002 AT32AP7000
- ATSTK1003 AT32AP7001
- ATSTK1004 AT32AP7002
- ATSTK1006 AT32AP7000
- ATNGW100 AT32AP7000
+ ATSTK1000 AT32AP7xxx
+ ATSTK1002 AT32AP7000
+ ATSTK1003 AT32AP7001
+ ATSTK1004 AT32AP7002
+ ATSTK1006 AT32AP7000
+ ATNGW100 AT32AP7000
#########################################################################
# SuperH Systems: #
# #
# Maintainer Name, Email Address #
-# Board CPU #
+# Board CPU #
#########################################################################
Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- MS7750SE SH7750
- MS7722SE SH7722
- R7780MP SH7780
- R2DPlus SH7751R
- SH7763RDP SH7763
+ MS7750SE SH7750
+ MS7722SE SH7722
+ R7780MP SH7780
+ R2DPlus SH7751R
+ SH7763RDP SH7763
Mark Jonas <mark.jonas@de.bosch.com>
- mpr2 SH7720
+ mpr2 SH7720
Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- MS7720SE SH7720
+ MS7720SE SH7720
Yusuke Goda <goda.yusuke@renesas.com>
- MIGO-R SH7722
+ MIGO-R SH7722
#########################################################################
# Blackfin Systems: #
# #
# Maintainer Name, Email Address #
-# Board CPU #
+# Board CPU #
#########################################################################
Mike Frysinger <vapier@gentoo.org>
Blackfin Team <u-boot-devel@blackfin.uclinux.org>
- BF533-EZKIT BF533
- BF533-STAMP BF533
- BF537-STAMP BF537
- BF561-EZKIT BF561
+ BF533-EZKIT BF533
+ BF533-STAMP BF533
+ BF537-STAMP BF537
+ BF561-EZKIT BF561
#########################################################################
# End of MAINTAINERS list #
diff --git a/MAKEALL b/MAKEALL
index 80b6060..a256e9a 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -462,13 +462,6 @@
#########################################################################
LIST_ARM9=" \
- at91cap9adk \
- at91rm9200dk \
- at91sam9260ek \
- at91sam9261ek \
- at91sam9263ek \
- at91sam9rlek \
- cmc_pu2 \
ap920t \
ap922_XA10 \
ap926ejs \
@@ -479,11 +472,7 @@
cp926ejs \
cp946es \
cp966 \
- csb637 \
- kb9202 \
lpd7a400 \
- m501sk \
- mp2usb \
mx1ads \
mx1fs2 \
netstar \
@@ -588,6 +577,7 @@
${LIST_ARM9} \
${LIST_ARM10} \
${LIST_ARM11} \
+ ${LIST_at91} \
${LIST_pxa} \
${LIST_ixp} \
"
@@ -702,7 +692,7 @@
M52277EVB \
M5235EVB \
M5249EVB \
- M5253EVB \
+ M5253EVBE \
M5271EVB \
M5272C3 \
M5275EVB \
diff --git a/board/BuS/EB+MCF-EV123/mii.c b/board/BuS/EB+MCF-EV123/mii.c
index 3ea20a6..8ae2ec6 100644
--- a/board/BuS/EB+MCF-EV123/mii.c
+++ b/board/BuS/EB+MCF-EV123/mii.c
@@ -201,7 +201,7 @@
}
#endif /* CFG_DISCOVER_PHY */
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
index d5cee64..8452054 100644
--- a/board/ads5121/ads5121.c
+++ b/board/ads5121/ads5121.c
@@ -23,6 +23,7 @@
#include <common.h>
#include <mpc512x.h>
+#include "iopin.h"
#include <asm/bitops.h>
#include <command.h>
#include <fdt_support.h>
diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c
index 87cf0cb..26628d3 100644
--- a/board/ads5121/ads5121_diu.c
+++ b/board/ads5121/ads5121_diu.c
@@ -57,7 +57,7 @@
/* Modify PXCLK in GUTS CLKDVDR */
debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr);
temp = *clkdvdr & 0xFFFFFF00;
- *clkdvdr = temp | (pixval & 0x1F);
+ *clkdvdr = temp | (pixval & 0xFF);
debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
}
diff --git a/board/ads5121/iopin.c b/board/ads5121/iopin.c
index 6a35c81..a6792a0 100644
--- a/board/ads5121/iopin.c
+++ b/board/ads5121/iopin.c
@@ -25,71 +25,90 @@
#include <linux/types.h>
#include "iopin.h"
-/*
- * IO PAD TYPES
- * for all types fmux is used to select the funtion
- * ds sets the slew rate
- * STD pins nothing extra (can set ds & fmux only)
- * STD_PU pue=1 to enable pull & pud sets whether up or down resistors
- * STD_ST st sets the Schmitt trigger
- * STD_PU_ST pue & pud sets pull-up/down resistors as in STD_PU
- * st sets the Schmitt trigger
- * PCI hold sets output delay
- * PCI_ST hold sets output delay and st sets the Schmitt trigger
- */
+/* IO pin fields */
+#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */
+#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */
+#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */
+#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */
+#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */
+#define IO_PIN_DS(v) ((v)) /* slew rate */
static struct iopin_t {
- u_short p_offset; /* offset from IOCTL_MEM_OFFSET */
- u_short p_no; /* number of pins to set this way */
- u_short bit_or:7; /* Do bitwise OR instead of setting */
- u_short fmux:2; /* pad function select 0-3 */
- u_short hold:2; /* PCI pad types only; */
- u_short pud:1; /* pull resistor; PU types only; */
- /* if pue=1 then 0=pull-down, 1=pull-up */
- u_short pue:1; /* Pull resistor enable; _PU types only */
- u_short st:1; /* Schmitt trigger enable; _ST types only */
- u_short ds:2; /* Slew rate class, 0=class1, ..., 3=class4 */
+ int p_offset; /* offset from IOCTL_MEM_OFFSET */
+ int nr_pins; /* number of pins to set this way */
+ int bit_or; /* or in the value instead of overwrite */
+ u_long val; /* value to write or or */
} ioregs_init[] = {
-/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
- {IOCTL_SPDIF_TXCLK, 3, 0, 1, 0, 0, 0, 0, 3},
-/* Set highest Slew on 9 PATA pins */
- {IOCTL_PATA_CE1, 9, 1, 0, 0, 0, 0, 0, 3},
-/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
- {IOCTL_PSC0_0, 15, 0, 1, 0, 0, 0, 0, 3},
-/* FUNC1=SPDIF_TXCLK */
- {IOCTL_LPC_CS1, 1, 0, 1, 0, 0, 0, 1, 3},
-/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
- {IOCTL_I2C1_SCL, 2, 0, 2, 0, 0, 0, 1, 3},
-/* FUNC2=DIU CLK */
- {IOCTL_PSC6_0, 1, 0, 2, 0, 0, 0, 1, 3},
-/* FUNC2=DIU_HSYNC */
- {IOCTL_PSC6_1, 1, 0, 2, 0, 0, 0, 0, 3},
-/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
- {IOCTL_PSC6_4, 26, 0, 2, 0, 0, 0, 0, 3}
+ /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+ {
+ IOCTL_SPDIF_TXCLK, 3, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* Set highest Slew on 9 PATA pins */
+ {
+ IOCTL_PATA_CE1, 9, 1,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+ {
+ IOCTL_PSC0_0, 15, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=SPDIF_TXCLK */
+ {
+ IOCTL_LPC_CS1, 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+ },
+ /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
+ {
+ IOCTL_I2C1_SCL, 2, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+ },
+ /* FUNC2=DIU CLK */
+ {
+ IOCTL_PSC6_0, 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+ },
+ /* FUNC2=DIU_HSYNC */
+ {
+ IOCTL_PSC6_1, 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+ {
+ IOCTL_PSC6_4, 26, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ }
};
void iopin_initialize(void)
{
short i, j, n, p;
u_long *reg;
+ immap_t *im = (immap_t *)CFG_IMMR;
+
+ reg = (u_long *)&(im->io_ctrl.regs[0]);
if (sizeof(ioregs_init) == 0)
return;
- immap_t *im = (immap_t *)CFG_IMMR;
- reg = (u_long *)&(im->io_ctrl.regs[0]);
n = sizeof(ioregs_init) / sizeof(ioregs_init[0]);
for (i = 0; i < n; i++) {
for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
- p < ioregs_init[i].p_no; p++, j++) {
- /* lowest 9 bits sets the register */
+ p < ioregs_init[i].nr_pins; p++, j++) {
if (ioregs_init[i].bit_or)
- reg[j] |= *((u_long *) &ioregs_init[i].p_no)
- & 0x000001ff;
+ reg[j] |= ioregs_init[i].val;
else
- reg[j] = *((u_long *) &ioregs_init[i].p_no)
- & 0x000001ff;
+ reg[j] = ioregs_init[i].val;
}
}
return;
diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c
index 040b800..5b8b88e 100644
--- a/board/amcc/taishan/showinfo.c
+++ b/board/amcc/taishan/showinfo.c
@@ -34,59 +34,59 @@
/* read clock regsiter */
printf("===== Display reset and initialize register Start =========\n");
mfcpr(clk_pllc,reg);
- printf("cpr_pllc = %#010x\n",reg);
+ printf("cpr_pllc = %#010lx\n",reg);
mfcpr(clk_plld,reg);
- printf("cpr_plld = %#010x\n",reg);
+ printf("cpr_plld = %#010lx\n",reg);
mfcpr(clk_primad,reg);
- printf("cpr_primad = %#010x\n",reg);
+ printf("cpr_primad = %#010lx\n",reg);
mfcpr(clk_primbd,reg);
- printf("cpr_primbd = %#010x\n",reg);
+ printf("cpr_primbd = %#010lx\n",reg);
mfcpr(clk_opbd,reg);
- printf("cpr_opbd = %#010x\n",reg);
+ printf("cpr_opbd = %#010lx\n",reg);
mfcpr(clk_perd,reg);
- printf("cpr_perd = %#010x\n",reg);
+ printf("cpr_perd = %#010lx\n",reg);
mfcpr(clk_mald,reg);
- printf("cpr_mald = %#010x\n",reg);
+ printf("cpr_mald = %#010lx\n",reg);
/* read sdr register */
mfsdr(sdr_ebc,reg);
- printf("sdr_ebc = %#010x\n",reg);
+ printf("sdr_ebc = %#010lx\n",reg);
mfsdr(sdr_cp440,reg);
- printf("sdr_cp440 = %#010x\n",reg);
+ printf("sdr_cp440 = %#010lx\n",reg);
mfsdr(sdr_xcr,reg);
- printf("sdr_xcr = %#010x\n",reg);
+ printf("sdr_xcr = %#010lx\n",reg);
mfsdr(sdr_xpllc,reg);
- printf("sdr_xpllc = %#010x\n",reg);
+ printf("sdr_xpllc = %#010lx\n",reg);
mfsdr(sdr_xplld,reg);
- printf("sdr_xplld = %#010x\n",reg);
+ printf("sdr_xplld = %#010lx\n",reg);
mfsdr(sdr_pfc0,reg);
- printf("sdr_pfc0 = %#010x\n",reg);
+ printf("sdr_pfc0 = %#010lx\n",reg);
mfsdr(sdr_pfc1,reg);
- printf("sdr_pfc1 = %#010x\n",reg);
+ printf("sdr_pfc1 = %#010lx\n",reg);
mfsdr(sdr_cust0,reg);
- printf("sdr_cust0 = %#010x\n",reg);
+ printf("sdr_cust0 = %#010lx\n",reg);
mfsdr(sdr_cust1,reg);
- printf("sdr_cust1 = %#010x\n",reg);
+ printf("sdr_cust1 = %#010lx\n",reg);
mfsdr(sdr_uart0,reg);
- printf("sdr_uart0 = %#010x\n",reg);
+ printf("sdr_uart0 = %#010lx\n",reg);
mfsdr(sdr_uart1,reg);
- printf("sdr_uart1 = %#010x\n",reg);
+ printf("sdr_uart1 = %#010lx\n",reg);
printf("===== Display reset and initialize register End =========\n");
}
@@ -97,13 +97,13 @@
printf("PCI-X chip control registers\n");
mfsdr(sdr_xcr, reg);
- printf("sdr_xcr = %#010x\n", reg);
+ printf("sdr_xcr = %#010lx\n", reg);
mfsdr(sdr_xpllc, reg);
- printf("sdr_xpllc = %#010x\n", reg);
+ printf("sdr_xpllc = %#010lx\n", reg);
mfsdr(sdr_xplld, reg);
- printf("sdr_xplld = %#010x\n", reg);
+ printf("sdr_xplld = %#010lx\n", reg);
printf("PCI-X Bridge Configure registers\n");
printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID));
@@ -116,49 +116,49 @@
printf("PCIX0_HDTYPE = %#04x\n", in8(PCIX0_HDTYPE));
printf("PCIX0_BIST = %#04x\n", in8(PCIX0_BIST));
- printf("PCIX0_BAR0 = %#010x\n", in32r(PCIX0_BAR0));
- printf("PCIX0_BAR1 = %#010x\n", in32r(PCIX0_BAR1));
- printf("PCIX0_BAR2 = %#010x\n", in32r(PCIX0_BAR2));
- printf("PCIX0_BAR3 = %#010x\n", in32r(PCIX0_BAR3));
- printf("PCIX0_BAR4 = %#010x\n", in32r(PCIX0_BAR4));
- printf("PCIX0_BAR5 = %#010x\n", in32r(PCIX0_BAR5));
+ printf("PCIX0_BAR0 = %#010lx\n", in32r(PCIX0_BAR0));
+ printf("PCIX0_BAR1 = %#010lx\n", in32r(PCIX0_BAR1));
+ printf("PCIX0_BAR2 = %#010lx\n", in32r(PCIX0_BAR2));
+ printf("PCIX0_BAR3 = %#010lx\n", in32r(PCIX0_BAR3));
+ printf("PCIX0_BAR4 = %#010lx\n", in32r(PCIX0_BAR4));
+ printf("PCIX0_BAR5 = %#010lx\n", in32r(PCIX0_BAR5));
- printf("PCIX0_CISPTR = %#010x\n", in32r(PCIX0_CISPTR));
+ printf("PCIX0_CISPTR = %#010lx\n", in32r(PCIX0_CISPTR));
printf("PCIX0_SBSSYSVID = %#010x\n", in16r(PCIX0_SBSYSVID));
printf("PCIX0_SBSSYSID = %#010x\n", in16r(PCIX0_SBSYSID));
- printf("PCIX0_EROMBA = %#010x\n", in32r(PCIX0_EROMBA));
+ printf("PCIX0_EROMBA = %#010lx\n", in32r(PCIX0_EROMBA));
printf("PCIX0_CAP = %#04x\n", in8(PCIX0_CAP));
printf("PCIX0_INTLN = %#04x\n", in8(PCIX0_INTLN));
printf("PCIX0_INTPN = %#04x\n", in8(PCIX0_INTPN));
printf("PCIX0_MINGNT = %#04x\n", in8(PCIX0_MINGNT));
printf("PCIX0_MAXLTNCY = %#04x\n", in8(PCIX0_MAXLTNCY));
- printf("PCIX0_BRDGOPT1 = %#010x\n", in32r(PCIX0_BRDGOPT1));
- printf("PCIX0_BRDGOPT2 = %#010x\n", in32r(PCIX0_BRDGOPT2));
+ printf("PCIX0_BRDGOPT1 = %#010lx\n", in32r(PCIX0_BRDGOPT1));
+ printf("PCIX0_BRDGOPT2 = %#010lx\n", in32r(PCIX0_BRDGOPT2));
- printf("PCIX0_POM0LAL = %#010x\n", in32r(PCIX0_POM0LAL));
- printf("PCIX0_POM0LAH = %#010x\n", in32r(PCIX0_POM0LAH));
- printf("PCIX0_POM0SA = %#010x\n", in32r(PCIX0_POM0SA));
- printf("PCIX0_POM0PCILAL = %#010x\n", in32r(PCIX0_POM0PCIAL));
- printf("PCIX0_POM0PCILAH = %#010x\n", in32r(PCIX0_POM0PCIAH));
- printf("PCIX0_POM1LAL = %#010x\n", in32r(PCIX0_POM1LAL));
- printf("PCIX0_POM1LAH = %#010x\n", in32r(PCIX0_POM1LAH));
- printf("PCIX0_POM1SA = %#010x\n", in32r(PCIX0_POM1SA));
- printf("PCIX0_POM1PCILAL = %#010x\n", in32r(PCIX0_POM1PCIAL));
- printf("PCIX0_POM1PCILAH = %#010x\n", in32r(PCIX0_POM1PCIAH));
- printf("PCIX0_POM2SA = %#010x\n", in32r(PCIX0_POM2SA));
+ printf("PCIX0_POM0LAL = %#010lx\n", in32r(PCIX0_POM0LAL));
+ printf("PCIX0_POM0LAH = %#010lx\n", in32r(PCIX0_POM0LAH));
+ printf("PCIX0_POM0SA = %#010lx\n", in32r(PCIX0_POM0SA));
+ printf("PCIX0_POM0PCILAL = %#010lx\n", in32r(PCIX0_POM0PCIAL));
+ printf("PCIX0_POM0PCILAH = %#010lx\n", in32r(PCIX0_POM0PCIAH));
+ printf("PCIX0_POM1LAL = %#010lx\n", in32r(PCIX0_POM1LAL));
+ printf("PCIX0_POM1LAH = %#010lx\n", in32r(PCIX0_POM1LAH));
+ printf("PCIX0_POM1SA = %#010lx\n", in32r(PCIX0_POM1SA));
+ printf("PCIX0_POM1PCILAL = %#010lx\n", in32r(PCIX0_POM1PCIAL));
+ printf("PCIX0_POM1PCILAH = %#010lx\n", in32r(PCIX0_POM1PCIAH));
+ printf("PCIX0_POM2SA = %#010lx\n", in32r(PCIX0_POM2SA));
- printf("PCIX0_PIM0SA = %#010x\n", in32r(PCIX0_PIM0SA));
- printf("PCIX0_PIM0LAL = %#010x\n", in32r(PCIX0_PIM0LAL));
- printf("PCIX0_PIM0LAH = %#010x\n", in32r(PCIX0_PIM0LAH));
- printf("PCIX0_PIM1SA = %#010x\n", in32r(PCIX0_PIM1SA));
- printf("PCIX0_PIM1LAL = %#010x\n", in32r(PCIX0_PIM1LAL));
- printf("PCIX0_PIM1LAH = %#010x\n", in32r(PCIX0_PIM1LAH));
- printf("PCIX0_PIM2SA = %#010x\n", in32r(PCIX0_PIM1SA));
- printf("PCIX0_PIM2LAL = %#010x\n", in32r(PCIX0_PIM1LAL));
- printf("PCIX0_PIM2LAH = %#010x\n", in32r(PCIX0_PIM1LAH));
+ printf("PCIX0_PIM0SA = %#010lx\n", in32r(PCIX0_PIM0SA));
+ printf("PCIX0_PIM0LAL = %#010lx\n", in32r(PCIX0_PIM0LAL));
+ printf("PCIX0_PIM0LAH = %#010lx\n", in32r(PCIX0_PIM0LAH));
+ printf("PCIX0_PIM1SA = %#010lx\n", in32r(PCIX0_PIM1SA));
+ printf("PCIX0_PIM1LAL = %#010lx\n", in32r(PCIX0_PIM1LAL));
+ printf("PCIX0_PIM1LAH = %#010lx\n", in32r(PCIX0_PIM1LAH));
+ printf("PCIX0_PIM2SA = %#010lx\n", in32r(PCIX0_PIM1SA));
+ printf("PCIX0_PIM2LAL = %#010lx\n", in32r(PCIX0_PIM1LAL));
+ printf("PCIX0_PIM2LAH = %#010lx\n", in32r(PCIX0_PIM1LAH));
- printf("PCIX0_XSTS = %#010x\n", in32r(PCIX0_STS));
+ printf("PCIX0_XSTS = %#010lx\n", in32r(PCIX0_STS));
}
int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
diff --git a/board/armadillo/flash.c b/board/armadillo/flash.c
index 037a643..8518856 100644
--- a/board/armadillo/flash.c
+++ b/board/armadillo/flash.c
@@ -279,7 +279,7 @@
int i, rc;
wp = (addr & ~1); /* get lower word aligned address */
- printf ("Writing %d short data to 0x%p from 0x%p.\n ", cnt, wp, src);
+ printf ("Writing %lu short data to 0x%lx from 0x%p.\n ", cnt, wp, src);
/*
* handle unaligned start bytes
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index 836a0c4..06d8512 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -188,8 +188,17 @@
at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
+#if defined(CONFIG_AT91SAM9260EK)
+ /*
+ * use PA10, PA11 for ETX2, ETX3.
+ * PA23 and PA24 are for TWI EEPROM
+ */
+ at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */
+ at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */
+#else
at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
+#endif
at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
#endif
diff --git a/board/cobra5272/mii.c b/board/cobra5272/mii.c
index d0a4a39..b30ba80 100644
--- a/board/cobra5272/mii.c
+++ b/board/cobra5272/mii.c
@@ -200,7 +200,7 @@
}
#endif /* CFG_DISCOVER_PHY */
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
diff --git a/board/delta/nand.c b/board/delta/nand.c
index a635a65..5024056 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -254,7 +254,7 @@
break;
}
if(get_delta(start) > timeout) {
- DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
+ DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
return 0xff000000;
}
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index c2c8fe8..bd8a4e5 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -75,9 +75,11 @@
sdram->dacr0 =
SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
+ asm("nop");
/* Initialize DMR0 */
sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
+ asm("nop");
/* Set IP (bit 3) in DACR */
sdram->dacr0 |= SDRAMC_DARCn_IP;
@@ -100,6 +102,7 @@
/* Finish the configuration by issuing the MRS. */
sdram->dacr0 |= SDRAMC_DARCn_IMRS;
+ asm("nop");
/* Write to the SDRAM Mode Register */
*(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
diff --git a/board/freescale/m5275evb/Makefile b/board/freescale/m5275evb/Makefile
index ef0b19e..f337a75 100644
--- a/board/freescale/m5275evb/Makefile
+++ b/board/freescale/m5275evb/Makefile
@@ -31,7 +31,7 @@
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): .depend $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
diff --git a/board/freescale/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c
index efa952c..ad80694 100644
--- a/board/freescale/mpc7448hpc2/tsi108_init.c
+++ b/board/freescale/mpc7448hpc2/tsi108_init.c
@@ -165,8 +165,8 @@
printf ("Invalid DDR2 clock setting\n");
return -1;
}
- printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
- printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
+ printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000);
+ printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
return 0;
}
@@ -622,8 +622,8 @@
#ifdef CFG_L2
l2cache_enable ();
#endif
- printf ("BUS: %d MHz\n", gd->bus_clk / 1000000);
- printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
+ printf ("BUS: %lu MHz\n", gd->bus_clk / 1000000);
+ printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
/*
* All the information needed to print the cache details is avaiblable
diff --git a/board/integratorcp/flash.c b/board/integratorcp/flash.c
index b653c05..59961cd 100644
--- a/board/integratorcp/flash.c
+++ b/board/integratorcp/flash.c
@@ -393,7 +393,7 @@
*addr = (FPW) 0x00D000D0;
} else {
#ifdef DEBUG
- printf ("Timeout,0x%08x\n", status);
+ printf ("Timeout,0x%08lx\n", status);
#else
printf("Timeout\n");
#endif
@@ -515,7 +515,7 @@
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
- printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+ printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
return (2);
}
@@ -542,7 +542,7 @@
#ifdef DEBUG
*addr = (FPW) 0x00700070;
status = *addr;
- printf("## status=0x%08x, addr=0x%08x\n", status, addr);
+ printf("## status=0x%08lx, addr=0x%p\n", status, addr);
#endif
*addr = (FPW) 0x00500050; /* clear status register cmd */
*addr = (FPW) 0x00FF00FF; /* restore read mode */
diff --git a/board/mp2usb/flash.c b/board/mp2usb/flash.c
index 89ced16..c19d445 100644
--- a/board/mp2usb/flash.c
+++ b/board/mp2usb/flash.c
@@ -426,7 +426,7 @@
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
- printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+ printf ("not erased at %08lx (%lx)\n", (ulong) addr, (ulong) *addr);
return (2);
}
/*
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
index 80e84ae..66a958c 100644
--- a/board/netstal/hcu5/sdram.c
+++ b/board/netstal/hcu5/sdram.c
@@ -71,7 +71,7 @@
}
get_sys_info(&board_cfg);
- printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
+ printf(", %lu MHz", (board_cfg.freqPLB * 2) / 1000000);
mfsdram(DDR0_03, val);
val = DDR0_03_CASLAT_DECODE(val);
diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
index 63c91dc..c38850d 100644
--- a/board/sandburst/metrobox/metrobox.c
+++ b/board/sandburst/metrobox/metrobox.c
@@ -282,7 +282,7 @@
}
printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
- printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, (char *)board_id_as[brd_id]);
+ printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name);
/* Fix the ack in the bme 32 */
udelay(5000);
diff --git a/board/versatile/flash.c b/board/versatile/flash.c
index ca77c8a..bbe5df7 100644
--- a/board/versatile/flash.c
+++ b/board/versatile/flash.c
@@ -476,7 +476,7 @@
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
- printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+ printf ("not erased at %08lx (%lx)\n", (ulong) addr, (ulong) *addr);
return (2);
}
diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c
index aa3932a..ca16578 100644
--- a/board/zylonite/nand.c
+++ b/board/zylonite/nand.c
@@ -254,7 +254,7 @@
break;
}
if(get_delta(start) > timeout) {
- DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
+ DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
return 0xff000000;
}
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index 85a0f94..7089706 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -99,7 +99,8 @@
}
}
- printf("\nEnvironment size: %d/%d bytes\n", i, ENV_SIZE);
+ printf("\nEnvironment size: %d/%ld bytes\n",
+ i, (ulong)ENV_SIZE);
return 0;
}
diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c
index aff11d1..ce99a38 100644
--- a/common/cmd_onenand.c
+++ b/common/cmd_onenand.c
@@ -70,14 +70,14 @@
if (!end || end < 0)
end = start;
- printf("Erase block from %d to %d\n", start, end);
+ printf("Erase block from %lu to %lu\n", start, end);
for (block = start; block <= end; block++) {
instr.addr = block << onenand_chip.erase_shift;
instr.len = 1 << onenand_chip.erase_shift;
ret = onenand_erase(&onenand_mtd, &instr);
if (ret) {
- printf("erase failed %d\n", block);
+ printf("erase failed %lu\n", block);
break;
}
}
diff --git a/common/env_onenand.c b/common/env_onenand.c
index ac8a8c1..ad5b1d7 100644
--- a/common/env_onenand.c
+++ b/common/env_onenand.c
@@ -103,7 +103,7 @@
instr.addr = env_addr;
instr.addr -= (unsigned long)onenand_chip.base;
if (onenand_erase(&onenand_mtd, &instr)) {
- printf("OneNAND: erase failed at 0x%08x\n", env_addr);
+ printf("OneNAND: erase failed at 0x%08lx\n", env_addr);
return 1;
}
diff --git a/common/image.c b/common/image.c
index ddd9e8b..535c302 100644
--- a/common/image.c
+++ b/common/image.c
@@ -827,13 +827,13 @@
cfg_noffset = fit_conf_get_node (fit_hdr, fit_uname_config);
if (cfg_noffset < 0) {
debug ("* ramdisk: no such config\n");
- return 0;
+ return 1;
}
rd_noffset = fit_conf_get_ramdisk_node (fit_hdr, cfg_noffset);
if (rd_noffset < 0) {
debug ("* ramdisk: no ramdisk in config\n");
- return 0;
+ return 1;
}
}
#endif
@@ -872,7 +872,7 @@
if (!fit_check_format (fit_hdr)) {
puts ("Bad FIT ramdisk image format!\n");
show_boot_progress (-120);
- return 0;
+ return 1;
}
show_boot_progress (121);
@@ -887,7 +887,7 @@
if (cfg_noffset < 0) {
puts ("Could not find configuration node\n");
show_boot_progress (-122);
- return 0;
+ return 1;
}
fit_uname_config = fdt_get_name (fit_hdr, cfg_noffset, NULL);
printf (" Using '%s' configuration\n", fit_uname_config);
@@ -902,20 +902,20 @@
if (rd_noffset < 0) {
puts ("Could not find subimage node\n");
show_boot_progress (-124);
- return 0;
+ return 1;
}
printf (" Trying '%s' ramdisk subimage\n", fit_uname_ramdisk);
show_boot_progress (125);
if (!fit_check_ramdisk (fit_hdr, rd_noffset, arch, images->verify))
- return 0;
+ return 1;
/* get ramdisk image data address and length */
if (fit_image_get_data (fit_hdr, rd_noffset, &data, &size)) {
puts ("Could not find ramdisk subimage data!\n");
show_boot_progress (-127);
- return 0;
+ return 1;
}
show_boot_progress (128);
@@ -925,7 +925,7 @@
if (fit_image_get_load (fit_hdr, rd_noffset, &rd_load)) {
puts ("Can't get ramdisk subimage load address!\n");
show_boot_progress (-129);
- return 0;
+ return 1;
}
show_boot_progress (129);
diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index 722732e..56c6289 100644
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -134,25 +134,52 @@
return (0);
}
-void icache_enable (void)
+/* cache_bit must be either C1_IC or C1_DC */
+static void cache_enable(uint32_t cache_bit)
{
- ulong reg;
+ uint32_t reg;
- reg = read_p15_c1 (); /* get control reg. */
- cp_delay ();
- write_p15_c1 (reg | C1_IC);
+ reg = read_p15_c1(); /* get control reg. */
+ cp_delay();
+ write_p15_c1(reg | cache_bit);
}
-void icache_disable (void)
+/* cache_bit must be either C1_IC or C1_DC */
+static void cache_disable(uint32_t cache_bit)
{
- ulong reg;
+ uint32_t reg;
- reg = read_p15_c1 ();
- cp_delay ();
- write_p15_c1 (reg & ~C1_IC);
+ reg = read_p15_c1();
+ cp_delay();
+ write_p15_c1(reg & ~cache_bit);
}
-int icache_status (void)
+void icache_enable(void)
{
- return (read_p15_c1 () & C1_IC) != 0;
+ cache_enable(C1_IC);
+}
+
+void icache_disable(void)
+{
+ cache_disable(C1_IC);
+}
+
+int icache_status(void)
+{
+ return (read_p15_c1() & C1_IC) != 0;
+}
+
+void dcache_enable(void)
+{
+ cache_enable(C1_DC);
+}
+
+void dcache_disable(void)
+{
+ cache_disable(C1_DC);
+}
+
+int dcache_status(void)
+{
+ return (read_p15_c1() & C1_DC) != 0;
}
diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c
index 71b053d..cf29559 100644
--- a/cpu/mcf5227x/cpu_init.c
+++ b/cpu/mcf5227x/cpu_init.c
@@ -106,7 +106,7 @@
*/
int cpu_init_r(void)
{
-#ifdef CONFIG_MCFTMR
+#ifdef CONFIG_MCFRTC
volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
u32 oscillator = CFG_RTC_OSCILLATOR;
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 207a37e..344bcee 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -419,8 +419,7 @@
else is doing it! */
#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
- defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
- defined(CFG_CS0_WS)
+ defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS)
MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
@@ -447,8 +446,7 @@
#endif
#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
- defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
- defined(CFG_CS1_WS)
+ defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS)
MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
@@ -476,8 +474,7 @@
#endif
#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
- defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
- defined(CFG_CS2_WS)
+ defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS)
MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
@@ -505,8 +502,7 @@
#endif
#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
- defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
- defined(CFG_CS3_WS)
+ defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS)
MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index 5fafcd8..f6edd5b 100644
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -69,7 +69,7 @@
/* Setup PLL */
pll->syncr = 0x01080000;
- while (!(pll->synsr & FMPLL_SYNSR_LOCK)
+ while (!(pll->synsr & FMPLL_SYNSR_LOCK))
;
pll->syncr = 0x01000000;
while (!(pll->synsr & FMPLL_SYNSR_LOCK))
diff --git a/cpu/mcf5445x/config.mk b/cpu/mcf5445x/config.mk
index 88433f2..67efa07 100644
--- a/cpu/mcf5445x/config.mk
+++ b/cpu/mcf5445x/config.mk
@@ -29,3 +29,9 @@
else
PLATFORM_CPPFLAGS += -m5407 -fPIC
endif
+
+ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
+ifneq (,$(findstring GOT,$(shell $(LD) --help)))
+PLATFORM_LDFLAGS += --got=single
+endif
+endif
diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c
index 585216d..e07748b 100644
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -110,7 +110,7 @@
*/
int cpu_init_r(void)
{
-#ifdef CONFIG_MCFTMR
+#ifdef CONFIG_MCFRTC
volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S
index 3241b27..89ec7bc 100644
--- a/cpu/mcf5445x/start.S
+++ b/cpu/mcf5445x/start.S
@@ -253,7 +253,7 @@
/* exception code */
.globl _fault
_fault:
- jmp _fault
+ bra _fault
.globl _exc_handler
_exc_handler:
diff --git a/cpu/mcf547x_8x/config.mk b/cpu/mcf547x_8x/config.mk
index e5f4385..567b281 100644
--- a/cpu/mcf547x_8x/config.mk
+++ b/cpu/mcf547x_8x/config.mk
@@ -29,3 +29,9 @@
else
PLATFORM_CPPFLAGS += -m5407 -fPIC
endif
+
+ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
+ifneq (,$(findstring GOT,$(shell $(LD) --help)))
+PLATFORM_LDFLAGS += --got=single
+endif
+endif
diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S
index 8b8708d..87355f9 100644
--- a/cpu/mcf547x_8x/start.S
+++ b/cpu/mcf547x_8x/start.S
@@ -259,7 +259,7 @@
/* exception code */
.globl _fault
_fault:
- jmp _fault
+ bra _fault
.globl _exc_handler
_exc_handler:
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index d50a538..9803fcc 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -25,11 +25,11 @@
#define DEBUG
#endif
-#include <asm/processor.h>
-#include <asm-ppc/io.h>
-#include <ppc4xx.h>
#include <common.h>
#include <pci.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <asm-ppc/io.h>
#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c
index 4495a80..2c86a01 100644
--- a/cpu/pxa/mmc.c
+++ b/cpu/pxa/mmc.c
@@ -535,8 +535,10 @@
mmc_dev.removable = 0;
mmc_dev.block_read = mmc_bread;
- printf("Detected: %u blocks of %u bytes (%uMB) ", mmc_dev.lba,
- mmc_dev.blksz, mmc_dev.lba * mmc_dev.blksz / (1024 * 1024));
+ printf("Detected: %lu blocks of %lu bytes (%luMB) ",
+ mmc_dev.lba,
+ mmc_dev.blksz,
+ mmc_dev.lba * mmc_dev.blksz / (1024 * 1024));
}
int
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 065433a..f09f145 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -30,13 +30,13 @@
LIB = $(obj)libhwmon.a
-COBJS-y += adm1021.o
-COBJS-y += ds1621.o
-COBJS-y += ds1722.o
-COBJS-y += ds1775.o
+COBJS-$(CONFIG_DTT_ADM1021) += adm1021.o
+COBJS-$(CONFIG_DTT_DS1621) += ds1621.o
+COBJS-$(CONFIG_DTT_DS1722) += ds1722.o
+COBJS-$(CONFIG_DTT_DS1775) += ds1775.o
COBJS-$(CONFIG_DTT_LM73) += lm73.o
-COBJS-y += lm75.o
-COBJS-y += lm81.o
+COBJS-$(CONFIG_DTT_LM75) += lm75.o
+COBJS-$(CONFIG_DTT_LM81) += lm81.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/hwmon/adm1021.c b/drivers/hwmon/adm1021.c
index 9f65cfb27..b791ec0 100644
--- a/drivers/hwmon/adm1021.c
+++ b/drivers/hwmon/adm1021.c
@@ -33,11 +33,40 @@
#include <common.h>
-#ifdef CONFIG_DTT_ADM1021
-
#include <i2c.h>
#include <dtt.h>
+#define DTT_READ_LOC_VALUE 0x00
+#define DTT_READ_REM_VALUE 0x01
+#define DTT_READ_STATUS 0x02
+#define DTT_READ_CONFIG 0x03
+#define DTT_READ_CONVRATE 0x04
+#define DTT_READ_LOC_HIGHLIM 0x05
+#define DTT_READ_LOC_LOWLIM 0x06
+#define DTT_READ_REM_HIGHLIM 0x07
+#define DTT_READ_REM_LOWLIM 0x08
+#define DTT_READ_DEVID 0xfe
+
+#define DTT_WRITE_CONFIG 0x09
+#define DTT_WRITE_CONVRATE 0x0a
+#define DTT_WRITE_LOC_HIGHLIM 0x0b
+#define DTT_WRITE_LOC_LOWLIM 0x0c
+#define DTT_WRITE_REM_HIGHLIM 0x0d
+#define DTT_WRITE_REM_LOWLIM 0x0e
+#define DTT_WRITE_ONESHOT 0x0f
+
+#define DTT_STATUS_BUSY 0x80 /* 1=ADC Converting */
+#define DTT_STATUS_LHIGH 0x40 /* 1=Local High Temp Limit Tripped */
+#define DTT_STATUS_LLOW 0x20 /* 1=Local Low Temp Limit Tripped */
+#define DTT_STATUS_RHIGH 0x10 /* 1=Remote High Temp Limit Tripped */
+#define DTT_STATUS_RLOW 0x08 /* 1=Remote Low Temp Limit Tripped */
+#define DTT_STATUS_OPEN 0x04 /* 1=Remote Sensor Open-Circuit */
+
+#define DTT_CONFIG_ALERT_MASKED 0x80 /* 0=ALERT Enabled, 1=ALERT Masked */
+#define DTT_CONFIG_STANDBY 0x40 /* 0=Run, 1=Standby */
+
+#define DTT_ADM1021_DEVID 0x41
+
typedef
struct {
uint i2c_addr:7; /* 7bit i2c chip address */
@@ -170,5 +199,3 @@
return (int) val;
} /* dtt_get_temp() */
-
-#endif /* CONFIG_DTT_ADM1021 */
diff --git a/drivers/hwmon/ds1621.c b/drivers/hwmon/ds1621.c
index 4948181..749aa26 100644
--- a/drivers/hwmon/ds1621.c
+++ b/drivers/hwmon/ds1621.c
@@ -27,7 +27,6 @@
#include <common.h>
-#ifdef CONFIG_DTT_DS1621
#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
(CFG_EEPROM_PAGE_WRITE_BITS < 1)
# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_DS1621"
@@ -39,6 +38,14 @@
* Device code
*/
#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */
+#define DTT_READ_TEMP 0xAA
+#define DTT_READ_COUNTER 0xA8
+#define DTT_READ_SLOPE 0xA9
+#define DTT_WRITE_START_CONV 0xEE
+#define DTT_WRITE_STOP_CONV 0x22
+#define DTT_TEMP_HIGH 0xA1
+#define DTT_TEMP_LOW 0xA2
+#define DTT_CONFIG 0xAC
int dtt_read(int sensor, int reg)
{
@@ -185,6 +192,3 @@
return (dtt_read(sensor, DTT_READ_TEMP) / 256);
} /* dtt_get_temp() */
-
-
-#endif /* CONFIG_DTT_DS1621 */
diff --git a/drivers/hwmon/ds1722.c b/drivers/hwmon/ds1722.c
index c19ee01..7e2f1ed 100644
--- a/drivers/hwmon/ds1722.c
+++ b/drivers/hwmon/ds1722.c
@@ -1,8 +1,5 @@
#include <common.h>
-
-#ifdef CONFIG_DS1722
-
#include <ssi.h>
static void ds1722_select(int dev)
@@ -138,5 +135,3 @@
printf("%d.%d deg C\n\n", (char)(temp >> 8), temp & 0xff);
return 0;
}
-
-#endif
diff --git a/drivers/hwmon/ds1775.c b/drivers/hwmon/ds1775.c
index 0fbb0b4..6a4d8e5 100644
--- a/drivers/hwmon/ds1775.c
+++ b/drivers/hwmon/ds1775.c
@@ -21,11 +21,14 @@
#include <common.h>
-#ifdef CONFIG_DTT_DS1775
#include <i2c.h>
#include <dtt.h>
#define DTT_I2C_DEV_CODE CFG_I2C_DTT_ADDR /* Dallas Semi's DS1775 device code */
+#define DTT_READ_TEMP 0x0
+#define DTT_CONFIG 0x1
+#define DTT_TEMP_HYST 0x2
+#define DTT_TEMP_OS 0x3
int dtt_read(int sensor, int reg)
{
@@ -151,6 +154,3 @@
{
return (dtt_read(sensor, DTT_READ_TEMP) / 256);
}
-
-
-#endif /* CONFIG_DTT_DS1775 */
diff --git a/drivers/hwmon/lm73.c b/drivers/hwmon/lm73.c
index 98e8bd2..dd24683 100644
--- a/drivers/hwmon/lm73.c
+++ b/drivers/hwmon/lm73.c
@@ -38,6 +38,12 @@
* Device code
*/
#define DTT_I2C_DEV_CODE 0x48 /* National Semi's LM73 device */
+#define DTT_READ_TEMP 0x0
+#define DTT_CONFIG 0x1
+#define DTT_TEMP_HIGH 0x2
+#define DTT_TEMP_LOW 0x3
+#define DTT_CONTROL 0x4
+#define DTT_ID 0x7
int dtt_read(int const sensor, int const reg)
{
diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c
index c348517..8051cb2 100644
--- a/drivers/hwmon/lm75.c
+++ b/drivers/hwmon/lm75.c
@@ -27,7 +27,6 @@
#include <common.h>
-#ifdef CONFIG_DTT_LM75
#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
(CFG_EEPROM_PAGE_WRITE_BITS < 1)
# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM75"
@@ -36,11 +35,14 @@
#include <i2c.h>
#include <dtt.h>
-
/*
* Device code
*/
#define DTT_I2C_DEV_CODE 0x48 /* ON Semi's LM75 device */
+#define DTT_READ_TEMP 0x0
+#define DTT_CONFIG 0x1
+#define DTT_TEMP_HYST 0x2
+#define DTT_TEMP_SET 0x3
int dtt_read(int sensor, int reg)
{
@@ -200,5 +202,3 @@
}
return (int)((int16_t) ret / 256);
} /* dtt_get_temp() */
-
-#endif /* CONFIG_DTT_LM75 */
diff --git a/drivers/hwmon/lm81.c b/drivers/hwmon/lm81.c
index 03bc53d..9349eb6 100644
--- a/drivers/hwmon/lm81.c
+++ b/drivers/hwmon/lm81.c
@@ -32,7 +32,6 @@
#include <common.h>
-#ifdef CONFIG_DTT_LM81
#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
(CFG_EEPROM_PAGE_WRITE_BITS < 1)
# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM81"
@@ -45,6 +44,11 @@
* Device code
*/
#define DTT_I2C_DEV_CODE 0x2c /* ON Semi's LM81 device */
+#define DTT_READ_TEMP 0x27
+#define DTT_CONFIG_TEMP 0x4b
+#define DTT_TEMP_MAX 0x39
+#define DTT_TEMP_HYST 0x3a
+#define DTT_CONFIG 0x40
int dtt_read(int sensor, int reg)
{
@@ -144,5 +148,3 @@
return (TEMP_FROM_REG((val << 1) + ((tmpcnf & 0x80) >> 7))) / 10;
} /* dtt_get_temp() */
-
-#endif /* CONFIG_DTT_LM81 */
diff --git a/drivers/mtd/dataflash.c b/drivers/mtd/dataflash.c
index 8247aa0..0ad48cd 100644
--- a/drivers/mtd/dataflash.c
+++ b/drivers/mtd/dataflash.c
@@ -54,6 +54,17 @@
&dataflash_info[i].Desc);
switch (dfcode) {
+ case AT45DB021:
+ dataflash_info[i].Device.pages_number = 1024;
+ dataflash_info[i].Device.pages_size = 263;
+ dataflash_info[i].Device.page_offset = 9;
+ dataflash_info[i].Device.byte_mask = 0x300;
+ dataflash_info[i].Device.cs = cs[i].cs;
+ dataflash_info[i].Desc.DataFlash_state = IDLE;
+ dataflash_info[i].logical_address = cs[i].addr;
+ dataflash_info[i].id = dfcode;
+ found[i] += dfcode;;
+ break;
case AT45DB161:
dataflash_info[i].Device.pages_number = 4096;
dataflash_info[i].Device.pages_size = 528;
@@ -162,7 +173,7 @@
if((env & FLAG_SETENV) == FLAG_SETENV) {
start =
dataflash_info[i].Device.area_list[j].start;
- sprintf((char*) s,"%X",start);
+ sprintf((char*) s,"%lX",start);
setenv((char*) area_list[part].label,(char*) s);
}
part++;
@@ -178,6 +189,9 @@
if (dataflash_info[i].id != 0) {
printf("DataFlash:");
switch (dataflash_info[i].id) {
+ case AT45DB021:
+ printf("AT45DB021\n");
+ break;
case AT45DB161:
printf("AT45DB161\n");
break;
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 1484b0b..0fff820 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -597,7 +597,7 @@
val = reg_read(BYTE_TEST);
if (val != 0x87654321) {
- printf(DRIVERNAME ": Invalid chip endian 0x%08x\n", val);
+ printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
goto err_out;
}
@@ -606,7 +606,7 @@
if (chip_ids[i].id == val) break;
}
if (!chip_ids[i].id) {
- printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
+ printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
goto err_out;
}
diff --git a/drivers/net/tsi108_eth.c b/drivers/net/tsi108_eth.c
index 57c0dc3..2534097 100644
--- a/drivers/net/tsi108_eth.c
+++ b/drivers/net/tsi108_eth.c
@@ -899,7 +899,7 @@
status = le32_to_cpu(tx_descr->config_status);
if ((status & DMA_DESCR_TX_OK) == 0) {
#ifdef TX_PRINT_ERRORS
- printf ("TX packet error: 0x%08x\n %s%s%s%s\n", status,
+ printf ("TX packet error: 0x%08lx\n %s%s%s%s\n", status,
status & DMA_DESCR_TX_OK ? "tx error, " : "",
status & DMA_DESCR_TX_RETRY_LIMIT ?
"retry limit reached, " : "",
@@ -959,7 +959,7 @@
status = le32_to_cpu(rx_descr->config_status);
if (status & DMA_DESCR_RX_BAD_FRAME) {
#ifdef RX_PRINT_ERRORS
- printf ("RX packet error: 0x%08x\n %s%s%s%s%s%s\n",
+ printf ("RX packet error: 0x%08lx\n %s%s%s%s%s%s\n",
status,
status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, "
: "",
diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c
index 88f3eb1..5eb4f45 100644
--- a/drivers/serial/mcfuart.c
+++ b/drivers/serial/mcfuart.c
@@ -63,8 +63,8 @@
uart->umr = UART_UMR_SB_STOP_BITS_1;
/* Setting up BaudRate */
- counter = (u32) (gd->bus_clk / (gd->baudrate));
- counter >>= 5;
+ counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
+ counter = counter / gd->baudrate;
/* write to CTUR: divide counter upper byte */
uart->ubg1 = (u8) ((counter & 0xff00) >> 8);
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 182ca2d..4ccaee2 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -124,6 +124,8 @@
static int calc_divisor (NS16550_t port)
{
+ uint32_t clk_divisor;
+
#ifdef CONFIG_OMAP1510
/* If can't cleanly clock 115200 set div to 1 */
if ((CFG_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) {
@@ -147,10 +149,15 @@
/* Compute divisor value. Normally, we should simply return:
* CFG_NS16550_CLK) / MODE_X_DIV / gd->baudrate
- * but we need to round that value by adding 0.5 or 8/16.
+ * but we need to round that value by adding 0.5 (2/4).
* Rounding is especially important at high baud rates.
*/
- return (((16 * CFG_NS16550_CLK) / MODE_X_DIV / gd->baudrate) + 8) / 16;
+ clk_divisor = (((4 * CFG_NS16550_CLK) /
+ (MODE_X_DIV * gd->baudrate)) + 2) / 4;
+
+ debug("NS16550 clock divisor = %d\n", clk_divisor);
+
+ return clk_divisor;
}
#if !defined(CONFIG_SERIAL_MULTI)
diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c
index d678ab6..5c41a1c 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -1,6 +1,8 @@
/*
- * (C) Copyright 2004 Atmark Techno, Inc.
+ * (C) Copyright 2008 Michal Simek <monstr@monstr.eu>
+ * Clean driver and add xilinx constant from header file
*
+ * (C) Copyright 2004 Atmark Techno, Inc.
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
@@ -13,7 +15,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -23,19 +25,21 @@
*/
#include <config.h>
+#include <asm/io.h>
#ifdef CONFIG_XILINX_UARTLITE
-#include <asm/serial_xuartlite.h>
+#define RX_FIFO_OFFSET 0 /* receive FIFO, read only */
+#define TX_FIFO_OFFSET 4 /* transmit FIFO, write only */
+#define STATUS_REG_OFFSET 8 /* status register, read only */
-/* FIXME: we should convert these to in32 and out32 */
-#define IO_WORD(offset) (*(volatile unsigned long *)(offset))
-#define IO_SERIAL(offset) IO_WORD(CONFIG_SERIAL_BASE + (offset))
+#define SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
+#define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
+#define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
-#define IO_SERIAL_RX_FIFO IO_SERIAL(XUL_RX_FIFO_OFFSET)
-#define IO_SERIAL_TX_FIFO IO_SERIAL(XUL_TX_FIFO_OFFSET)
-#define IO_SERIAL_STATUS IO_SERIAL(XUL_STATUS_REG_OFFSET)
-#define IO_SERIAL_CONTROL IO_SERIAL(XUL_CONTROL_REG_OFFSET)
+#define UARTLITE_STATUS (CONFIG_SERIAL_BASE + STATUS_REG_OFFSET)
+#define UARTLITE_TX_FIFO (CONFIG_SERIAL_BASE + TX_FIFO_OFFSET)
+#define UARTLITE_RX_FIFO (CONFIG_SERIAL_BASE + RX_FIFO_OFFSET)
int serial_init(void)
{
@@ -50,9 +54,10 @@
void serial_putc(const char c)
{
- if (c == '\n') serial_putc('\r');
- while (IO_SERIAL_STATUS & XUL_SR_TX_FIFO_FULL);
- IO_SERIAL_TX_FIFO = (unsigned char) (c & 0xff);
+ if (c == '\n')
+ serial_putc('\r');
+ while (in_be32(UARTLITE_STATUS) & SR_TX_FIFO_FULL);
+ out_be32(UARTLITE_TX_FIFO, (unsigned char) (c & 0xff));
}
void serial_puts(const char * s)
@@ -64,13 +69,13 @@
int serial_getc(void)
{
- while (!(IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA));
- return IO_SERIAL_RX_FIFO & 0xff;
+ while (!(in_be32(UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA));
+ return in_be32(UARTLITE_RX_FIFO) & 0xff;
}
int serial_tstc(void)
{
- return (IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA);
+ return (in_be32(UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA);
}
#endif /* CONFIG_MICROBLZE */
diff --git a/drivers/usb/usbdcore.c b/drivers/usb/usbdcore.c
index a621ce7..808da9f 100644
--- a/drivers/usb/usbdcore.c
+++ b/drivers/usb/usbdcore.c
@@ -546,21 +546,23 @@
*
* NOTE: endpoint_address MUST contain a direction flag.
*/
-struct urb *usbd_alloc_urb (struct usb_device_instance *device, struct usb_endpoint_instance *endpoint)
+struct urb *usbd_alloc_urb (struct usb_device_instance *device,
+ struct usb_endpoint_instance *endpoint)
{
struct urb *urb;
- if( !(urb = (struct urb*)malloc(sizeof(struct urb))) ) {
- usberr(" F A T A L: malloc(%u) FAILED!!!!", sizeof(struct urb));
- return NULL;
+ if (!(urb = (struct urb *) malloc (sizeof (struct urb)))) {
+ usberr (" F A T A L: malloc(%u) FAILED!!!!",
+ sizeof (struct urb));
+ return NULL;
}
/* Fill in known fields */
- memset(urb, 0, sizeof(struct urb));
+ memset (urb, 0, sizeof (struct urb));
urb->endpoint = endpoint;
urb->device = device;
- urb->buffer = (u8*)urb->buffer_data;
- urb->buffer_length = sizeof(urb->buffer_data);
+ urb->buffer = (u8 *) urb->buffer_data;
+ urb->buffer_length = sizeof (urb->buffer_data);
urb_link_init (&urb->link);
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c
index 9684cf3..733d9a2 100644
--- a/drivers/video/mb862xx.c
+++ b/drivers/video/mb862xx.c
@@ -173,6 +173,8 @@
DE_WR_FIFO (0x09410000);
DE_WR_FIFO (0x00000000);
DE_WR_FIFO (pGD->winSizeY<<16 | pGD->winSizeX);
+ /* sync with SW access to framebuffer */
+ de_wait ();
}
#if defined(CONFIG_VIDEO_CORALP)
diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index d1423c1..5c1d265 100644
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -1213,12 +1213,12 @@
} else if (node->nodetype == JFFS2_NODETYPE_CLEANMARKER) {
if (node->totlen != sizeof(struct jffs2_unknown_node))
printf("OOPS Cleanmarker has bad size "
- "%d != %d\n", node->totlen,
+ "%d != %u\n", node->totlen,
sizeof(struct jffs2_unknown_node));
} else if (node->nodetype == JFFS2_NODETYPE_PADDING) {
if (node->totlen < sizeof(struct jffs2_unknown_node))
printf("OOPS Padding has bad size "
- "%d < %d\n", node->totlen,
+ "%d < %u\n", node->totlen,
sizeof(struct jffs2_unknown_node));
} else {
printf("Unknown node type: %x len %d "
diff --git a/include/asm-m68k/timer.h b/include/asm-m68k/timer.h
index 030720c..1a5de05 100644
--- a/include/asm-m68k/timer.h
+++ b/include/asm-m68k/timer.h
@@ -33,7 +33,7 @@
/****************************************************************************/
/* DMA Timer module registers */
typedef struct dtimer_ctrl {
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272)
u16 tmr; /* 0x00 Mode register */
u16 res1; /* 0x02 */
u16 trr; /* 0x04 Reference register */
diff --git a/include/asm-microblaze/arch-microblaze/xbasic_types.h b/include/asm-microblaze/arch-microblaze/xbasic_types.h
deleted file mode 100644
index 25012e6..0000000
--- a/include/asm-microblaze/arch-microblaze/xbasic_types.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2003 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.h
-*
-* This file contains basic types for Xilinx software IP. These types do not
-* follow the standard naming convention with respect to using the component
-* name in front of each name because they are considered to be primitives.
-*
-* @note
-*
-* This file contains items which are architecture dependent.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 12/14/01 First release
-* rmm 05/09/03 Added "xassert always" macros to rid ourselves of diab
-* compiler warnings
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
-#define XBASIC_TYPES_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-/** Null */
-
-#define XCOMPONENT_IS_READY 0x11111111 /* component has been initialized */
-#define XCOMPONENT_IS_STARTED 0x22222222 /* component has been started */
-
-/* the following constants and declarations are for unit test purposes and are
- * designed to be used in test applications.
- */
-#define XTEST_PASSED 0
-#define XTEST_FAILED 1
-
-#define XASSERT_NONE 0
-#define XASSERT_OCCURRED 1
-
-extern unsigned int XAssertStatus;
-extern void XAssert(char *, int);
-
-/**************************** Type Definitions *******************************/
-
-/** @name Primitive types
- * These primitive types are created for transportability.
- * They are dependent upon the target architecture.
- * @{
- */
-#include <linux/types.h>
-
-typedef struct {
- u32 Upper;
- u32 Lower;
-} Xuint64;
-
-/* Xilinx's unsigned integer types */
-typedef u32 Xuint32;
-typedef u16 Xuint16;
-typedef u8 Xuint8;
-
-/* and signed integer types */
-typedef s32 Xint32;
-typedef s16 Xint16;
-typedef s8 Xint8;
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-typedef unsigned long Xboolean;
-#define XNULL NULL
-
-#define XTRUE 1
-#define XFALSE 0
-
-/*@}*/
-
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Return the most significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return
-*
-* The upper 32 bits of the 64 bit word.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XUINT64_MSW(x) ((x).Upper)
-
-/*****************************************************************************/
-/**
-* Return the least significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return
-*
-* The lower 32 bits of the 64 bit word.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XUINT64_LSW(x) ((x).Lower)
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* This assert macro is to be used for functions that do not return anything
-* (void). This in conjunction with the XWaitInAssert boolean can be used to
-* accomodate tests so that asserts which fail allow execution to continue.
-*
-* @param expression is the expression to evaluate. If it evaluates to false,
-* the assert occurs.
-*
-* @return
-*
-* Returns void unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_VOID(expression) \
-{ \
- if (expression) { \
- XAssertStatus = XASSERT_NONE; \
- } else { \
- XAssert(__FILE__, __LINE__); \
- XAssertStatus = XASSERT_OCCURRED; \
- return; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* This assert macro is to be used for functions that do return a value. This in
-* conjunction with the XWaitInAssert boolean can be used to accomodate tests so
-* that asserts which fail allow execution to continue.
-*
-* @param expression is the expression to evaluate. If it evaluates to false,
-* the assert occurs.
-*
-* @return
-*
-* Returns 0 unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_NONVOID(expression) \
-{ \
- if (expression) { \
- XAssertStatus = XASSERT_NONE; \
- } else { \
- XAssert(__FILE__, __LINE__); \
- XAssertStatus = XASSERT_OCCURRED; \
- return 0; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* Always assert. This assert macro is to be used for functions that do not
-* return anything (void). Use for instances where an assert should always
-* occur.
-*
-* @return
-*
-* Returns void unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_VOID_ALWAYS() \
-{ \
- XAssert(__FILE__, __LINE__); \
- XAssertStatus = XASSERT_OCCURRED; \
- return; \
-}
-
-/*****************************************************************************/
-/**
-* Always assert. This assert macro is to be used for functions that do return
-* a value. Use for instances where an assert should always occur.
-*
-* @return
-*
-* Returns void unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_NONVOID_ALWAYS() \
-{ \
- XAssert(__FILE__, __LINE__); \
- XAssertStatus = XASSERT_OCCURRED; \
- return 0; \
-}
-
-#else
-
-#define XASSERT_VOID(expression)
-#define XASSERT_VOID_ALWAYS()
-#define XASSERT_NONVOID(expression)
-#define XASSERT_NONVOID_ALWAYS()
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void XAssertSetCallback(XAssertCallback Routine);
-
-#endif /* end of protection macro */
diff --git a/include/asm-microblaze/arch-microblaze/xio.h b/include/asm-microblaze/arch-microblaze/xio.h
deleted file mode 100644
index 7eed327..0000000
--- a/include/asm-microblaze/arch-microblaze/xio.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * xio.h
- *
- * Defines XIo functions for Xilinx OCP in terms of Linux primitives
- *
- * Author: MontaVista Software, Inc.
- * source@mvista.com
- *
- * 2002 (c) MontaVista, Software, Inc. This file is licensed under the terms
- * of the GNU General Public License version 2. This program is licensed
- * "as is" without any warranty of any kind, whether express or implied.
- */
-
-#ifndef XIO_H
-#define XIO_H
-
-#include "xbasic_types.h"
-#include <asm/io.h>
-
-typedef u32 XIo_Address;
-
-extern inline u8
-XIo_In8(XIo_Address InAddress)
-{
- return (u8) in_8((volatile unsigned char *) InAddress);
-}
-extern inline u16
-XIo_In16(XIo_Address InAddress)
-{
- return (u16) in_be16((volatile unsigned short *) InAddress);
-}
-extern inline u32
-XIo_In32(XIo_Address InAddress)
-{
- return (u32) in_be32((volatile unsigned *) InAddress);
-}
-extern inline void
-XIo_Out8(XIo_Address OutAddress, u8 Value)
-{
- out_8((volatile unsigned char *) OutAddress, Value);
-}
-extern inline void
-XIo_Out16(XIo_Address OutAddress, u16 Value)
-{
- out_be16((volatile unsigned short *) OutAddress, Value);
-}
-extern inline void
-XIo_Out32(XIo_Address OutAddress, u32 Value)
-{
- out_be32((volatile unsigned *) OutAddress, Value);
-}
-
-#define XIo_ToLittleEndian16(s,d) (*(u16*)(d) = cpu_to_le16((u16)(s)))
-#define XIo_ToLittleEndian32(s,d) (*(u32*)(d) = cpu_to_le32((u32)(s)))
-#define XIo_ToBigEndian16(s,d) (*(u16*)(d) = cpu_to_be16((u16)(s)))
-#define XIo_ToBigEndian32(s,d) (*(u32*)(d) = cpu_to_be32((u32)(s)))
-
-#define XIo_FromLittleEndian16(s,d) (*(u16*)(d) = le16_to_cpu((u16)(s)))
-#define XIo_FromLittleEndian32(s,d) (*(u32*)(d) = le32_to_cpu((u32)(s)))
-#define XIo_FromBigEndian16(s,d) (*(u16*)(d) = be16_to_cpu((u16)(s)))
-#define XIo_FromBigEndian32(s,d) (*(u32*)(d) = be32_to_cpu((u32)(s)))
-
-#endif /* XIO_H */
diff --git a/include/asm-microblaze/arch-microblaze/xuartlite_l.h b/include/asm-microblaze/arch-microblaze/xuartlite_l.h
deleted file mode 100644
index b381a0d..0000000
--- a/include/asm-microblaze/arch-microblaze/xuartlite_l.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/*****************************************************************************
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
-* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE.
-*
-* (c) Copyright 2002 Xilinx Inc.
-* All rights reserved.
-*
-*****************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartlite_l.h
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the device. High-level driver functions
-* are defined in xuartlite.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b rpm 04/25/02 First release
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XUARTLITE_L_H /* prevent circular inclusions */
-#define XUARTLITE_L_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xbasic_types.h"
-#include "xio.h"
-
-/************************** Constant Definitions ****************************/
-
-/* UART Lite register offsets */
-
-#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */
-#define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */
-#define XUL_STATUS_REG_OFFSET 8 /* status register, read only */
-#define XUL_CONTROL_REG_OFFSET 12 /* control register, write only */
-
-/* control register bit positions */
-
-#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */
-#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */
-#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */
-
-/* status register bit positions */
-
-#define XUL_SR_PARITY_ERROR 0x80
-#define XUL_SR_FRAMING_ERROR 0x40
-#define XUL_SR_OVERRUN_ERROR 0x20
-#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */
-#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
-#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */
-#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
-#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
-
-/* the following constant specifies the size of the FIFOs, the size of the
- * FIFOs includes the transmitter and receiver such that it is the total number
- * of bytes that the UART can buffer
- */
-#define XUL_FIFO_SIZE 16
-
-/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a
- * per instance basis
- */
-#define XUL_STOP_BITS 1
-
-/* Parity definitions
- */
-#define XUL_PARITY_NONE 0
-#define XUL_PARITY_ODD 1
-#define XUL_PARITY_EVEN 2
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/*****************************************************************************
-*
-* Low-level driver macros and functions. The list below provides signatures
-* to help the user use the macros.
-*
-* void XUartLite_mSetControlReg(u32 BaseAddress, u32 Mask)
-* u32 XUartLite_mGetControlReg(u32 BaseAddress)
-* u32 XUartLite_mGetStatusReg(u32 BaseAddress)
-*
-* Xboolean XUartLite_mIsReceiveEmpty(u32 BaseAddress)
-* Xboolean XUartLite_mIsTransmitFull(u32 BaseAddress)
-* Xboolean XUartLite_mIsIntrEnabled(u32 BaseAddress)
-*
-* void XUartLite_mEnableIntr(u32 BaseAddress)
-* void XUartLite_mDisableIntr(u32 BaseAddress)
-*
-* void XUartLite_SendByte(u32 BaseAddress, u8 Data);
-* u8 XUartLite_RecvByte(u32 BaseAddress);
-*
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the control register. Use the XUL_CR_* constants defined
-* above to create the bit-mask to be written to the register.
-*
-* @param BaseAddress is the base address of the device
-* @param Mask is the 32-bit value to write to the control register
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XUartLite_mSetControlReg(BaseAddress, Mask) \
- XIo_Out32((BaseAddress) + XUL_CONTROL_REG_OFFSET, (Mask))
-
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the control register. Use the XUL_CR_* constants defined
-* above to interpret the bit-mask returned.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return A 32-bit value representing the contents of the control register.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XUartLite_mGetControlReg(BaseAddress) \
- XIo_In32((BaseAddress) + XUL_CONTROL_REG_OFFSET)
-
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the status register. Use the XUL_SR_* constants defined
-* above to interpret the bit-mask returned.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return A 32-bit value representing the contents of the status register.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XUartLite_mGetStatusReg(BaseAddress) \
- XIo_In32((BaseAddress) + XUL_STATUS_REG_OFFSET)
-
-
-/****************************************************************************/
-/**
-*
-* Check to see if the receiver has data.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return XTRUE if the receiver is empty, XFALSE if there is data present.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XUartLite_mIsReceiveEmpty(BaseAddress) \
- (!(XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA))
-
-
-/****************************************************************************/
-/**
-*
-* Check to see if the transmitter is full.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return XTRUE if the transmitter is full, XFALSE otherwise.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XUartLite_mIsTransmitFull(BaseAddress) \
- (XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL)
-
-
-/****************************************************************************/
-/**
-*
-* Check to see if the interrupt is enabled.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return XTRUE if the interrupt is enabled, XFALSE otherwise.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XUartLite_mIsIntrEnabled(BaseAddress) \
- (XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED)
-
-
-/****************************************************************************/
-/**
-*
-* Enable the device interrupt. Preserve the contents of the control register.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XUartLite_mEnableIntr(BaseAddress) \
- XUartLite_mSetControlReg((BaseAddress), \
- XUartLite_mGetControlReg((BaseAddress)) | XUL_CR_ENABLE_INTR)
-
-
-/****************************************************************************/
-/**
-*
-* Disable the device interrupt. Preserve the contents of the control register.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XUartLite_mDisableIntr(BaseAddress) \
- XUartLite_mSetControlReg((BaseAddress), \
- XUartLite_mGetControlReg((BaseAddress)) & ~XUL_CR_ENABLE_INTR)
-
-
-/************************** Function Prototypes *****************************/
-
-void XUartLite_SendByte(u32 BaseAddress, u8 Data);
-u8 XUartLite_RecvByte(u32 BaseAddress);
-
-
-#endif /* end of protection macro */
diff --git a/include/asm-microblaze/io.h b/include/asm-microblaze/io.h
index aa37a60..8804724 100644
--- a/include/asm-microblaze/io.h
+++ b/include/asm-microblaze/io.h
@@ -16,6 +16,8 @@
#ifndef __MICROBLAZE_IO_H__
#define __MICROBLAZE_IO_H__
+#include <asm/types.h>
+
#define IO_SPACE_LIMIT 0xFFFFFFFF
#define readb(addr) \
diff --git a/include/asm-microblaze/serial_xuartlite.h b/include/asm-microblaze/serial_xuartlite.h
deleted file mode 100644
index 6cd1e83..0000000
--- a/include/asm-microblaze/serial_xuartlite.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * (C) Copyright 2004 Atmark Techno, Inc.
- *
- * Yasushi SHOJI <yashi@atmark-techno.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/xuartlite_l.h>
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index 417099e..324eb6c 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -84,6 +84,8 @@
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
+#define CONFIG_MCFTMR
+
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_MULTI 1
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index a19c342..e8804b5 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -303,9 +303,9 @@
#define CFG_CS0_CTRL 0x00101980
#ifdef CFG_NOR1SZ
-#define CFG_CS1_BASE 0xF8000000
+#define CFG_CS1_BASE 0xE0000000
#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
-#define CFG_CS1_CTRL 0x00000D80
+#define CFG_CS1_CTRL 0x00101D80
#endif
#endif /* _M5475EVB_H */
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index b73e2e0..0f957ff 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -289,9 +289,9 @@
#define CFG_CS0_CTRL 0x00101980
#ifdef CFG_NOR1SZ
-#define CFG_CS1_BASE 0xF8000000
+#define CFG_CS1_BASE 0xE0000000
#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
-#define CFG_CS1_CTRL 0x00000D80
+#define CFG_CS1_CTRL 0x00101D80
#endif
#endif /* _M5485EVB_H */
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index 0e49e6c..7c860e5 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -137,6 +137,7 @@
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_NAND
#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index 4a9cadb..b7ea1a9 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -208,6 +208,10 @@
/* "protect off" */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+/* #define CONFIG_INITRD_TAG 1 */
+
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h
index 051b2e0..072675b 100644
--- a/include/configs/sc520_spunk.h
+++ b/include/configs/sc520_spunk.h
@@ -144,7 +144,7 @@
#define CONFIG_SPI_EEPROM /* SPI EEPROMs such as AT25010 or AT25640 */
#define CONFIG_MW_EEPROM /* MicroWire EEPROMS such as AT93LC46 */
-#define CONFIG_DS1722 /* Dallas DS1722 SPI Temperature probe */
+#define CONFIG_DTT_DS1722 /* Dallas DS1722 SPI Temperature probe */
/* allow to overwrite serial and ethaddr */
diff --git a/include/dataflash.h b/include/dataflash.h
index f20c738..80f0633 100644
--- a/include/dataflash.h
+++ b/include/dataflash.h
@@ -137,6 +137,7 @@
/*-------------------------------------------------------------------------------------------------*/
#define AT45DB161 0x2c
+#define AT45DB021 0x14
#define AT45DB321 0x34
#define AT45DB642 0x3c
#define AT45DB128 0x10
diff --git a/include/dtt.h b/include/dtt.h
index 4e8aaad..34053d1 100644
--- a/include/dtt.h
+++ b/include/dtt.h
@@ -40,9 +40,11 @@
#define DTT_COMMERCIAL_MAX_TEMP 70 /* 0 - +70 C */
#define DTT_INDUSTRIAL_MAX_TEMP 85 /* -40 - +85 C */
#define DTT_AUTOMOTIVE_MAX_TEMP 105 /* -40 - +105 C */
+
#ifndef CFG_DTT_MAX_TEMP
#define CFG_DTT_MAX_TEMP DTT_COMMERCIAL_MAX_TEMP
#endif
+
#ifndef CFG_DTT_HYSTERESIS
#define CFG_DTT_HYSTERESIS 5 /* 5 C */
#endif
@@ -54,79 +56,4 @@
extern int dtt_get_temp(int sensor);
#endif
-#if defined(CONFIG_DTT_LM75)
-#define DTT_READ_TEMP 0x0
-#define DTT_CONFIG 0x1
-#define DTT_TEMP_HYST 0x2
-#define DTT_TEMP_SET 0x3
-#endif
-
-#if defined(CONFIG_DTT_LM81)
-#define DTT_READ_TEMP 0x27
-#define DTT_CONFIG_TEMP 0x4b
-#define DTT_TEMP_MAX 0x39
-#define DTT_TEMP_HYST 0x3a
-#define DTT_CONFIG 0x40
-#endif
-
-#if defined(CONFIG_DTT_DS1621)
-#define DTT_READ_TEMP 0xAA
-#define DTT_READ_COUNTER 0xA8
-#define DTT_READ_SLOPE 0xA9
-#define DTT_WRITE_START_CONV 0xEE
-#define DTT_WRITE_STOP_CONV 0x22
-#define DTT_TEMP_HIGH 0xA1
-#define DTT_TEMP_LOW 0xA2
-#define DTT_CONFIG 0xAC
-#endif
-
-#if defined(CONFIG_DTT_DS1775)
-#define DTT_READ_TEMP 0x0
-#define DTT_CONFIG 0x1
-#define DTT_TEMP_HYST 0x2
-#define DTT_TEMP_OS 0x3
-#endif
-
-#if defined(CONFIG_DTT_ADM1021)
-#define DTT_READ_LOC_VALUE 0x00
-#define DTT_READ_REM_VALUE 0x01
-#define DTT_READ_STATUS 0x02
-#define DTT_READ_CONFIG 0x03
-#define DTT_READ_CONVRATE 0x04
-#define DTT_READ_LOC_HIGHLIM 0x05
-#define DTT_READ_LOC_LOWLIM 0x06
-#define DTT_READ_REM_HIGHLIM 0x07
-#define DTT_READ_REM_LOWLIM 0x08
-#define DTT_READ_DEVID 0xfe
-
-#define DTT_WRITE_CONFIG 0x09
-#define DTT_WRITE_CONVRATE 0x0a
-#define DTT_WRITE_LOC_HIGHLIM 0x0b
-#define DTT_WRITE_LOC_LOWLIM 0x0c
-#define DTT_WRITE_REM_HIGHLIM 0x0d
-#define DTT_WRITE_REM_LOWLIM 0x0e
-#define DTT_WRITE_ONESHOT 0x0f
-
-#define DTT_STATUS_BUSY 0x80 /* 1=ADC Converting */
-#define DTT_STATUS_LHIGH 0x40 /* 1=Local High Temp Limit Tripped */
-#define DTT_STATUS_LLOW 0x20 /* 1=Local Low Temp Limit Tripped */
-#define DTT_STATUS_RHIGH 0x10 /* 1=Remote High Temp Limit Tripped */
-#define DTT_STATUS_RLOW 0x08 /* 1=Remote Low Temp Limit Tripped */
-#define DTT_STATUS_OPEN 0x04 /* 1=Remote Sensor Open-Circuit */
-
-#define DTT_CONFIG_ALERT_MASKED 0x80 /* 0=ALERT Enabled, 1=ALERT Masked */
-#define DTT_CONFIG_STANDBY 0x40 /* 0=Run, 1=Standby */
-
-#define DTT_ADM1021_DEVID 0x41
-#endif
-
-#if defined(CONFIG_DTT_LM73)
-#define DTT_READ_TEMP 0x0
-#define DTT_CONFIG 0x1
-#define DTT_TEMP_HIGH 0x2
-#define DTT_TEMP_LOW 0x3
-#define DTT_CONTROL 0x4
-#define DTT_ID 0x7
-#endif
-
#endif /* _DTT_H_ */
diff --git a/lib_m68k/board.c b/lib_m68k/board.c
index ae942e5..d27c89c 100644
--- a/lib_m68k/board.c
+++ b/lib_m68k/board.c
@@ -176,7 +176,7 @@
static int init_baudrate (void)
{
- uchar tmp[64]; /* long enough for environment variables */
+ char tmp[64]; /* long enough for environment variables */
int i = getenv_r ("baudrate", tmp, sizeof (tmp));
gd->baudrate = (i > 0)
@@ -267,7 +267,7 @@
#ifdef CONFIG_PRAM
int i;
ulong reg;
- uchar tmp[64]; /* long enough for environment variables */
+ char tmp[64]; /* long enough for environment variables */
#endif
/* Pointer is writable since we allocated a register for it */
@@ -752,7 +752,7 @@
*/
{
ulong pram;
- uchar memsz[32];
+ char memsz[32];
#ifdef CONFIG_PRAM
char *s;
diff --git a/net/net.c b/net/net.c
index 2a26bc0..c96f566 100644
--- a/net/net.c
+++ b/net/net.c
@@ -1390,7 +1390,7 @@
puts ("Got IP\n");
#endif
if (len < IP_HDR_SIZE) {
- debug ("len bad %d < %d\n", len, IP_HDR_SIZE);
+ debug ("len bad %d < %ld\n", len, IP_HDR_SIZE);
return;
}
if (len < ntohs(ip->ip_len)) {
diff --git a/tools/gdb/Makefile b/tools/gdb/Makefile
index 632103d..c44cc8a 100644
--- a/tools/gdb/Makefile
+++ b/tools/gdb/Makefile
@@ -47,7 +47,7 @@
ifeq ($(HOSTOS),cygwin)
all:
-.depend:
+$(obj).depend:
else # ! CYGWIN