diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index c000aca..72f2ed4 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -65,6 +65,9 @@
 	int sata_node, gma_node;
 	int ret;
 
+	if (!(gd->flags & GD_FLG_RELOC))
+		return 0;
+
 	hose = pci_bus_to_hose(0);
 	lpc_enable(PCH_LPC_DEV);
 	lpc_init(hose, PCH_LPC_DEV);
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 343bfb4..6ffc843 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -126,7 +126,7 @@
 {
 	const void *blob = gd->fdt_blob;
 	struct pci_controller *hose;
-	struct udevice *bus;
+	struct udevice *bus, *dev;
 	int node;
 	int ret;
 
@@ -141,6 +141,10 @@
 	/* TODO(sjg@chromium.org): Get rid of gd->hose */
 	gd->hose = hose;
 
+	ret = uclass_first_device(UCLASS_LPC, &dev);
+	if (!dev)
+		return -ENODEV;
+
 	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
 	if (node < 0)
 		return -ENOENT;
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index af5d4a8..51a4073 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -559,6 +559,11 @@
 	setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
 }
 
+static int bd82x6x_lpc_probe(struct udevice *dev)
+{
+	return 0;
+}
+
 static const struct udevice_id bd82x6x_lpc_ids[] = {
 	{ .compatible = "intel,bd82x6x-lpc" },
 	{ }
@@ -568,4 +573,5 @@
 	.name		= "lpc",
 	.id		= UCLASS_LPC,
 	.of_match	= bd82x6x_lpc_ids,
+	.probe		= bd82x6x_lpc_probe,
 };
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index a5c5dc1..d5c5bfd 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -223,6 +223,7 @@
 				compatible = "intel,bd82x6x-lpc";
 				#address-cells = <1>;
 				#size-cells = <0>;
+				u-boot,dm-pre-reloc;
 				cros-ec@200 {
 					compatible = "google,cros-ec";
 					reg = <0x204 1 0x200 1 0x880 0x80>;