| commit | 49e508e962df731590c3785af0d94493864c61ff | [log] [tgz] |
|---|---|---|
| author | Marek Vasut <marex@denx.de> | Mon Aug 06 21:47:50 2018 +0200 |
| committer | Marek Vasut <marex@denx.de> | Mon Aug 13 22:35:42 2018 +0200 |
| tree | 7d34cc991f680217fba88bc9d774fe31fc1f3b52 | |
| parent | 934aec71d6491ed3e5555f92255613dfdf402aa8 [diff] |
ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only The L4SP and MMC clock precalculation is specific to Gen5, it is not needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper clock driver for Gen5, at which point this will go away completely. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>