diff --git a/.gitignore b/.gitignore
index ed21203..771b860 100644
--- a/.gitignore
+++ b/.gitignore
@@ -46,6 +46,7 @@
 /u-boot.ais
 /u-boot.dtb
 /u-boot.sb
+/u-boot.bd
 /u-boot.geany
 
 #
@@ -79,5 +80,11 @@
 /ctags
 /etags
 
+# gnu global files
+GPATH
+GRTAGS
+GSYMS
+GTAGS
+
 # spl ais files
 /spl/*.ais
diff --git a/MAINTAINERS b/MAINTAINERS
index 643a5ac..14075af 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -607,6 +607,7 @@
 	igep0020	ARM ARMV7 (OMAP3xx SoC)
 	igep0030	ARM ARMV7 (OMAP3xx SoC)
 	igep0032	ARM ARMV7 (OMAP3xx SoC)
+	igep0033	ARM ARMV7 (AM33xx Soc)
 
 Eric Benard <eric@eukrea.com>
 
@@ -664,6 +665,7 @@
 	mx6qsabresd	i.MX6Q
 	mx6qsabreauto	i.MX6Q
 	wandboard	i.MX6DL/S
+	mx6slevk	i.MX6SL
 
 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
 
@@ -683,7 +685,7 @@
 
 Igor Grinberg <grinberg@compulab.co.il>
 
-	cm-t35		ARM ARMV7 (OMAP3xx Soc)
+	cm_t35		ARM ARMV7 (OMAP3xx Soc)
 
 Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
 
@@ -848,6 +850,10 @@
 	omap4_sdp4430	ARM ARMV7 (OMAP4xx SoC)
 	omap5_evm	ARM ARMV7 (OMAP5xx Soc)
 
+Suriyan Ramasami <suriyan.r@gmail.com>
+
+	goflexhome	ARM926EJS (Kirkwood SoC)
+
 Thierry Reding <thierry.reding@avionic-design.de>
 
 	plutux		Tegra20 (ARM7 & A9 Dual Core)
@@ -877,6 +883,8 @@
 
 	x600		ARM926EJS (spear600 Soc)
 
+	titanium	i.MX6Q
+
 	pdnb3		xscale/ixp
 	scpu		xscale/ixp
 
@@ -914,6 +922,7 @@
 
 Bo Shen <voice.shen@atmel.com>
 	at91sam9x5ek		ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
+	sama5d3xek		ARMV7 (SAMA5D31, D33, D34, D35 SoC)
 
 Rajeshwari Shinde <rajeshwari.s@samsung.com>
 
@@ -954,6 +963,7 @@
 	mx23_olinuxino	i.MX23
 	m28evk		i.MX28
 	sc_sps_1	i.MX28
+	m53evk		i.MX53
 
 Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
 
@@ -961,7 +971,8 @@
 
 Matt Waddel <matt.waddel@linaro.org>
 
-	ca9x4_ct_vxp	ARM ARMV7 (Quad Core)
+	vexpress_ca9x4	ARM ARMV7 (Quad Core)
+	vexpress_ca5x2	ARM ARMV7 (Dual Core)
 
 Otavio Salvador <otavio@ossystems.com.br>
 
@@ -1018,6 +1029,9 @@
 
 	omap2420h4	ARM1136EJS
 
+Josh Wu <josh.wu@atmel.com>
+	at91sam9n12ek	ARM926EJS (AT91SAM9N12 SoC)
+
 Ilya Yanok <yanok@emcraft.com>
 
 	mcx		ARM ARMV7 (AM35x SoC)
@@ -1072,9 +1086,19 @@
 #	Board		CPU						#
 #########################################################################
 
-Graeme Russ <graeme.russ@gmail.com>
+Simon Glass <sjg@chromium.org>
 
-	eNET		AMD SC520
+	chromebook-x86	Coreboot runs first, then U-Boot
+			Supports Intel Sandy Bridge / Ivy Bridge so far
+
+			Chromebooks for x86, including:
+				Samsung Series 5 Chromebook
+				Acer AC700 Chromebook
+				Acer C7 Chromebook
+				Samsung Chromebook 550
+				HP Pavillion Chromebook
+				Acer C710 Chromebook
+				Chromebook Pixel
 
 #########################################################################
 # MIPS Systems:								#
@@ -1340,5 +1364,16 @@
 	openrisc-generic	OpenRISC
 
 #########################################################################
+# Sandbox:								#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Simon Glass <sjg@chromium.org>
+
+	sandbox		sandbox
+
+#########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index 2737eab..2e16e0d 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -268,12 +268,6 @@
 LIST_4xx="$(boards_by_cpu ppc4xx)"
 
 #########################################################################
-## MPC8220 Systems
-#########################################################################
-
-LIST_8220="$(boards_by_cpu mpc8220)"
-
-#########################################################################
 ## MPC824x Systems
 #########################################################################
 
@@ -324,7 +318,6 @@
 	${LIST_512x}	\
 	${LIST_5xxx}	\
 	${LIST_8xx}	\
-	${LIST_8220}	\
 	${LIST_824x}	\
 	${LIST_8260}	\
 	${LIST_83xx}	\
diff --git a/Makefile b/Makefile
index dbc4b70..ef154aa 100644
--- a/Makefile
+++ b/Makefile
@@ -341,7 +341,7 @@
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs))
 LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
 endif
 
@@ -522,13 +522,9 @@
 		cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.img > \
 			$(obj)u-boot.ais
 
-# Specify the target for use in elftosb call
-ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
-ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
 
 $(obj)u-boot.sb:       $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
-		elftosb -zf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
-			-o $(obj)u-boot.sb
+		$(MAKE) -C $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb
 
 # On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
 # Both images are created using mkimage (crc etc), so that the ROM
@@ -547,18 +543,15 @@
 		cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
 
 ifneq ($(CONFIG_TEGRA),)
-ifeq ($(CONFIG_OF_SEPARATE),y)
-nodtb=dtb
-dtbfile=$(obj)u-boot.dtb
-else
-nodtb=nodtb
-dtbfile=
-endif
-
-$(obj)u-boot-$(nodtb)-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(dtbfile)
+$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
 		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
-		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(dtbfile) > $@
+		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
 		rm $(obj)spl/u-boot-spl-pad.bin
+
+ifeq ($(CONFIG_OF_SEPARATE),y)
+$(obj)u-boot-dtb-tegra.bin: $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb
+		cat $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb > $@
+endif
 endif
 
 $(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
@@ -871,6 +864,7 @@
 	@rm -f $(obj)u-boot.ais
 	@rm -f $(obj)u-boot.dtb
 	@rm -f $(obj)u-boot.sb
+	@rm -f $(obj)u-boot.bd
 	@rm -f $(obj)u-boot.spr
 	@rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
 	@rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
diff --git a/README b/README
index 0d37d56..3780564 100644
--- a/README
+++ b/README
@@ -201,7 +201,6 @@
       /mpc5xx		Files specific to Freescale MPC5xx CPUs
       /mpc5xxx		Files specific to Freescale MPC5xxx CPUs
       /mpc8xx		Files specific to Freescale MPC8xx CPUs
-      /mpc8220		Files specific to Freescale MPC8220 CPUs
       /mpc824x		Files specific to Freescale MPC824x CPUs
       /mpc8260		Files specific to Freescale MPC8260 CPUs
       /mpc85xx		Files specific to Freescale MPC85xx CPUs
@@ -844,6 +843,7 @@
 		CONFIG_CMD_FDOS		* Dos diskette Support
 		CONFIG_CMD_FLASH	  flinfo, erase, protect
 		CONFIG_CMD_FPGA		  FPGA device initialization support
+		CONFIG_CMD_FUSE		  Device fuse support
 		CONFIG_CMD_GETTIME	* Get time since boot
 		CONFIG_CMD_GO		* the 'go' command (exec code)
 		CONFIG_CMD_GREPENV	* search environment
@@ -898,6 +898,7 @@
 		CONFIG_CMD_SF		* Read/write/erase SPI NOR flash
 		CONFIG_CMD_SHA1SUM	  print sha1 memory digest
 					  (requires CONFIG_CMD_MEMORY)
+		CONFIG_CMD_SOFTSWITCH	* Soft switch setting command for BF60x
 		CONFIG_CMD_SOURCE	  "source" command Support
 		CONFIG_CMD_SPI		* SPI serial bus support
 		CONFIG_CMD_TFTPSRV	* TFTP transfer in server mode
@@ -1208,7 +1209,23 @@
 			If this option is set, the driver enables cache flush.
 
 - TPM Support:
-		CONFIG_GENERIC_LPC_TPM
+		CONFIG_TPM
+		Support TPM devices.
+
+		CONFIG_TPM_TIS_I2C
+		Support for i2c bus TPM devices. Only one device
+		per system is supported at this time.
+
+			CONFIG_TPM_TIS_I2C_BUS_NUMBER
+			Define the the i2c bus number for the TPM device
+
+			CONFIG_TPM_TIS_I2C_SLAVE_ADDRESS
+			Define the TPM's address on the i2c bus
+
+			CONFIG_TPM_TIS_I2C_BURST_LIMITATION
+			Define the burst count bytes upper limit
+
+		CONFIG_TPM_TIS_LPC
 		Support for generic parallel port TPM devices. Only one device
 		per system is supported at this time.
 
@@ -2996,6 +3013,12 @@
 		use an arch-specific makefile fragment instead, for
 		example if more than one image needs to be produced.
 
+		CONFIG_FIT_SPL_PRINT
+		Printing information about a FIT image adds quite a bit of
+		code to SPL. So this is normally disabled in SPL. Use this
+		option to re-enable it. This will affect the output of the
+		bootm command when booting a FIT image.
+
 Modem Support:
 --------------
 
@@ -3339,6 +3362,10 @@
 	offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
 	directly. You should not need to touch this setting.
 
+- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
+	This is set by OMAP boards for the max time that reset should
+	be asserted. See doc/README.omap-reset-time for details on how
+	the value can be calulated on a given board.
 
 The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
@@ -5057,7 +5084,7 @@
 using the "bootz" command. The syntax of "bootz" command is the same
 as the syntax of "bootm" command.
 
-Note, defining the CONFIG_SUPPORT_INITRD_RAW allows user to supply
+Note, defining the CONFIG_SUPPORT_RAW_INITRD allows user to supply
 kernel with raw initrd images. The syntax is slightly different, the
 address of the initrd must be augmented by it's size, in the following
 format: "<initrd addres>:<initrd size>".
diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c
index a3d981f..ceb1271 100644
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
@@ -55,8 +55,6 @@
 #define bi_bar	bi_mbar_base
 #elif defined(CONFIG_MPC83xx)
 #define bi_bar	bi_immrbar
-#elif defined(CONFIG_MPC8220)
-#define bi_bar	bi_mbar_base
 #endif
 
 #if defined(bi_bar)
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 461899e..dc64160 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -31,6 +31,9 @@
 endif
 endif
 
+LDFLAGS_FINAL += --gc-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+
 # Support generic board on ARM
 __HAVE_ARCH_GENERIC_BOARD := y
 
diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile
index f4ababb..23adac0 100644
--- a/arch/arm/cpu/arm1136/mx35/Makefile
+++ b/arch/arm/cpu/arm1136/mx35/Makefile
@@ -29,7 +29,6 @@
 
 COBJS	+= generic.o
 COBJS	+= timer.o
-COBJS	+= iomux.o
 COBJS	+= mx35_sdram.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/arm1136/mx35/iomux.c b/arch/arm/cpu/arm1136/mx35/iomux.c
deleted file mode 100644
index a302575..0000000
--- a/arch/arm/cpu/arm1136/mx35/iomux.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx35_pins.h>
-#include <asm/arch/iomux.h>
-
-/*
- * IOMUX register (base) addresses
- */
-enum iomux_reg_addr {
-	IOMUXGPR = IOMUXC_BASE_ADDR,			/* General purpose */
-	IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4,		/* MUX control */
-	IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324,	/* last MUX control */
-	IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328,	/* Pad control */
-	IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794,	/* last Pad control */
-	IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC,	/* input select */
-	IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4,	/* last input select */
-};
-
-#define MUX_PIN_NUM_MAX		\
-		(((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1)
-#define MUX_INPUT_NUM_MUX	\
-		(((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used.
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-	u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
-	if (mux_reg != NON_MUX_I) {
-		mux_reg += IOMUXGPR;
-		writel(cfg, mux_reg);
-	}
-}
-
-/*
- * Release ownership for an IO pin
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param  pin     a pin number as defined in iomux_pin_name_t
- * @param  config  the ORed value of elements defined in iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
-	u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin);
-
-	writel(config, pad_reg);
-}
-
-/*
- * This function enables/disables the general purpose function for a particular
- * signal.
- *
- * @param  gp   one signal as defined in iomux_gp_func_t
- * @param  en   enable/disable
- */
-void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en)
-{
-	u32 l;
-
-	l = readl(IOMUXGPR);
-	if (en)
-		l |= gp;
-	else
-		l &= ~gp;
-
-	writel(l, IOMUXGPR);
-}
-
-/*
- * This function configures input path.
- *
- * @param input index of input select register as defined in
- *			iomux_input_select_t
- * @param config the binary value of elements defined in
- *			iomux_input_config_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
-	u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
-	writel(config, reg);
-}
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index ccea2d5..edf249d 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -104,10 +104,6 @@
 _bss_start_ofs:
 	.word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-	.word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end - _start
@@ -173,83 +169,6 @@
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r6, r0	/* save addr of destination */
-
-	adr	r0, _start
-	subs	r9, r6, r0		/* r9 <- relocation offset */
-	beq	relocate_done		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _image_copy_end_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
-	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-relocate_done:
-
-	bx	lr
-
-#ifndef CONFIG_SPL_BUILD
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-#endif
-
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index f20da8e..65292bc 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -112,10 +112,6 @@
 _bss_start_ofs:
 	.word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-	.word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end - _start
@@ -225,79 +221,6 @@
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r6, r0	/* save addr of destination */
-
-	adr	r0, _start
-	subs	r9, r6, r0		/* r9 <- relocation offset */
-	beq	relocate_done		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _image_copy_end_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
-	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-relocate_done:
-
-	bx	lr
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 9facc7e..a396ebc 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -101,10 +101,6 @@
 _bss_start_ofs:
 	.word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-	.word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end - _start
@@ -155,79 +151,6 @@
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r6, r0	/* save addr of destination */
-
-	adr	r0, _start
-	subs	r9, r6, r0		/* r9 <- relocation offset */
-	beq	relocate_done		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _image_copy_end_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
-	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-relocate_done:
-
-	mov	pc, lr
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
@@ -244,9 +167,9 @@
  *************************************************************************
  */
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 
-#if !defined(CONFIG_TEGRA)
 	mov	ip, lr
 	/*
 	 * before relocating, we have to setup RAM timing
@@ -255,9 +178,9 @@
 	 */
 	bl	lowlevel_init
 	mov	lr, ip
-#endif
 
 	mov	pc, lr
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index 6250025..3232065 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -89,10 +89,6 @@
 _bss_start_ofs:
 	.word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-	.word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end - _start
@@ -194,79 +190,6 @@
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r6, r0	/* save addr of destination */
-
-	adr	r0, _start
-	subs	r9, r6, r0		/* r9 <- relocation offset */
-	beq	relocate_done		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _image_copy_end_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
-	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-relocate_done:
-
-	mov	pc, lr
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S
index 021e241..97eb276 100644
--- a/arch/arm/cpu/arm925t/start.S
+++ b/arch/arm/cpu/arm925t/start.S
@@ -95,10 +95,6 @@
 _bss_start_ofs:
 	.word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-	.word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end - _start
@@ -184,79 +180,6 @@
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r6, r0	/* save addr of destination */
-
-	adr	r0, _start
-	subs	r9, r6, r0		/* r9 <- relocation offset */
-	beq	relocate_done		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _image_copy_end_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
-	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-relocate_done:
-
-	mov	pc, lr
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile
index 346e58f..c4408f6 100644
--- a/arch/arm/cpu/arm926ejs/at91/Makefile
+++ b/arch/arm/cpu/arm926ejs/at91/Makefile
@@ -35,6 +35,7 @@
 COBJS-$(CONFIG_AT91SAM9RL)	+= at91sam9rl_devices.o
 COBJS-$(CONFIG_AT91SAM9M10G45)	+= at91sam9m10g45_devices.o
 COBJS-$(CONFIG_AT91SAM9G45)	+= at91sam9m10g45_devices.o
+COBJS-$(CONFIG_AT91SAM9N12)	+= at91sam9n12_devices.o
 COBJS-$(CONFIG_AT91SAM9X5)	+= at91sam9x5_devices.o
 COBJS-$(CONFIG_AT91_EFLASH)	+= eflash.o
 COBJS-$(CONFIG_AT91_LED)	+= led.o
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
index 19ec615..5e995e1 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
@@ -203,6 +203,10 @@
 #if defined(CONFIG_GENERIC_ATMEL_MCI)
 void at91_mci_hw_init(void)
 {
+	/* Enable mci clock */
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	writel(1 << ATMEL_ID_MCI, &pmc->pcer);
+
 	at91_set_a_periph(AT91_PIO_PORTA, 8, 1);	/* MCCK */
 #if defined(CONFIG_ATMEL_MCI_PORTB)
 	at91_set_b_periph(AT91_PIO_PORTA, 1, 1);	/* MCCDB */
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c
new file mode 100644
index 0000000..6eaeac0
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2013 Atmel Corporation
+ * Josh Wu <josh.wu@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+
+unsigned int has_lcdc()
+{
+	return 1;
+}
+
+void at91_serial0_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 0, 1);		/* TXD0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 1, 0);		/* RXD0 */
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 5, 1);		/* TXD1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 6, 0);		/* RXD1 */
+	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 7, 1);		/* TXD2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 8, 0);		/* RXD2 */
+	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+}
+
+void at91_serial3_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_b_periph(AT91_PIO_PORTC, 22, 1);		/* TXD3 */
+	at91_set_b_periph(AT91_PIO_PORTC, 23, 0);		/* RXD3 */
+	writel(1 << ATMEL_ID_USART3, &pmc->pcer);
+}
+
+void at91_seriald_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);		/* DTXD */
+	at91_set_a_periph(AT91_PIO_PORTA, 9, 0);		/* DRXD */
+	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+}
+
+#ifdef CONFIG_ATMEL_SPI
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
+
+	if (cs_mask & (1 << 0))
+		at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
+	if (cs_mask & (1 << 1))
+		at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
+	if (cs_mask & (1 << 2))
+		at91_set_pio_output(AT91_PIO_PORTA, 1, 1);
+	if (cs_mask & (1 << 3))
+		at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_b_periph(AT91_PIO_PORTA, 21, 0);	/* SPI1_MISO */
+	at91_set_b_periph(AT91_PIO_PORTA, 22, 0);	/* SPI1_MOSI */
+	at91_set_b_periph(AT91_PIO_PORTA, 23, 0);	/* SPI1_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
+
+	if (cs_mask & (1 << 0))
+		at91_set_pio_output(AT91_PIO_PORTA, 8, 1);
+	if (cs_mask & (1 << 1))
+		at91_set_pio_output(AT91_PIO_PORTA, 0, 1);
+	if (cs_mask & (1 << 2))
+		at91_set_pio_output(AT91_PIO_PORTA, 31, 1);
+	if (cs_mask & (1 << 3))
+		at91_set_pio_output(AT91_PIO_PORTA, 30, 1);
+}
+#endif
+
+void at91_mci_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* MCCK */
+	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* MCCDA */
+	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* MCDA0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* MCDA1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* MCDA2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* MCDA3 */
+
+	writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
+}
+
+#ifdef CONFIG_LCD
+void at91_lcd_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDDPWR */
+	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDVSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 28, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* LCDDEN */
+	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);	/* LCDDOTCK */
+
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDD0 */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDD1 */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTC, 4, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD8 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD9 */
+	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD12 */
+	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD15 */
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD16 */
+	at91_set_a_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD17 */
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTC, 20, 0);	/* LCDD20 */
+	at91_set_a_periph(AT91_PIO_PORTC, 21, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD23 */
+
+	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c
index f825388..5b4923f 100644
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ b/arch/arm/cpu/arm926ejs/at91/clock.c
@@ -156,7 +156,7 @@
 	 */
 	mckr = readl(&pmc->mckr);
 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
-		|| defined(CONFIG_AT91SAM9X5)
+		|| defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
 	/* plla divisor by 2 */
 	gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
 #endif
@@ -171,7 +171,7 @@
 	if (mckr & AT91_PMC_MCKR_MDIV_MASK)
 		freq /= 2;			/* processor clock division */
 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
-		|| defined(CONFIG_AT91SAM9X5)
+		|| defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
 	/* mdiv <==> divisor
 	 *  0   <==>   1
 	 *  1   <==>   2
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index ff2e2e3..127beb8 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -32,6 +32,14 @@
 #include <asm/arch/emif_defs.h>
 #include <asm/arch/pll_defs.h>
 
+void davinci_enable_uart0(void)
+{
+	lpsc_on(DAVINCI_LPSC_UART0);
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x00006001;
+}
+
 #if defined(CONFIG_SYS_DA850_PLL_INIT)
 void da850_waitloop(unsigned long loopcnt)
 {
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
index 679273b..7cbbe65 100644
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -27,7 +27,6 @@
 #include <netdev.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/imx25-pinmux.h>
 #include <asm/arch/clock.h>
 
 #ifdef CONFIG_FSL_ESDHC
@@ -248,123 +247,7 @@
 }
 #endif
 
-#ifdef CONFIG_MXC_UART
-void mx25_uart1_init_pins(void)
-{
-	struct iomuxc_mux_ctl *muxctl;
-	struct iomuxc_pad_ctl *padctl;
-	u32 inpadctl;
-	u32 outpadctl;
-	u32 muxmode0;
-
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-	muxmode0 = MX25_PIN_MUX_MODE(0);
-	/*
-	 * set up input pins with hysteresis and 100K pull-ups
-	 */
-	inpadctl = MX25_PIN_PAD_CTL_HYS
-	    | MX25_PIN_PAD_CTL_PKE
-	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU;
-
-	/*
-	 * set up output pins with 100K pull-downs
-	 * FIXME: need to revisit this
-	 *      PUE is ignored if PKE is not set
-	 *      so the right value here is likely
-	 *        0x0 for no pull up/down
-	 *      or
-	 *        0xc0 for 100k pull down
-	 */
-	outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-
-	/* UART1 */
-	/* rxd */
-	writel(muxmode0, &muxctl->pad_uart1_rxd);
-	writel(inpadctl, &padctl->pad_uart1_rxd);
-
-	/* txd */
-	writel(muxmode0, &muxctl->pad_uart1_txd);
-	writel(outpadctl, &padctl->pad_uart1_txd);
-
-	/* rts */
-	writel(muxmode0, &muxctl->pad_uart1_rts);
-	writel(outpadctl, &padctl->pad_uart1_rts);
-
-	/* cts */
-	writel(muxmode0, &muxctl->pad_uart1_cts);
-	writel(inpadctl, &padctl->pad_uart1_cts);
-}
-#endif /* CONFIG_MXC_UART */
-
 #ifdef CONFIG_FEC_MXC
-void mx25_fec_init_pins(void)
-{
-	struct iomuxc_mux_ctl *muxctl;
-	struct iomuxc_pad_ctl *padctl;
-	u32 inpadctl_100kpd;
-	u32 inpadctl_22kpu;
-	u32 outpadctl;
-	u32 muxmode0;
-
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-	muxmode0 = MX25_PIN_MUX_MODE(0);
-	inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
-	    | MX25_PIN_PAD_CTL_PKE
-	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-	inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
-	    | MX25_PIN_PAD_CTL_PKE
-	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU;
-	/*
-	 * set up output pins with 100K pull-downs
-	 * FIXME: need to revisit this
-	 *      PUE is ignored if PKE is not set
-	 *      so the right value here is likely
-	 *        0x0 for no pull
-	 *      or
-	 *        0xc0 for 100k pull down
-	 */
-	outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-
-	/* FEC_TX_CLK */
-	writel(muxmode0, &muxctl->pad_fec_tx_clk);
-	writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk);
-
-	/* FEC_RX_DV */
-	writel(muxmode0, &muxctl->pad_fec_rx_dv);
-	writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv);
-
-	/* FEC_RDATA0 */
-	writel(muxmode0, &muxctl->pad_fec_rdata0);
-	writel(inpadctl_100kpd, &padctl->pad_fec_rdata0);
-
-	/* FEC_TDATA0 */
-	writel(muxmode0, &muxctl->pad_fec_tdata0);
-	writel(outpadctl, &padctl->pad_fec_tdata0);
-
-	/* FEC_TX_EN */
-	writel(muxmode0, &muxctl->pad_fec_tx_en);
-	writel(outpadctl, &padctl->pad_fec_tx_en);
-
-	/* FEC_MDC */
-	writel(muxmode0, &muxctl->pad_fec_mdc);
-	writel(outpadctl, &padctl->pad_fec_mdc);
-
-	/* FEC_MDIO */
-	writel(muxmode0, &muxctl->pad_fec_mdio);
-	writel(inpadctl_22kpu, &padctl->pad_fec_mdio);
-
-	/* FEC_RDATA1 */
-	writel(muxmode0, &muxctl->pad_fec_rdata1);
-	writel(inpadctl_100kpd, &padctl->pad_fec_rdata1);
-
-	/* FEC_TDATA1 */
-	writel(muxmode0, &muxctl->pad_fec_tdata1);
-	writel(outpadctl, &padctl->pad_fec_tdata1);
-
-}
-
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
 	int i;
diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile
index eeecf89..038c1c1 100644
--- a/arch/arm/cpu/arm926ejs/mxs/Makefile
+++ b/arch/arm/cpu/arm926ejs/mxs/Makefile
@@ -40,6 +40,16 @@
 $(LIB):	$(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+# Specify the target for use in elftosb call
+ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
+ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
+
+$(OBJTREE)/u-boot.bd: $(SRCTREE)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd
+	sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@
+
+$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot.bd
+		elftosb -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb
+
 #########################################################################
 
 # defines $(obj).depend target
diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
index 43e7663..f94107f 100644
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -325,6 +325,99 @@
 		bus, tgtclk, freq);
 }
 
+void mxs_set_lcdclk(uint32_t freq)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	uint32_t fp, x, k_rest, k_best, x_best, tk;
+	int32_t k_best_l = 999, k_best_t = 0, x_best_l = 0xff, x_best_t = 0xff;
+
+	if (freq == 0)
+		return;
+
+#if defined(CONFIG_MX23)
+	writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr);
+#elif defined(CONFIG_MX28)
+	writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr);
+#endif
+
+	/*
+	 *             /               18 \     1       1
+	 * freq kHz = | 480000000 Hz * --  | * --- * ------
+	 *             \                x /     k     1000
+	 *
+	 *      480000000 Hz   18
+	 *      ------------ * --
+	 *        freq kHz      x
+	 * k = -------------------
+	 *             1000
+	 */
+
+	fp = ((PLL_FREQ_KHZ * 1000) / freq) * 18;
+
+	for (x = 18; x <= 35; x++) {
+		tk = fp / x;
+		if ((tk / 1000 == 0) || (tk / 1000 > 255))
+			continue;
+
+		k_rest = tk % 1000;
+
+		if (k_rest < (k_best_l % 1000)) {
+			k_best_l = tk;
+			x_best_l = x;
+		}
+
+		if (k_rest > (k_best_t % 1000)) {
+			k_best_t = tk;
+			x_best_t = x;
+		}
+	}
+
+	if (1000 - (k_best_t % 1000) > (k_best_l % 1000)) {
+		k_best = k_best_l;
+		x_best = x_best_l;
+	} else {
+		k_best = k_best_t;
+		x_best = x_best_t;
+	}
+
+	k_best /= 1000;
+
+#if defined(CONFIG_MX23)
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]);
+	writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
+		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]);
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]);
+
+	writel(CLKCTRL_PIX_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_pix_set);
+	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix,
+			CLKCTRL_PIX_DIV_MASK | CLKCTRL_PIX_CLKGATE,
+			k_best << CLKCTRL_PIX_DIV_OFFSET);
+
+	while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY)
+		;
+#elif defined(CONFIG_MX28)
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]);
+	writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
+		&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_PIX]);
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_PIX]);
+
+	writel(CLKCTRL_DIS_LCDIF_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_lcdif_set);
+	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_lcdif,
+			CLKCTRL_DIS_LCDIF_DIV_MASK | CLKCTRL_DIS_LCDIF_CLKGATE,
+			k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET);
+
+	while (readl(&clkctrl_regs->hw_clkctrl_lcdif) & CLKCTRL_DIS_LCDIF_BUSY)
+		;
+#endif
+}
+
 uint32_t mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index e2b4196..a5e388b 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -30,7 +30,7 @@
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
@@ -39,12 +39,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* 1 second delay should be plenty of time for block reset. */
-#define	RESET_MAX_TIMEOUT	1000000
-
-#define	MXS_BLOCK_SFTRST	(1 << 31)
-#define	MXS_BLOCK_CLKGATE	(1 << 30)
-
 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
 inline void lowlevel_init(void) {}
 
@@ -82,63 +76,6 @@
 #endif
 }
 
-int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
-								int timeout)
-{
-	while (--timeout) {
-		if ((readl(&reg->reg) & mask) == mask)
-			break;
-		udelay(1);
-	}
-
-	return !timeout;
-}
-
-int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
-								int timeout)
-{
-	while (--timeout) {
-		if ((readl(&reg->reg) & mask) == 0)
-			break;
-		udelay(1);
-	}
-
-	return !timeout;
-}
-
-int mxs_reset_block(struct mxs_register_32 *reg)
-{
-	/* Clear SFTRST */
-	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
-
-	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
-		return 1;
-
-	/* Clear CLKGATE */
-	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
-
-	/* Set SFTRST */
-	writel(MXS_BLOCK_SFTRST, &reg->reg_set);
-
-	/* Wait for CLKGATE being set */
-	if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
-		return 1;
-
-	/* Clear SFTRST */
-	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
-
-	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
-		return 1;
-
-	/* Clear CLKGATE */
-	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
-
-	if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
-		return 1;
-
-	return 0;
-}
-
 void mx28_fixup_vt(uint32_t start_addr)
 {
 	uint32_t *vt = (uint32_t *)0x20;
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index bc2d69c..07db279 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -110,6 +110,7 @@
 {
 }
 
+#ifdef CONFIG_MX28
 static void initialize_dram_values(void)
 {
 	int i;
@@ -118,15 +119,36 @@
 
 	for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
 		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+}
+#else
+static void initialize_dram_values(void)
+{
+	int i;
 
-#ifdef CONFIG_MX23
+	mxs_adjust_memory_params(dram_vals);
+
+	/*
+	 * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
+	 * per FSL bootlets code.
+	 *
+	 * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
+	 * "reserved".
+	 * HW_DRAM_CTL8 is setup as the last element.
+	 * So skip the initialization of these HW_DRAM_CTL registers.
+	 */
+	for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
+		if (i == 8 || i == 27 || i == 28 || i == 35)
+			continue;
+		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+	}
+
 	/*
 	 * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
 	 * element to be set
 	 */
 	writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
-#endif
 }
+#endif
 
 static void mxs_mem_init_clock(void)
 {
@@ -234,17 +256,9 @@
 	struct mxs_power_regs *power_regs =
 		(struct mxs_power_regs *)MXS_POWER_BASE;
 
-	writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
-		POWER_VDDMEMCTRL_ENABLE_ILIMIT |
-		POWER_VDDMEMCTRL_ENABLE_LINREG |
-		POWER_VDDMEMCTRL_PULLDOWN_ACTIVE,
-		&power_regs->hw_power_vddmemctrl);
+	clrbits_le32(&power_regs->hw_power_vddmemctrl,
+		POWER_VDDMEMCTRL_ENABLE_ILIMIT);
 
-	early_delay(10000);
-
-	writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
-		POWER_VDDMEMCTRL_ENABLE_LINREG,
-		&power_regs->hw_power_vddmemctrl);
 }
 
 static void mx23_mem_init(void)
@@ -267,22 +281,18 @@
 
 	initialize_dram_values();
 
-	/* Set START bit in DRAM_CTL16 */
+	/* Set START bit in DRAM_CTL8 */
 	setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
 
 	clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
 	early_delay(20000);
 
 	/* Adjust EMI port priority. */
-	clrsetbits_le32(0x80020000, 0x1f << 16, 0x8);
+	clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
 	early_delay(20000);
 
 	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
 	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
-
-	/* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
-	while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
-		;
 }
 #endif
 
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index 287c698..21cac7b 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -687,6 +687,12 @@
 	mxs_init_batt_bo();
 
 	mxs_switch_vddd_to_dcdc_source();
+
+#ifdef CONFIG_MX23
+	/* Fire up the VDDMEM LinReg now that we're all set. */
+	writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
+		&power_regs->hw_power_vddmemctrl);
+#endif
 }
 
 static void mxs_enable_output_rail_protection(void)
@@ -781,7 +787,11 @@
 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
 	.reg			= &(((struct mxs_power_regs *)MXS_POWER_BASE)->
 					hw_power_vddioctrl),
+#if defined(CONFIG_MX23)
+	.step_mV		= 25,
+#else
 	.step_mV		= 50,
+#endif
 	.lowest_mV		= 2800,
 	.powered_by_linreg	= mxs_get_vddio_power_source_off,
 	.trg_mask		= POWER_VDDIOCTRL_TRG_MASK,
@@ -804,6 +814,21 @@
 	.bo_offset_offset	= POWER_VDDDCTRL_BO_OFFSET_OFFSET,
 };
 
+#ifdef CONFIG_MX23
+static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
+	.reg			= &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+					hw_power_vddmemctrl),
+	.step_mV		= 50,
+	.lowest_mV		= 1700,
+	.powered_by_linreg	= NULL,
+	.trg_mask		= POWER_VDDMEMCTRL_TRG_MASK,
+	.bo_irq			= 0,
+	.bo_enirq		= 0,
+	.bo_offset_mask		= 0,
+	.bo_offset_offset	= 0,
+};
+#endif
+
 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
 				uint32_t new_target, uint32_t new_brownout)
 {
@@ -821,9 +846,10 @@
 	cur_target += cfg->lowest_mV;
 
 	adjust_up = new_target > cur_target;
-	powered_by_linreg = cfg->powered_by_linreg();
+	if (cfg->powered_by_linreg)
+		powered_by_linreg = cfg->powered_by_linreg();
 
-	if (adjust_up) {
+	if (adjust_up && cfg->bo_irq) {
 		if (powered_by_linreg) {
 			bo_int = readl(cfg->reg);
 			clrbits_le32(cfg->reg, cfg->bo_enirq);
@@ -864,14 +890,16 @@
 		cur_target += cfg->lowest_mV;
 	} while (new_target > cur_target);
 
-	if (adjust_up && powered_by_linreg) {
-		writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
-		if (bo_int & cfg->bo_enirq)
-			setbits_le32(cfg->reg, cfg->bo_enirq);
-	}
+	if (cfg->bo_irq) {
+		if (adjust_up && powered_by_linreg) {
+			writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
+			if (bo_int & cfg->bo_enirq)
+				setbits_le32(cfg->reg, cfg->bo_enirq);
+		}
 
-	clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
-			new_brownout << cfg->bo_offset_offset);
+		clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
+				new_brownout << cfg->bo_offset_offset);
+	}
 }
 
 static void mxs_setup_batt_detect(void)
@@ -910,7 +938,9 @@
 
 	mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
 	mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
-
+#ifdef CONFIG_MX23
+	mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
+#endif
 	writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
 		POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
 		POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
index 3a51879..8b6c30e 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
@@ -4,8 +4,8 @@
 }
 
 sources {
-	u_boot_spl="spl/u-boot-spl.bin";
-	u_boot="u-boot.bin";
+	u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
+	u_boot="OBJTREE/u-boot.bin";
 }
 
 section (0) {
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
index c60615a..a5fa648 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
@@ -1,6 +1,6 @@
 sources {
-	u_boot_spl="spl/u-boot-spl.bin";
-	u_boot="u-boot.bin";
+	u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
+	u_boot="OBJTREE/u-boot.bin";
 }
 
 section (0) {
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 4c567110..5fc8e04 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -136,10 +136,6 @@
 _bss_start_ofs:
 	.word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-	.word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end - _start
@@ -190,83 +186,6 @@
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r6, r0	/* save addr of destination */
-
-	adr	r0, _start
-	subs	r9, r6, r0		/* r9 <- relocation offset */
-	beq	relocate_done		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy loop */
-	ldr	r3, _image_copy_end_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
-	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-relocate_done:
-
-	bx	lr
-
-#ifndef CONFIG_SPL_BUILD
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-#endif
-
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
index 9c2b70d..e9d0c34 100644
--- a/arch/arm/cpu/arm946es/start.S
+++ b/arch/arm/cpu/arm946es/start.S
@@ -105,10 +105,6 @@
 _bss_start_ofs:
 	.word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-	.word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end - _start
@@ -159,79 +155,6 @@
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r6, r0	/* save addr of destination */
-
-	adr	r0, _start
-	subs	r9, r6, r0		/* r9 <- relocation offset */
-	beq	relocate_done		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _image_copy_end_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
-	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-relocate_done:
-
-	mov	pc, lr
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S
index 5e8c528..8dfd919 100644
--- a/arch/arm/cpu/arm_intcm/start.S
+++ b/arch/arm/cpu/arm_intcm/start.S
@@ -101,10 +101,6 @@
 _bss_start_ofs:
 	.word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-	.word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end - _start
@@ -155,79 +151,6 @@
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r6, r0	/* save addr of destination */
-
-	adr	r0, _start
-	subs	r9, r6, r0		/* r9 <- relocation offset */
-	beq	relocate_done		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _image_copy_end_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
-	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-relocate_done:
-
-	bx	lr
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index cb4210f..8b2878d 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -109,6 +109,8 @@
 #define OSC_SRC_CTRL			(PLL_SUBSYS_BASE + 0x2C0)
 
 /* PRCM */
+#define ENET_CLKCTRL_CMPL		0x30000
+
 #define CM_DEFAULT_BASE			(PRCM_BASE + 0x0500)
 
 struct cm_def {
@@ -183,7 +185,7 @@
 	unsigned int resv5[2];
 	unsigned int gpmcclkctrl;
 	unsigned int ethernet0clkctrl;
-	unsigned int resv6[1];
+	unsigned int ethernet1clkctrl;
 	unsigned int mpuclkctrl;
 	unsigned int debugssclkctrl;
 	unsigned int l3clkctrl;
@@ -203,9 +205,67 @@
 	unsigned int custefuseclkctrl;
 };
 
+#define SATA_PLL_BASE			(CTRL_BASE + 0x0720)
+
+struct sata_pll {
+	unsigned int pllcfg0;
+	unsigned int pllcfg1;
+	unsigned int pllcfg2;
+	unsigned int pllcfg3;
+	unsigned int pllcfg4;
+	unsigned int pllstatus;
+	unsigned int rxstatus;
+	unsigned int txstatus;
+	unsigned int testcfg;
+};
+
+#define SEL_IN_FREQ		(0x1 << 31)
+#define DIGCLRZ			(0x1 << 30)
+#define ENDIGLDO		(0x1 << 4)
+#define APLL_CP_CURR		(0x1 << 3)
+#define ENBGSC_REF		(0x1 << 2)
+#define ENPLLLDO		(0x1 << 1)
+#define ENPLL			(0x1 << 0)
+
+#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
+#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
+#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
+#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
+			ENPLLLDO | ENPLL)
+
+#define PLL_LOCK		(0x1 << 0)
+
+#define ENSATAMODE		(0x1 << 31)
+#define PLLREFSEL		(0x1 << 30)
+#define MDIVINT			(0x4b << 18)
+#define EN_CLKAUX		(0x1 << 5)
+#define EN_CLK125M		(0x1 << 4)
+#define EN_CLK100M		(0x1 << 3)
+#define EN_CLK50M		(0x1 << 2)
+
+#define SATA_PLLCFG1 (ENSATAMODE |	\
+		      PLLREFSEL |	\
+		      MDIVINT |		\
+		      EN_CLKAUX |	\
+		      EN_CLK125M |	\
+		      EN_CLK100M |	\
+		      EN_CLK50M)
+
+#define DIGLDO_EN_CAPLESSMODE	(0x1 << 22)
+#define PLLDO_EN_LDO_STABLE	(0x1 << 11)
+#define PLLDO_EN_BUF_CUR	(0x1 << 7)
+#define PLLDO_EN_LP		(0x1 << 6)
+#define PLLDO_CTRL_TRIM_1_4V	(0x10 << 1)
+
+#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE |	\
+		      PLLDO_EN_LDO_STABLE |	\
+		      PLLDO_EN_BUF_CUR |	\
+		      PLLDO_EN_LP |		\
+		      PLLDO_CTRL_TRIM_1_4V)
 
 const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
 const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
+const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
 
 /*
  * Enable the peripheral clock for required peripherals
@@ -221,6 +281,15 @@
 	writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
 	while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
 		;
+
+	/* Ethernet */
+	writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
+	writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
+	while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
+		;
+	writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
+	while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
+		;
 }
 
 /*
@@ -365,6 +434,35 @@
 	pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
 }
 
+void sata_pll_config(void)
+{
+	/*
+	 * This sequence for configuring the SATA PLL
+	 * resident in the control module is documented
+	 * in TI8148 TRM section 21.3.1
+	 */
+	writel(SATA_PLLCFG1, &spll->pllcfg1);
+	udelay(50);
+
+	writel(SATA_PLLCFG3, &spll->pllcfg3);
+	udelay(50);
+
+	writel(SATA_PLLCFG0_1, &spll->pllcfg0);
+	udelay(50);
+
+	writel(SATA_PLLCFG0_2, &spll->pllcfg0);
+	udelay(50);
+
+	writel(SATA_PLLCFG0_3, &spll->pllcfg0);
+	udelay(50);
+
+	writel(SATA_PLLCFG0_4, &spll->pllcfg0);
+	udelay(50);
+
+	while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
+		;
+}
+
 void enable_emif_clocks(void) {};
 
 void enable_dmm_clocks(void)
@@ -397,9 +495,10 @@
 	/* Enable the control module */
 	writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
 
+	/* Configure PLLs */
 	mpu_pll_config();
-
 	l3_pll_config();
+	sata_pll_config();
 
 	/* Enable the required peripherals */
 	enable_per_clocks();
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c
index 5fd8b47..ac049ac 100644
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -92,7 +92,6 @@
 int print_cpuinfo(void)
 {
 	char *cpu_s, *sec_s;
-	int arm_freq, ddr_freq;
 
 	switch (get_cpu_type()) {
 	case AM335X:
@@ -123,10 +122,7 @@
 		sec_s = "?";
 	}
 
-	printf("%s-%s rev %d\n",
-			cpu_s, sec_s, get_cpu_rev());
-
-	/* TODO: Print ARM and DDR frequencies  */
+	printf("%s-%s rev %d\n", cpu_s, sec_s, get_cpu_rev());
 
 	return 0;
 }
diff --git a/board/alaska/Makefile b/arch/arm/cpu/armv7/at91/Makefile
similarity index 72%
copy from board/alaska/Makefile
copy to arch/arm/cpu/armv7/at91/Makefile
index a21f851..040c67d 100644
--- a/board/alaska/Makefile
+++ b/arch/arm/cpu/armv7/at91/Makefile
@@ -1,7 +1,10 @@
 #
-# (C) Copyright 2003-2006
+# (C) Copyright 2000-2008
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
+# (C) Copyright 2013
+# Bo Shen <voice.shen@atmel.com>
+#
 # See file CREDITS for list of people who contributed to this
 # project.
 #
@@ -12,7 +15,7 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
@@ -23,13 +26,18 @@
 
 include $(TOPDIR)/config.mk
 
-LIB	= $(obj)lib$(BOARD).o
+LIB	= $(obj)lib$(SOC).o
 
-COBJS	:= $(BOARD).o flash.o
+COBJS-$(CONFIG_SAMA5D3)	+= sama5d3_devices.o
+COBJS-y += clock.o
+COBJS-y += cpu.o
+COBJS-y += reset.o
+COBJS-y += timer.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+SRCS    := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS    := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
 
 $(LIB):	$(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
diff --git a/arch/arm/cpu/armv7/at91/clock.c b/arch/arm/cpu/armv7/at91/clock.c
new file mode 100644
index 0000000..624b52c
--- /dev/null
+++ b/arch/arm/cpu/armv7/at91/clock.c
@@ -0,0 +1,125 @@
+/*
+ * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
+ *
+ * Copyright (C) 2005 David Brownell
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static unsigned long at91_css_to_rate(unsigned long css)
+{
+	switch (css) {
+	case AT91_PMC_MCKR_CSS_SLOW:
+		return CONFIG_SYS_AT91_SLOW_CLOCK;
+	case AT91_PMC_MCKR_CSS_MAIN:
+		return gd->arch.main_clk_rate_hz;
+	case AT91_PMC_MCKR_CSS_PLLA:
+		return gd->arch.plla_rate_hz;
+	}
+
+	return 0;
+}
+
+static u32 at91_pll_rate(u32 freq, u32 reg)
+{
+	unsigned mul, div;
+
+	div = reg & 0xff;
+	mul = (reg >> 18) & 0x7f;
+	if (div && mul) {
+		freq /= div;
+		freq *= mul + 1;
+	} else {
+		freq = 0;
+	}
+
+	return freq;
+}
+
+int at91_clock_init(unsigned long main_clock)
+{
+	unsigned freq, mckr;
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+	unsigned tmp;
+	/*
+	 * When the bootloader initialized the main oscillator correctly,
+	 * there's no problem using the cycle counter.  But if it didn't,
+	 * or when using oscillator bypass mode, we must be told the speed
+	 * of the main clock.
+	 */
+	if (!main_clock) {
+		do {
+			tmp = readl(&pmc->mcfr);
+		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
+		tmp &= AT91_PMC_MCFR_MAINF_MASK;
+		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+	}
+#endif
+	gd->arch.main_clk_rate_hz = main_clock;
+
+	/* report if PLLA is more than mildly overclocked */
+	gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+
+	/*
+	 * MCK and CPU derive from one of those primary clocks.
+	 * For now, assume this parentage won't change.
+	 */
+	mckr = readl(&pmc->mckr);
+
+	/* plla divisor by 2 */
+	if (mckr & (1 << 12))
+		gd->arch.plla_rate_hz >>= 1;
+
+	gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+	freq = gd->arch.mck_rate_hz;
+
+	/* prescale */
+	freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
+
+	switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
+	case AT91_PMC_MCKR_MDIV_2:
+		gd->arch.mck_rate_hz = freq / 2;
+		break;
+	case AT91_PMC_MCKR_MDIV_3:
+		gd->arch.mck_rate_hz = freq / 3;
+		break;
+	case AT91_PMC_MCKR_MDIV_4:
+		gd->arch.mck_rate_hz = freq / 4;
+		break;
+	default:
+		break;
+	}
+
+	gd->arch.cpu_clk_rate_hz = freq;
+
+	return 0;
+}
+
+void at91_periph_clk_enable(int id)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	if (id > 31)
+		writel(1 << (id - 32), &pmc->pcer1);
+	else
+		writel(1 << id, &pmc->pcer);
+}
diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c
new file mode 100644
index 0000000..3df6143
--- /dev/null
+++ b/arch/arm/cpu/armv7/at91/cpu.c
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ * (C) Copyright 2009
+ * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_dbu.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_gpbr.h>
+#include <asm/arch/clk.h>
+
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#endif
+
+int arch_cpu_init(void)
+{
+	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+}
+
+void arch_preboot_os(void)
+{
+	ulong cpiv;
+	at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+	cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
+
+	/*
+	 * Disable PITC
+	 * Add 0x1000 to current counter to stop it faster
+	 * without waiting for wrapping back to 0
+	 */
+	writel(cpiv + 0x1000, &pit->mr);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	char buf[32];
+
+	printf("CPU: %s\n", get_cpu_name());
+	printf("Crystal frequency: %8s MHz\n",
+	       strmhz(buf, get_main_clk_rate()));
+	printf("CPU clock        : %8s MHz\n",
+	       strmhz(buf, get_cpu_clk_rate()));
+	printf("Master clock     : %8s MHz\n",
+	       strmhz(buf, get_mck_clk_rate()));
+
+	return 0;
+}
+#endif
+
+void enable_caches(void)
+{
+}
+
+unsigned int get_chip_id(void)
+{
+	return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK;
+}
+
+unsigned int get_extension_chip_id(void)
+{
+	return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID);
+}
diff --git a/arch/arm/cpu/armv7/at91/reset.c b/arch/arm/cpu/armv7/at91/reset.c
new file mode 100644
index 0000000..b9f83d9
--- /dev/null
+++ b/arch/arm/cpu/armv7/at91/reset.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_rstc.h>
+
+/* Reset the cpu by telling the reset controller to do so */
+void reset_cpu(ulong ignored)
+{
+	at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
+
+	writel(AT91_RSTC_KEY
+		| AT91_RSTC_CR_PROCRST	/* Processor Reset */
+		| AT91_RSTC_CR_PERRST	/* Peripheral Reset */
+#ifdef CONFIG_AT91RESET_EXTRST
+		| AT91_RSTC_CR_EXTRST	/* External Reset (assert nRST pin) */
+#endif
+		, &rstc->cr);
+	/* never reached */
+	do { } while (1);
+}
diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
new file mode 100644
index 0000000..acf8b43
--- /dev/null
+++ b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2012-2013 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/sama5d3.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+
+unsigned int has_emac()
+{
+	return cpu_is_sama5d31() || cpu_is_sama5d35();
+}
+
+unsigned int has_gmac()
+{
+	return !cpu_is_sama5d31();
+}
+
+unsigned int has_lcdc()
+{
+	return !cpu_is_sama5d35();
+}
+
+char *get_cpu_name()
+{
+	unsigned int extension_id = get_extension_chip_id();
+
+	if (cpu_is_sama5d3())
+		switch (extension_id) {
+		case ARCH_EXID_SAMA5D31:
+			return "SAMA5D31";
+		case ARCH_EXID_SAMA5D33:
+			return "SAMA5D33";
+		case ARCH_EXID_SAMA5D34:
+			return "SAMA5D34";
+		case ARCH_EXID_SAMA5D35:
+			return "SAMA5D35";
+		default:
+			return "Unknown CPU type";
+		}
+	else
+		return "Unknown CPU type";
+}
+
+void at91_serial0_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTD, 18, 1);	/* TXD0 */
+	at91_set_a_periph(AT91_PIO_PORTD, 17, 0);	/* RXD0 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_USART0);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTB, 29, 1);	/* TXD1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 28, 0);	/* RXD1 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_USART1);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_set_b_periph(AT91_PIO_PORTE, 26, 1);	/* TXD2 */
+	at91_set_b_periph(AT91_PIO_PORTE, 25, 0);	/* RXD2 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_USART2);
+}
+
+void at91_seriald_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTB, 31, 1);	/* DTXD */
+	at91_set_a_periph(AT91_PIO_PORTB, 30, 0);	/* DRXD */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SYS);
+}
+
+#if defined(CONFIG_ATMEL_SPI)
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+	at91_set_a_periph(AT91_PIO_PORTD, 10, 0);       /* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTD, 11, 0);       /* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTD, 12, 0);       /* SPI0_SPCK */
+
+	if (cs_mask & (1 << 0))
+		at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
+	if (cs_mask & (1 << 1))
+		at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
+	if (cs_mask & (1 << 2))
+		at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
+	if (cs_mask & (1 << 3))
+		at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void at91_mci_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTD, 0, 0);	/* MCI0 CMD */
+	at91_set_a_periph(AT91_PIO_PORTD, 1, 0);	/* MCI0 DA0 */
+	at91_set_a_periph(AT91_PIO_PORTD, 2, 0);	/* MCI0 DA1 */
+	at91_set_a_periph(AT91_PIO_PORTD, 3, 0);        /* MCI0 DA2 */
+	at91_set_a_periph(AT91_PIO_PORTD, 4, 0);        /* MCI0 DA3 */
+#ifdef CONFIG_ATMEL_MCI_8BIT
+	at91_set_a_periph(AT91_PIO_PORTD, 5, 0);        /* MCI0 DA4 */
+	at91_set_a_periph(AT91_PIO_PORTD, 6, 0);        /* MCI0 DA5 */
+	at91_set_a_periph(AT91_PIO_PORTD, 7, 0);        /* MCI0 DA6 */
+	at91_set_a_periph(AT91_PIO_PORTD, 8, 0);        /* MCI0 DA7 */
+#endif
+	at91_set_a_periph(AT91_PIO_PORTD, 9, 0);        /* MCI0 CLK */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_MCI0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* ETXCK_EREFCK */
+	at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* ERXDV */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* ERX0 */
+	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* ERX1 */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* ERXER */
+	at91_set_a_periph(AT91_PIO_PORTC, 4, 0);	/* ETXEN */
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* ETX0 */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* ETX1 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* EMDIO */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* EMDC */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
+}
+#endif
+
+#ifdef CONFIG_LCD
+void at91_lcd_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTA, 24, 0);	/* LCDPWM */
+	at91_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* LCDDISP */
+	at91_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* LCDVSYNC */
+	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTA, 28, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTA, 29, 0);	/* LCDDEN */
+
+	/* The lower 16-bit of LCD only available on Port A */
+	at91_set_a_periph(AT91_PIO_PORTA,  0, 0);	/* LCDD0 */
+	at91_set_a_periph(AT91_PIO_PORTA,  1, 0);	/* LCDD1 */
+	at91_set_a_periph(AT91_PIO_PORTA,  2, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTA,  3, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTA,  4, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTA,  5, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTA,  6, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTA,  7, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTA,  8, 0);	/* LCDD8 */
+	at91_set_a_periph(AT91_PIO_PORTA,  9, 0);	/* LCDD9 */
+	at91_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* LCDD12 */
+	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* LCDD15 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c
new file mode 100644
index 0000000..b3a450f
--- /dev/null
+++ b/arch/arm/cpu/armv7/at91/timer.c
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <div64.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * We're using the SAMA5D3x PITC in 32 bit mode, by
+ * setting the 20 bit counter period to its maximum (0xfffff).
+ * (See the relevant data sheets to understand that this really works)
+ *
+ * We do also mimic the typical powerpc way of incrementing
+ * two 32 bit registers called tbl and tbu.
+ *
+ * Those registers increment at 1/16 the main clock rate.
+ */
+
+#define TIMER_LOAD_VAL	0xfffff
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, gd->arch.timer_rate_hz);
+
+	return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+	usec *= gd->arch.timer_rate_hz;
+	do_div(usec, 1000000);
+
+	return usec;
+}
+
+/*
+ * Use the PITC in full 32 bit incrementing mode
+ */
+int timer_init(void)
+{
+	at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+	/* Enable PITC Clock */
+	at91_periph_clk_enable(ATMEL_ID_SYS);
+
+	/* Enable PITC */
+	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
+
+	gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
+	gd->arch.tbu = 0;
+	gd->arch.tbl = 0;
+
+	return 0;
+}
+
+/*
+ * Get the current 64 bit timer tick count
+ */
+unsigned long long get_ticks(void)
+{
+	at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+	ulong now = readl(&pit->piir);
+
+	/* increment tbu if tbl has rolled over */
+	if (now < gd->arch.tbl)
+		gd->arch.tbu++;
+	gd->arch.tbl = now;
+	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long start;
+	ulong tmo;
+
+	start = get_ticks();		/* get current timestamp */
+	tmo = usec_to_tick(usec);	/* convert usecs to ticks */
+	while ((get_ticks() - start) < tmo)
+		;			/* loop till time has passed */
+}
+
+/*
+ * get_timer(base) can be used to check for timeouts or
+ * to measure elasped time relative to an event:
+ *
+ * ulong start_time = get_timer(0) sets start_time to the current
+ * time value.
+ * get_timer(start_time) returns the time elapsed since then.
+ *
+ * The time is used in CONFIG_SYS_HZ units!
+ */
+ulong get_timer(ulong base)
+{
+	return tick_to_time(get_ticks()) - base;
+}
+
+/*
+ * Return the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return gd->arch.timer_rate_hz;
+}
diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S
index 0d45528..0a15aa4 100644
--- a/arch/arm/cpu/armv7/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/lowlevel_init.S
@@ -37,7 +37,13 @@
 	 */
 	ldr	sp, =CONFIG_SYS_INIT_SP_ADDR
 	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
+#ifdef CONFIG_SPL_BUILD
+	ldr	r8, =gdata
+#else
+	sub	sp, #GD_SIZE
+	bic	sp, sp, #7
+	mov	r8, sp
+#endif
 	/*
 	 * Save the old lr(passed in ip) and the current lr to stack
 	 */
diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile
index ecd1184..e05fae9 100644
--- a/arch/arm/cpu/armv7/mx5/Makefile
+++ b/arch/arm/cpu/armv7/mx5/Makefile
@@ -27,7 +27,7 @@
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	= soc.o clock.o iomux.o
+COBJS	= soc.o clock.o
 SOBJS = lowlevel_init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 76c2c52..431756e 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -739,10 +739,11 @@
 static int config_nfc_clk(u32 nfc_clk)
 {
 	u32 parent_rate = get_emi_slow_clk();
-	u32 div = parent_rate / nfc_clk;
+	u32 div;
 
-	if (nfc_clk <= 0)
+	if (nfc_clk == 0)
 		return -EINVAL;
+	div = parent_rate / nfc_clk;
 	if (div == 0)
 		div++;
 	if (parent_rate / div > NFC_CLK_MAX)
@@ -755,6 +756,15 @@
 	return 0;
 }
 
+void enable_nfc_clk(unsigned char enable)
+{
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR5,
+		MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
+		MXC_CCM_CCGR5_EMI_ENFC(cg));
+}
+
 /* Config main_bus_clock for periphs */
 static int config_periph_clk(u32 ref, u32 freq)
 {
diff --git a/arch/arm/cpu/armv7/mx5/iomux.c b/arch/arm/cpu/armv7/mx5/iomux.c
deleted file mode 100644
index d4e3bbb..0000000
--- a/arch/arm/cpu/armv7/mx5/iomux.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/sys_proto.h>
-
-/* IOMUX register (base) addresses */
-enum iomux_reg_addr {
-	IOMUXGPR0 = IOMUXC_BASE_ADDR,
-	IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
-	IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
-	IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
-	IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
-	IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
-};
-
-#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
-
-/* Get the iomux register address of this pin */
-static inline u32 get_mux_reg(iomux_pin_name_t pin)
-{
-	u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
-#if defined(CONFIG_MX51)
-	if (is_soc_rev(CHIP_REV_2_0) < 0) {
-		/*
-		 * Fixup register address:
-		 * i.MX51 TO1 has offset with the register
-		 * which is define as TO2.
-		 */
-		if ((pin == MX51_PIN_NANDF_RB5) ||
-			(pin == MX51_PIN_NANDF_RB6) ||
-			(pin == MX51_PIN_NANDF_RB7))
-			; /* Do nothing */
-		else if (mux_reg >= 0x2FC)
-			mux_reg += 8;
-		else if (mux_reg >= 0x130)
-			mux_reg += 0xC;
-	}
-#endif
-	mux_reg += IOMUXSW_MUX_CTL;
-	return mux_reg;
-}
-
-/* Get the pad register address of this pin */
-static inline u32 get_pad_reg(iomux_pin_name_t pin)
-{
-	u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
-
-#if defined(CONFIG_MX51)
-	if (is_soc_rev(CHIP_REV_2_0) < 0) {
-		/*
-		 * Fixup register address:
-		 * i.MX51 TO1 has offset with the register
-		 * which is define as TO2.
-		 */
-		if ((pin == MX51_PIN_NANDF_RB5) ||
-			(pin == MX51_PIN_NANDF_RB6) ||
-			(pin == MX51_PIN_NANDF_RB7))
-			; /* Do nothing */
-		else if (pad_reg == 0x4D0 - PAD_I_START)
-			pad_reg += 0x4C;
-		else if (pad_reg == 0x860 - PAD_I_START)
-			pad_reg += 0x9C;
-		else if (pad_reg >= 0x804 - PAD_I_START)
-			pad_reg += 0xB0;
-		else if (pad_reg >= 0x7FC - PAD_I_START)
-			pad_reg += 0xB4;
-		else if (pad_reg >= 0x4E4 - PAD_I_START)
-			pad_reg += 0xCC;
-		else
-			pad_reg += 8;
-	}
-#endif
-	pad_reg += IOMUXSW_PAD_CTL;
-	return pad_reg;
-}
-
-/* Get the last iomux register address */
-static inline u32 get_mux_end(void)
-{
-#if defined(CONFIG_MX51)
-	if (is_soc_rev(CHIP_REV_2_0) < 0)
-		return IOMUXC_BASE_ADDR + (0x3F8 - 4);
-	else
-		return IOMUXC_BASE_ADDR + (0x3F0 - 4);
-#endif
-	return IOMUXSW_MUX_END;
-}
-
-/*
- * This function is used to configure a pin through the IOMUX module.
- * @param  pin		a pin number as defined in iomux_pin_name_t
- * @param  cfg		an output function as defined in iomux_pin_cfg_t
- *
- * @return 		0 if successful; Non-zero otherwise
- */
-static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-	u32 mux_reg = get_mux_reg(pin);
-
-	if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
-		return ;
-	if (cfg == IOMUX_CONFIG_GPIO)
-		writel(PIN_TO_ALT_GPIO(pin), mux_reg);
-	else
-		writel(cfg, mux_reg);
-}
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param  pin		a name defined by iomux_pin_name_t
- * @param  cfg		an input function as defined in iomux_pin_cfg_t
- *
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-	iomux_config_mux(pin, cfg);
-}
-
-/*
- * Release ownership for an IO pin
- *
- * @param  pin		a name defined by iomux_pin_name_t
- * @param  cfg		an input function as defined in iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param  pin     a pin number as defined in iomux_pin_name_t
- * @param  config  the ORed value of elements defined in iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
-	u32 pad_reg = get_pad_reg(pin);
-	writel(config, pad_reg);
-}
-
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
-{
-	u32 pad_reg = get_pad_reg(pin);
-	return readl(pad_reg);
-}
-
-/*
- * This function configures daisy-chain
- *
- * @param input    index of input select register
- * @param config   the binary value of elements
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
-	u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
-	writel(config, reg);
-}
diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index 263658a..3d50a5d 100644
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -72,6 +72,13 @@
 	return system_rev;
 }
 
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+#endif
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index a50db70..3c0d908 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -37,6 +37,20 @@
 
 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+	u32 reg;
+
+	reg = __raw_readl(&imx_ccm->CCGR2);
+	if (enable)
+		reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+	else
+		reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+	__raw_writel(reg, &imx_ccm->CCGR2);
+}
+#endif
+
 void enable_usboh3_clk(unsigned char enable)
 {
 	u32 reg;
@@ -186,12 +200,16 @@
 static u32 get_uart_clk(void)
 {
 	u32 reg, uart_podf;
-
+	u32 freq = PLL3_80M;
 	reg = __raw_readl(&imx_ccm->cscdr1);
+#ifdef CONFIG_MX6SL
+	if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+		freq = MXC_HCLK;
+#endif
 	reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 	uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 
-	return PLL3_80M / (uart_podf + 1);
+	return freq / (uart_podf + 1);
 }
 
 static u32 get_cspi_clk(void)
@@ -252,6 +270,35 @@
 	return root_freq / (emi_slow_pof + 1);
 }
 
+#ifdef CONFIG_MX6SL
+static u32 get_mmdc_ch0_clk(void)
+{
+	u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
+	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+	u32 freq, podf;
+
+	podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
+			>> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+
+	switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+		MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+	case 0:
+		freq = decode_pll(PLL_BUS, MXC_HCLK);
+		break;
+	case 1:
+		freq = PLL2_PFD2_FREQ;
+		break;
+	case 2:
+		freq = PLL2_PFD0_FREQ;
+		break;
+	case 3:
+		freq = PLL2_PFD2_DIV_FREQ;
+	}
+
+	return freq / (podf + 1);
+
+}
+#else
 static u32 get_mmdc_ch0_clk(void)
 {
 	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
@@ -260,6 +307,7 @@
 
 	return get_periph_clk() / (mmdc_ch0_podf + 1);
 }
+#endif
 
 static u32 get_usdhc_clk(u32 port)
 {
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 2ea8ca3..fc436fb 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -30,6 +30,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/dma.h>
 #include <stdbool.h>
 
 struct scu_regs {
@@ -151,6 +152,12 @@
 	set_vddsoc(1200);	/* Set VDDSOC to 1.2V */
 
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+
+#ifdef CONFIG_APBH_DMA
+	/* Start APBH DMA */
+	mxs_dma_init();
+#endif
+
 	return 0;
 }
 
@@ -165,8 +172,8 @@
 #if defined(CONFIG_FEC_MXC)
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
-	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-	struct fuse_bank *bank = &iim->bank[4];
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[4];
 	struct fuse_bank4_regs *fuse =
 			(struct fuse_bank4_regs *)bank->fuse_regs;
 
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 24cbe2d..76ae1b6 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -23,31 +23,56 @@
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 
-/*
- * This is used to verify if the configuration header
- * was executed by rom code prior to control of transfer
- * to the bootloader. SPL is responsible for saving and
- * passing the boot_params pointer to the u-boot.
- */
-struct omap_boot_parameters boot_params __attribute__ ((section(".data")));
+DECLARE_GLOBAL_DATA_PTR;
+
+void save_omap_boot_params(void)
+{
+	u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
+	u8 boot_device;
+	u32 dev_desc, dev_data;
+
+	if ((rom_params <  NON_SECURE_SRAM_START) ||
+	    (rom_params > NON_SECURE_SRAM_END))
+		return;
+
+	/*
+	 * rom_params can be type casted to omap_boot_parameters and
+	 * used. But it not correct to assume that romcode structure
+	 * encoding would be same as u-boot. So use the defined offsets.
+	 */
+	gd->arch.omap_boot_params.omap_bootdevice = boot_device =
+				   *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+
+	gd->arch.omap_boot_params.ch_flags =
+				*((u8 *)(rom_params + CH_FLAGS_OFFSET));
+
+	if ((boot_device >= MMC_BOOT_DEVICES_START) &&
+	    (boot_device <= MMC_BOOT_DEVICES_END)) {
+#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX)
+		if ((omap_hw_init_context() ==
+				      OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
+			gd->arch.omap_boot_params.omap_bootmode =
+			*((u8 *)(rom_params + BOOT_MODE_OFFSET));
+		} else
+#endif
+		{
+			dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET));
+			dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET));
+			gd->arch.omap_boot_params.omap_bootmode =
+					*((u32 *)(dev_data + BOOT_MODE_OFFSET));
+		}
+	}
+}
 
 #ifdef CONFIG_SPL_BUILD
-/*
- * We use static variables because global data is not ready yet.
- * Initialized data is available in SPL right from the beginning.
- * We would not typically need to save these parameters in regular
- * U-Boot. This is needed only in SPL at the moment.
- */
-u32 omap_bootmode = MMCSD_MODE_FAT;
-
 u32 spl_boot_device(void)
 {
-	return (u32) (boot_params.omap_bootdevice);
+	return (u32) (gd->arch.omap_boot_params.omap_bootdevice);
 }
 
 u32 spl_boot_mode(void)
 {
-	return omap_bootmode;
+	return gd->arch.omap_boot_params.omap_bootmode;
 }
 
 void spl_board_init(void)
@@ -73,4 +98,15 @@
 	}
 	return 0;
 }
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	typedef void __noreturn (*image_entry_noargs_t)(u32 *);
+	image_entry_noargs_t image_entry =
+			(image_entry_noargs_t) spl_image->entry_point;
+
+	debug("image entry point: 0x%X\n", spl_image->entry_point);
+	/* Pass the saved boot_params from rom code */
+	image_entry((u32 *)&gd->arch.omap_boot_params);
+}
 #endif
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 2b955c7..99910cd 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -716,6 +716,7 @@
 		setup_non_essential_dplls();
 		enable_non_essential_clocks();
 #endif
+		setup_warmreset_time();
 		break;
 	default:
 		break;
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index cdb4439..11e830a 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1075,6 +1075,11 @@
 		else
 			ddr3_init(base, regs);
 	}
+	if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
+		set_lpmode_selfrefresh(base);
+		emif_reset_phy(base);
+		ddr3_leveling(base, regs);
+	}
 
 	/* Write to the shadow registers */
 	emif_update_timings(base, regs);
@@ -1262,10 +1267,10 @@
 	in_sdram = running_from_sdram();
 	debug("in_sdram = %d\n", in_sdram);
 
-	if (!(in_sdram || warm_reset())) {
-		if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
+	if (!in_sdram) {
+		if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
 			bypass_dpll((*prcm)->cm_clkmode_dpll_core);
-		else
+		else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
 			writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
 	}
 
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 70d16a8..0776d5c 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -84,7 +84,7 @@
 	return rev;
 }
 
-void omap_rev_string(void)
+static void omap_rev_string(void)
 {
 	u32 omap_rev = omap_revision();
 	u32 soc_variant	= (omap_rev & 0xF0000000) >> 28;
@@ -101,11 +101,6 @@
 }
 
 #ifdef CONFIG_SPL_BUILD
-static void init_boot_params(void)
-{
-	boot_params_ptr = (u32 *) &boot_params;
-}
-
 void spl_display_print(void)
 {
 	omap_rev_string();
@@ -116,6 +111,17 @@
 {
 }
 
+#ifdef CONFIG_ARCH_CPU_INIT
+/*
+ * SOC specific cpu init
+ */
+int arch_cpu_init(void)
+{
+	save_omap_boot_params();
+	return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
 /*
  * Routine: s_init
  * Description: Does early system init of watchdog, muxing,  andclocks
@@ -132,6 +138,14 @@
  */
 void s_init(void)
 {
+	/*
+	 * Save the boot parameters passed from romcode.
+	 * We cannot delay the saving further than this,
+	 * to prevent overwrites.
+	 */
+#ifdef CONFIG_SPL_BUILD
+	save_omap_boot_params();
+#endif
 	init_omap_revision();
 	hw_data_init();
 
@@ -156,7 +170,6 @@
 
 	/* For regular u-boot sdram_init() is called from dram_init() */
 	sdram_init();
-	init_boot_params();
 #endif
 }
 
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 90b3c8a..c489536 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -28,59 +28,13 @@
 
 #include <config.h>
 #include <asm/arch/omap.h>
+#include <asm/omap_common.h>
 #include <asm/arch/spl.h>
 #include <linux/linkage.h>
 
 ENTRY(save_boot_params)
-	/*
-	 * See if the rom code passed pointer is valid:
-	 * It is not valid if it is not in non-secure SRAM
-	 * This may happen if you are booting with the help of
-	 * debugger
-	 */
-	ldr     r2, =NON_SECURE_SRAM_START
-	cmp	r2, r0
-	bgt	1f
-	ldr	r2, =NON_SECURE_SRAM_END
-	cmp	r2, r0
-	blt	1f
-
-	/*
-	 * store the boot params passed from rom code or saved
-	 * and passed by SPL
-	 */
-	cmp	r0, #0
-	beq	1f
-	ldr	r1, =boot_params
+	ldr	r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
 	str	r0, [r1]
-#ifdef CONFIG_SPL_BUILD
-	/* Store the boot device in spl_boot_device */
-	ldrb	r2, [r0, #BOOT_DEVICE_OFFSET]	@ r1 <- value of boot device
-	and	r2, #BOOT_DEVICE_MASK
-	ldr	r3, =boot_params
-	strb	r2, [r3, #BOOT_DEVICE_OFFSET]	@ spl_boot_device <- r1
-
-	/*
-	 * boot mode is only valid for device that can be raw or FAT booted.
-	 * in other cases it may be fatal to look.  While platforms differ
-	 * in the values used for each MMC slot, they are contiguous.
-	 */
-	cmp	r2, #MMC_BOOT_DEVICES_START
-	blt	2f
-	cmp	r2, #MMC_BOOT_DEVICES_END
-	bgt	2f
-	/* Store the boot mode (raw/FAT) in omap_bootmode */
-	ldr	r2, [r0, #DEV_DESC_PTR_OFFSET]	@ get the device descriptor ptr
-	ldr	r2, [r2, #DEV_DATA_PTR_OFFSET]	@ get the pDeviceData ptr
-	ldr	r2, [r2, #BOOT_MODE_OFFSET]	@ get the boot mode
-	ldr	r3, =omap_bootmode
-	str	r2, [r3]
-#endif
-2:
-	ldrb	r2, [r0, #CH_FLAGS_OFFSET]
-	ldr	r3, =boot_params
-	strb	r2, [r3, #CH_FLAGS_OFFSET]
-1:
 	bx	lr
 ENDPROC(save_boot_params)
 
diff --git a/arch/arm/cpu/armv7/omap-common/reset.c b/arch/arm/cpu/armv7/omap-common/reset.c
index 587bb47..57ea9d9 100644
--- a/arch/arm/cpu/armv7/omap-common/reset.c
+++ b/arch/arm/cpu/armv7/omap-common/reset.c
@@ -39,3 +39,7 @@
 {
 	return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK);
 }
+
+void __weak setup_warmreset_time(void)
+{
+}
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 53f6063..0ddf35f 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -31,8 +31,8 @@
 #include <asm/utils.h>
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
-u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
+u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
+u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
 #endif
 
 #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 04977b4..06a2fc8 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -40,7 +40,7 @@
 struct vcores_data const **omap_vcores =
 		(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
 struct omap_sys_ctrl_regs const **ctrl =
-	(struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL;
+	(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
 
 /*
  * The M & N values in the following tables are created using the
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
index 2db517b..81f5a48 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -34,10 +34,11 @@
 #include <asm/sizes.h>
 #include <asm/emif.h>
 #include <asm/arch/gpio.h>
+#include <asm/omap_common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 *const omap_si_rev = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
+u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
 
 static const struct gpio_bank gpio_bank_44xx[6] = {
 	{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
diff --git a/arch/arm/cpu/armv7/omap5/emif.c b/arch/arm/cpu/armv7/omap5/emif.c
index 3f37abd..b4c1319 100644
--- a/arch/arm/cpu/armv7/omap5/emif.c
+++ b/arch/arm/cpu/armv7/omap5/emif.c
@@ -32,8 +32,8 @@
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
-static u32 *const T_num = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_NUM;
-static u32 *const T_den = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_DEN;
+static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
+static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
 #endif
 
 #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index ced274e..604fa42 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -41,7 +41,7 @@
 struct vcores_data const **omap_vcores =
 		(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
 struct omap_sys_ctrl_regs const **ctrl =
-	(struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;
+	(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
 
 /* OPP HIGH FREQUENCY for ES2.0 */
 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
@@ -403,6 +403,7 @@
 	};
 
 	u32 const clk_modules_hw_auto_essential[] = {
+		(*prcm)->cm_l3init_hsusbtll_clkctrl,
 		0
 	};
 
@@ -411,7 +412,7 @@
 		(*prcm)->cm_l4per_i2c2_clkctrl,
 		(*prcm)->cm_l4per_i2c3_clkctrl,
 		(*prcm)->cm_l4per_i2c4_clkctrl,
-		(*prcm)->cm_l3init_hsusbtll_clkctrl,
+		(*prcm)->cm_l4per_i2c5_clkctrl,
 		(*prcm)->cm_l3init_hsusbhost_clkctrl,
 		(*prcm)->cm_l3init_fsusb_clkctrl,
 		0
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 2f4b247..e192fea 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -37,10 +37,11 @@
 #include <asm/utils.h>
 #include <asm/arch/gpio.h>
 #include <asm/emif.h>
+#include <asm/omap_common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
+u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
 
 static struct gpio_bank gpio_bank_54xx[6] = {
 	{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -363,3 +364,22 @@
 {
 	return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
 }
+
+void setup_warmreset_time(void)
+{
+	u32 rst_time, rst_val;
+
+#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
+	rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
+#else
+	rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
+#endif
+	rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
+
+	if (rst_time > RSTTIME1_MASK)
+		rst_time = RSTTIME1_MASK;
+
+	rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
+	rst_val |= rst_time;
+	writel(rst_val, (*prcm)->prm_rsttime);
+}
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index b8a61fe..e9f6a32 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -729,6 +729,7 @@
 	.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
 	.prm_rstctrl = 0x4ae07c00,
 	.prm_rstst = 0x4ae07c04,
+	.prm_rsttime = 0x4ae07c08,
 	.prm_vc_val_bypass = 0x4ae07ca0,
 	.prm_vc_cfg_i2c_mode = 0x4ae07cb4,
 	.prm_vc_cfg_i2c_clk = 0x4ae07cb8,
@@ -952,6 +953,7 @@
 	.cm_wkupaon_scrm_clkctrl		= 0x4ae07890,
 	.prm_rstctrl				= 0x4ae07d00,
 	.prm_rstst				= 0x4ae07d04,
+	.prm_rsttime				= 0x4ae07d08,
 	.prm_vc_val_bypass			= 0x4ae07da0,
 	.prm_vc_cfg_i2c_mode			= 0x4ae07db4,
 	.prm_vc_cfg_i2c_clk			= 0x4ae07db8,
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index e9e57e6..8e9cb19 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -94,10 +94,6 @@
 _bss_start_ofs:
 	.word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-	.word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end - _start
@@ -167,80 +163,6 @@
 
 /*------------------------------------------------------------------------------*/
 
-#ifndef CONFIG_SPL_BUILD
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-ENTRY(relocate_code)
-	mov	r6, r0	/* save addr of destination */
-
-	adr	r0, _start
-	subs	r9, r6, r0		/* r9 <- relocation offset */
-	beq	relocate_done		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _image_copy_end_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
-	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-
-relocate_done:
-
-	bx	lr
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-ENDPROC(relocate_code)
-
-#endif
-
 ENTRY(c_runtime_cpu_setup)
 /*
  * If I-cache is enabled invalidate it
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 788a8fd..52048c6 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -28,6 +28,9 @@
 #define SLCR_LOCK_MAGIC		0x767B
 #define SLCR_UNLOCK_MAGIC	0xDF0D
 
+#define SLCR_IDCODE_MASK	0x1F000
+#define SLCR_IDCODE_SHIFT	12
+
 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
 
 void zynq_slcr_lock(void)
@@ -61,3 +64,61 @@
 
 	writel(1, &slcr_base->pss_rst_ctrl);
 }
+
+/* Setup clk for network */
+void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
+{
+	zynq_slcr_unlock();
+
+	if (gem_id > 1) {
+		printf("Non existing GEM id %d\n", gem_id);
+		goto out;
+	}
+
+	if (gem_id) {
+		/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
+		writel(clk, &slcr_base->gem1_clk_ctrl);
+		/* Configure GEM_RCLK_CTRL */
+		writel(rclk, &slcr_base->gem1_rclk_ctrl);
+	} else {
+		/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
+		writel(clk, &slcr_base->gem0_clk_ctrl);
+		/* Configure GEM_RCLK_CTRL */
+		writel(rclk, &slcr_base->gem0_rclk_ctrl);
+	}
+
+out:
+	zynq_slcr_lock();
+}
+
+void zynq_slcr_devcfg_disable(void)
+{
+	zynq_slcr_unlock();
+
+	/* Disable AXI interface */
+	writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
+
+	/* Set Level Shifters DT618760 */
+	writel(0xA, &slcr_base->lvl_shftr_en);
+
+	zynq_slcr_lock();
+}
+
+void zynq_slcr_devcfg_enable(void)
+{
+	zynq_slcr_unlock();
+
+	/* Set Level Shifters DT618760 */
+	writel(0xF, &slcr_base->lvl_shftr_en);
+
+	/* Disable AXI interface */
+	writel(0x0, &slcr_base->fpga_rst_ctrl);
+
+	zynq_slcr_lock();
+}
+
+u32 zynq_slcr_get_idcode(void)
+{
+	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
+							SLCR_IDCODE_SHIFT;
+}
diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c
index 45b405a..8c4357d 100644
--- a/arch/arm/cpu/armv7/zynq/timer.c
+++ b/arch/arm/cpu/armv7/zynq/timer.c
@@ -44,6 +44,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
+#include <asm/arch/hardware.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -54,7 +55,7 @@
 };
 
 static struct scu_timer *timer_base =
-			      (struct scu_timer *) CONFIG_SCUTIMER_BASEADDR;
+			      (struct scu_timer *)ZYNQ_SCUTIMER_BASEADDR;
 
 #define SCUTIMER_CONTROL_PRESCALER_MASK	0x0000FF00 /* Prescaler */
 #define SCUTIMER_CONTROL_PRESCALER_SHIFT	8
@@ -114,15 +115,43 @@
 
 void __udelay(unsigned long usec)
 {
-	unsigned long long tmp;
-	ulong tmo;
+	u32 countticks;
+	u32 timeend;
+	u32 timediff;
+	u32 timenow;
 
-	tmo = usec / (1000000 / CONFIG_SYS_HZ);
-	tmp = get_ticks() + tmo; /* Get current timestamp */
+	if (usec == 0)
+		return;
 
-	while (get_ticks() < tmp) { /* Loop till event */
-		 /* NOP */;
-	}
+	countticks = (u32) (((unsigned long long) TIMER_TICK_HZ * usec) /
+								1000000);
+
+	/* decrementing timer */
+	timeend = readl(&timer_base->counter) - countticks;
+
+#if TIMER_LOAD_VAL != 0xFFFFFFFF
+	/* do not manage multiple overflow */
+	if (countticks >= TIMER_LOAD_VAL)
+		countticks = TIMER_LOAD_VAL - 1;
+#endif
+
+	do {
+		timenow = readl(&timer_base->counter);
+
+		if (timenow >= timeend) {
+			/* normal case */
+			timediff = timenow - timeend;
+		} else {
+			if ((TIMER_LOAD_VAL - timeend + timenow) <=
+								countticks) {
+				/* overflow */
+				timediff = TIMER_LOAD_VAL - timeend + timenow;
+			} else {
+				/* missed the exact match */
+				break;
+			}
+		}
+	} while (timediff > 0);
 }
 
 /* Timer without interrupts */
diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk
index b02e8af..fd3c29f 100644
--- a/arch/arm/cpu/ixp/config.mk
+++ b/arch/arm/cpu/ixp/config.mk
@@ -31,10 +31,6 @@
 PLATFORM_LDFLAGS += -EB
 USE_PRIVATE_LIBGCC = yes
 
-# -fdata-sections triggers "section .bss overlaps section .rel.dyn" linker error
-PLATFORM_RELFLAGS += -ffunction-sections
-LDFLAGS_u-boot += --gc-sections
-
 # =========================================================================
 #
 # Supply options according to compiler version
diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S
index 69ef8aa..46cba0c 100644
--- a/arch/arm/cpu/ixp/start.S
+++ b/arch/arm/cpu/ixp/start.S
@@ -114,10 +114,6 @@
 _bss_start_ofs:
 	.word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-	.word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end - _start
@@ -257,79 +253,6 @@
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r6, r0	/* save addr of destination */
-
-	adr	r0, _start
-	subs	r9, r6, r0		/* r9 <- relocation offset */
-	beq	relocate_done		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _image_copy_end_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
-	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-relocate_done:
-
-	bx	lr
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c
index 09e8177..0c18610 100644
--- a/arch/arm/cpu/pxa/pxa2xx.c
+++ b/arch/arm/cpu/pxa/pxa2xx.c
@@ -284,7 +284,7 @@
 	writel(readl(CKEN) | CKEN14_I2C, CKEN);
 }
 
-void reset_cpu(ulong ignored) __attribute__((noreturn));
+void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn));
 
 void reset_cpu(ulong ignored)
 {
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index ada91a6..2e3f65e 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -118,10 +118,6 @@
 _bss_start_ofs:
 	.word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-	.word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end - _start
@@ -171,93 +167,23 @@
 	bl	_main
 
 /*------------------------------------------------------------------------------*/
-#ifndef CONFIG_SPL_BUILD
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r6, r0	/* save addr of destination */
-
-/* Disable the Dcache RAM lock for stack now */
-#ifdef	CONFIG_CPU_PXA25X
-	mov	r12, lr
-	bl	cpu_init_crit
-	mov	lr, r12
-#endif
-
-	adr	r0, _start
-	subs	r9, r6, r0		/* r9 <- relocation offset */
-	beq	relocate_done		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _image_copy_end_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
-	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-relocate_done:
-
-	bx	lr
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-#endif
 
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
+#ifdef CONFIG_CPU_PXA25X
+	/*
+	 * Unlock (actually, disable) the cache now that board_init_f
+	 * is done. We could do this earlier but we would need to add
+	 * a new C runtime hook, whereas c_runtime_cpu_setup already
+	 * exists.
+	 * As this routine is just a call to cpu_init_crit, let us
+	 * tail-optimize and do a simple branch here.
+	 */
+	b	cpu_init_crit
+#else
 	bx	lr
+#endif
 
 /*
  *************************************************************************
diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S
index 7361aa2..78183fc 100644
--- a/arch/arm/cpu/s3c44b0/start.S
+++ b/arch/arm/cpu/s3c44b0/start.S
@@ -80,10 +80,6 @@
 _bss_start_ofs:
 	.word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-	.word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end - _start
@@ -140,79 +136,6 @@
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r6, r0	/* save addr of destination */
-
-	adr	r0, _start
-	subs	r9, r6, r0		/* r9 <- relocation offset */
-	beq	relocate_done		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _image_copy_end_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
-	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-relocate_done:
-
-	bx	lr
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index 8a2eafd..30d5a90 100644
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -90,10 +90,6 @@
 _bss_start_ofs:
 	.word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-	.word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end - _start
@@ -144,79 +140,6 @@
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r6, r0	/* save addr of destination */
-
-	adr	r0, _start
-	subs	r9, r6, r0		/* r9 <- relocation offset */
-	beq	relocate_done		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _image_copy_end_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
-	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-relocate_done:
-
-	mov	pc, lr
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 9b77b2b..e099683 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -72,6 +72,7 @@
 	switch (chip_id) {
 	case CHIPID_TEGRA20:
 		switch (sku_id) {
+		case SKU_ID_T20_7:
 		case SKU_ID_T20:
 			return TEGRA_SOC_T20;
 		case SKU_ID_T25SE:
@@ -92,6 +93,7 @@
 	case CHIPID_TEGRA114:
 		switch (sku_id) {
 		case SKU_ID_T114_ENG:
+		case SKU_ID_T114_1:
 			return TEGRA_SOC_T114;
 		}
 		break;
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index 9156d00..268fb91 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -321,17 +321,17 @@
 	unsigned effective_rate;
 	int mux_bits, divider_bits, source;
 	int divider;
+	int xdiv = 0;
 
 	/* work out the source clock and set it */
 	source = get_periph_clock_source(periph_id, parent, &mux_bits,
 					 &divider_bits);
 
+	divider = find_best_divider(divider_bits, pll_rate[parent],
+				    rate, &xdiv);
 	if (extra_div)
-		divider = find_best_divider(divider_bits, pll_rate[parent],
-						rate, extra_div);
-	else
-		divider = clk_get_divider(divider_bits, pll_rate[parent],
-					  rate);
+		*extra_div = xdiv;
+
 	assert(divider >= 0);
 	if (adjust_periph_pll(periph_id, source, mux_bits, divider))
 		return -1U;
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 44b6822..8bba8a5 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -27,10 +27,16 @@
 
 LIB     = $(obj)libimx-common.o
 
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6))
+COBJS-y	= iomux-v3.o
+endif
 ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
-COBJS-y	= iomux-v3.o timer.o cpu.o speed.o
+COBJS-y	+= timer.o cpu.o speed.o
 COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
 endif
+ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
+COBJS-y	+= misc.o
+endif
 COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
 COBJS-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
 COBJS	:= $(sort $(COBJS-y))
@@ -58,8 +64,11 @@
 $(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
 	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
 		-I binary -O binary $< $(OBJTREE)/spl/u-boot-spl-pad.imx
-	cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.bin > $@
-	rm $(OBJTREE)/spl/u-boot-spl-pad.imx
+	$(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
+		-e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \
+		$(OBJTREE)/u-boot.uim
+	cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim > $@
+	rm $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim
 
 $(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
 	(echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \
@@ -69,8 +78,11 @@
 		-I binary -O binary $(OBJTREE)/spl/u-boot-nand-spl.imx \
 		$(OBJTREE)/spl/u-boot-nand-spl-pad.imx
 	rm $(OBJTREE)/spl/u-boot-nand-spl.imx
-	cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.bin > $@
-	rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx
+	$(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
+		-e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \
+		$(OBJTREE)/u-boot.uim
+	cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim > $@
+	rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim
 
 
 #########################################################################
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 08fad78..7fe5ce7 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -30,7 +30,7 @@
 /*
  * configures a single pad in the iomuxer
  */
-int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
+void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 {
 	u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
 	u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
@@ -50,22 +50,14 @@
 
 	if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
 		__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
-
-	return 0;
 }
 
-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
-				     unsigned count)
+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+				      unsigned count)
 {
 	iomux_v3_cfg_t const *p = pad_list;
 	int i;
-	int ret;
 
-	for (i = 0; i < count; i++) {
-		ret = imx_iomux_v3_setup_pad(*p);
-		if (ret)
-			return ret;
-		p++;
-	}
-	return 0;
+	for (i = 0; i < count; i++)
+		imx_iomux_v3_setup_pad(*p++);
 }
diff --git a/arch/arm/imx-common/misc.c b/arch/arm/imx-common/misc.c
new file mode 100644
index 0000000..220785c
--- /dev/null
+++ b/arch/arm/imx-common/misc.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2013 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/imx-common/regs-common.h>
+
+/* 1 second delay should be plenty of time for block reset. */
+#define	RESET_MAX_TIMEOUT	1000000
+
+#define	MXS_BLOCK_SFTRST	(1 << 31)
+#define	MXS_BLOCK_CLKGATE	(1 << 30)
+
+int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
+								int timeout)
+{
+	while (--timeout) {
+		if ((readl(&reg->reg) & mask) == mask)
+			break;
+		udelay(1);
+	}
+
+	return !timeout;
+}
+
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
+								int timeout)
+{
+	while (--timeout) {
+		if ((readl(&reg->reg) & mask) == 0)
+			break;
+		udelay(1);
+	}
+
+	return !timeout;
+}
+
+int mxs_reset_block(struct mxs_register_32 *reg)
+{
+	/* Clear SFTRST */
+	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
+
+	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+		return 1;
+
+	/* Clear CLKGATE */
+	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
+
+	/* Set SFTRST */
+	writel(MXS_BLOCK_SFTRST, &reg->reg_set);
+
+	/* Wait for CLKGATE being set */
+	if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+		return 1;
+
+	/* Clear SFTRST */
+	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
+
+	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+		return 1;
+
+	/* Clear CLKGATE */
+	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
+
+	if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+		return 1;
+
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index fb4e78e..bb53a6a 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -117,6 +117,23 @@
 #define MT41J512M8RH125_PHY_WR_DATA		0x74
 #define MT41J512M8RH125_IOCTRL_VALUE		0x18B
 
+/* Samsung K4B2G1646E-BIH9 */
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY	0x06
+#define K4B2G1646EBIH9_EMIF_TIM1		0x0888A39B
+#define K4B2G1646EBIH9_EMIF_TIM2		0x2A04011A
+#define K4B2G1646EBIH9_EMIF_TIM3		0x501F820F
+#define K4B2G1646EBIH9_EMIF_SDCFG		0x61C24AB2
+#define K4B2G1646EBIH9_EMIF_SDREF		0x0000093B
+#define K4B2G1646EBIH9_ZQ_CFG			0x50074BE4
+#define K4B2G1646EBIH9_DLL_LOCK_DIFF		0x1
+#define K4B2G1646EBIH9_RATIO			0x40
+#define K4B2G1646EBIH9_INVERT_CLKOUT		0x1
+#define K4B2G1646EBIH9_RD_DQS			0x3B
+#define K4B2G1646EBIH9_WR_DQS			0x85
+#define K4B2G1646EBIH9_PHY_FIFO_WE		0x100
+#define K4B2G1646EBIH9_PHY_WR_DATA		0xC1
+#define K4B2G1646EBIH9_IOCTRL_VALUE		0x18B
+
 /**
  * Configure DMM
  */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
index a950ac3..8f9315c 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
@@ -29,6 +29,7 @@
 
 /* Control Module Base Address */
 #define CTRL_BASE			0x48140000
+#define CTRL_DEVICE_BASE		0x48140600
 
 /* PRCM Base Address */
 #define PRCM_BASE			0x48180000
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index d28f9a8..e7576c1 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -29,35 +29,12 @@
  * at 0x40304000(EMU base) so that our code works for both EMU and GP
  */
 #ifdef CONFIG_AM33XX
-#define NON_SECURE_SRAM_START	0x40304000
-#define NON_SECURE_SRAM_END	0x4030E000
+#define NON_SECURE_SRAM_START	0x402F0400
+#define NON_SECURE_SRAM_END	0x40310000
+#define SRAM_SCRATCH_SPACE_ADDR	0x4030C000
 #elif defined(CONFIG_TI814X)
 #define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40320000
-#endif
-
-/* ROM code defines */
-/* Boot device */
-#define BOOT_DEVICE_MASK	0xFF
-#define BOOT_DEVICE_OFFSET	0x8
-#define DEV_DESC_PTR_OFFSET	0x4
-#define DEV_DATA_PTR_OFFSET	0x18
-#define BOOT_MODE_OFFSET	0x8
-#define RESET_REASON_OFFSET	0x9
-#define CH_FLAGS_OFFSET		0xA
-
-#define CH_FLAGS_CHSETTINGS	(0x1 << 0)
-#define CH_FLAGS_CHRAM		(0x1 << 1)
-#define CH_FLAGS_CHFLASH	(0x1 << 2)
-#define CH_FLAGS_CHMMCSD	(0x1 << 3)
-
-#ifndef __ASSEMBLY__
-struct omap_boot_parameters {
-	char *boot_message;
-	unsigned int mem_boot_descriptor;
-	unsigned char omap_bootdevice;
-	unsigned char reset_reason;
-	unsigned char ch_flags;
-};
+#define SRAM_SCRATCH_SPACE_ADDR	0x4031B800
 #endif
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index c913b5f..fedc674 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -30,6 +30,7 @@
 
 extern struct ctrl_stat *cstat;
 u32 get_device_type(void);
+void save_omap_boot_params(void);
 void setup_clocks_for_console(void);
 void ddr_pll_config(unsigned int ddrpll_M);
 
diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h
index 8282f46..5843935 100644
--- a/arch/arm/include/asm/arch-at91/at91_common.h
+++ b/arch/arm/include/asm/arch-at91/at91_common.h
@@ -35,5 +35,6 @@
 void at91_spi0_hw_init(unsigned long cs_mask);
 void at91_spi1_hw_init(unsigned long cs_mask);
 void at91_uhp_hw_init(void);
+void at91_lcd_hw_init(void);
 
 #endif /* AT91_COMMON_H */
diff --git a/arch/arm/include/asm/arch-at91/at91_dbu.h b/arch/arm/include/asm/arch-at91/at91_dbu.h
index 3429293..9a640a5 100644
--- a/arch/arm/include/asm/arch-at91/at91_dbu.h
+++ b/arch/arm/include/asm/arch-at91/at91_dbu.h
@@ -38,4 +38,8 @@
 #define AT91_DBU_CID_ARCH_9xx		0x01900000
 #define AT91_DBU_CID_ARCH_9XExx	0x02900000
 
+#define AT91_DBU_CIDR_MASK		0x1f
+#define AT91_DBU_CIDR			0x40
+#define AT91_DBU_EXID			0x44
+
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h
index 086cb9b..66075b4 100644
--- a/arch/arm/include/asm/arch-at91/at91_pmc.h
+++ b/arch/arm/include/asm/arch-at91/at91_pmc.h
@@ -55,7 +55,16 @@
 	u32	reserved5[21];
 	u32	wpmr;		/* 0xE4 Write Protect Mode Register (CAP0) */
 	u32	wpsr;		/* 0xE8 Write Protect Status Register (CAP0) */
+#ifdef CONFIG_SAMA5D3
+	u32	reserved6[8];
+	u32	pcer1;		/* 0x100 Periperial Clock Enable Register 1 */
+	u32	pcdr1;		/* 0x104 Periperial Clock Disable Register 1 */
+	u32	pcsr1;		/* 0x108 Periperial Clock Status Register 1 */
+	u32	pcr;		/* 0x10c Periperial Control Register */
+	u32	ocr;		/* 0x110 Oscillator Calibration Register */
+#else
 	u32	reserved8[5];
+#endif
 } at91_pmc_t;
 
 #endif	/* end not assembly */
@@ -82,6 +91,16 @@
 #define AT91_PMC_MCKR_CSS_PLLB		0x00000003
 #define AT91_PMC_MCKR_CSS_MASK		0x00000003
 
+#ifdef CONFIG_SAMA5D3
+#define AT91_PMC_MCKR_PRES_1		0x00000000
+#define AT91_PMC_MCKR_PRES_2		0x00000010
+#define AT91_PMC_MCKR_PRES_4		0x00000020
+#define AT91_PMC_MCKR_PRES_8		0x00000030
+#define AT91_PMC_MCKR_PRES_16		0x00000040
+#define AT91_PMC_MCKR_PRES_32		0x00000050
+#define AT91_PMC_MCKR_PRES_64		0x00000060
+#define AT91_PMC_MCKR_PRES_MASK		0x00000070
+#else
 #define AT91_PMC_MCKR_PRES_1		0x00000000
 #define AT91_PMC_MCKR_PRES_2		0x00000004
 #define AT91_PMC_MCKR_PRES_4		0x00000008
@@ -90,6 +109,7 @@
 #define AT91_PMC_MCKR_PRES_32		0x00000014
 #define AT91_PMC_MCKR_PRES_64		0x00000018
 #define AT91_PMC_MCKR_PRES_MASK		0x0000001C
+#endif
 
 #ifdef CONFIG_AT91RM9200
 #define AT91_PMC_MCKR_MDIV_1		0x00000000
@@ -100,6 +120,9 @@
 #else
 #define AT91_PMC_MCKR_MDIV_1		0x00000000
 #define AT91_PMC_MCKR_MDIV_2		0x00000100
+#ifdef CONFIG_SAMA5D3
+#define AT91_PMC_MCKR_MDIV_3		0x00000300
+#endif
 #define AT91_PMC_MCKR_MDIV_4		0x00000200
 #define AT91_PMC_MCKR_MDIV_MASK		0x00000300
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
index b9a93b0..6e0bebd 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
@@ -23,7 +23,7 @@
 #include <asm/arch/at91cap9_matrix.h>
 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 #include <asm/arch/at91sam9g45_matrix.h>
-#elif defined(CONFIG_AT91SAM9X5)
+#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
 #include <asm/arch/at91sam9x5_matrix.h>
 #else
 #error "Unsupported AT91SAM9/CAP9 processor"
diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h
index b7d1932..85e42f5 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9x5.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h
@@ -1,10 +1,10 @@
 /*
  * Chip-specific header file for the AT91SAM9x5 family
  *
- *  Copyright (C) 2012 Atmel Corporation.
+ *  Copyright (C) 2012-2013 Atmel Corporation.
  *
  * Definitions for the SoC:
- * AT91SAM9x5
+ * AT91SAM9x5 & AT91SAM9N12
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,10 +22,12 @@
 #define ATMEL_ID_SYS	1	/* System Controller Interrupt */
 #define ATMEL_ID_PIOAB	2	/* Parallel I/O Controller A and B */
 #define ATMEL_ID_PIOCD	3	/* Parallel I/O Controller C and D */
-#define ATMEL_ID_SMD	4	/* SMD Soft Modem (SMD) */
+#define ATMEL_ID_SMD	4	/* SMD Soft Modem (SMD), only for AT91SAM9X5 */
+#define ATMEL_ID_FUSE	4	/* FUSE Controller, only for AT91SAM9N12 */
 #define ATMEL_ID_USART0	5	/* USART 0 */
 #define ATMEL_ID_USART1	6	/* USART 1 */
 #define ATMEL_ID_USART2	7	/* USART 2 */
+#define ATMEL_ID_USART3	8	/* USART 3 */
 #define ATMEL_ID_TWI0	9	/* Two-Wire Interface 0 */
 #define ATMEL_ID_TWI1	10	/* Two-Wire Interface 1 */
 #define ATMEL_ID_TWI2	11	/* Two-Wire Interface 2 */
@@ -46,6 +48,7 @@
 #define ATMEL_ID_HSMCI1	26	/* High Speed Multimedia Card Interface 1 */
 #define ATMEL_ID_EMAC1	27	/* Ethernet MAC1 */
 #define ATMEL_ID_SSC	28	/* Synchronous Serial Controller */
+#define ATMEL_ID_TRNG	30	/* True Random Number Generator */
 #define ATMEL_ID_IRQ	31	/* Advanced Interrupt Controller */
 
 /*
@@ -85,6 +88,7 @@
 /*
  * System Peripherals
  */
+#define ATMEL_BASE_FUSE		0xffffdc00
 #define ATMEL_BASE_MATRIX	0xffffde00
 #define ATMEL_BASE_PMECC	0xffffe000
 #define ATMEL_BASE_PMERRLOC	0xffffe600
@@ -111,10 +115,15 @@
  */
 #define ATMEL_BASE_ROM		0x00100000 /* Internal ROM base address */
 #define ATMEL_BASE_SRAM		0x00300000 /* Internal SRAM base address */
+
+#ifdef CONFIG_AT91SAM9N12
+#define ATMEL_BASE_OHCI		0x00500000 /* USB Host controller */
+#else	/* AT91SAM9X5 */
 #define ATMEL_BASE_SMD		0x00400000 /* SMD Controller */
 #define ATMEL_BASE_UDPHS_FIFO	0x00500000 /* USB Device HS controller */
 #define ATMEL_BASE_OHCI		0x00600000 /* USB Host controller (OHCI) */
 #define ATMEL_BASE_EHCI		0x00700000 /* USB Host controller (EHCI) */
+#endif
 
 /* 9x5 series chip id definitions */
 #define ARCH_ID_AT91SAM9X5	0x819a05a0
@@ -140,7 +149,11 @@
 /*
  * Cpu Name
  */
+#ifdef CONFIG_AT91SAM9N12
+#define ATMEL_CPU_NAME	"AT91SAM9N12"
+#else	/* AT91SAM9X5 */
 #define ATMEL_CPU_NAME	get_cpu_name()
+#endif
 
 /*
  * Other misc defines
diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
index d6ce6fa..0d33069 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
@@ -1,10 +1,10 @@
 /*
  * Matrix-centric header file for the AT91SAM9X5 family
  *
- *  Copyright (C) 2012 Atmel Corporation.
+ *  Copyright (C) 2012-2013 Atmel Corporation.
  *
  * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9X5 preliminary datasheet.
+ * Based on AT91SAM9X5 & AT91SAM9N12 preliminary datasheet.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,14 +17,25 @@
 
 #ifndef __ASSEMBLY__
 
+/* AT91SAM9N12 Matrix definition is a subset of AT91SAM9X5. */
 struct at91_matrix {
 	u32	mcfg[16];
 	u32	scfg[16];
 	u32	pras[16][2];
 	u32	mrcr;           /* 0x100 Master Remap Control */
-	u32	filler[7];
+	u32	filler[5];
+#ifdef CONFIG_AT91SAM9X5
+	u32	filler1[2];
+#endif
+	/* EBI Chip Select Assignment Register
+	 * 0x118: AT91SAM9N12
+	 * 0x120: AT91SAM9X5
+	 */
 	u32	ebicsa;
 	u32	filler4[47];
+#ifdef CONFIG_AT91SAM9N12
+	u32	filler5[2];
+#endif
 	u32	wpmr;
 	u32	wpsr;
 };
diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h
index d4852a3..04b0f83 100644
--- a/arch/arm/include/asm/arch-at91/clk.h
+++ b/arch/arm/include/asm/arch-at91/clk.h
@@ -95,4 +95,5 @@
 }
 
 int at91_clock_init(unsigned long main_clock);
+void at91_periph_clk_enable(int id);
 #endif /* __ASM_ARM_ARCH_CLK_H__ */
diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h
index 4c4ee70..b04641e 100644
--- a/arch/arm/include/asm/arch-at91/hardware.h
+++ b/arch/arm/include/asm/arch-at91/hardware.h
@@ -37,12 +37,14 @@
 # include <asm/arch/at91sam9rl.h>
 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 # include <asm/arch/at91sam9g45.h>
-#elif defined(CONFIG_AT91SAM9X5)
+#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
 # include <asm/arch/at91sam9x5.h>
 #elif defined(CONFIG_AT91CAP9)
 # include <asm/arch/at91cap9.h>
 #elif defined(CONFIG_AT91X40)
 # include <asm/arch/at91x40.h>
+#elif defined(CONFIG_SAMA5D3)
+# include <asm/arch/sama5d3.h>
 #else
 # error "Unsupported AT91 processor"
 #endif
diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/include/asm/arch-at91/sama5d3.h
new file mode 100644
index 0000000..883b932
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/sama5d3.h
@@ -0,0 +1,212 @@
+/*
+ * Chip-specific header file for the SAMA5D3 family
+ *
+ * (C) 2012 - 2013 Atmel Corporation.
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * Definitions for the SoC:
+ * SAMA5D3
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef SAMA5D3_H
+#define SAMA5D3_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_ARMV7		/* ARM A5 Core */
+#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS	1	/* System Controller Interrupt */
+#define ATMEL_ID_DBGU	2	/* Debug Unit Interrupt */
+#define ATMEL_ID_PIT	3	/* Periodic Interval Timer Interrupt */
+#define ATMEL_ID_WDT	4	/* Watchdog timer Interrupt */
+#define ATMEL_ID_SMC	5	/* Multi-bit ECC Interrupt */
+#define ATMEL_ID_PIOA	6	/* Parallel I/O Controller A */
+#define ATMEL_ID_PIOB	7	/* Parallel I/O Controller B */
+#define ATMEL_ID_PIOC	8	/* Parallel I/O Controller C */
+#define ATMEL_ID_PIOD	9	/* Parallel I/O Controller D */
+#define ATMEL_ID_PIOE	10	/* Parallel I/O Controller E */
+#define ATMEL_ID_SMD	11	/* SMD Soft Modem */
+#define ATMEL_ID_USART0	12	/* USART 0 */
+#define ATMEL_ID_USART1	13	/* USART 1 */
+#define ATMEL_ID_USART2	14	/* USART 2 */
+#define ATMEL_ID_USART3	15	/* USART 3 */
+#define ATMEL_ID_UART0	16
+#define ATMEL_ID_UART1	17
+#define ATMEL_ID_TWI0	18	/* Two-Wire Interface 0 */
+#define ATMEL_ID_TWI1	19	/* Two-Wire Interface 1 */
+#define ATMEL_ID_TWI2	20	/* Two-Wire Interface 2 */
+#define ATMEL_ID_MCI0	21	/* High Speed Multimedia Card Interface 0 */
+#define ATMEL_ID_MCI1	22	/*  */
+#define ATMEL_ID_MCI2	23	/*  */
+#define ATMEL_ID_SPI0	24	/* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1	25	/* Serial Peripheral Interface 1 */
+#define ATMEL_ID_TC0	26	/* */
+#define ATMEL_ID_TC1	27	/* */
+#define ATMEL_ID_PWMC	28	/* Pulse Width Modulation Controller */
+#define ATMEL_ID_TSC	29	/* Touch Screen ADC Controller */
+#define ATMEL_ID_DMA0	30	/* DMA Controller */
+#define ATMEL_ID_DMA1	31	/* DMA Controller */
+#define ATMEL_ID_UHPHS	32	/* USB Host High Speed */
+#define ATMEL_ID_UDPHS	33	/* USB Device High Speed */
+#define ATMEL_ID_GMAC	34
+#define ATMEL_ID_EMAC	35	/* Ethernet MAC */
+#define ATMEL_ID_LCDC	36	/* LCD Controller */
+#define ATMEL_ID_ISI	37	/* Image Sensor Interface */
+#define ATMEL_ID_SSC0	38	/* Synchronous Serial Controller 0 */
+#define ATMEL_ID_SSC1	39	/* Synchronous Serial Controller 1 */
+#define ATMEL_ID_CAN0	40
+#define ATMEL_ID_CAN1	41
+#define ATMEL_ID_SHA	42
+#define ATMEL_ID_AES	43
+#define ATMEL_ID_TDES	44
+#define ATMEL_ID_TRNG	45
+#define ATMEL_ID_ARM	46
+#define ATMEL_ID_IRQ0	47	/* Advanced Interrupt Controller */
+#define ATMEL_ID_FUSE	48
+#define ATMEL_ID_MPDDRC	49
+
+/* sama5d3 series chip id definitions */
+#define ARCH_ID_SAMA5D3		0x8a5c07c0
+#define ARCH_EXID_SAMA5D31	0x00444300
+#define ARCH_EXID_SAMA5D33	0x00414300
+#define ARCH_EXID_SAMA5D34	0x00414301
+#define ARCH_EXID_SAMA5D35	0x00584300
+
+#define cpu_is_sama5d3()	(get_chip_id() == ARCH_ID_SAMA5D3)
+#define cpu_is_sama5d31()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D31))
+#define cpu_is_sama5d33()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D33))
+#define cpu_is_sama5d34()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D34))
+#define cpu_is_sama5d35()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D35))
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_MCI0		0xf0000000
+#define ATMEL_BASE_SPI0		0xf0004000
+#define ATMEL_BASE_SSC0		0xf000C000
+#define ATMEL_BASE_TC2		0xf0010000
+#define ATMEL_BASE_TWI0		0xf0014000
+#define ATMEL_BASE_TWI1		0xf0018000
+#define ATMEL_BASE_USART0	0xf001c000
+#define ATMEL_BASE_USART1	0xf0020000
+#define ATMEL_BASE_UART0	0xf0024000
+#define ATMEL_BASE_GMAC		0xf0028000
+#define ATMEL_BASE_PWMC		0xf002c000
+#define ATMEL_BASE_LCDC		0xf0030000
+#define ATMEL_BASE_ISI		0xf0034000
+#define ATMEL_BASE_SFR		0xf0038000
+/* Reserved: 0xf003c000 - 0xf8000000 */
+#define ATMEL_BASE_MCI1		0xf8000000
+#define ATMEL_BASE_MCI2		0xf8004000
+#define ATMEL_BASE_SPI1		0xf8008000
+#define ATMEL_BASE_SSC1		0xf800c000
+#define ATMEL_BASE_CAN1		0xf8010000
+#define ATMEL_BASE_TC3		0xf8014000
+#define ATMEL_BASE_TSADC	0xf8018000
+#define ATMEL_BASE_TWI2		0xf801c000
+#define ATMEL_BASE_USART2	0xf8020000
+#define ATMEL_BASE_USART3	0xf8024000
+#define ATMEL_BASE_UART1	0xf8028000
+#define ATMEL_BASE_EMAC		0xf802c000
+#define ATMEL_BASE_UDHPS	0xf8030000
+#define ATMEL_BASE_SHA		0xf8034000
+#define ATMEL_BASE_AES		0xf8038000
+#define ATMEL_BASE_TDES		0xf803c000
+#define ATMEL_BASE_TRNG		0xf8040000
+/* Reserved:	0xf804400 - 0xffffc00 */
+
+/*
+ * System Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_SYS		0xffffc000
+#define ATMEL_BASE_SMC		0xffffc000
+#define ATMEL_BASE_PMECC	(ATMEL_BASE_SMC + 0x070)
+#define ATMEL_BASE_PMERRLOC	(ATMEL_BASE_SMC + 0x500)
+#define ATMEL_BASE_FUSE		0xffffe400
+#define ATMEL_BASE_DMAC0	0xffffe600
+#define ATMEL_BASE_DMAC1	0xffffe800
+#define ATMEL_BASE_MPDDRC	0xffffea00
+#define ATMEL_BASE_MATRIX	0xffffec00
+#define ATMEL_BASE_DBGU		0xffffee00
+#define ATMEL_BASE_AIC		0xfffff000
+#define ATMEL_BASE_PIOA		0xfffff200
+#define ATMEL_BASE_PIOB		0xfffff400
+#define ATMEL_BASE_PIOC		0xfffff600
+#define ATMEL_BASE_PIOD		0xfffff800
+#define ATMEL_BASE_PIOE		0xfffffa00
+#define ATMEL_BASE_PMC		0xfffffc00
+#define ATMEL_BASE_RSTC		0xfffffe00
+#define ATMEL_BASE_SHDWN	0xfffffe10
+#define ATMEL_BASE_PIT		0xfffffe30
+#define ATMEL_BASE_WDT		0xfffffe40
+#define ATMEL_BASE_SCKCR	0xfffffe50
+#define ATMEL_BASE_GPBR		0xfffffe60
+#define ATMEL_BASE_RTC		0xfffffeb0
+/* Reserved:	0xfffffee0 - 0xffffffff */
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_ROM		0x00100000	/* Internal ROM base address */
+#define ATMEL_BASE_SRAM		0x00200000	/* Internal ROM base address */
+#define ATMEL_BASE_SRAM0	0x00300000	/* Internal SRAM base address */
+#define ATMEL_BASE_SRAM1	0x00310000	/* Internal SRAM base address */
+#define ATMEL_BASE_SMD		0x00400000	/* Internal ROM base address */
+#define ATMEL_BASE_UDPHS_FIFO	0x00500000	/* USB Device HS controller */
+#define ATMEL_BASE_OHCI		0x00600000	/* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI		0x00700000	/* USB Host controller (EHCI) */
+#define ATMEL_BASE_AXI		0x00800000	/* Video Decoder Controller */
+#define ATMEL_BASE_DAP		0x00900000	/* Video Decoder Controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0		0x10000000
+#define ATMEL_BASE_DDRCS	0x20000000
+#define ATMEL_BASE_CS1		0x40000000
+#define ATMEL_BASE_CS2		0x50000000
+#define ATMEL_BASE_CS3		0x60000000
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS		5
+#define CPU_HAS_PIO3
+#define PIO_SCDR_DIV		0x3fff
+
+/*
+ * PMECC table in ROM
+ */
+#define ATMEL_PMECC_INDEX_OFFSET_512	0x10000
+#define ATMEL_PMECC_INDEX_OFFSET_1024	0x18000
+#define ATMEL_PMECC_ALPHA_OFFSET_512	0x10000
+#define ATMEL_PMECC_ALPHA_OFFSET_1024	0x18000
+
+/*
+ * SAMA5D3 specific prototypes
+ */
+#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
+unsigned int has_emac(void);
+unsigned int has_gmac(void);
+unsigned int has_lcdc(void);
+char *get_cpu_name(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/sama5d3_smc.h b/arch/arm/include/asm/arch-at91/sama5d3_smc.h
new file mode 100644
index 0000000..eb53eba
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/sama5d3_smc.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2012 Atmel Corporation.
+ *
+ * Static Memory Controllers (SMC) - System peripherals registers.
+ * Based on SAMA5D3 datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef SAMA5D3_SMC_H
+#define SAMA5D3_SMC_H
+
+#ifdef __ASSEMBLY__
+#define AT91_ASM_SMC_SETUP0	(ATMEL_BASE_SMC + 0x600)
+#define AT91_ASM_SMC_PULSE0	(ATMEL_BASE_SMC + 0x604)
+#define AT91_ASM_SMC_CYCLE0	(ATMEL_BASE_SMC + 0x608)
+#define AT91_ASM_SMC_MODE0	(ATMEL_BASE_SMC + 0x60C)
+#else
+struct at91_cs {
+	u32	reserved[96];
+	u32	setup;		/* 0x600 SMC Setup Register */
+	u32	pulse;		/* 0x604 SMC Pulse Register */
+	u32	cycle;		/* 0x608 SMC Cycle Register */
+	u32	timings;	/* 0x60C SMC Cycle Register */
+	u32	mode;		/* 0x610 SMC Mode Register */
+};
+
+struct at91_smc {
+	struct at91_cs cs[4];
+};
+#endif /*  __ASSEMBLY__ */
+
+#define AT91_SMC_SETUP_NWE(x)		(x & 0x3f)
+#define AT91_SMC_SETUP_NCS_WR(x)	((x & 0x3f) << 8)
+#define AT91_SMC_SETUP_NRD(x)		((x & 0x3f) << 16)
+#define AT91_SMC_SETUP_NCS_RD(x)	((x & 0x3f) << 24)
+
+#define AT91_SMC_PULSE_NWE(x)		(x & 0x3f)
+#define AT91_SMC_PULSE_NCS_WR(x)	((x & 0x3f) << 8)
+#define AT91_SMC_PULSE_NRD(x)		((x & 0x3f) << 16)
+#define AT91_SMC_PULSE_NCS_RD(x)	((x & 0x3f) << 24)
+
+#define AT91_SMC_CYCLE_NWE(x)		(x & 0x1ff)
+#define AT91_SMC_CYCLE_NRD(x)		((x & 0x1ff) << 16)
+
+#define AT91_SMC_TIMINGS_TCLR(x)	(x & 0xf)
+#define AT91_SMC_TIMINGS_TADL(x)	((x & 0xf) << 4)
+#define AT91_SMC_TIMINGS_TAR(x)		((x & 0xf) << 8)
+#define AT91_SMC_TIMINGS_OCMS(x)	((x & 0x1) << 12)
+#define AT91_SMC_TIMINGS_TRR(x)		((x & 0xf) << 16)
+#define AT91_SMC_TIMINGS_TWB(x)		((x & 0xf) << 24)
+#define AT91_SMC_TIMINGS_RBNSEL(x)	((x & 0xf) << 28)
+#define AT91_SMC_TIMINGS_NFSEL(x)	((x & 0x1) << 31)
+
+#define AT91_SMC_MODE_RM_NCS		0x00000000
+#define AT91_SMC_MODE_RM_NRD		0x00000001
+#define AT91_SMC_MODE_WM_NCS		0x00000000
+#define AT91_SMC_MODE_WM_NWE		0x00000002
+
+#define AT91_SMC_MODE_EXNW_DISABLE	0x00000000
+#define AT91_SMC_MODE_EXNW_FROZEN	0x00000020
+#define AT91_SMC_MODE_EXNW_READY	0x00000030
+
+#define AT91_SMC_MODE_BAT		0x00000100
+#define AT91_SMC_MODE_DBW_8		0x00000000
+#define AT91_SMC_MODE_DBW_16		0x00001000
+#define AT91_SMC_MODE_DBW_32		0x00002000
+#define AT91_SMC_MODE_TDF_CYCLE(x)	((x & 0xf) << 16)
+#define AT91_SMC_MODE_TDF		0x00100000
+#define AT91_SMC_MODE_PMEN		0x01000000
+#define AT91_SMC_MODE_PS_4		0x00000000
+#define AT91_SMC_MODE_PS_8		0x10000000
+#define AT91_SMC_MODE_PS_16		0x20000000
+#define AT91_SMC_MODE_PS_32		0x30000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 6eed6c9..a9017e4 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -346,6 +346,8 @@
 #define PSC_PSC0_MODULE_ID_CNT		16
 #define PSC_PSC1_MODULE_ID_CNT		32
 
+#define UART0_PWREMU_MGMT		(0x01c42030)
+
 struct davinci_psc_regs {
 	dv_reg	revid;
 	dv_reg	rsvd0[71];
diff --git a/arch/arm/include/asm/arch-davinci/nand_defs.h b/arch/arm/include/asm/arch-davinci/nand_defs.h
index 10f3a39..4a30813 100644
--- a/arch/arm/include/asm/arch-davinci/nand_defs.h
+++ b/arch/arm/include/asm/arch-davinci/nand_defs.h
@@ -36,6 +36,15 @@
 #define	MASK_ALE	0x08
 #endif
 
+#ifdef CONFIG_SYS_NAND_MASK_CLE
+#undef MASK_CLE
+#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
+#endif
+#ifdef CONFIG_SYS_NAND_MASK_ALE
+#undef MASK_ALE
+#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
+#endif
+
 #define NAND_READ_START		0x00
 #define NAND_READ_END		0x30
 #define NAND_STATUS		0x70
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 5f4b543..46f59d7 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -113,8 +113,12 @@
 	u32 iim_sdat;
 	u32 iim_prev;
 	u32 iim_srev;
-	u32 iim_prog_p;
-	u32 res1[0x1f5];
+	u32 iim_prg_p;
+	u32 iim_scs0;
+	u32 iim_scs1;
+	u32 iim_scs2;
+	u32 iim_scs3;
+	u32 res1[0x1f1];
 	struct fuse_bank {
 		u32 fuse_regs[0x20];
 		u32 fuse_rsvd[0xe0];
@@ -122,10 +126,19 @@
 };
 
 struct fuse_bank0_regs {
-	u32 fuse0_25[0x1a];
+	u32 fuse0_7[8];
+	u32 uid[8];
+	u32 fuse16_25[0xa];
 	u32 mac_addr[6];
 };
 
+struct fuse_bank1_regs {
+	u32 fuse0_21[0x16];
+	u32 usr5;
+	u32 fuse23_29[7];
+	u32 usr6[2];
+};
+
 /* Multi-Layer AHB Crossbar Switch (MAX) registers */
 struct max_regs {
 	u32 mpr0;
@@ -187,6 +200,7 @@
 #define IMX_CSPI1_BASE		(0x43FA4000)
 #define IMX_KPP_BASE		(0x43FA8000)
 #define IMX_IOPADMUX_BASE	(0x43FAC000)
+#define IOMUXC_BASE_ADDR	IMX_IOPADMUX_BASE
 #define IMX_IOPADCTL_BASE	(0x43FAC22C)
 #define IMX_IOPADGRPCTL_BASE	(0x43FAC418)
 #define IMX_IOPADINPUTSEL_BASE	(0x43FAC460)
@@ -240,6 +254,7 @@
 #define IMX_PWM1_BASE		(0x53FE0000)
 #define IMX_RTIC_BASE		(0x53FEC000)
 #define IMX_IIM_BASE		(0x53FF0000)
+#define IIM_BASE_ADDR		IMX_IIM_BASE
 #define IMX_USB_BASE		(0x53FF4000)
 #define IMX_USB_PORT_OFFSET	0x200
 #define IMX_CSI_BASE		(0x53FF8000)
diff --git a/arch/arm/include/asm/arch-mx25/imx25-pinmux.h b/arch/arm/include/asm/arch-mx25/imx25-pinmux.h
deleted file mode 100644
index a4c658b..0000000
--- a/arch/arm/include/asm/arch-mx25/imx25-pinmux.h
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * iopin settings are controlled by four different sets of registers
- *	iopad mux control
- *	individual iopad setup (voltage select, pull/keep, drive strength ...)
- *	group iopad setup (same as above but for groups of signals)
- *	input select when multiple inputs are possible
- */
-
-/*
- * software pad mux control
- */
-/* SW Input On (Loopback) */
-#define MX25_PIN_MUX_SION		(1 << 4)
-/* MUX Mode (0-7) */
-#define MX25_PIN_MUX_MODE(mode)		((mode & 0x7) << 0)
-struct iomuxc_mux_ctl {
-	u32 gpr1;
-	u32 observe_int_mux;
-	u32 pad_a10;
-	u32 pad_a13;
-	u32 pad_a14;
-	u32 pad_a15;
-	u32 pad_a16;
-	u32 pad_a17;
-	u32 pad_a18;
-	u32 pad_a19;
-	u32 pad_a20;
-	u32 pad_a21;
-	u32 pad_a22;
-	u32 pad_a23;
-	u32 pad_a24;
-	u32 pad_a25;
-	u32 pad_eb0;
-	u32 pad_eb1;
-	u32 pad_oe;
-	u32 pad_cs0;
-	u32 pad_cs1;
-	u32 pad_cs4;
-	u32 pad_cs5;
-	u32 pad_nf_ce0;
-	u32 pad_ecb;
-	u32 pad_lba;
-	u32 pad_bclk;
-	u32 pad_rw;
-	u32 pad_nfwe_b;
-	u32 pad_nfre_b;
-	u32 pad_nfale;
-	u32 pad_nfcle;
-	u32 pad_nfwp_b;
-	u32 pad_nfrb;
-	u32 pad_d15;
-	u32 pad_d14;
-	u32 pad_d13;
-	u32 pad_d12;
-	u32 pad_d11;
-	u32 pad_d10;
-	u32 pad_d9;
-	u32 pad_d8;
-	u32 pad_d7;
-	u32 pad_d6;
-	u32 pad_d5;
-	u32 pad_d4;
-	u32 pad_d3;
-	u32 pad_d2;
-	u32 pad_d1;
-	u32 pad_d0;
-	u32 pad_ld0;
-	u32 pad_ld1;
-	u32 pad_ld2;
-	u32 pad_ld3;
-	u32 pad_ld4;
-	u32 pad_ld5;
-	u32 pad_ld6;
-	u32 pad_ld7;
-	u32 pad_ld8;
-	u32 pad_ld9;
-	u32 pad_ld10;
-	u32 pad_ld11;
-	u32 pad_ld12;
-	u32 pad_ld13;
-	u32 pad_ld14;
-	u32 pad_ld15;
-	u32 pad_hsync;
-	u32 pad_vsync;
-	u32 pad_lsclk;
-	u32 pad_oe_acd;
-	u32 pad_contrast;
-	u32 pad_pwm;
-	u32 pad_csi_d2;
-	u32 pad_csi_d3;
-	u32 pad_csi_d4;
-	u32 pad_csi_d5;
-	u32 pad_csi_d6;
-	u32 pad_csi_d7;
-	u32 pad_csi_d8;
-	u32 pad_csi_d9;
-	u32 pad_csi_mclk;
-	u32 pad_csi_vsync;
-	u32 pad_csi_hsync;
-	u32 pad_csi_pixclk;
-	u32 pad_i2c1_clk;
-	u32 pad_i2c1_dat;
-	u32 pad_cspi1_mosi;
-	u32 pad_cspi1_miso;
-	u32 pad_cspi1_ss0;
-	u32 pad_cspi1_ss1;
-	u32 pad_cspi1_sclk;
-	u32 pad_cspi1_rdy;
-	u32 pad_uart1_rxd;
-	u32 pad_uart1_txd;
-	u32 pad_uart1_rts;
-	u32 pad_uart1_cts;
-	u32 pad_uart2_rxd;
-	u32 pad_uart2_txd;
-	u32 pad_uart2_rts;
-	u32 pad_uart2_cts;
-	u32 pad_sd1_cmd;
-	u32 pad_sd1_clk;
-	u32 pad_sd1_data0;
-	u32 pad_sd1_data1;
-	u32 pad_sd1_data2;
-	u32 pad_sd1_data3;
-	u32 pad_kpp_row0;
-	u32 pad_kpp_row1;
-	u32 pad_kpp_row2;
-	u32 pad_kpp_row3;
-	u32 pad_kpp_col0;
-	u32 pad_kpp_col1;
-	u32 pad_kpp_col2;
-	u32 pad_kpp_col3;
-	u32 pad_fec_mdc;
-	u32 pad_fec_mdio;
-	u32 pad_fec_tdata0;
-	u32 pad_fec_tdata1;
-	u32 pad_fec_tx_en;
-	u32 pad_fec_rdata0;
-	u32 pad_fec_rdata1;
-	u32 pad_fec_rx_dv;
-	u32 pad_fec_tx_clk;
-	u32 pad_rtck;
-	u32 pad_de_b;
-	u32 pad_gpio_a;
-	u32 pad_gpio_b;
-	u32 pad_gpio_c;
-	u32 pad_gpio_d;
-	u32 pad_gpio_e;
-	u32 pad_gpio_f;
-	u32 pad_ext_armclk;
-	u32 pad_upll_bypclk;
-	u32 pad_vstby_req;
-	u32 pad_vstby_ack;
-	u32 pad_power_fail;
-	u32 pad_clko;
-	u32 pad_boot_mode0;
-	u32 pad_boot_mode1;
-};
-
-/*
- * software pad control
- */
-/* Select 3.3 or 1.8 volts */
-#define MX25_PIN_PAD_CTL_DVS_33			(0 << 13)
-#define MX25_PIN_PAD_CTL_DVS_18			(1 << 13)
-/* Enable hysteresis */
-#define MX25_PIN_PAD_CTL_HYS			(1 << 8)
-/* Enable pull/keeper */
-#define MX25_PIN_PAD_CTL_PKE			(1 << 7)
-/* 0 - keeper / 1 - pull */
-#define MX25_PIN_PAD_CTL_PUE			(1 << 6)
-/* pull up/down strength */
-#define MX25_PIN_PAD_CTL_100K_PD		(0 << 4)
-#define MX25_PIN_PAD_CTL_47K_PU			(1 << 4)
-#define MX25_PIN_PAD_CTL_100K_PU		(2 << 4)
-#define MX25_PIN_PAD_CTL_22K_PU			(3 << 4)
-/* open drain control */
-#define MX25_PIN_PAD_CTL_OD			(1 << 3)
-/* drive strength */
-#define MX25_PIN_PAD_CTL_DS_NOM			(0 << 1)
-#define MX25_PIN_PAD_CTL_DS_HIGH		(1 << 1)
-#define MX25_PIN_PAD_CTL_DS_MAX			(2 << 1)
-#define MX25_PIN_PAD_CTL_DS_MAX11		(3 << 1)
-/* slew rate */
-#define MX25_PIN_PAD_CTL_SRE_SLOW		(0 << 0)
-#define MX25_PIN_PAD_CTL_SRE_FAST		(1 << 0)
-struct  iomuxc_pad_ctl {
-	u32 pad_a13;
-	u32 pad_a14;
-	u32 pad_a15;
-	u32 pad_a17;
-	u32 pad_a18;
-	u32 pad_a19;
-	u32 pad_a20;
-	u32 pad_a21;
-	u32 pad_a23;
-	u32 pad_a24;
-	u32 pad_a25;
-	u32 pad_eb0;
-	u32 pad_eb1;
-	u32 pad_oe;
-	u32 pad_cs4;
-	u32 pad_cs5;
-	u32 pad_nf_ce0;
-	u32 pad_ecb;
-	u32 pad_lba;
-	u32 pad_rw;
-	u32 pad_nfrb;
-	u32 pad_d15;
-	u32 pad_d14;
-	u32 pad_d13;
-	u32 pad_d12;
-	u32 pad_d11;
-	u32 pad_d10;
-	u32 pad_d9;
-	u32 pad_d8;
-	u32 pad_d7;
-	u32 pad_d6;
-	u32 pad_d5;
-	u32 pad_d4;
-	u32 pad_d3;
-	u32 pad_d2;
-	u32 pad_d1;
-	u32 pad_d0;
-	u32 pad_ld0;
-	u32 pad_ld1;
-	u32 pad_ld2;
-	u32 pad_ld3;
-	u32 pad_ld4;
-	u32 pad_ld5;
-	u32 pad_ld6;
-	u32 pad_ld7;
-	u32 pad_ld8;
-	u32 pad_ld9;
-	u32 pad_ld10;
-	u32 pad_ld11;
-	u32 pad_ld12;
-	u32 pad_ld13;
-	u32 pad_ld14;
-	u32 pad_ld15;
-	u32 pad_hsync;
-	u32 pad_vsync;
-	u32 pad_lsclk;
-	u32 pad_oe_acd;
-	u32 pad_contrast;
-	u32 pad_pwm;
-	u32 pad_csi_d2;
-	u32 pad_csi_d3;
-	u32 pad_csi_d4;
-	u32 pad_csi_d5;
-	u32 pad_csi_d6;
-	u32 pad_csi_d7;
-	u32 pad_csi_d8;
-	u32 pad_csi_d9;
-	u32 pad_csi_mclk;
-	u32 pad_csi_vsync;
-	u32 pad_csi_hsync;
-	u32 pad_csi_pixclk;
-	u32 pad_i2c1_clk;
-	u32 pad_i2c1_dat;
-	u32 pad_cspi1_mosi;
-	u32 pad_cspi1_miso;
-	u32 pad_cspi1_ss0;
-	u32 pad_cspi1_ss1;
-	u32 pad_cspi1_sclk;
-	u32 pad_cspi1_rdy;
-	u32 pad_uart1_rxd;
-	u32 pad_uart1_txd;
-	u32 pad_uart1_rts;
-	u32 pad_uart1_cts;
-	u32 pad_uart2_rxd;
-	u32 pad_uart2_txd;
-	u32 pad_uart2_rts;
-	u32 pad_uart2_cts;
-	u32 pad_sd1_cmd;
-	u32 pad_sd1_clk;
-	u32 pad_sd1_data0;
-	u32 pad_sd1_data1;
-	u32 pad_sd1_data2;
-	u32 pad_sd1_data3;
-	u32 pad_kpp_row0;
-	u32 pad_kpp_row1;
-	u32 pad_kpp_row2;
-	u32 pad_kpp_row3;
-	u32 pad_kpp_col0;
-	u32 pad_kpp_col1;
-	u32 pad_kpp_col2;
-	u32 pad_kpp_col3;
-	u32 pad_fec_mdc;
-	u32 pad_fec_mdio;
-	u32 pad_fec_tdata0;
-	u32 pad_fec_tdata1;
-	u32 pad_fec_tx_en;
-	u32 pad_fec_rdata0;
-	u32 pad_fec_rdata1;
-	u32 pad_fec_rx_dv;
-	u32 pad_fec_tx_clk;
-	u32 pad_rtck;
-	u32 pad_tdo;
-	u32 pad_de_b;
-	u32 pad_gpio_a;
-	u32 pad_gpio_b;
-	u32 pad_gpio_c;
-	u32 pad_gpio_d;
-	u32 pad_gpio_e;
-	u32 pad_gpio_f;
-	u32 pad_vstby_req;
-	u32 pad_vstby_ack;
-	u32 pad_power_fail;
-	u32 pad_clko;
-};
-
-
-/*
- * Pad group drive strength and voltage select
- * Same fields as iomuxc_pad_ctl plus ddr type
- */
-/* Select DDR type */
-#define MX25_PIN_PAD_CTL_DDR_18			(0 << 11)
-#define MX25_PIN_PAD_CTL_DDR_33			(1 << 11)
-#define MX25_PIN_PAD_CTL_DDR_MAX		(2 << 11)
-struct iomuxc_pad_grp_ctl {
-	u32 grp_dvs_misc;
-	u32 grp_dse_fec;
-	u32 grp_dvs_jtag;
-	u32 grp_dse_nfc;
-	u32 grp_dse_csi;
-	u32 grp_dse_weim;
-	u32 grp_dse_ddr;
-	u32 grp_dvs_crm;
-	u32 grp_dse_kpp;
-	u32 grp_dse_sdhc1;
-	u32 grp_dse_lcd;
-	u32 grp_dse_uart;
-	u32 grp_dvs_nfc;
-	u32 grp_dvs_csi;
-	u32 grp_dse_cspi1;
-	u32 grp_ddrtype;
-	u32 grp_dvs_sdhc1;
-	u32 grp_dvs_lcd;
-};
-
-/*
- * Pad input select control
- * Select which pad to connect to an input port
- * where multiple pads can function as given input
- */
-#define MX25_PAD_INPUT_SELECT_DAISY(in)		((in & 0x7) << 0)
-struct iomuxc_pad_input_select {
-	u32 audmux_p4_input_da_amx;
-	u32 audmux_p4_input_db_amx;
-	u32 audmux_p4_input_rxclk_amx;
-	u32 audmux_p4_input_rxfs_amx;
-	u32 audmux_p4_input_txclk_amx;
-	u32 audmux_p4_input_txfs_amx;
-	u32 audmux_p7_input_da_amx;
-	u32 audmux_p7_input_txfs_amx;
-	u32 can1_ipp_ind_canrx;
-	u32 can2_ipp_ind_canrx;
-	u32 csi_ipp_csi_d_0;
-	u32 csi_ipp_csi_d_1;
-	u32 cspi1_ipp_ind_ss3_b;
-	u32 cspi2_ipp_cspi_clk_in;
-	u32 cspi2_ipp_ind_dataready_b;
-	u32 cspi2_ipp_ind_miso;
-	u32 cspi2_ipp_ind_mosi;
-	u32 cspi2_ipp_ind_ss0_b;
-	u32 cspi2_ipp_ind_ss1_b;
-	u32 cspi3_ipp_cspi_clk_in;
-	u32 cspi3_ipp_ind_dataready_b;
-	u32 cspi3_ipp_ind_miso;
-	u32 cspi3_ipp_ind_mosi;
-	u32 cspi3_ipp_ind_ss0_b;
-	u32 cspi3_ipp_ind_ss1_b;
-	u32 cspi3_ipp_ind_ss2_b;
-	u32 cspi3_ipp_ind_ss3_b;
-	u32 esdhc1_ipp_dat4_in;
-	u32 esdhc1_ipp_dat5_in;
-	u32 esdhc1_ipp_dat6_in;
-	u32 esdhc1_ipp_dat7_in;
-	u32 esdhc2_ipp_card_clk_in;
-	u32 esdhc2_ipp_cmd_in;
-	u32 esdhc2_ipp_dat0_in;
-	u32 esdhc2_ipp_dat1_in;
-	u32 esdhc2_ipp_dat2_in;
-	u32 esdhc2_ipp_dat3_in;
-	u32 esdhc2_ipp_dat4_in;
-	u32 esdhc2_ipp_dat5_in;
-	u32 esdhc2_ipp_dat6_in;
-	u32 esdhc2_ipp_dat7_in;
-	u32 fec_fec_col;
-	u32 fec_fec_crs;
-	u32 fec_fec_rdata_2;
-	u32 fec_fec_rdata_3;
-	u32 fec_fec_rx_clk;
-	u32 fec_fec_rx_er;
-	u32 i2c2_ipp_scl_in;
-	u32 i2c2_ipp_sda_in;
-	u32 i2c3_ipp_scl_in;
-	u32 i2c3_ipp_sda_in;
-	u32 kpp_ipp_ind_col_4;
-	u32 kpp_ipp_ind_col_5;
-	u32 kpp_ipp_ind_col_6;
-	u32 kpp_ipp_ind_col_7;
-	u32 kpp_ipp_ind_row_4;
-	u32 kpp_ipp_ind_row_5;
-	u32 kpp_ipp_ind_row_6;
-	u32 kpp_ipp_ind_row_7;
-	u32 sim1_pin_sim_rcvd1_in;
-	u32 sim1_pin_sim_simpd1;
-	u32 sim1_sim_rcvd1_io;
-	u32 sim2_pin_sim_rcvd1_in;
-	u32 sim2_pin_sim_simpd1;
-	u32 sim2_sim_rcvd1_io;
-	u32 uart3_ipp_uart_rts_b;
-	u32 uart3_ipp_uart_rxd_mux;
-	u32 uart4_ipp_uart_rts_b;
-	u32 uart4_ipp_uart_rxd_mux;
-	u32 uart5_ipp_uart_rts_b;
-	u32 uart5_ipp_uart_rxd_mux;
-	u32 usb_top_ipp_ind_otg_usb_oc;
-	u32 usb_top_ipp_ind_uh2_usb_oc;
-};
diff --git a/arch/arm/include/asm/arch-mx25/iomux-mx25.h b/arch/arm/include/asm/arch-mx25/iomux-mx25.h
new file mode 100644
index 0000000..c0f5c61
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx25/iomux-mx25.h
@@ -0,0 +1,545 @@
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on mainline Linux i.MX iomux-mx25.h file:
+ * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
+ *
+ * Based on Linux arch/arm/mach-mx25/mx25_pins.h:
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IOMUX_MX25_H__
+#define __IOMUX_MX25_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Pad control groupings */
+#define MX25_KPP_ROW_PAD_CTRL	PAD_CTL_PUS_100K_UP
+#define MX25_KPP_COL_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+/*
+ * The naming convention for the pad modes is MX25_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/*							    PAD    MUX    ALT INPSE PATH PADCTRL */
+enum {
+	MX25_PAD_A10__A10			= IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A10__GPIO_4_0			= IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A13__A13			= IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A13__GPIO_4_1			= IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A14__A14			= IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A14__GPIO_2_0			= IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A15__A15			= IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A15__GPIO_2_1			= IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A16__A16			= IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A16__GPIO_2_2			= IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A17__A17			= IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A17__GPIO_2_3			= IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A18__A18			= IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A18__GPIO_2_4			= IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A18__FEC_COL			= IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A19__A19			= IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A19__FEC_RX_ER			= IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL),
+	MX25_PAD_A19__GPIO_2_5			= IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A20__A20			= IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A20__GPIO_2_6			= IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A20__FEC_RDATA2		= IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A21__A21			= IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A21__GPIO_2_7			= IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A21__FEC_RDATA3		= IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A22__A22			= IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A22__GPIO_2_8			= IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A23__A23			= IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A23__GPIO_2_9			= IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A24__A24			= IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A24__GPIO_2_10			= IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A24__FEC_RX_CLK		= IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A25__A25			= IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A25__GPIO_2_11			= IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A25__FEC_CRS			= IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL),
+
+	MX25_PAD_EB0__EB0			= IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EB0__AUD4_TXD			= IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL),
+	MX25_PAD_EB0__GPIO_2_12			= IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_EB1__EB1			= IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EB1__AUD4_RXD			= IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL),
+	MX25_PAD_EB1__GPIO_2_13			= IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_OE__OE				= IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_OE__AUD4_TXC			= IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_OE__GPIO_2_14			= IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CS0__CS0			= IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS0__GPIO_4_2			= IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CS1__CS1			= IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS1__NF_CE3			= IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS1__GPIO_4_3			= IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CS4__CS4			= IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS4__NF_CE1			= IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS4__UART5_CTS			= IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS4__GPIO_3_20			= IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CS5__CS5			= IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS5__NF_CE2			= IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS5__UART5_RTS			= IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL),
+	MX25_PAD_CS5__GPIO_3_21			= IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NF_CE0__NF_CE0			= IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NF_CE0__GPIO_3_22		= IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_ECB__ECB			= IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_ECB__UART5_TXD_MUX		= IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_ECB__GPIO_3_23			= IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LBA__LBA			= IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LBA__UART5_RXD_MUX		= IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL),
+	MX25_PAD_LBA__GPIO_3_24			= IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_BCLK__BCLK			= IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_BCLK__GPIO_4_4			= IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_RW__RW				= IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_RW__AUD4_TXFS			= IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL),
+	MX25_PAD_RW__GPIO_3_25			= IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFWE_B__NFWE_B			= IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFWE_B__GPIO_3_26		= IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFRE_B__NFRE_B			= IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFRE_B__GPIO_3_27		= IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFALE__NFALE			= IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFALE__GPIO_3_28		= IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFCLE__NFCLE			= IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFCLE__GPIO_3_29		= IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFWP_B__NFWP_B			= IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFWP_B__GPIO_3_30		= IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFRB__NFRB			= IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE),
+	MX25_PAD_NFRB__GPIO_3_31		= IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D15__D15			= IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D15__LD16			= IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_D15__GPIO_4_5			= IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D14__D14			= IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D14__LD17			= IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_D14__GPIO_4_6			= IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D13__D13			= IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D13__LD18			= IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_D13__GPIO_4_7			= IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D12__D12			= IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D12__GPIO_4_8			= IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D11__D11			= IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D11__GPIO_4_9			= IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D10__D10			= IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D10__GPIO_4_10			= IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D10__USBOTG_OC			= IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP),
+
+	MX25_PAD_D9__D9				= IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D9__GPIO_4_11			= IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D9__USBH2_PWR			= IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE),
+
+	MX25_PAD_D8__D8				= IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D8__GPIO_4_12			= IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D8__USBH2_OC			= IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP),
+
+	MX25_PAD_D7__D7				= IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D7__GPIO_4_13			= IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D6__D6				= IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D6__GPIO_4_14			= IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D5__D5				= IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D5__GPIO_4_15			= IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D4__D4				= IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D4__GPIO_4_16			= IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D3__D3				= IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D3__GPIO_4_17			= IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D2__D2				= IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D2__GPIO_4_18			= IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D1__D1				= IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D1__GPIO_4_19			= IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D0__D0				= IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D0__GPIO_4_20			= IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD0__LD0			= IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD0__CSI_D0			= IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL),
+	MX25_PAD_LD0__GPIO_2_15			= IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD1__LD1			= IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD1__CSI_D1			= IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL),
+	MX25_PAD_LD1__GPIO_2_16			= IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD2__LD2			= IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD2__GPIO_2_17			= IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD3__LD3			= IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD3__GPIO_2_18			= IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD4__LD4			= IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD4__GPIO_2_19			= IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD5__LD5			= IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD5__GPIO_1_19			= IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD6__LD6			= IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD6__GPIO_1_20			= IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD7__LD7			= IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD7__GPIO_1_21			= IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD8__LD8			= IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD8__FEC_TX_ERR		= IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD9__LD9			= IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD9__FEC_COL			= IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL),
+
+	MX25_PAD_LD10__LD10			= IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD10__FEC_RX_ER		= IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL),
+
+	MX25_PAD_LD11__LD11			= IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD11__FEC_RDATA2		= IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL),
+
+	MX25_PAD_LD12__LD12			= IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD12__FEC_RDATA3		= IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL),
+
+	MX25_PAD_LD13__LD13			= IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD13__FEC_TDATA2		= IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD14__LD14			= IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD14__FEC_TDATA3		= IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD15__LD15			= IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD15__FEC_RX_CLK		= IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL),
+
+	MX25_PAD_HSYNC__HSYNC			= IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_HSYNC__GPIO_1_22		= IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_VSYNC__VSYNC			= IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSYNC__GPIO_1_23		= IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LSCLK__LSCLK			= IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LSCLK__GPIO_1_24		= IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_OE_ACD__OE_ACD			= IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_OE_ACD__GPIO_1_25		= IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CONTRAST__CONTRAST		= IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CONTRAST__PWM4_PWMO		= IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CONTRAST__FEC_CRS		= IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL),
+
+	MX25_PAD_PWM__PWM			= IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_PWM__GPIO_1_26			= IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_PWM__USBH2_OC			= IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP),
+
+	MX25_PAD_CSI_D2__CSI_D2			= IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D2__UART5_RXD_MUX		= IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL),
+	MX25_PAD_CSI_D2__GPIO_1_27		= IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D2__CSPI3_MOSI		= IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D3__CSI_D3			= IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D3__GPIO_1_28		= IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D3__CSPI3_MISO		= IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D4__CSI_D4			= IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D4__UART5_RTS		= IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL),
+	MX25_PAD_CSI_D4__GPIO_1_29		= IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D4__CSPI3_SCLK		= IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D5__CSI_D5			= IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D5__GPIO_1_30		= IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D5__CSPI3_RDY		= IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D6__CSI_D6			= IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D6__GPIO_1_31		= IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D7__CSI_D7			= IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D7__GPIO_1_6		= IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D8__CSI_D8			= IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D8__GPIO_1_7		= IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D9__CSI_D9			= IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D9__GPIO_4_21		= IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_MCLK__CSI_MCLK		= IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_MCLK__GPIO_1_8		= IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_VSYNC__CSI_VSYNC		= IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_VSYNC__GPIO_1_9		= IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_HSYNC__CSI_HSYNC		= IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_HSYNC__GPIO_1_10		= IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_PIXCLK__CSI_PIXCLK		= IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_PIXCLK__GPIO_1_11		= IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_I2C1_CLK__I2C1_CLK		= IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_I2C1_CLK__GPIO_1_12		= IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_I2C1_DAT__I2C1_DAT		= IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_I2C1_DAT__GPIO_1_13		= IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_MOSI__CSPI1_MOSI		= IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_MOSI__GPIO_1_14		= IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_MISO__CSPI1_MISO		= IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_MISO__GPIO_1_15		= IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_SS0__CSPI1_SS0		= IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS0__GPIO_1_16		= IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_SS1__CSPI1_SS1		= IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS1__I2C3_DAT		= IOMUX_PAD(0x35c, 0x164, 0x11, 0x528, 1, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS1__GPIO_1_17		= IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_SCLK__CSPI1_SCLK		= IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SCLK__GPIO_1_18		= IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_RDY__CSPI1_RDY		= IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE),
+	MX25_PAD_CSPI1_RDY__GPIO_2_22		= IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART1_RXD__UART1_RXD		= IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_UART1_RXD__GPIO_4_22		= IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART1_TXD__UART1_TXD		= IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART1_TXD__GPIO_4_23		= IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART1_RTS__UART1_RTS		= IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_UART1_RTS__CSI_D0		= IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL),
+	MX25_PAD_UART1_RTS__GPIO_4_24		= IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART1_CTS__UART1_CTS		= IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_UART1_CTS__CSI_D1		= IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL),
+	MX25_PAD_UART1_CTS__GPIO_4_25		= IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART2_RXD__UART2_RXD		= IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_RXD__GPIO_4_26		= IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART2_TXD__UART2_TXD		= IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_TXD__GPIO_4_27		= IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART2_RTS__UART2_RTS		= IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_RTS__FEC_COL		= IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL),
+	MX25_PAD_UART2_RTS__GPIO_4_28		= IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART2_CTS__FEC_RX_ER		= IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL),
+	MX25_PAD_UART2_CTS__UART2_CTS		= IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_CTS__GPIO_4_29		= IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_CMD__SD1_CMD		= IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_CMD__FEC_RDATA2		= IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_CMD__GPIO_2_23		= IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_CLK__SD1_CLK		= IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_CLK__FEC_RDATA3		= IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_CLK__GPIO_2_24		= IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_DATA0__SD1_DATA0		= IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA0__GPIO_2_25		= IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_DATA1__SD1_DATA1		= IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA1__AUD7_RXD		= IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA1__GPIO_2_26		= IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_DATA2__SD1_DATA2		= IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA2__FEC_RX_CLK		= IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA2__GPIO_2_27		= IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_DATA3__SD1_DATA3		= IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA3__FEC_CRS		= IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA3__GPIO_2_28		= IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_ROW0__KPP_ROW0		= IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW0__GPIO_2_29		= IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_ROW1__KPP_ROW1		= IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW1__GPIO_2_30		= IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_ROW2__KPP_ROW2		= IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW2__CSI_D0		= IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL),
+	MX25_PAD_KPP_ROW2__GPIO_2_31		= IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_ROW3__KPP_ROW3		= IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW3__CSI_LD1		= IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL),
+	MX25_PAD_KPP_ROW3__GPIO_3_0		= IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_COL0__KPP_COL0		= IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL0__UART4_RXD_MUX	= IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL0__AUD5_TXD		= IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL0__GPIO_3_1		= IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_COL1__KPP_COL1		= IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL1__UART4_TXD_MUX	= IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL1__AUD5_RXD		= IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL1__GPIO_3_2		= IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_COL2__KPP_COL2		= IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL2__UART4_RTS		= IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL2__AUD5_TXC		= IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL2__GPIO_3_3		= IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_COL3__KPP_COL3		= IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL3__UART4_CTS		= IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL3__AUD5_TXFS		= IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL3__GPIO_3_4		= IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_MDC__FEC_MDC		= IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_MDC__AUD4_TXD		= IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL),
+	MX25_PAD_FEC_MDC__GPIO_3_5		= IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_MDIO__FEC_MDIO		= IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
+	MX25_PAD_FEC_MDIO__AUD4_RXD		= IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL),
+	MX25_PAD_FEC_MDIO__GPIO_3_6		= IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_TDATA0__FEC_TDATA0		= IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TDATA0__GPIO_3_7		= IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_TDATA1__FEC_TDATA1		= IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TDATA1__AUD4_TXFS		= IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL),
+	MX25_PAD_FEC_TDATA1__GPIO_3_8		= IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_TX_EN__FEC_TX_EN		= IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TX_EN__GPIO_3_9		= IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_RDATA0__FEC_RDATA0		= IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_RDATA0__GPIO_3_10		= IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_RDATA1__FEC_RDATA1		= IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_RDATA1__GPIO_3_11		= IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_RX_DV__FEC_RX_DV		= IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_RX_DV__CAN2_RX		= IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP),
+	MX25_PAD_FEC_RX_DV__GPIO_3_12		= IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		= IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_TX_CLK__GPIO_3_13		= IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_RTCK__RTCK			= IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_RTCK__OWIRE			= IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_RTCK__GPIO_3_14		= IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_DE_B__DE_B			= IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_DE_B__GPIO_2_20		= IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_TDO__TDO			= IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_GPIO_A__GPIO_A			= IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_A__CAN1_TX		= IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
+	MX25_PAD_GPIO_A__USBOTG_PWR		= IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE),
+
+	MX25_PAD_GPIO_B__GPIO_B			= IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_B__CAN1_RX		= IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP),
+	MX25_PAD_GPIO_B__USBOTG_OC		= IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP),
+
+	MX25_PAD_GPIO_C__GPIO_C			= IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_C__CAN2_TX		= IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
+
+	MX25_PAD_GPIO_D__GPIO_D			= IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_E__LD16			= IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_GPIO_D__CAN2_RX		= IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP),
+
+	MX25_PAD_GPIO_E__GPIO_E			= IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_F__LD17			= IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_GPIO_E__I2C3_CLK		= IOMUX_PAD(0x400, 0x204, 0x11, 0x524, 2, NO_PAD_CTRL),
+	MX25_PAD_GPIO_E__AUD7_TXD		= IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_GPIO_F__GPIO_F			= IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_F__AUD7_TXC		= IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_EXT_ARMCLK__EXT_ARMCLK		= IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EXT_ARMCLK__GPIO_3_15		= IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK	= IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UPLL_BYPCLK__GPIO_3_16		= IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_VSTBY_REQ__VSTBY_REQ		= IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_REQ__AUD7_TXFS		= IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_REQ__GPIO_3_17		= IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_ACK__VSTBY_ACK		= IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_ACK__GPIO_3_18		= IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_POWER_FAIL__POWER_FAIL		= IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_POWER_FAIL__AUD7_RXD		= IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL),
+	MX25_PAD_POWER_FAIL__GPIO_3_19		= IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CLKO__CLKO			= IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CLKO__GPIO_2_21		= IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_BOOT_MODE0__BOOT_MODE0		= IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_BOOT_MODE0__GPIO_4_30		= IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_BOOT_MODE1__BOOT_MODE1		= IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_BOOT_MODE1__GPIO_4_31		= IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CTL_GRP_DVS_MISC		= IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_FEC		= IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_JTAG		= IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_NFC		= IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_CSI		= IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_WEIM		= IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_DDR		= IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_CRM		= IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_KPP		= IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_SDHC1		= IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_LCD		= IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_UART		= IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_NFC		= IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_CSI		= IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_CSPI1		= IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DDRTYPE		= IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_SDHC1		= IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_LCD		= IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX25_H__ */
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
index 2f6c823..8867e9f 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -176,7 +176,7 @@
 	u32 iim_sdat;
 	u32 iim_prev;
 	u32 iim_srev;
-	u32 iim_prog_p;
+	u32 iim_prg_p;
 	u32 iim_scs0;
 	u32 iim_scs1;
 	u32 iim_scs2;
@@ -222,6 +222,7 @@
 #define IMX_PLL_BASE		(0x27000 + IMX_IO_BASE)
 #define IMX_SYSTEM_CTL_BASE	(0x27800 + IMX_IO_BASE)
 #define IMX_IIM_BASE		(0x28000 + IMX_IO_BASE)
+#define IIM_BASE_ADDR		IMX_IIM_BASE
 #define IMX_FEC_BASE		(0x2b000 + IMX_IO_BASE)
 
 #define IMX_ESD_BASE		(0xD8001000)
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 3f58318..67fddac 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -68,7 +68,7 @@
 	u32 test;
 };
 
-/* IIM Control Registers */
+/* IIM control registers */
 struct iim_regs {
 	u32 iim_stat;
 	u32 iim_statm;
@@ -80,11 +80,28 @@
 	u32 iim_sdat;
 	u32 iim_prev;
 	u32 iim_srev;
-	u32 iim_prog_p;
+	u32 iim_prg_p;
 	u32 iim_scs0;
 	u32 iim_scs1;
 	u32 iim_scs2;
 	u32 iim_scs3;
+	u32 res[0x1f1];
+	struct fuse_bank {
+		u32 fuse_regs[0x20];
+		u32 fuse_rsvd[0xe0];
+	} bank[3];
+};
+
+struct fuse_bank0_regs {
+	u32 fuse0_5[6];
+	u32 usr;
+	u32 fuse7_15[9];
+};
+
+struct fuse_bank2_regs {
+	u32 fuse0;
+	u32 uid[8];
+	u32 fuse9_15[7];
 };
 
 struct iomuxc_regs {
@@ -557,6 +574,7 @@
 #define CCMR_CKIH	(2 << 1)
 
 #define MX31_IIM_BASE_ADDR	0x5001C000
+#define IIM_BASE_ADDR		MX31_IIM_BASE_ADDR
 
 #define PDR0_CSI_PODF(x)	(((x) & 0x3f) << 26)
 #define PDR0_CSI_PRDF(x)	(((x) & 0x7) << 23)
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
index 7f337be..63c6e24 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -262,11 +262,28 @@
 	u32 iim_sdat;
 	u32 iim_prev;
 	u32 iim_srev;
-	u32 iim_prog_p;
+	u32 iim_prg_p;
 	u32 iim_scs0;
 	u32 iim_scs1;
 	u32 iim_scs2;
 	u32 iim_scs3;
+	u32 res1[0x1f1];
+	struct fuse_bank {
+		u32 fuse_regs[0x20];
+		u32 fuse_rsvd[0xe0];
+	} bank[3];
+};
+
+struct fuse_bank0_regs {
+	u32 fuse0_7[8];
+	u32 uid[8];
+	u32 fuse16_31[0x10];
+};
+
+struct fuse_bank1_regs {
+	u32 fuse0_21[0x16];
+	u32 usr;
+	u32 fuse23_31[9];
 };
 
 /* General Purpose Timer (GPT) registers */
diff --git a/arch/arm/include/asm/arch-mx35/iomux-mx35.h b/arch/arm/include/asm/arch-mx35/iomux-mx35.h
new file mode 100644
index 0000000..8016cb3
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx35/iomux-mx35.h
@@ -0,0 +1,1276 @@
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on mainline Linux i.MX iomux-mx35.h file:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IOMUX_MX35_H__
+#define __IOMUX_MX35_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/*
+ * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/*									    PAD    MUX   ALT INPSE PATH PADCTRL */
+enum {
+	MX35_PAD_CAPTURE__GPT_CAPIN1				= IOMUX_PAD(0x328, 0x004, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__GPT_CMPOUT2				= IOMUX_PAD(0x328, 0x004, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__CSPI2_SS1				= IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__EPIT1_EPITO				= IOMUX_PAD(0x328, 0x004, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__CCM_CLK32K				= IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__GPIO1_4				= IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL),
+
+	MX35_PAD_COMPARE__GPT_CMPOUT1				= IOMUX_PAD(0x32c, 0x008, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__GPT_CAPIN2				= IOMUX_PAD(0x32c, 0x008, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__GPT_CMPOUT3				= IOMUX_PAD(0x32c, 0x008, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__EPIT2_EPITO				= IOMUX_PAD(0x32c, 0x008, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__GPIO1_5				= IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__SDMA_EXTDMA_2				= IOMUX_PAD(0x32c, 0x008, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_WDOG_RST__WDOG_WDOG_B				= IOMUX_PAD(0x330, 0x00c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_WDOG_RST__IPU_FLASH_STROBE			= IOMUX_PAD(0x330, 0x00c, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_WDOG_RST__GPIO1_6				= IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL),
+
+	MX35_PAD_GPIO1_0__GPIO1_0				= IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_0__CCM_PMIC_RDY				= IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_0__OWIRE_LINE				= IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_0__SDMA_EXTDMA_0				= IOMUX_PAD(0x334, 0x010, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_GPIO1_1__GPIO1_1				= IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_1__PWM_PWMO				= IOMUX_PAD(0x338, 0x014, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_1__CSPI1_SS2				= IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT			= IOMUX_PAD(0x338, 0x014, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_1__SDMA_EXTDMA_1				= IOMUX_PAD(0x338, 0x014, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_GPIO2_0__GPIO2_0				= IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK			= IOMUX_PAD(0x33c, 0x018, 1, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_GPIO3_0__GPIO3_0				= IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK			= IOMUX_PAD(0x340, 0x01c, 1, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RESET_IN_B__CCM_RESET_IN_B			= IOMUX_PAD(0x344, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_POR_B__CCM_POR_B				= IOMUX_PAD(0x348, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CLKO__CCM_CLKO					= IOMUX_PAD(0x34c, 0x020, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CLKO__GPIO1_8					= IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL),
+
+	MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0			= IOMUX_PAD(0x350, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1			= IOMUX_PAD(0x354, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0			= IOMUX_PAD(0x358, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1			= IOMUX_PAD(0x35c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26		= IOMUX_PAD(0x360, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_VSTBY__CCM_VSTBY				= IOMUX_PAD(0x364, 0x024, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_VSTBY__GPIO1_7					= IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL),
+
+	MX35_PAD_A0__EMI_EIM_DA_L_0				= IOMUX_PAD(0x368, 0x028, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A1__EMI_EIM_DA_L_1				= IOMUX_PAD(0x36c, 0x02c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A2__EMI_EIM_DA_L_2				= IOMUX_PAD(0x370, 0x030, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A3__EMI_EIM_DA_L_3				= IOMUX_PAD(0x374, 0x034, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A4__EMI_EIM_DA_L_4				= IOMUX_PAD(0x378, 0x038, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A5__EMI_EIM_DA_L_5				= IOMUX_PAD(0x37c, 0x03c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A6__EMI_EIM_DA_L_6				= IOMUX_PAD(0x380, 0x040, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A7__EMI_EIM_DA_L_7				= IOMUX_PAD(0x384, 0x044, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A8__EMI_EIM_DA_H_8				= IOMUX_PAD(0x388, 0x048, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A9__EMI_EIM_DA_H_9				= IOMUX_PAD(0x38c, 0x04c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A10__EMI_EIM_DA_H_10				= IOMUX_PAD(0x390, 0x050, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_MA10__EMI_MA10					= IOMUX_PAD(0x394, 0x054, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A11__EMI_EIM_DA_H_11				= IOMUX_PAD(0x398, 0x058, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A12__EMI_EIM_DA_H_12				= IOMUX_PAD(0x39c, 0x05c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A13__EMI_EIM_DA_H_13				= IOMUX_PAD(0x3a0, 0x060, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A14__EMI_EIM_DA_H2_14				= IOMUX_PAD(0x3a4, 0x064, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A15__EMI_EIM_DA_H2_15				= IOMUX_PAD(0x3a8, 0x068, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A16__EMI_EIM_A_16				= IOMUX_PAD(0x3ac, 0x06c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A17__EMI_EIM_A_17				= IOMUX_PAD(0x3b0, 0x070, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A18__EMI_EIM_A_18				= IOMUX_PAD(0x3b4, 0x074, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A19__EMI_EIM_A_19				= IOMUX_PAD(0x3b8, 0x078, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A20__EMI_EIM_A_20				= IOMUX_PAD(0x3bc, 0x07c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A21__EMI_EIM_A_21				= IOMUX_PAD(0x3c0, 0x080, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A22__EMI_EIM_A_22				= IOMUX_PAD(0x3c4, 0x084, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A23__EMI_EIM_A_23				= IOMUX_PAD(0x3c8, 0x088, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A24__EMI_EIM_A_24				= IOMUX_PAD(0x3cc, 0x08c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A25__EMI_EIM_A_25				= IOMUX_PAD(0x3d0, 0x090, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDBA1__EMI_EIM_SDBA1				= IOMUX_PAD(0x3d4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDBA0__EMI_EIM_SDBA0				= IOMUX_PAD(0x3d8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD0__EMI_DRAM_D_0				= IOMUX_PAD(0x3dc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1__EMI_DRAM_D_1				= IOMUX_PAD(0x3e0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD2__EMI_DRAM_D_2				= IOMUX_PAD(0x3e4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD3__EMI_DRAM_D_3				= IOMUX_PAD(0x3e8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD4__EMI_DRAM_D_4				= IOMUX_PAD(0x3ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD5__EMI_DRAM_D_5				= IOMUX_PAD(0x3f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD6__EMI_DRAM_D_6				= IOMUX_PAD(0x3f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD7__EMI_DRAM_D_7				= IOMUX_PAD(0x3f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD8__EMI_DRAM_D_8				= IOMUX_PAD(0x3fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD9__EMI_DRAM_D_9				= IOMUX_PAD(0x400, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD10__EMI_DRAM_D_10				= IOMUX_PAD(0x404, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD11__EMI_DRAM_D_11				= IOMUX_PAD(0x408, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD12__EMI_DRAM_D_12				= IOMUX_PAD(0x40c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD13__EMI_DRAM_D_13				= IOMUX_PAD(0x410, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD14__EMI_DRAM_D_14				= IOMUX_PAD(0x414, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD15__EMI_DRAM_D_15				= IOMUX_PAD(0x418, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD16__EMI_DRAM_D_16				= IOMUX_PAD(0x41c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD17__EMI_DRAM_D_17				= IOMUX_PAD(0x420, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD18__EMI_DRAM_D_18				= IOMUX_PAD(0x424, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD19__EMI_DRAM_D_19				= IOMUX_PAD(0x428, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD20__EMI_DRAM_D_20				= IOMUX_PAD(0x42c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD21__EMI_DRAM_D_21				= IOMUX_PAD(0x430, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD22__EMI_DRAM_D_22				= IOMUX_PAD(0x434, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD23__EMI_DRAM_D_23				= IOMUX_PAD(0x438, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD24__EMI_DRAM_D_24				= IOMUX_PAD(0x43c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD25__EMI_DRAM_D_25				= IOMUX_PAD(0x440, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD26__EMI_DRAM_D_26				= IOMUX_PAD(0x444, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD27__EMI_DRAM_D_27				= IOMUX_PAD(0x448, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD28__EMI_DRAM_D_28				= IOMUX_PAD(0x44c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD29__EMI_DRAM_D_29				= IOMUX_PAD(0x450, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD30__EMI_DRAM_D_30				= IOMUX_PAD(0x454, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD31__EMI_DRAM_D_31				= IOMUX_PAD(0x458, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DQM0__EMI_DRAM_DQM_0				= IOMUX_PAD(0x45c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DQM1__EMI_DRAM_DQM_1				= IOMUX_PAD(0x460, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DQM2__EMI_DRAM_DQM_2				= IOMUX_PAD(0x464, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DQM3__EMI_DRAM_DQM_3				= IOMUX_PAD(0x468, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_EB0__EMI_EIM_EB0_B				= IOMUX_PAD(0x46c, 0x094, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_EB1__EMI_EIM_EB1_B				= IOMUX_PAD(0x470, 0x098, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_OE__EMI_EIM_OE					= IOMUX_PAD(0x474, 0x09c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS0__EMI_EIM_CS0				= IOMUX_PAD(0x478, 0x0a0, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS1__EMI_EIM_CS1				= IOMUX_PAD(0x47c, 0x0a4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS1__EMI_NANDF_CE3				= IOMUX_PAD(0x47c, 0x0a4, 3, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS2__EMI_EIM_CS2				= IOMUX_PAD(0x480, 0x0a8, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS3__EMI_EIM_CS3				= IOMUX_PAD(0x484, 0x0ac, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS4__EMI_EIM_CS4				= IOMUX_PAD(0x488, 0x0b0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS4__EMI_DTACK_B				= IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL),
+	MX35_PAD_CS4__EMI_NANDF_CE1				= IOMUX_PAD(0x488, 0x0b0, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS4__GPIO1_20					= IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL),
+
+	MX35_PAD_CS5__EMI_EIM_CS5				= IOMUX_PAD(0x48c, 0x0b4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS5__CSPI2_SS2					= IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL),
+	MX35_PAD_CS5__CSPI1_SS2					= IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL),
+	MX35_PAD_CS5__EMI_NANDF_CE2				= IOMUX_PAD(0x48c, 0x0b4, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS5__GPIO1_21					= IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL),
+
+	MX35_PAD_NF_CE0__EMI_NANDF_CE0				= IOMUX_PAD(0x490, 0x0b8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NF_CE0__GPIO1_22				= IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL),
+
+	MX35_PAD_ECB__EMI_EIM_ECB				= IOMUX_PAD(0x494, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LBA__EMI_EIM_LBA				= IOMUX_PAD(0x498, 0x0bc, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_BCLK__EMI_EIM_BCLK				= IOMUX_PAD(0x49c, 0x0c0, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RW__EMI_EIM_RW					= IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RAS__EMI_DRAM_RAS				= IOMUX_PAD(0x4a4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CAS__EMI_DRAM_CAS				= IOMUX_PAD(0x4a8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDWE__EMI_DRAM_SDWE				= IOMUX_PAD(0x4ac, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0			= IOMUX_PAD(0x4b0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1			= IOMUX_PAD(0x4b4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDCLK__EMI_DRAM_SDCLK				= IOMUX_PAD(0x4b8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDQS0__EMI_DRAM_SDQS_0				= IOMUX_PAD(0x4bc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDQS1__EMI_DRAM_SDQS_1				= IOMUX_PAD(0x4c0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDQS2__EMI_DRAM_SDQS_2				= IOMUX_PAD(0x4c4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDQS3__EMI_DRAM_SDQS_3				= IOMUX_PAD(0x4c8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFWE_B__EMI_NANDF_WE_B				= IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3			= IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC			= IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWE_B__GPIO2_18				= IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0			= IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFRE_B__EMI_NANDF_RE_B				= IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR			= IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL),
+	MX35_PAD_NFRE_B__IPU_DISPB_BCLK				= IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFRE_B__GPIO2_19				= IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL),
+	MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1			= IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFALE__EMI_NANDF_ALE				= IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFALE__USB_TOP_USBH2_STP			= IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFALE__IPU_DISPB_CS0				= IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFALE__GPIO2_20				= IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL),
+	MX35_PAD_NFALE__ARM11P_TOP_TRACE_2			= IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFCLE__EMI_NANDF_CLE				= IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFCLE__USB_TOP_USBH2_NXT			= IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL),
+	MX35_PAD_NFCLE__IPU_DISPB_PAR_RS			= IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFCLE__GPIO2_21				= IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL),
+	MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3			= IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFWP_B__EMI_NANDF_WP_B				= IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7			= IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWP_B__IPU_DISPB_WR				= IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFWP_B__GPIO2_22				= IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL			= IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFRB__EMI_NANDF_RB				= IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFRB__IPU_DISPB_RD				= IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFRB__GPIO2_23					= IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL),
+	MX35_PAD_NFRB__ARM11P_TOP_TRCLK				= IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D15__EMI_EIM_D_15				= IOMUX_PAD(0x4e4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D14__EMI_EIM_D_14				= IOMUX_PAD(0x4e8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D13__EMI_EIM_D_13				= IOMUX_PAD(0x4ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D12__EMI_EIM_D_12				= IOMUX_PAD(0x4f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D11__EMI_EIM_D_11				= IOMUX_PAD(0x4f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D10__EMI_EIM_D_10				= IOMUX_PAD(0x4f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D9__EMI_EIM_D_9				= IOMUX_PAD(0x4fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D8__EMI_EIM_D_8				= IOMUX_PAD(0x500, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D7__EMI_EIM_D_7				= IOMUX_PAD(0x504, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D6__EMI_EIM_D_6				= IOMUX_PAD(0x508, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D5__EMI_EIM_D_5				= IOMUX_PAD(0x50c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D4__EMI_EIM_D_4				= IOMUX_PAD(0x510, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3__EMI_EIM_D_3				= IOMUX_PAD(0x514, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D2__EMI_EIM_D_2				= IOMUX_PAD(0x518, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D1__EMI_EIM_D_1				= IOMUX_PAD(0x51c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D0__EMI_EIM_D_0				= IOMUX_PAD(0x520, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D8__IPU_CSI_D_8				= IOMUX_PAD(0x524, 0x0e0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D8__KPP_COL_0				= IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D8__GPIO1_20				= IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL),
+	MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13			= IOMUX_PAD(0x524, 0x0e0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D9__IPU_CSI_D_9				= IOMUX_PAD(0x528, 0x0e4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D9__KPP_COL_1				= IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D9__GPIO1_21				= IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL),
+	MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14			= IOMUX_PAD(0x528, 0x0e4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D10__IPU_CSI_D_10				= IOMUX_PAD(0x52c, 0x0e8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D10__KPP_COL_2				= IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D10__GPIO1_22				= IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL),
+	MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15			= IOMUX_PAD(0x52c, 0x0e8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D11__IPU_CSI_D_11				= IOMUX_PAD(0x530, 0x0ec, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D11__KPP_COL_3				= IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D11__GPIO1_23				= IOMUX_PAD(0x530, 0x0ec, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D12__IPU_CSI_D_12				= IOMUX_PAD(0x534, 0x0f0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D12__KPP_ROW_0				= IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D12__GPIO1_24				= IOMUX_PAD(0x534, 0x0f0, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D13__IPU_CSI_D_13				= IOMUX_PAD(0x538, 0x0f4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D13__KPP_ROW_1				= IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D13__GPIO1_25				= IOMUX_PAD(0x538, 0x0f4, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D14__IPU_CSI_D_14				= IOMUX_PAD(0x53c, 0x0f8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D14__KPP_ROW_2				= IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D14__GPIO1_26				= IOMUX_PAD(0x53c, 0x0f8, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D15__IPU_CSI_D_15				= IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D15__KPP_ROW_3				= IOMUX_PAD(0x540, 0x0fc, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D15__GPIO1_27				= IOMUX_PAD(0x540, 0x0fc, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_MCLK__IPU_CSI_MCLK				= IOMUX_PAD(0x544, 0x100, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_MCLK__GPIO1_28				= IOMUX_PAD(0x544, 0x100, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC			= IOMUX_PAD(0x548, 0x104, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_VSYNC__GPIO1_29				= IOMUX_PAD(0x548, 0x104, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC			= IOMUX_PAD(0x54c, 0x108, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_HSYNC__GPIO1_30				= IOMUX_PAD(0x54c, 0x108, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK			= IOMUX_PAD(0x550, 0x10c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_PIXCLK__GPIO1_31				= IOMUX_PAD(0x550, 0x10c, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_I2C1_CLK__I2C1_SCL				= IOMUX_PAD(0x554, 0x110, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C1_CLK__GPIO2_24				= IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK			= IOMUX_PAD(0x554, 0x110, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_I2C1_DAT__I2C1_SDA				= IOMUX_PAD(0x558, 0x114, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C1_DAT__GPIO2_25				= IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL),
+
+	MX35_PAD_I2C2_CLK__I2C2_SCL				= IOMUX_PAD(0x55c, 0x118, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_CLK__CAN1_TXCAN				= IOMUX_PAD(0x55c, 0x118, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR			= IOMUX_PAD(0x55c, 0x118, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_CLK__GPIO2_26				= IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2		= IOMUX_PAD(0x55c, 0x118, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_I2C2_DAT__I2C2_SDA				= IOMUX_PAD(0x560, 0x11c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_DAT__CAN1_RXCAN				= IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC			= IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_DAT__GPIO2_27				= IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3		= IOMUX_PAD(0x560, 0x11c, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_STXD4__AUDMUX_AUD4_TXD				= IOMUX_PAD(0x564, 0x120, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXD4__GPIO2_28				= IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL),
+	MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0		= IOMUX_PAD(0x564, 0x120, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SRXD4__AUDMUX_AUD4_RXD				= IOMUX_PAD(0x568, 0x124, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SRXD4__GPIO2_29				= IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL),
+	MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1		= IOMUX_PAD(0x568, 0x124, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SCK4__AUDMUX_AUD4_TXC				= IOMUX_PAD(0x56c, 0x128, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SCK4__GPIO2_30					= IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL),
+	MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2			= IOMUX_PAD(0x56c, 0x128, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS			= IOMUX_PAD(0x570, 0x12c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXFS4__GPIO2_31				= IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL),
+	MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3		= IOMUX_PAD(0x570, 0x12c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_STXD5__AUDMUX_AUD5_TXD				= IOMUX_PAD(0x574, 0x130, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXD5__SPDIF_SPDIF_OUT1			= IOMUX_PAD(0x574, 0x130, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXD5__CSPI2_MOSI				= IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL),
+	MX35_PAD_STXD5__GPIO1_0					= IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL),
+	MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4		= IOMUX_PAD(0x574, 0x130, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SRXD5__AUDMUX_AUD5_RXD				= IOMUX_PAD(0x578, 0x134, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SRXD5__SPDIF_SPDIF_IN1				= IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL),
+	MX35_PAD_SRXD5__CSPI2_MISO				= IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL),
+	MX35_PAD_SRXD5__GPIO1_1					= IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL),
+	MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5		= IOMUX_PAD(0x578, 0x134, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SCK5__AUDMUX_AUD5_TXC				= IOMUX_PAD(0x57c, 0x138, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL),
+	MX35_PAD_SCK5__CSPI2_SCLK				= IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL),
+	MX35_PAD_SCK5__GPIO1_2					= IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL),
+	MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6			= IOMUX_PAD(0x57c, 0x138, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS			= IOMUX_PAD(0x580, 0x13c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXFS5__CSPI2_RDY				= IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL),
+	MX35_PAD_STXFS5__GPIO1_3				= IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL),
+	MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7		= IOMUX_PAD(0x580, 0x13c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SCKR__ESAI_SCKR				= IOMUX_PAD(0x584, 0x140, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SCKR__GPIO1_4					= IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL),
+	MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10			= IOMUX_PAD(0x584, 0x140, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FSR__ESAI_FSR					= IOMUX_PAD(0x588, 0x144, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FSR__GPIO1_5					= IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL),
+	MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11			= IOMUX_PAD(0x588, 0x144, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_HCKR__ESAI_HCKR				= IOMUX_PAD(0x58c, 0x148, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_HCKR__AUDMUX_AUD5_RXFS				= IOMUX_PAD(0x58c, 0x148, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_HCKR__CSPI2_SS0				= IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL),
+	MX35_PAD_HCKR__IPU_FLASH_STROBE				= IOMUX_PAD(0x58c, 0x148, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_HCKR__GPIO1_6					= IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL),
+	MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12			= IOMUX_PAD(0x58c, 0x148, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SCKT__ESAI_SCKT				= IOMUX_PAD(0x590, 0x14c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SCKT__GPIO1_7					= IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL),
+	MX35_PAD_SCKT__IPU_CSI_D_0				= IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL),
+	MX35_PAD_SCKT__KPP_ROW_2				= IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL),
+
+	MX35_PAD_FST__ESAI_FST					= IOMUX_PAD(0x594, 0x150, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FST__GPIO1_8					= IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL),
+	MX35_PAD_FST__IPU_CSI_D_1				= IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL),
+	MX35_PAD_FST__KPP_ROW_3					= IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL),
+
+	MX35_PAD_HCKT__ESAI_HCKT				= IOMUX_PAD(0x598, 0x154, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_HCKT__AUDMUX_AUD5_RXC				= IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL),
+	MX35_PAD_HCKT__GPIO1_9					= IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL),
+	MX35_PAD_HCKT__IPU_CSI_D_2				= IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL),
+	MX35_PAD_HCKT__KPP_COL_3				= IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX5_RX0__ESAI_TX5_RX0				= IOMUX_PAD(0x59c, 0x158, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC			= IOMUX_PAD(0x59c, 0x158, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__CSPI2_SS2				= IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__CAN2_TXCAN				= IOMUX_PAD(0x59c, 0x158, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__UART2_DTR				= IOMUX_PAD(0x59c, 0x158, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__GPIO1_10				= IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0		= IOMUX_PAD(0x59c, 0x158, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TX4_RX1__ESAI_TX4_RX1				= IOMUX_PAD(0x5a0, 0x15c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS			= IOMUX_PAD(0x5a0, 0x15c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__CSPI2_SS3				= IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__CAN2_RXCAN				= IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__UART2_DSR				= IOMUX_PAD(0x5a0, 0x15c, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__GPIO1_11				= IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__IPU_CSI_D_3				= IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__KPP_ROW_0				= IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX3_RX2__ESAI_TX3_RX2				= IOMUX_PAD(0x5a4, 0x160, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__I2C3_SCL				= IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__EMI_NANDF_CE1				= IOMUX_PAD(0x5a4, 0x160, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__GPIO1_12				= IOMUX_PAD(0x5a4, 0x160, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__IPU_CSI_D_4				= IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__KPP_ROW_1				= IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX2_RX3__ESAI_TX2_RX3				= IOMUX_PAD(0x5a8, 0x164, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__I2C3_SDA				= IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__EMI_NANDF_CE2				= IOMUX_PAD(0x5a8, 0x164, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__GPIO1_13				= IOMUX_PAD(0x5a8, 0x164, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__IPU_CSI_D_5				= IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__KPP_COL_0				= IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX1__ESAI_TX1					= IOMUX_PAD(0x5ac, 0x168, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX1__CCM_PMIC_RDY				= IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL),
+	MX35_PAD_TX1__CSPI1_SS2					= IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL),
+	MX35_PAD_TX1__EMI_NANDF_CE3				= IOMUX_PAD(0x5ac, 0x168, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX1__UART2_RI					= IOMUX_PAD(0x5ac, 0x168, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX1__GPIO1_14					= IOMUX_PAD(0x5ac, 0x168, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX1__IPU_CSI_D_6				= IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL),
+	MX35_PAD_TX1__KPP_COL_1					= IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX0__ESAI_TX0					= IOMUX_PAD(0x5b0, 0x16c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL),
+	MX35_PAD_TX0__CSPI1_SS3					= IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL),
+	MX35_PAD_TX0__EMI_DTACK_B				= IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL),
+	MX35_PAD_TX0__UART2_DCD					= IOMUX_PAD(0x5b0, 0x16c, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX0__GPIO1_15					= IOMUX_PAD(0x5b0, 0x16c, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX0__IPU_CSI_D_7				= IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL),
+	MX35_PAD_TX0__KPP_COL_2					= IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_MOSI__CSPI1_MOSI				= IOMUX_PAD(0x5b4, 0x170, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_MOSI__GPIO1_16				= IOMUX_PAD(0x5b4, 0x170, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2		= IOMUX_PAD(0x5b4, 0x170, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_MISO__CSPI1_MISO				= IOMUX_PAD(0x5b8, 0x174, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_MISO__GPIO1_17				= IOMUX_PAD(0x5b8, 0x174, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3		= IOMUX_PAD(0x5b8, 0x174, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_SS0__CSPI1_SS0				= IOMUX_PAD(0x5bc, 0x178, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS0__OWIRE_LINE				= IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS0__CSPI2_SS3				= IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS0__GPIO1_18				= IOMUX_PAD(0x5bc, 0x178, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4			= IOMUX_PAD(0x5bc, 0x178, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_SS1__CSPI1_SS1				= IOMUX_PAD(0x5c0, 0x17c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__PWM_PWMO				= IOMUX_PAD(0x5c0, 0x17c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__CCM_CLK32K				= IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__GPIO1_19				= IOMUX_PAD(0x5c0, 0x17c, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__IPU_DIAGB_29			= IOMUX_PAD(0x5c0, 0x17c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5			= IOMUX_PAD(0x5c0, 0x17c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_SCLK__CSPI1_SCLK				= IOMUX_PAD(0x5c4, 0x180, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SCLK__GPIO3_4				= IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30			= IOMUX_PAD(0x5c4, 0x180, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1		= IOMUX_PAD(0x5c4, 0x180, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY			= IOMUX_PAD(0x5c8, 0x184, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SPI_RDY__GPIO3_5				= IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31			= IOMUX_PAD(0x5c8, 0x184, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2	= IOMUX_PAD(0x5c8, 0x184, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RXD1__UART1_RXD_MUX				= IOMUX_PAD(0x5cc, 0x188, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RXD1__CSPI2_MOSI				= IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL),
+	MX35_PAD_RXD1__KPP_COL_4				= IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL),
+	MX35_PAD_RXD1__GPIO3_6					= IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL),
+	MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16			= IOMUX_PAD(0x5cc, 0x188, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TXD1__UART1_TXD_MUX				= IOMUX_PAD(0x5d0, 0x18c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TXD1__CSPI2_MISO				= IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL),
+	MX35_PAD_TXD1__KPP_COL_5				= IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL),
+	MX35_PAD_TXD1__GPIO3_7					= IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL),
+	MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17			= IOMUX_PAD(0x5d0, 0x18c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RTS1__UART1_RTS				= IOMUX_PAD(0x5d4, 0x190, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RTS1__CSPI2_SCLK				= IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS1__I2C3_SCL					= IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS1__IPU_CSI_D_0				= IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS1__KPP_COL_6				= IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL),
+	MX35_PAD_RTS1__GPIO3_8					= IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL),
+	MX35_PAD_RTS1__EMI_NANDF_CE1				= IOMUX_PAD(0x5d4, 0x190, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18			= IOMUX_PAD(0x5d4, 0x190, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CTS1__UART1_CTS				= IOMUX_PAD(0x5d8, 0x194, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS1__CSPI2_RDY				= IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL),
+	MX35_PAD_CTS1__I2C3_SDA					= IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL),
+	MX35_PAD_CTS1__IPU_CSI_D_1				= IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL),
+	MX35_PAD_CTS1__KPP_COL_7				= IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL),
+	MX35_PAD_CTS1__GPIO3_9					= IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL),
+	MX35_PAD_CTS1__EMI_NANDF_CE2				= IOMUX_PAD(0x5d8, 0x194, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19			= IOMUX_PAD(0x5d8, 0x194, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RXD2__UART2_RXD_MUX				= IOMUX_PAD(0x5dc, 0x198, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RXD2__KPP_ROW_4				= IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL),
+	MX35_PAD_RXD2__GPIO3_10					= IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL),
+
+	MX35_PAD_TXD2__UART2_TXD_MUX				= IOMUX_PAD(0x5e0, 0x19c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL),
+	MX35_PAD_TXD2__KPP_ROW_5				= IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL),
+	MX35_PAD_TXD2__GPIO3_11					= IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL),
+
+	MX35_PAD_RTS2__UART2_RTS				= IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RTS2__SPDIF_SPDIF_IN1				= IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS2__CAN2_RXCAN				= IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS2__IPU_CSI_D_2				= IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS2__KPP_ROW_6				= IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL),
+	MX35_PAD_RTS2__GPIO3_12					= IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL),
+	MX35_PAD_RTS2__AUDMUX_AUD5_RXC				= IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RTS2__UART3_RXD_MUX				= IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL),
+
+	MX35_PAD_CTS2__UART2_CTS				= IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__SPDIF_SPDIF_OUT1				= IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__CAN2_TXCAN				= IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__IPU_CSI_D_3				= IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL),
+	MX35_PAD_CTS2__KPP_ROW_7				= IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__GPIO3_13					= IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__AUDMUX_AUD5_RXFS				= IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__UART3_TXD_MUX				= IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RTCK__ARM11P_TOP_RTCK				= IOMUX_PAD(0x5ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TCK__SJC_TCK					= IOMUX_PAD(0x5f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TMS__SJC_TMS					= IOMUX_PAD(0x5f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TDI__SJC_TDI					= IOMUX_PAD(0x5f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TDO__SJC_TDO					= IOMUX_PAD(0x5fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TRSTB__SJC_TRSTB				= IOMUX_PAD(0x600, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DE_B__SJC_DE_B					= IOMUX_PAD(0x604, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SJC_MOD__SJC_MOD				= IOMUX_PAD(0x608, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR			= IOMUX_PAD(0x60c, 0x1a8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR			= IOMUX_PAD(0x60c, 0x1a8, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_USBOTG_PWR__GPIO3_14				= IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL),
+
+	MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC			= IOMUX_PAD(0x610, 0x1ac, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC			= IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL),
+	MX35_PAD_USBOTG_OC__GPIO3_15				= IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL),
+
+	MX35_PAD_LD0__IPU_DISPB_DAT_0				= IOMUX_PAD(0x614, 0x1b0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD0__GPIO2_0					= IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL),
+	MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0			= IOMUX_PAD(0x614, 0x1b0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD1__IPU_DISPB_DAT_1				= IOMUX_PAD(0x618, 0x1b4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD1__GPIO2_1					= IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL),
+	MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1			= IOMUX_PAD(0x618, 0x1b4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD2__IPU_DISPB_DAT_2				= IOMUX_PAD(0x61c, 0x1b8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD2__GPIO2_2					= IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2			= IOMUX_PAD(0x61c, 0x1b8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD3__IPU_DISPB_DAT_3				= IOMUX_PAD(0x620, 0x1bc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD3__GPIO2_3					= IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL),
+	MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3			= IOMUX_PAD(0x620, 0x1bc, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD4__IPU_DISPB_DAT_4				= IOMUX_PAD(0x624, 0x1c0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD4__GPIO2_4					= IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4			= IOMUX_PAD(0x624, 0x1c0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD5__IPU_DISPB_DAT_5				= IOMUX_PAD(0x628, 0x1c4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD5__GPIO2_5					= IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL),
+	MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5			= IOMUX_PAD(0x628, 0x1c4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD6__IPU_DISPB_DAT_6				= IOMUX_PAD(0x62c, 0x1c8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD6__GPIO2_6					= IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL),
+	MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6			= IOMUX_PAD(0x62c, 0x1c8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD7__IPU_DISPB_DAT_7				= IOMUX_PAD(0x630, 0x1cc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD7__GPIO2_7					= IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL),
+	MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7			= IOMUX_PAD(0x630, 0x1cc, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD8__IPU_DISPB_DAT_8				= IOMUX_PAD(0x634, 0x1d0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD8__GPIO2_8					= IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8			= IOMUX_PAD(0x634, 0x1d0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD9__IPU_DISPB_DAT_9				= IOMUX_PAD(0x638, 0x1d4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD9__GPIO2_9					= IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL),
+	MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9			= IOMUX_PAD(0x638, 0x1d4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD10__IPU_DISPB_DAT_10				= IOMUX_PAD(0x63c, 0x1d8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD10__GPIO2_10					= IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL),
+	MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10			= IOMUX_PAD(0x63c, 0x1d8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD11__IPU_DISPB_DAT_11				= IOMUX_PAD(0x640, 0x1dc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD11__GPIO2_11					= IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL),
+	MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11			= IOMUX_PAD(0x640, 0x1dc, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD11__ARM11P_TOP_TRACE_4			= IOMUX_PAD(0x640, 0x1dc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD12__IPU_DISPB_DAT_12				= IOMUX_PAD(0x644, 0x1e0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD12__GPIO2_12					= IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL),
+	MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12			= IOMUX_PAD(0x644, 0x1e0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD12__ARM11P_TOP_TRACE_5			= IOMUX_PAD(0x644, 0x1e0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD13__IPU_DISPB_DAT_13				= IOMUX_PAD(0x648, 0x1e4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD13__GPIO2_13					= IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL),
+	MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13			= IOMUX_PAD(0x648, 0x1e4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD13__ARM11P_TOP_TRACE_6			= IOMUX_PAD(0x648, 0x1e4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD14__IPU_DISPB_DAT_14				= IOMUX_PAD(0x64c, 0x1e8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD14__GPIO2_14					= IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL),
+	MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0		= IOMUX_PAD(0x64c, 0x1e8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD14__ARM11P_TOP_TRACE_7			= IOMUX_PAD(0x64c, 0x1e8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD15__IPU_DISPB_DAT_15				= IOMUX_PAD(0x650, 0x1ec, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD15__GPIO2_15					= IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL),
+	MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1		= IOMUX_PAD(0x650, 0x1ec, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD15__ARM11P_TOP_TRACE_8			= IOMUX_PAD(0x650, 0x1ec, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD16__IPU_DISPB_DAT_16				= IOMUX_PAD(0x654, 0x1f0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD16__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL),
+	MX35_PAD_LD16__GPIO2_16					= IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL),
+	MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2		= IOMUX_PAD(0x654, 0x1f0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD16__ARM11P_TOP_TRACE_9			= IOMUX_PAD(0x654, 0x1f0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD17__IPU_DISPB_DAT_17				= IOMUX_PAD(0x658, 0x1f4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD17__IPU_DISPB_CS2				= IOMUX_PAD(0x658, 0x1f4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD17__GPIO2_17					= IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL),
+	MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3		= IOMUX_PAD(0x658, 0x1f4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD17__ARM11P_TOP_TRACE_10			= IOMUX_PAD(0x658, 0x1f4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD18__IPU_DISPB_DAT_18				= IOMUX_PAD(0x65c, 0x1f8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD18__IPU_DISPB_D0_VSYNC			= IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL),
+	MX35_PAD_LD18__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL),
+	MX35_PAD_LD18__ESDHC3_CMD				= IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL),
+	MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3			= IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD18__GPIO3_24					= IOMUX_PAD(0x65c, 0x1f8, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4		= IOMUX_PAD(0x65c, 0x1f8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD18__ARM11P_TOP_TRACE_11			= IOMUX_PAD(0x65c, 0x1f8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD19__IPU_DISPB_DAT_19				= IOMUX_PAD(0x660, 0x1fc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__IPU_DISPB_BCLK				= IOMUX_PAD(0x660, 0x1fc, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__IPU_DISPB_CS1				= IOMUX_PAD(0x660, 0x1fc, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__ESDHC3_CLK				= IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL),
+	MX35_PAD_LD19__USB_TOP_USBOTG_DIR			= IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL),
+	MX35_PAD_LD19__GPIO3_25					= IOMUX_PAD(0x660, 0x1fc, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5		= IOMUX_PAD(0x660, 0x1fc, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__ARM11P_TOP_TRACE_12			= IOMUX_PAD(0x660, 0x1fc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD20__IPU_DISPB_DAT_20				= IOMUX_PAD(0x664, 0x200, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__IPU_DISPB_CS0				= IOMUX_PAD(0x664, 0x200, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__IPU_DISPB_SD_CLK				= IOMUX_PAD(0x664, 0x200, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__ESDHC3_DAT0				= IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL),
+	MX35_PAD_LD20__GPIO3_26					= IOMUX_PAD(0x664, 0x200, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3		= IOMUX_PAD(0x664, 0x200, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__ARM11P_TOP_TRACE_13			= IOMUX_PAD(0x664, 0x200, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD21__IPU_DISPB_DAT_21				= IOMUX_PAD(0x668, 0x204, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__IPU_DISPB_PAR_RS				= IOMUX_PAD(0x668, 0x204, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__IPU_DISPB_SER_RS				= IOMUX_PAD(0x668, 0x204, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__ESDHC3_DAT1				= IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL),
+	MX35_PAD_LD21__USB_TOP_USBOTG_STP			= IOMUX_PAD(0x668, 0x204, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__GPIO3_27					= IOMUX_PAD(0x668, 0x204, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL		= IOMUX_PAD(0x668, 0x204, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__ARM11P_TOP_TRACE_14			= IOMUX_PAD(0x668, 0x204, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD22__IPU_DISPB_DAT_22				= IOMUX_PAD(0x66c, 0x208, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD22__IPU_DISPB_WR				= IOMUX_PAD(0x66c, 0x208, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD22__IPU_DISPB_SD_D_I				= IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL),
+	MX35_PAD_LD22__ESDHC3_DAT2				= IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL),
+	MX35_PAD_LD22__USB_TOP_USBOTG_NXT			= IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL),
+	MX35_PAD_LD22__GPIO3_28					= IOMUX_PAD(0x66c, 0x208, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR			= IOMUX_PAD(0x66c, 0x208, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD22__ARM11P_TOP_TRCTL				= IOMUX_PAD(0x66c, 0x208, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD23__IPU_DISPB_DAT_23				= IOMUX_PAD(0x670, 0x20c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD23__IPU_DISPB_RD				= IOMUX_PAD(0x670, 0x20c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD23__IPU_DISPB_SD_D_IO			= IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL),
+	MX35_PAD_LD23__ESDHC3_DAT3				= IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL),
+	MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7			= IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD23__GPIO3_29					= IOMUX_PAD(0x670, 0x20c, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS			= IOMUX_PAD(0x670, 0x20c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD23__ARM11P_TOP_TRCLK				= IOMUX_PAD(0x670, 0x20c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC			= IOMUX_PAD(0x674, 0x210, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO			= IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_HSYNC__GPIO3_30				= IOMUX_PAD(0x674, 0x210, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE		= IOMUX_PAD(0x674, 0x210, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15			= IOMUX_PAD(0x674, 0x210, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK			= IOMUX_PAD(0x678, 0x214, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK			= IOMUX_PAD(0x678, 0x214, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_FPSHIFT__GPIO3_31				= IOMUX_PAD(0x678, 0x214, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0	= IOMUX_PAD(0x678, 0x214, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16		= IOMUX_PAD(0x678, 0x214, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY			= IOMUX_PAD(0x67c, 0x218, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O			= IOMUX_PAD(0x67c, 0x218, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_DRDY__GPIO1_0				= IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1		= IOMUX_PAD(0x67c, 0x218, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17			= IOMUX_PAD(0x67c, 0x218, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CONTRAST__IPU_DISPB_CONTR			= IOMUX_PAD(0x680, 0x21c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CONTRAST__GPIO1_1				= IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL),
+	MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2	= IOMUX_PAD(0x680, 0x21c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18			= IOMUX_PAD(0x680, 0x21c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC			= IOMUX_PAD(0x684, 0x220, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_VSYNC__IPU_DISPB_CS1			= IOMUX_PAD(0x684, 0x220, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_VSYNC__GPIO1_2				= IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL),
+	MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD			= IOMUX_PAD(0x684, 0x220, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19			= IOMUX_PAD(0x684, 0x220, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_REV__IPU_DISPB_D3_REV			= IOMUX_PAD(0x688, 0x224, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_REV__IPU_DISPB_SER_RS			= IOMUX_PAD(0x688, 0x224, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_REV__GPIO1_3				= IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL),
+	MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB			= IOMUX_PAD(0x688, 0x224, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20			= IOMUX_PAD(0x688, 0x224, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS			= IOMUX_PAD(0x68c, 0x228, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_CLS__IPU_DISPB_CS2				= IOMUX_PAD(0x68c, 0x228, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_CLS__GPIO1_4				= IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0		= IOMUX_PAD(0x68c, 0x228, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21			= IOMUX_PAD(0x68c, 0x228, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL			= IOMUX_PAD(0x690, 0x22c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_SPL__GPIO1_5				= IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1		= IOMUX_PAD(0x690, 0x22c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22			= IOMUX_PAD(0x690, 0x22c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_CMD__ESDHC1_CMD				= IOMUX_PAD(0x694, 0x230, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__MSHC_SCLK				= IOMUX_PAD(0x694, 0x230, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC			= IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4			= IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__GPIO1_6				= IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL			= IOMUX_PAD(0x694, 0x230, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_CLK__ESDHC1_CLK				= IOMUX_PAD(0x698, 0x234, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__MSHC_BS				= IOMUX_PAD(0x698, 0x234, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__IPU_DISPB_BCLK			= IOMUX_PAD(0x698, 0x234, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5			= IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__GPIO1_7				= IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK			= IOMUX_PAD(0x698, 0x234, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_DATA0__ESDHC1_DAT0				= IOMUX_PAD(0x69c, 0x238, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__MSHC_DATA_0				= IOMUX_PAD(0x69c, 0x238, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__IPU_DISPB_CS0			= IOMUX_PAD(0x69c, 0x238, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6		= IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__GPIO1_8				= IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23			= IOMUX_PAD(0x69c, 0x238, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_DATA1__ESDHC1_DAT1				= IOMUX_PAD(0x6a0, 0x23c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__MSHC_DATA_1				= IOMUX_PAD(0x6a0, 0x23c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS			= IOMUX_PAD(0x6a0, 0x23c, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0		= IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__GPIO1_9				= IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24			= IOMUX_PAD(0x6a0, 0x23c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_DATA2__ESDHC1_DAT2				= IOMUX_PAD(0x6a4, 0x240, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__MSHC_DATA_2				= IOMUX_PAD(0x6a4, 0x240, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__IPU_DISPB_WR			= IOMUX_PAD(0x6a4, 0x240, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1		= IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__GPIO1_10				= IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25			= IOMUX_PAD(0x6a4, 0x240, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_DATA3__ESDHC1_DAT3				= IOMUX_PAD(0x6a8, 0x244, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__MSHC_DATA_3				= IOMUX_PAD(0x6a8, 0x244, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__IPU_DISPB_RD			= IOMUX_PAD(0x6a8, 0x244, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2		= IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__GPIO1_11				= IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26			= IOMUX_PAD(0x6a8, 0x244, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_CMD__ESDHC2_CMD				= IOMUX_PAD(0x6ac, 0x248, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__I2C3_SCL				= IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__ESDHC1_DAT4				= IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__IPU_CSI_D_2				= IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4			= IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__GPIO2_0				= IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1			= IOMUX_PAD(0x6ac, 0x248, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_CLK__ESDHC2_CLK				= IOMUX_PAD(0x6b0, 0x24c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__I2C3_SDA				= IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__ESDHC1_DAT5				= IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__IPU_CSI_D_3				= IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5			= IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__GPIO2_1				= IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1			= IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__IPU_DISPB_CS2				= IOMUX_PAD(0x6b0, 0x24c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_DATA0__ESDHC2_DAT0				= IOMUX_PAD(0x6b4, 0x250, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__UART3_RXD_MUX			= IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__ESDHC1_DAT6				= IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__IPU_CSI_D_4				= IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6		= IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__GPIO2_2				= IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_DATA1__ESDHC2_DAT1				= IOMUX_PAD(0x6b8, 0x254, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__UART3_TXD_MUX			= IOMUX_PAD(0x6b8, 0x254, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__ESDHC1_DAT7				= IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__IPU_CSI_D_5				= IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0		= IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__GPIO2_3				= IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_DATA2__ESDHC2_DAT2				= IOMUX_PAD(0x6bc, 0x258, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__UART3_RTS				= IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__CAN1_RXCAN				= IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__IPU_CSI_D_6				= IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1		= IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__GPIO2_4				= IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_DATA3__ESDHC2_DAT3				= IOMUX_PAD(0x6c0, 0x25c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__UART3_CTS				= IOMUX_PAD(0x6c0, 0x25c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__CAN1_TXCAN				= IOMUX_PAD(0x6c0, 0x25c, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__IPU_CSI_D_7				= IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2		= IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__GPIO2_5				= IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_CS0__ATA_CS0				= IOMUX_PAD(0x6c4, 0x260, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__CSPI1_SS3				= IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__IPU_DISPB_CS1				= IOMUX_PAD(0x6c4, 0x260, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__GPIO2_6				= IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__IPU_DIAGB_0				= IOMUX_PAD(0x6c4, 0x260, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0		= IOMUX_PAD(0x6c4, 0x260, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_CS1__ATA_CS1				= IOMUX_PAD(0x6c8, 0x264, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__IPU_DISPB_CS2				= IOMUX_PAD(0x6c8, 0x264, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__CSPI2_SS0				= IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__GPIO2_7				= IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__IPU_DIAGB_1				= IOMUX_PAD(0x6c8, 0x264, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1		= IOMUX_PAD(0x6c8, 0x264, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DIOR__ATA_DIOR				= IOMUX_PAD(0x6cc, 0x268, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__ESDHC3_DAT0				= IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR			= IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__IPU_DISPB_BE0			= IOMUX_PAD(0x6cc, 0x268, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__CSPI2_SS1				= IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__GPIO2_8				= IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__IPU_DIAGB_2				= IOMUX_PAD(0x6cc, 0x268, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2		= IOMUX_PAD(0x6cc, 0x268, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DIOW__ATA_DIOW				= IOMUX_PAD(0x6d0, 0x26c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__ESDHC3_DAT1				= IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP			= IOMUX_PAD(0x6d0, 0x26c, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__IPU_DISPB_BE1			= IOMUX_PAD(0x6d0, 0x26c, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__CSPI2_MOSI				= IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__GPIO2_9				= IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__IPU_DIAGB_3				= IOMUX_PAD(0x6d0, 0x26c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3		= IOMUX_PAD(0x6d0, 0x26c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DMACK__ATA_DMACK				= IOMUX_PAD(0x6d4, 0x270, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__ESDHC3_DAT2				= IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT			= IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__CSPI2_MISO				= IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__GPIO2_10				= IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__IPU_DIAGB_4				= IOMUX_PAD(0x6d4, 0x270, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0		= IOMUX_PAD(0x6d4, 0x270, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_RESET_B__ATA_RESET_B			= IOMUX_PAD(0x6d8, 0x274, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__ESDHC3_DAT3			= IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0		= IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O			= IOMUX_PAD(0x6d8, 0x274, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__CSPI2_RDY				= IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__GPIO2_11				= IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__IPU_DIAGB_5			= IOMUX_PAD(0x6d8, 0x274, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1		= IOMUX_PAD(0x6d8, 0x274, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_IORDY__ATA_IORDY				= IOMUX_PAD(0x6dc, 0x278, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__ESDHC3_DAT4				= IOMUX_PAD(0x6dc, 0x278, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1		= IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO			= IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__ESDHC2_DAT4				= IOMUX_PAD(0x6dc, 0x278, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__GPIO2_12				= IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__IPU_DIAGB_6				= IOMUX_PAD(0x6dc, 0x278, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2		= IOMUX_PAD(0x6dc, 0x278, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA0__ATA_DATA_0				= IOMUX_PAD(0x6e0, 0x27c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__ESDHC3_DAT5				= IOMUX_PAD(0x6e0, 0x27c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2		= IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__ESDHC2_DAT5				= IOMUX_PAD(0x6e0, 0x27c, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__GPIO2_13				= IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__IPU_DIAGB_7				= IOMUX_PAD(0x6e0, 0x27c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3		= IOMUX_PAD(0x6e0, 0x27c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA1__ATA_DATA_1				= IOMUX_PAD(0x6e4, 0x280, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__ESDHC3_DAT6				= IOMUX_PAD(0x6e4, 0x280, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3		= IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK			= IOMUX_PAD(0x6e4, 0x280, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__ESDHC2_DAT6				= IOMUX_PAD(0x6e4, 0x280, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__GPIO2_14				= IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__IPU_DIAGB_8				= IOMUX_PAD(0x6e4, 0x280, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27			= IOMUX_PAD(0x6e4, 0x280, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA2__ATA_DATA_2				= IOMUX_PAD(0x6e8, 0x284, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__ESDHC3_DAT7				= IOMUX_PAD(0x6e8, 0x284, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4		= IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS			= IOMUX_PAD(0x6e8, 0x284, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__ESDHC2_DAT7				= IOMUX_PAD(0x6e8, 0x284, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__GPIO2_15				= IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__IPU_DIAGB_9				= IOMUX_PAD(0x6e8, 0x284, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28			= IOMUX_PAD(0x6e8, 0x284, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA3__ATA_DATA_3				= IOMUX_PAD(0x6ec, 0x288, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__ESDHC3_CLK				= IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5		= IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__CSPI2_SCLK				= IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__GPIO2_16				= IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__IPU_DIAGB_10			= IOMUX_PAD(0x6ec, 0x288, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29			= IOMUX_PAD(0x6ec, 0x288, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA4__ATA_DATA_4				= IOMUX_PAD(0x6f0, 0x28c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__ESDHC3_CMD				= IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6		= IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__GPIO2_17				= IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__IPU_DIAGB_11			= IOMUX_PAD(0x6f0, 0x28c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30			= IOMUX_PAD(0x6f0, 0x28c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA5__ATA_DATA_5				= IOMUX_PAD(0x6f4, 0x290, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7		= IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA5__GPIO2_18				= IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA5__IPU_DIAGB_12			= IOMUX_PAD(0x6f4, 0x290, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31			= IOMUX_PAD(0x6f4, 0x290, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA6__ATA_DATA_6				= IOMUX_PAD(0x6f8, 0x294, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__CAN1_TXCAN				= IOMUX_PAD(0x6f8, 0x294, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__UART1_DTR				= IOMUX_PAD(0x6f8, 0x294, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD			= IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__GPIO2_19				= IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__IPU_DIAGB_13			= IOMUX_PAD(0x6f8, 0x294, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA7__ATA_DATA_7				= IOMUX_PAD(0x6fc, 0x298, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__CAN1_RXCAN				= IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__UART1_DSR				= IOMUX_PAD(0x6fc, 0x298, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD			= IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__GPIO2_20				= IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__IPU_DIAGB_14			= IOMUX_PAD(0x6fc, 0x298, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA8__ATA_DATA_8				= IOMUX_PAD(0x700, 0x29c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__UART3_RTS				= IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__UART1_RI				= IOMUX_PAD(0x700, 0x29c, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC			= IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__GPIO2_21				= IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__IPU_DIAGB_15			= IOMUX_PAD(0x700, 0x29c, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA9__ATA_DATA_9				= IOMUX_PAD(0x704, 0x2a0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__UART3_CTS				= IOMUX_PAD(0x704, 0x2a0, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__UART1_DCD				= IOMUX_PAD(0x704, 0x2a0, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS			= IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__GPIO2_22				= IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__IPU_DIAGB_16			= IOMUX_PAD(0x704, 0x2a0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA10__ATA_DATA_10			= IOMUX_PAD(0x708, 0x2a4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA10__UART3_RXD_MUX			= IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC			= IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA10__GPIO2_23				= IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA10__IPU_DIAGB_17			= IOMUX_PAD(0x708, 0x2a4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA11__ATA_DATA_11			= IOMUX_PAD(0x70c, 0x2a8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA11__UART3_TXD_MUX			= IOMUX_PAD(0x70c, 0x2a8, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS			= IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA11__GPIO2_24				= IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA11__IPU_DIAGB_18			= IOMUX_PAD(0x70c, 0x2a8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA12__ATA_DATA_12			= IOMUX_PAD(0x710, 0x2ac, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA12__I2C3_SCL				= IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA12__GPIO2_25				= IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA12__IPU_DIAGB_19			= IOMUX_PAD(0x710, 0x2ac, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA13__ATA_DATA_13			= IOMUX_PAD(0x714, 0x2b0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA13__I2C3_SDA				= IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA13__GPIO2_26				= IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA13__IPU_DIAGB_20			= IOMUX_PAD(0x714, 0x2b0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA14__ATA_DATA_14			= IOMUX_PAD(0x718, 0x2b4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA14__IPU_CSI_D_0			= IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA14__KPP_ROW_0				= IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA14__GPIO2_27				= IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA14__IPU_DIAGB_21			= IOMUX_PAD(0x718, 0x2b4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA15__ATA_DATA_15			= IOMUX_PAD(0x71c, 0x2b8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA15__IPU_CSI_D_1			= IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA15__KPP_ROW_1				= IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA15__GPIO2_28				= IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA15__IPU_DIAGB_22			= IOMUX_PAD(0x71c, 0x2b8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_INTRQ__ATA_INTRQ				= IOMUX_PAD(0x720, 0x2bc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_INTRQ__IPU_CSI_D_2				= IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_INTRQ__KPP_ROW_2				= IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_INTRQ__GPIO2_29				= IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_INTRQ__IPU_DIAGB_23			= IOMUX_PAD(0x720, 0x2bc, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN			= IOMUX_PAD(0x724, 0x2c0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3			= IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_BUFF_EN__KPP_ROW_3				= IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_BUFF_EN__GPIO2_30				= IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24			= IOMUX_PAD(0x724, 0x2c0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DMARQ__ATA_DMARQ				= IOMUX_PAD(0x728, 0x2c4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__IPU_CSI_D_4				= IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__KPP_COL_0				= IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__GPIO2_31				= IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__IPU_DIAGB_25			= IOMUX_PAD(0x728, 0x2c4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4			= IOMUX_PAD(0x728, 0x2c4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DA0__ATA_DA_0				= IOMUX_PAD(0x72c, 0x2c8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__IPU_CSI_D_5				= IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__KPP_COL_1				= IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__GPIO3_0				= IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__IPU_DIAGB_26				= IOMUX_PAD(0x72c, 0x2c8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5			= IOMUX_PAD(0x72c, 0x2c8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DA1__ATA_DA_1				= IOMUX_PAD(0x730, 0x2cc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__IPU_CSI_D_6				= IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__KPP_COL_2				= IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__GPIO3_1				= IOMUX_PAD(0x730, 0x2cc, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__IPU_DIAGB_27				= IOMUX_PAD(0x730, 0x2cc, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6			= IOMUX_PAD(0x730, 0x2cc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DA2__ATA_DA_2				= IOMUX_PAD(0x734, 0x2d0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__IPU_CSI_D_7				= IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__KPP_COL_3				= IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__GPIO3_2				= IOMUX_PAD(0x734, 0x2d0, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__IPU_DIAGB_28				= IOMUX_PAD(0x734, 0x2d0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7			= IOMUX_PAD(0x734, 0x2d0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_MLB_CLK__MLB_MLBCLK				= IOMUX_PAD(0x738, 0x2d4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_MLB_CLK__GPIO3_3				= IOMUX_PAD(0x738, 0x2d4, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_MLB_DAT__MLB_MLBDAT				= IOMUX_PAD(0x73c, 0x2d8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_MLB_DAT__GPIO3_4				= IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL),
+
+	MX35_PAD_MLB_SIG__MLB_MLBSIG				= IOMUX_PAD(0x740, 0x2dc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_MLB_SIG__GPIO3_5				= IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK				= IOMUX_PAD(0x744, 0x2e0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4			= IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX			= IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR			= IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__CSPI2_MOSI				= IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__GPIO3_6				= IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC		= IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0		= IOMUX_PAD(0x744, 0x2e0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK				= IOMUX_PAD(0x748, 0x2e4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5			= IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX			= IOMUX_PAD(0x748, 0x2e4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP			= IOMUX_PAD(0x748, 0x2e4, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__CSPI2_MISO				= IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__GPIO3_7				= IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I			= IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1		= IOMUX_PAD(0x748, 0x2e4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RX_DV__FEC_RX_DV				= IOMUX_PAD(0x74c, 0x2e8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__ESDHC1_DAT6				= IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__UART3_RTS				= IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT			= IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__CSPI2_SCLK				= IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__GPIO3_8				= IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK			= IOMUX_PAD(0x74c, 0x2e8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2		= IOMUX_PAD(0x74c, 0x2e8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_COL__FEC_COL				= IOMUX_PAD(0x750, 0x2ec, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__ESDHC1_DAT7				= IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__UART3_CTS				= IOMUX_PAD(0x750, 0x2ec, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0			= IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__CSPI2_RDY				= IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__GPIO3_9				= IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__IPU_DISPB_SER_RS			= IOMUX_PAD(0x750, 0x2ec, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3			= IOMUX_PAD(0x750, 0x2ec, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RDATA0__FEC_RDATA_0			= IOMUX_PAD(0x754, 0x2f0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__PWM_PWMO				= IOMUX_PAD(0x754, 0x2f0, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__UART3_DTR				= IOMUX_PAD(0x754, 0x2f0, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1		= IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__CSPI2_SS0				= IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__GPIO3_10				= IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1			= IOMUX_PAD(0x754, 0x2f0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4		= IOMUX_PAD(0x754, 0x2f0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TDATA0__FEC_TDATA_0			= IOMUX_PAD(0x758, 0x2f4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1			= IOMUX_PAD(0x758, 0x2f4, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__UART3_DSR				= IOMUX_PAD(0x758, 0x2f4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2		= IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__CSPI2_SS1				= IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__GPIO3_11				= IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0			= IOMUX_PAD(0x758, 0x2f4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5		= IOMUX_PAD(0x758, 0x2f4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TX_EN__FEC_TX_EN				= IOMUX_PAD(0x75c, 0x2f8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1			= IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__UART3_RI				= IOMUX_PAD(0x75c, 0x2f8, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3		= IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__GPIO3_12				= IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS			= IOMUX_PAD(0x75c, 0x2f8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6		= IOMUX_PAD(0x75c, 0x2f8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_MDC__FEC_MDC				= IOMUX_PAD(0x760, 0x2fc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__CAN2_TXCAN				= IOMUX_PAD(0x760, 0x2fc, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__UART3_DCD				= IOMUX_PAD(0x760, 0x2fc, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4			= IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__GPIO3_13				= IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__IPU_DISPB_WR				= IOMUX_PAD(0x760, 0x2fc, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7			= IOMUX_PAD(0x760, 0x2fc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_MDIO__FEC_MDIO				= IOMUX_PAD(0x764, 0x300, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__CAN2_RXCAN				= IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5			= IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__GPIO3_14				= IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__IPU_DISPB_RD				= IOMUX_PAD(0x764, 0x300, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8			= IOMUX_PAD(0x764, 0x300, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR				= IOMUX_PAD(0x768, 0x304, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__OWIRE_LINE				= IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6		= IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__GPIO3_15				= IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC			= IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9		= IOMUX_PAD(0x768, 0x304, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR				= IOMUX_PAD(0x76c, 0x308, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0			= IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7		= IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__KPP_COL_4				= IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__GPIO3_16				= IOMUX_PAD(0x76c, 0x308, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO			= IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_CRS__FEC_CRS				= IOMUX_PAD(0x770, 0x30c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__IPU_CSI_D_1				= IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR			= IOMUX_PAD(0x770, 0x30c, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__KPP_COL_5				= IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__GPIO3_17				= IOMUX_PAD(0x770, 0x30c, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__IPU_FLASH_STROBE			= IOMUX_PAD(0x770, 0x30c, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RDATA1__FEC_RDATA_1			= IOMUX_PAD(0x774, 0x310, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__IPU_CSI_D_2			= IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC			= IOMUX_PAD(0x774, 0x310, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC			= IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__KPP_COL_6				= IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__GPIO3_18				= IOMUX_PAD(0x774, 0x310, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0			= IOMUX_PAD(0x774, 0x310, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TDATA1__FEC_TDATA_1			= IOMUX_PAD(0x778, 0x314, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__IPU_CSI_D_3			= IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS			= IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__KPP_COL_7				= IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__GPIO3_19				= IOMUX_PAD(0x778, 0x314, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1			= IOMUX_PAD(0x778, 0x314, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RDATA2__FEC_RDATA_2			= IOMUX_PAD(0x77c, 0x318, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA2__IPU_CSI_D_4			= IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD			= IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA2__KPP_ROW_4				= IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA2__GPIO3_20				= IOMUX_PAD(0x77c, 0x318, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TDATA2__FEC_TDATA_2			= IOMUX_PAD(0x780, 0x31c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA2__IPU_CSI_D_5			= IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD			= IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA2__KPP_ROW_5				= IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA2__GPIO3_21				= IOMUX_PAD(0x780, 0x31c, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RDATA3__FEC_RDATA_3			= IOMUX_PAD(0x784, 0x320, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA3__IPU_CSI_D_6			= IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC			= IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA3__KPP_ROW_6				= IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA3__GPIO3_22				= IOMUX_PAD(0x784, 0x320, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TDATA3__FEC_TDATA_3			= IOMUX_PAD(0x788, 0x324, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA3__IPU_CSI_D_7			= IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS			= IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA3__KPP_ROW_7				= IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA3__GPIO3_23				= IOMUX_PAD(0x788, 0x324, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK			= IOMUX_PAD(0x78c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TEST_MODE__TCU_TEST_MODE			= IOMUX_PAD(0x790, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX35_H__ */
diff --git a/arch/arm/include/asm/arch-mx35/iomux.h b/arch/arm/include/asm/arch-mx35/iomux.h
deleted file mode 100644
index 52c15bc..0000000
--- a/arch/arm/include/asm/arch-mx35/iomux.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MACH_MX35_IOMUX_H__
-#define __MACH_MX35_IOMUX_H__
-
-#include <asm/arch/imx-regs.h>
-
-/*
- * various IOMUX functions
- */
-typedef enum iomux_pin_config {
-	MUX_CONFIG_FUNC = 0,	/* used as function */
-	MUX_CONFIG_ALT1,	/* used as alternate function 1 */
-	MUX_CONFIG_ALT2,	/* used as alternate function 2 */
-	MUX_CONFIG_ALT3,	/* used as alternate function 3 */
-	MUX_CONFIG_ALT4,	/* used as alternate function 4 */
-	MUX_CONFIG_ALT5,	/* used as alternate function 5 */
-	MUX_CONFIG_ALT6,	/* used as alternate function 6 */
-	MUX_CONFIG_ALT7,	/* used as alternate function 7 */
-	MUX_CONFIG_SION = 0x1 << 4,	/* used as LOOPBACK:MUX SION bit */
-	MUX_CONFIG_GPIO = MUX_CONFIG_ALT5,	/* used as GPIO */
-} iomux_pin_cfg_t;
-
-/*
- * various IOMUX pad functions
- */
-typedef enum iomux_pad_config {
-	PAD_CTL_DRV_3_3V = 0x0 << 13,
-	PAD_CTL_DRV_1_8V = 0x1 << 13,
-	PAD_CTL_HYS_CMOS = 0x0 << 8,
-	PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
-	PAD_CTL_PKE_NONE = 0x0 << 7,
-	PAD_CTL_PKE_ENABLE = 0x1 << 7,
-	PAD_CTL_PUE_KEEPER = 0x0 << 6,
-	PAD_CTL_PUE_PUD = 0x1 << 6,
-	PAD_CTL_100K_PD = 0x0 << 4,
-	PAD_CTL_47K_PU = 0x1 << 4,
-	PAD_CTL_100K_PU = 0x2 << 4,
-	PAD_CTL_22K_PU = 0x3 << 4,
-	PAD_CTL_ODE_CMOS = 0x0 << 3,
-	PAD_CTL_ODE_OpenDrain = 0x1 << 3,
-	PAD_CTL_DRV_NORMAL = 0x0 << 1,
-	PAD_CTL_DRV_HIGH = 0x1 << 1,
-	PAD_CTL_DRV_MAX = 0x2 << 1,
-	PAD_CTL_SRE_SLOW = 0x0 << 0,
-	PAD_CTL_SRE_FAST = 0x1 << 0
-} iomux_pad_config_t;
-
-/*
- * various IOMUX general purpose functions
- */
-typedef enum iomux_gp_func {
-	MUX_SDCTL_CSD0_SEL = 0x1 << 0,
-	MUX_SDCTL_CSD1_SEL = 0x1 << 1,
-	MUX_TAMPER_DETECT_EN = 0x1 << 2,
-} iomux_gp_func_t;
-
-/*
- * various IOMUX input select register index
- */
-typedef enum iomux_input_select {
-	MUX_IN_AMX_P5_RXCLK = 0,
-	MUX_IN_AMX_P5_RXFS,
-	MUX_IN_AMX_P6_DA,
-	MUX_IN_AMX_P6_DB,
-	MUX_IN_AMX_P6_RXCLK,
-	MUX_IN_AMX_P6_RXFS,
-	MUX_IN_AMX_P6_TXCLK,
-	MUX_IN_AMX_P6_TXFS,
-	MUX_IN_CAN1_CANRX,
-	MUX_IN_CAN2_CANRX,
-	MUX_IN_CCM_32K_MUXED,
-	MUX_IN_CCM_PMIC_RDY,
-	MUX_IN_CSPI1_SS2_B,
-	MUX_IN_CSPI1_SS3_B,
-	MUX_IN_CSPI2_CLK_IN,
-	MUX_IN_CSPI2_DATAREADY_B,
-	MUX_IN_CSPI2_MISO,
-	MUX_IN_CSPI2_MOSI,
-	MUX_IN_CSPI2_SS0_B,
-	MUX_IN_CSPI2_SS1_B,
-	MUX_IN_CSPI2_SS2_B,
-	MUX_IN_CSPI2_SS3_B,
-	MUX_IN_EMI_WEIM_DTACK_B,
-	MUX_IN_ESDHC1_DAT4_IN,
-	MUX_IN_ESDHC1_DAT5_IN,
-	MUX_IN_ESDHC1_DAT6_IN,
-	MUX_IN_ESDHC1_DAT7_IN,
-	MUX_IN_ESDHC3_CARD_CLK_IN,
-	MUX_IN_ESDHC3_CMD_IN,
-	MUX_IN_ESDHC3_DAT0,
-	MUX_IN_ESDHC3_DAT1,
-	MUX_IN_ESDHC3_DAT2,
-	MUX_IN_ESDHC3_DAT3,
-	MUX_IN_GPIO1_IN_0,
-	MUX_IN_GPIO1_IN_10,
-	MUX_IN_GPIO1_IN_11,
-	MUX_IN_GPIO1_IN_1,
-	MUX_IN_GPIO1_IN_20,
-	MUX_IN_GPIO1_IN_21,
-	MUX_IN_GPIO1_IN_22,
-	MUX_IN_GPIO1_IN_2,
-	MUX_IN_GPIO1_IN_3,
-	MUX_IN_GPIO1_IN_4,
-	MUX_IN_GPIO1_IN_5,
-	MUX_IN_GPIO1_IN_6,
-	MUX_IN_GPIO1_IN_7,
-	MUX_IN_GPIO1_IN_8,
-	MUX_IN_GPIO1_IN_9,
-	MUX_IN_GPIO2_IN_0,
-	MUX_IN_GPIO2_IN_10,
-	MUX_IN_GPIO2_IN_11,
-	MUX_IN_GPIO2_IN_12,
-	MUX_IN_GPIO2_IN_13,
-	MUX_IN_GPIO2_IN_14,
-	MUX_IN_GPIO2_IN_15,
-	MUX_IN_GPIO2_IN_16,
-	MUX_IN_GPIO2_IN_17,
-	MUX_IN_GPIO2_IN_18,
-	MUX_IN_GPIO2_IN_19,
-	MUX_IN_GPIO2_IN_20,
-	MUX_IN_GPIO2_IN_21,
-	MUX_IN_GPIO2_IN_22,
-	MUX_IN_GPIO2_IN_23,
-	MUX_IN_GPIO2_IN_24,
-	MUX_IN_GPIO2_IN_25,
-	MUX_IN_GPIO2_IN_26,
-	MUX_IN_GPIO2_IN_27,
-	MUX_IN_GPIO2_IN_28,
-	MUX_IN_GPIO2_IN_29,
-	MUX_IN_GPIO2_IN_2,
-	MUX_IN_GPIO2_IN_30,
-	MUX_IN_GPIO2_IN_31,
-	MUX_IN_GPIO2_IN_3,
-	MUX_IN_GPIO2_IN_4,
-	MUX_IN_GPIO2_IN_5,
-	MUX_IN_GPIO2_IN_6,
-	MUX_IN_GPIO2_IN_7,
-	MUX_IN_GPIO2_IN_8,
-	MUX_IN_GPIO2_IN_9,
-	MUX_IN_GPIO3_IN_0,
-	MUX_IN_GPIO3_IN_10,
-	MUX_IN_GPIO3_IN_11,
-	MUX_IN_GPIO3_IN_12,
-	MUX_IN_GPIO3_IN_13,
-	MUX_IN_GPIO3_IN_14,
-	MUX_IN_GPIO3_IN_15,
-	MUX_IN_GPIO3_IN_4,
-	MUX_IN_GPIO3_IN_5,
-	MUX_IN_GPIO3_IN_6,
-	MUX_IN_GPIO3_IN_7,
-	MUX_IN_GPIO3_IN_8,
-	MUX_IN_GPIO3_IN_9,
-	MUX_IN_I2C3_SCL_IN,
-	MUX_IN_I2C3_SDA_IN,
-	MUX_IN_IPU_DISPB_D0_VSYNC,
-	MUX_IN_IPU_DISPB_D12_VSYNC,
-	MUX_IN_IPU_DISPB_SD_D,
-	MUX_IN_IPU_SENSB_DATA_0,
-	MUX_IN_IPU_SENSB_DATA_1,
-	MUX_IN_IPU_SENSB_DATA_2,
-	MUX_IN_IPU_SENSB_DATA_3,
-	MUX_IN_IPU_SENSB_DATA_4,
-	MUX_IN_IPU_SENSB_DATA_5,
-	MUX_IN_IPU_SENSB_DATA_6,
-	MUX_IN_IPU_SENSB_DATA_7,
-	MUX_IN_KPP_COL_0,
-	MUX_IN_KPP_COL_1,
-	MUX_IN_KPP_COL_2,
-	MUX_IN_KPP_COL_3,
-	MUX_IN_KPP_COL_4,
-	MUX_IN_KPP_COL_5,
-	MUX_IN_KPP_COL_6,
-	MUX_IN_KPP_COL_7,
-	MUX_IN_KPP_ROW_0,
-	MUX_IN_KPP_ROW_1,
-	MUX_IN_KPP_ROW_2,
-	MUX_IN_KPP_ROW_3,
-	MUX_IN_KPP_ROW_4,
-	MUX_IN_KPP_ROW_5,
-	MUX_IN_KPP_ROW_6,
-	MUX_IN_KPP_ROW_7,
-	MUX_IN_OWIRE_BATTERY_LINE,
-	MUX_IN_SPDIF_HCKT_CLK2,
-	MUX_IN_SPDIF_SPDIF_IN1,
-	MUX_IN_UART3_UART_RTS_B,
-	MUX_IN_UART3_UART_RXD_MUX,
-	MUX_IN_USB_OTG_DATA_0,
-	MUX_IN_USB_OTG_DATA_1,
-	MUX_IN_USB_OTG_DATA_2,
-	MUX_IN_USB_OTG_DATA_3,
-	MUX_IN_USB_OTG_DATA_4,
-	MUX_IN_USB_OTG_DATA_5,
-	MUX_IN_USB_OTG_DATA_6,
-	MUX_IN_USB_OTG_DATA_7,
-	MUX_IN_USB_OTG_DIR,
-	MUX_IN_USB_OTG_NXT,
-	MUX_IN_USB_UH2_DATA_0,
-	MUX_IN_USB_UH2_DATA_1,
-	MUX_IN_USB_UH2_DATA_2,
-	MUX_IN_USB_UH2_DATA_3,
-	MUX_IN_USB_UH2_DATA_4,
-	MUX_IN_USB_UH2_DATA_5,
-	MUX_IN_USB_UH2_DATA_6,
-	MUX_IN_USB_UH2_DATA_7,
-	MUX_IN_USB_UH2_DIR,
-	MUX_IN_USB_UH2_NXT,
-	MUX_IN_USB_UH2_USB_OC,
-} iomux_input_select_t;
-
-/*
- * various IOMUX input functions
- */
-typedef enum iomux_input_config {
-	INPUT_CTL_PATH0 = 0x0,
-	INPUT_CTL_PATH1,
-	INPUT_CTL_PATH2,
-	INPUT_CTL_PATH3,
-	INPUT_CTL_PATH4,
-	INPUT_CTL_PATH5,
-	INPUT_CTL_PATH6,
-	INPUT_CTL_PATH7,
-} iomux_input_cfg_t;
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param  pin		a name defined by iomux_pin_name_t
- * @param  cfg		an input function as defined in iomux_pin_cfg_t
- *
- * @return		0 if successful; Non-zero otherwise
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
-
-/*
- * Release ownership for an IO pin
- *
- * @param  pin		a name defined by iomux_pin_name_t
- * @param  cfg		an input function as defined in iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
-
-/*
- * This function enables/disables the general purpose function for a particular
- * signal.
- *
- * @param  gp   one signal as defined in iomux_gp_func_t
- * @param  en   1 to enable; 0 to disable
- */
-void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en);
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param  pin          a pin number as defined in iomux_pin_name_t
- * @param  config       the ORed value of elements defined in
- *				iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-
-/*
- * This function configures input path.
- *
- * @param  input        index of input select register as defined in
- *				iomux_input_select_t
- * @param  config       the binary value of elements defined in
- *				iomux_input_cfg_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-#endif
diff --git a/arch/arm/include/asm/arch-mx35/mx35_pins.h b/arch/arm/include/asm/arch-mx35/mx35_pins.h
deleted file mode 100644
index 00e5e75..0000000
--- a/arch/arm/include/asm/arch-mx35/mx35_pins.h
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MXC_MX35_PINS_H__
-#define __ASM_ARCH_MXC_MX35_PINS_H__
-
-/*!
- * @file arch-mxc/mx35_pins.h
- *
- * @brief MX35 I/O Pin List
- *
- * @ingroup GPIO_MX35
- */
-
-#ifndef __ASSEMBLY__
-
-/*!
- * @name IOMUX/PAD Bit field definitions
- */
-
-/*! @{ */
-
-/*!
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P  |  IO_I   | RSVD  | PAD_I | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 7 contains MUX_I used to identify the register
- * offset (base is IOMUX_module_base ) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field
- * definitions are used for the pad control register.the MX35_PIN_A0 is
- * defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I)
- * So the absolute address is: IOMUX_module_base + 0x28.
- * The pad control register offset is: 0x368.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I		0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I		10
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * reserved filed
- */
-#define RSVD_I		21
-
-#define MUX_IO_P                29
-#define MUX_IO_I                24
-#define IOMUX_TO_GPIO(pin)      ((((unsigned int)pin >> MUX_IO_P) * \
-					GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
-					((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-#define IOMUX_TO_IRQ(pin)       (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-
-#define NON_GPIO_I	0x7
-#define PIN_TO_MUX_MASK	((1<<(PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK	((1<<(RSVD_I - PAD_I)) - 1)
-#define NON_MUX_I	PIN_TO_MUX_MASK
-
-#define _MXC_BUILD_PIN(gp, gi, mi, pi) \
-		(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
-		((mi) << MUX_I) | ((pi) << PAD_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \
-		_MXC_BUILD_PIN(gp, gi, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
-		_MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
-
-/*! @} End IOMUX/PAD Bit field definitions */
-
-/*!
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-typedef enum iomux_pins {
-	MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328),
-	MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C),
-	MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330),
-	MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334),
-	MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338),
-	MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C),
-	MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340),
-	MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C),
-
-	MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360),
-	MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364),
-	MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368),
-	MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C),
-	MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370),
-	MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374),
-	MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378),
-	MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C),
-	MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380),
-	MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384),
-	MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388),
-	MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C),
-	MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390),
-	MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394),
-	MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398),
-	MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C),
-	MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0),
-	MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4),
-	MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8),
-	MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC),
-	MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0),
-	MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4),
-	MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8),
-	MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC),
-	MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0),
-	MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4),
-	MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8),
-	MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC),
-	MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0),
-
-	MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C),
-	MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470),
-	MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474),
-	MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478),
-	MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C),
-	MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480),
-	MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484),
-	MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488),
-	MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C),
-	MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490),
-
-	MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498),
-	MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C),
-	MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0),
-
-	MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC),
-	MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0),
-	MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4),
-	MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8),
-	MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC),
-	MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0),
-
-	MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4),
-	MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8),
-	MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC),
-	MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0),
-	MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4),
-	MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8),
-	MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC),
-	MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500),
-	MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504),
-	MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508),
-	MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C),
-	MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510),
-	MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514),
-	MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518),
-	MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C),
-	MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520),
-
-	MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524),
-	MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528),
-	MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C),
-	MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530),
-	MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534),
-	MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538),
-	MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C),
-	MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540),
-	MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544),
-	MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548),
-	MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C),
-	MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550),
-
-	MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554),
-	MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558),
-	MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C),
-	MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560),
-
-	MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564),
-	MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568),
-	MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C),
-	MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570),
-	MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574),
-	MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578),
-	MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C),
-	MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580),
-
-	MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584),
-	MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588),
-	MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C),
-	MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590),
-	MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594),
-	MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598),
-	MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C),
-	MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0),
-	MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4),
-	MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8),
-	MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC),
-	MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0),
-
-	MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4),
-	MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8),
-	MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC),
-	MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0),
-	MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4),
-	MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8),
-
-	MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC),
-	MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0),
-	MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4),
-	MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8),
-	MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC),
-	MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0),
-	MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4),
-	MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8),
-
-	MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C),
-	MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610),
-
-	MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614),
-	MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618),
-	MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C),
-	MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620),
-	MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624),
-	MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628),
-	MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C),
-	MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630),
-	MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634),
-	MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638),
-	MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C),
-	MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640),
-	MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644),
-	MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648),
-	MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C),
-	MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650),
-	MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654),
-	MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658),
-	MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C),
-	MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660),
-	MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664),
-	MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668),
-	MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C),
-	MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670),
-
-	MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674),
-	MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678),
-	MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C),
-	MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680),
-	MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684),
-	MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688),
-	MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C),
-	MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690),
-
-	MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694),
-	MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698),
-	MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C),
-	MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0),
-	MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4),
-	MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8),
-	MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC),
-	MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0),
-	MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4),
-	MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8),
-	MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC),
-	MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0),
-
-	MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4),
-	MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8),
-	MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC),
-	MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0),
-	MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4),
-	MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8),
-	MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC),
-	MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0),
-	MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4),
-	MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8),
-	MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC),
-	MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0),
-	MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4),
-	MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8),
-	MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC),
-	MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700),
-	MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704),
-	MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708),
-	MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C),
-	MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710),
-	MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714),
-	MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718),
-	MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C),
-	MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720),
-	MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724),
-	MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728),
-	MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C),
-	MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730),
-	MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734),
-
-	MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738),
-	MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C),
-	MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740),
-
-	MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744),
-	MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748),
-	MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C),
-	MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750),
-	MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754),
-	MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758),
-	MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C),
-	MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760),
-	MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764),
-	MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768),
-	MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C),
-	MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770),
-	MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774),
-	MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778),
-	MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C),
-	MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780),
-	MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784),
-	MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788),
-} iomux_pin_name_t;
-
-#endif
-#endif
diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
index 9cdfb48..6910192 100644
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -68,5 +68,6 @@
 void enable_usboh3_clk(unsigned char enable);
 void mxc_set_sata_internal_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+void enable_nfc_clk(unsigned char enable);
 
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index a71cc13..8984e42 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -267,6 +267,8 @@
 /* M4IF */
 #define M4IF_FBPM0	0x40
 #define M4IF_FIDBP	0x48
+#define M4IF_GENP_WEIM_MM_MASK		0x00000001
+#define WEIM_GCR2_MUX16_BYP_GRANT_MASK	0x00001000
 
 /* Assuming 24MHz input clock with doubler ON */
 /*                            MFI         PDF */
@@ -499,7 +501,7 @@
 	u32	sdat;
 	u32	prev;
 	u32	srev;
-	u32	preg_p;
+	u32	prg_p;
 	u32	scs0;
 	u32	scs1;
 	u32	scs2;
@@ -508,12 +510,22 @@
 	struct fuse_bank {
 		u32	fuse_regs[0x20];
 		u32	fuse_rsvd[0xe0];
+#if defined(CONFIG_MX51)
 	} bank[4];
+#elif defined(CONFIG_MX53)
+	} bank[5];
+#endif
 };
 
 struct fuse_bank0_regs {
-	u32	fuse0_23[24];
+	u32	fuse0_7[8];
+	u32	uid[8];
+	u32	fuse16_23[8];
+#if defined(CONFIG_MX51)
+	u32	imei[8];
+#elif defined(CONFIG_MX53)
 	u32	gp[8];
+#endif
 };
 
 struct fuse_bank1_regs {
@@ -522,6 +534,14 @@
 	u32	fuse15_31[0x11];
 };
 
+#if defined(CONFIG_MX53)
+struct fuse_bank4_regs {
+	u32	fuse0_4[5];
+	u32	gp[3];
+	u32	fuse8_31[0x18];
+};
+#endif
+
 #endif /* __ASSEMBLER__*/
 
 #endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
index 4f37295..70aaa37 100644
--- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
@@ -21,29 +21,8 @@
 
 #include <asm/imx-common/iomux-v3.h>
 
-#define PAD_CTL_DVS			(1 << 13)
-#define PAD_CTL_INPUT_DDR		(1 << 9)
-#define PAD_CTL_HYS			(1 << 8)
-
-#define PAD_CTL_PKE			(1 << 7)
-#define PAD_CTL_PUE			(1 << 6 | PAD_CTL_PKE)
-#define PAD_CTL_PUS_100K_DOWN		(0 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_47K_UP		(1 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_100K_UP		(2 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_22K_UP		(3 << 4 | PAD_CTL_PUE)
-
-#define PAD_CTL_ODE			(1 << 3)
-
-#define PAD_CTL_DSE_LOW			(0 << 1)
-#define PAD_CTL_DSE_MED			(1 << 1)
-#define PAD_CTL_DSE_HIGH		(2 << 1)
-#define PAD_CTL_DSE_MAX			(3 << 1)
-
-#define PAD_CTL_SRE_FAST		(1 << 0)
-#define PAD_CTL_SRE_SLOW		(0 << 0)
-
 /* Pad control groupings */
-#define MX51_UART_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
+#define MX51_UART_PAD_CTRL	(PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
 				PAD_CTL_HYS | PAD_CTL_SRE_FAST)
 #define MX51_I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
 				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
@@ -51,17 +30,17 @@
 #define MX51_ESDHC_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
 				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
 				PAD_CTL_HYS)
-#define MX51_USBH1_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
-				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
-				PAD_CTL_HYS | PAD_CTL_PUE)
+#define MX51_USBH_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+				PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
 #define MX51_ECSPI_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_HYS | \
 				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
-#define MX51_SDHCI_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
-				PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
+#define MX51_SDHCI_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
 				PAD_CTL_SRE_FAST | PAD_CTL_DVS)
 #define MX51_GPIO_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
 
-#define __NA_ 0x000
+#define MX51_PAD_CTRL_2		(PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_4		(PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_5		(PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 
 /*
  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
@@ -69,26 +48,57 @@
  * See also iomux-v3.h
  */
 
-/*								PAD    MUX   ALT INPSE PATH PADCTRL */
+/*							    PAD    MUX   ALT INPSE PATH PADCTRL */
 enum {
-	MX51_PAD_EIM_D16__USBH2_DATA0		= IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_D17__USBH2_DATA1		= IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_D18__USBH2_DATA2		= IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_D19__USBH2_DATA3		= IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_D20__USBH2_DATA4		= IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_D21__USBH2_DATA5		= IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_D22__USBH2_DATA6		= IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_D23__USBH2_DATA7		= IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_D16__USBH2_DATA0		= IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D17__GPIO2_1		= IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_D17__USBH2_DATA1		= IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D18__USBH2_DATA2		= IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D19__USBH2_DATA3		= IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D20__USBH2_DATA4		= IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D21__GPIO2_5		= IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_D21__USBH2_DATA5		= IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D22__USBH2_DATA6		= IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D23__USBH2_DATA7		= IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D25__UART3_RXD		= IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL),
+	MX51_PAD_EIM_D26__UART3_TXD		= IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL),
 	MX51_PAD_EIM_D27__GPIO2_9		= IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
-	MX51_PAD_EIM_A24__USBH2_CLK		= IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_A25__USBH2_DIR		= IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_A16__GPIO2_10		= IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A17__GPIO2_11		= IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A20__GPIO2_14		= IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A22__GPIO2_16		= IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A24__USBH2_CLK		= IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_A25__USBH2_DIR		= IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
 	MX51_PAD_EIM_A26__GPIO2_20		= IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
-	MX51_PAD_EIM_A26__USBH2_STP		= IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_A27__USBH2_NXT		= IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_A26__USBH2_STP		= IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_A27__USBH2_NXT		= IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_EB2__FEC_MDIO		= IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_HYS),
+	MX51_PAD_EIM_EB3__FEC_RDATA1		= IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_EB3__GPIO2_23		= IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_EIM_CS0__GPIO2_25		= IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
-	MX51_PAD_EIM_CS2__SD1_CD		= IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+	MX51_PAD_EIM_CS2__FEC_RDATA2		= IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_CS2__GPIO2_27		= IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS3__FEC_RDATA3		= IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
 	MX51_PAD_EIM_CS3__GPIO2_28		= IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS4__FEC_RX_ER		= IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
 	MX51_PAD_EIM_CS4__GPIO2_29		= IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS5__FEC_CRS		= IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2),
+	MX51_PAD_DRAM_RAS__DRAM_RAS		= IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_CAS__DRAM_CAS		= IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDWE__DRAM_SDWE		= IOMUX_PAD(0x4ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0	= IOMUX_PAD(0x4b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1	= IOMUX_PAD(0x4b4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDCLK__DRAM_SDCLK		= IOMUX_PAD(0x4b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS0__DRAM_SDQS0		= IOMUX_PAD(0x4bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS1__DRAM_SDQS1		= IOMUX_PAD(0x4c0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS2__DRAM_SDQS2		= IOMUX_PAD(0x4c4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS3__DRAM_SDQS3		= IOMUX_PAD(0x4c8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_CS0__DRAM_CS0		= IOMUX_PAD(0x4cc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_CS1__DRAM_CS1		= IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM0__DRAM_DQM0		= IOMUX_PAD(0x4d4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM1__DRAM_DQM1		= IOMUX_PAD(0x4d8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM2__DRAM_DQM2		= IOMUX_PAD(0x4dc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM3__DRAM_DQM3		= IOMUX_PAD(0x4e0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_WE_B__PATA_DIOW		= IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_RE_B__PATA_DIOR		= IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_ALE__PATA_BUFFER_EN	= IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
@@ -96,19 +106,38 @@
 	MX51_PAD_NANDF_WP_B__PATA_DMACK		= IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_RB0__PATA_DMARQ		= IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_RB1__PATA_IORDY		= IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_RB2__FEC_COL		= IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2),
+	MX51_PAD_NANDF_RB2__GPIO3_10		= IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_NANDF_RB3__FEC_RX_CLK		= IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2),
+	MX51_PAD_NANDF_RB3__GPIO3_11		= IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_GPIO_NAND__PATA_INTRQ		= IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS2__FEC_TX_ER		= IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5),
 	MX51_PAD_NANDF_CS2__PATA_CS_0		= IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS3__FEC_MDC		= IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5),
 	MX51_PAD_NANDF_CS3__PATA_CS_1		= IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS4__FEC_TDATA1		= IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5),
 	MX51_PAD_NANDF_CS4__PATA_DA_0		= IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS5__FEC_TDATA2		= IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5),
 	MX51_PAD_NANDF_CS5__PATA_DA_1		= IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS6__FEC_TDATA3		= IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5),
 	MX51_PAD_NANDF_CS6__PATA_DA_2		= IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS7__FEC_TX_EN		= IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK	= IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4),
+	MX51_PAD_NANDF_D15__GPIO3_25		= IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_NANDF_D15__PATA_DATA15		= IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D14__GPIO3_26		= IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_NANDF_D14__PATA_DATA14		= IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D13__GPIO3_27		= IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_NANDF_D13__PATA_DATA13		= IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_D12__PATA_DATA12		= IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D11__FEC_RX_DV		= IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_D11__PATA_DATA11		= IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D10__GPIO3_30		= IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_NANDF_D10__PATA_DATA10		= IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D9__FEC_RDATA0		= IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4),
+	MX51_PAD_NANDF_D9__GPIO3_31		= IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_NANDF_D9__PATA_DATA9		= IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D8__FEC_TDATA0		= IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5),
 	MX51_PAD_NANDF_D8__PATA_DATA8		= IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_D7__PATA_DATA7		= IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_D6__PATA_DATA6		= IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
@@ -118,34 +147,52 @@
 	MX51_PAD_NANDF_D2__PATA_DATA2		= IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_D1__PATA_DATA1		= IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_D0__PATA_DATA0		= IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_CSI2_D12__GPIO4_9		= IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSI2_D13__GPIO4_10		= IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	= IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
 	MX51_PAD_CSPI1_MISO__ECSPI1_MISO	= IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_CSPI1_SS0__ECSPI1_SS0		= IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
 	MX51_PAD_CSPI1_SS0__GPIO4_24		= IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSPI1_SS1__ECSPI1_SS1		= IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
 	MX51_PAD_CSPI1_SS1__GPIO4_25		= IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSPI1_RDY__ECSPI1_RDY		= IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_CSPI1_RDY__GPIO4_26		= IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	= IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
 	MX51_PAD_UART1_RXD__UART1_RXD		= IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL),
 	MX51_PAD_UART1_TXD__UART1_TXD		= IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
 	MX51_PAD_UART1_RTS__UART1_RTS		= IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL),
 	MX51_PAD_UART1_CTS__UART1_CTS		= IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL),
-	MX51_PAD_USBH1_CLK__USBH1_CLK		= IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DIR__USBH1_DIR		= IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_STP__USBH1_STP		= IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+	MX51_PAD_USBH1_CLK__USBH1_CLK		= IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DIR__USBH1_DIR		= IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
 	MX51_PAD_USBH1_STP__GPIO1_27		= IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL),
-	MX51_PAD_USBH1_NXT__USBH1_NXT		= IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA0__USBH1_DATA0	= IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA1__USBH1_DATA1	= IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA2__USBH1_DATA2	= IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA3__USBH1_DATA3	= IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA4__USBH1_DATA4	= IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA5__USBH1_DATA5	= IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA6__USBH1_DATA6	= IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA7__USBH1_DATA7	= IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+	MX51_PAD_USBH1_STP__USBH1_STP		= IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_NXT__USBH1_NXT		= IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA0__USBH1_DATA0	= IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA1__USBH1_DATA1	= IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA2__USBH1_DATA2	= IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA3__USBH1_DATA3	= IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA4__USBH1_DATA4	= IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA5__USBH1_DATA5	= IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA6__USBH1_DATA6	= IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA7__USBH1_DATA7	= IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_DI1_PIN11__ECSPI1_SS2		= IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_DI1_PIN12__GPIO3_1		= IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_PIN13__GPIO3_2		= IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_D0_CS__GPIO3_3		= IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_D1_CS__GPIO3_4		= IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DISPB2_SER_DIN__GPIO3_5	= IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DISPB2_SER_DIO__GPIO3_6	= IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_PIN3__DI1_PIN3		= IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DI1_PIN2__DI1_PIN2		= IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	= IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DI_GP4__DI2_PIN15		= IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_SD1_CMD__SD1_CMD		= IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
 	MX51_PAD_SD1_CLK__SD1_CLK		= IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
 	MX51_PAD_SD1_DATA0__SD1_DATA0		= IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
 	MX51_PAD_SD1_DATA1__SD1_DATA1		= IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
 	MX51_PAD_SD1_DATA2__SD1_DATA2		= IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
 	MX51_PAD_SD1_DATA3__SD1_DATA3		= IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_GPIO1_0__GPIO1_0		= IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_GPIO1_0__SD1_CD		= IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
 	MX51_PAD_GPIO1_1__SD1_WP		= IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
 	MX51_PAD_SD2_CMD__SD2_CMD		= IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
@@ -154,11 +201,36 @@
 	MX51_PAD_SD2_DATA1__SD2_DATA1		= IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
 	MX51_PAD_SD2_DATA2__SD2_DATA2		= IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
 	MX51_PAD_SD2_DATA3__SD2_DATA3		= IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_GPIO1_2__GPIO1_2		= IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_2__PWM1_PWMO		= IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_GPIO1_3__GPIO1_3		= IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_GPIO1_5__GPIO1_5		= IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_GPIO1_6__GPIO1_6		= IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_7__GPIO1_7		= IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_GPIO1_7__SD2_WP		= IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
 	MX51_PAD_GPIO1_8__SD2_CD		= IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+	MX51_GRP_DDRPKS				= IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B4			= IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_PKEDDR				= IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDR_A0				= IOMUX_PAD(0x83c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDR_A1				= IOMUX_PAD(0x848, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDRAPUS			= IOMUX_PAD(0x84c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR0			= IOMUX_PAD(0x85c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR1			= IOMUX_PAD(0x864, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR2			= IOMUX_PAD(0x86c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR3			= IOMUX_PAD(0x874, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B0			= IOMUX_PAD(0x878, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDRAPKS			= IOMUX_PAD(0x87c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B1			= IOMUX_PAD(0x880, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDRPUS				= IOMUX_PAD(0x884, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B2			= IOMUX_PAD(0x88c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_PKEADDR			= IOMUX_PAD(0x890, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B4			= IOMUX_PAD(0x89c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_INMODE1			= IOMUX_PAD(0x8a0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B0			= IOMUX_PAD(0x8a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B1			= IOMUX_PAD(0x8ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B2			= IOMUX_PAD(0x8b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDR_SR_A1			= IOMUX_PAD(0x8bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
 };
 
 #endif /* __IOMUX_MX51_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx53.h b/arch/arm/include/asm/arch-mx5/iomux-mx53.h
new file mode 100644
index 0000000..f55c0f5
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx5/iomux-mx53.h
@@ -0,0 +1,1232 @@
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on Freescale's Linux i.MX iomux-mx53.h file:
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IOMUX_MX53_H__
+#define __IOMUX_MX53_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Pad control groupings */
+#define MX53_UART_PAD_CTRL	(PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define MX53_SDHC_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
+
+/*
+ * The naming convention for the pad modes is MX53_PAD_<padname>__<padmode>
+ * If <padname> refers to a GPIO, it is named GPIO_<unit>
+ * If <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/*								    PAD    MUX   ALT INPSE PATH PADCTRL */
+enum {
+	MX53_PAD_GPIO_19__KPP_COL_5			= IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__GPIO4_5			= IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__CCM_CLKO			= IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__SPDIF_OUT1			= IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2		= IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__ECSPI1_RDY			= IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__FEC_TDATA_3			= IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__SRC_INT_BOOT			= IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__KPP_COL_0			= IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__GPIO4_6			= IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC		= IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__UART4_TXD_MUX		= IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_COL0__ECSPI1_SCLK			= IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__FEC_RDATA_3			= IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__SRC_ANY_PU_RST		= IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__KPP_ROW_0			= IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__GPIO4_7			= IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD		= IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__UART4_RXD_MUX		= IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__ECSPI1_MOSI			= IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__FEC_TX_ER			= IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__KPP_COL_1			= IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__GPIO4_8			= IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS		= IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__UART5_TXD_MUX		= IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_COL1__ECSPI1_MISO			= IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__FEC_RX_CLK			= IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__USBPHY1_TXREADY		= IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__KPP_ROW_1			= IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__GPIO4_9			= IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD		= IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__UART5_RXD_MUX		= IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__ECSPI1_SS0			= IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__FEC_COL			= IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__USBPHY1_RXVALID		= IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__KPP_COL_2			= IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__GPIO4_10			= IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__CAN1_TXCAN			= IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__FEC_MDIO			= IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__ECSPI1_SS1			= IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__FEC_RDATA_2			= IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE		= IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__KPP_ROW_2			= IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__GPIO4_11			= IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__CAN1_RXCAN			= IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__FEC_MDC			= IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__ECSPI1_SS2			= IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__FEC_TDATA_2			= IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__USBPHY1_RXERROR		= IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__KPP_COL_3			= IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__GPIO4_12			= IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__USBOH3_H2_DP			= IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__SPDIF_IN1			= IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__I2C2_SCL			= IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__ECSPI1_SS3			= IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__FEC_CRS			= IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK		= IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__KPP_ROW_3			= IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__GPIO4_13			= IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__USBOH3_H2_DM			= IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK		= IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__I2C2_SDA			= IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__OSC32K_32K_OUT		= IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__CCM_PLL4_BYP			= IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0		= IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__KPP_COL_4			= IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__GPIO4_14			= IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__CAN2_TXCAN			= IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__IPU_SISG_4			= IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__UART5_RTS			= IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC		= IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1		= IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__KPP_ROW_4			= IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__GPIO4_15			= IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__CAN2_RXCAN			= IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__IPU_SISG_5			= IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__UART5_CTS			= IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR		= IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID		= IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK		= IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__GPIO4_16			= IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR		= IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0	= IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0		= IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID		= IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__IPU_DI0_PIN15		= IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__GPIO4_17			= IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC		= IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1	= IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1		= IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__USBPHY1_BVALID		= IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__IPU_DI0_PIN2			= IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__GPIO4_18			= IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD		= IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2	= IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2		= IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION		= IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__IPU_DI0_PIN3			= IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__GPIO4_19			= IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS		= IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3	= IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3		= IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__USBPHY1_IDDIG		= IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__IPU_DI0_PIN4			= IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__GPIO4_20			= IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD		= IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__ESDHC1_WP			= IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD		= IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4		= IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT	= IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0		= IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__GPIO4_21			= IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__CSPI_SCLK			= IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0	= IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN	= IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5		= IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY		= IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1		= IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__GPIO4_22			= IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__CSPI_MOSI			= IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1	= IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL
+							= IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6		= IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID		= IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2		= IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__GPIO4_23			= IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__CSPI_MISO			= IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2	= IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE		= IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7		= IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE		= IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3		= IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__GPIO4_24			= IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__CSPI_SS0			= IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3	= IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR	= IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8		= IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR		= IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4		= IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__GPIO4_25			= IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__CSPI_SS1			= IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4	= IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB		= IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9		= IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK		= IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5		= IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__GPIO4_26			= IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__CSPI_SS2			= IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5	= IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS	= IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10		= IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0	= IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6		= IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__GPIO4_27			= IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__CSPI_SS3			= IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6	= IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE	= IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11		= IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1	= IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7		= IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__GPIO4_28			= IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__CSPI_RDY			= IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7	= IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0	= IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12		= IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID		= IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8		= IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__GPIO4_29			= IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__PWM1_PWMO			= IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B		= IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1	= IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13		= IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__USBPHY2_AVALID		= IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9		= IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__GPIO4_30			= IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__PWM2_PWMO			= IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B		= IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2	= IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14		= IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0		= IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10		= IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__GPIO4_31			= IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP		= IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3
+							= IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15		= IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1		= IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11		= IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__GPIO5_5			= IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT		= IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4
+							= IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16		= IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2		= IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12		= IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__GPIO5_6			= IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK		= IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5
+							= IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17		= IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3		= IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13		= IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__GPIO5_7			= IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS		= IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0
+							= IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18		= IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4		= IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14		= IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__GPIO5_8			= IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC		= IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1
+							= IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19		= IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5		= IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15		= IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__GPIO5_9			= IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__ECSPI1_SS1		= IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__ECSPI2_SS1		= IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2
+							= IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20		= IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6		= IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16		= IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__GPIO5_10			= IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__ECSPI2_MOSI		= IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC		= IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0		= IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3
+							= IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21		= IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7		= IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17		= IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__GPIO5_11			= IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__ECSPI2_MISO		= IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD		= IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1		= IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4
+							= IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22		= IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18		= IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__GPIO5_12			= IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__ECSPI2_SS0		= IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS		= IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS		= IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5
+							= IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23		= IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2		= IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19		= IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__GPIO5_13			= IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__ECSPI2_SCLK		= IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD		= IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC		= IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6
+							= IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24		= IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3		= IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20		= IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__GPIO5_14			= IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__ECSPI1_SCLK		= IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC		= IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7
+							= IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25		= IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__SATA_PHY_TDI		= IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21		= IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__GPIO5_15			= IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__ECSPI1_MOSI		= IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD		= IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0	= IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26		= IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__SATA_PHY_TDO		= IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22		= IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__GPIO5_16			= IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__ECSPI1_MISO		= IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS		= IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1	= IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27		= IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__SATA_PHY_TCK		= IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23		= IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__GPIO5_17			= IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__ECSPI1_SS0		= IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD		= IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2	= IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28		= IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__SATA_PHY_TMS		= IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK		= IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__GPIO5_18			= IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0		= IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29		= IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC		= IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__GPIO5_19			= IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK		= IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1		= IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30		= IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__TPIU_TRCTL			= IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN		= IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__GPIO5_20			= IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2		= IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31		= IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK		= IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC		= IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__GPIO5_21			= IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3		= IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32		= IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0		= IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4		= IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__GPIO5_22			= IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__KPP_COL_5			= IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__ECSPI1_SCLK			= IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP		= IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC		= IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33		= IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__TPIU_TRACE_1		= IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5		= IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__GPIO5_23			= IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__KPP_ROW_5			= IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__ECSPI1_MOSI			= IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT		= IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD		= IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34		= IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__TPIU_TRACE_2		= IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6		= IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__GPIO5_24			= IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__KPP_COL_6			= IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__ECSPI1_MISO			= IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK		= IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS		= IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35		= IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__TPIU_TRACE_3		= IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7		= IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__GPIO5_25			= IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__KPP_ROW_6			= IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__ECSPI1_SS0			= IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR		= IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD		= IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36		= IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__TPIU_TRACE_4		= IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8		= IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__GPIO5_26			= IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__KPP_COL_7			= IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__ECSPI2_SCLK			= IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC		= IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__I2C1_SDA			= IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37		= IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__TPIU_TRACE_5		= IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9		= IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__GPIO5_27			= IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__KPP_ROW_7			= IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__ECSPI2_MOSI			= IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR		= IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__I2C1_SCL			= IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38		= IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__TPIU_TRACE_6		= IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10		= IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__GPIO5_28			= IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__UART1_TXD_MUX		= IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__ECSPI2_MISO		= IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC		= IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4		= IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39		= IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__TPIU_TRACE_7		= IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11		= IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__GPIO5_29			= IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__UART1_RXD_MUX		= IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__ECSPI2_SS0			= IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS		= IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5		= IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40		= IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__TPIU_TRACE_8		= IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12		= IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__GPIO5_30			= IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__UART4_TXD_MUX		= IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0	= IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6		= IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41		= IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__TPIU_TRACE_9		= IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13		= IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__GPIO5_31			= IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__UART4_RXD_MUX		= IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1	= IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7		= IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42		= IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__TPIU_TRACE_10		= IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14		= IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__GPIO6_0			= IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__UART5_TXD_MUX		= IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2	= IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8		= IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43		= IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__TPIU_TRACE_11		= IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15		= IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__GPIO6_1			= IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__UART5_RXD_MUX		= IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3	= IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9		= IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44		= IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__TPIU_TRACE_12		= IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16		= IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__GPIO6_2			= IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__UART4_RTS			= IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4	= IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10		= IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45		= IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__TPIU_TRACE_13		= IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17		= IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__GPIO6_3			= IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__UART4_CTS			= IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5	= IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11		= IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46		= IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__TPIU_TRACE_14		= IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18		= IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__GPIO6_4			= IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__UART5_RTS			= IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6	= IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12		= IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47		= IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__TPIU_TRACE_15		= IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19		= IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__GPIO6_5			= IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__UART5_CTS			= IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7	= IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13		= IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48		= IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK		= IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__EMI_WEIM_A_25			= IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__GPIO5_2			= IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__ECSPI2_RDY			= IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__IPU_DI1_PIN12			= IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__CSPI_SS1			= IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__IPU_DI0_D1_CS			= IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__USBPHY1_BISTOK		= IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__EMI_WEIM_EB_2			= IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__GPIO2_30			= IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK		= IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS		= IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__ECSPI1_SS0			= IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__I2C2_SCL			= IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__EMI_WEIM_D_16			= IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__GPIO3_16			= IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__IPU_DI0_PIN5			= IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK		= IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__ECSPI1_SCLK			= IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__I2C2_SDA			= IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__EMI_WEIM_D_17			= IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__GPIO3_17			= IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__IPU_DI0_PIN6			= IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN		= IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__ECSPI1_MISO			= IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__I2C3_SCL			= IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__EMI_WEIM_D_18			= IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__GPIO3_18			= IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__IPU_DI0_PIN7			= IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO		= IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__ECSPI1_MOSI			= IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__I2C3_SDA			= IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__IPU_DI1_D0_CS			= IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__EMI_WEIM_D_19			= IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__GPIO3_19			= IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__IPU_DI0_PIN8			= IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS		= IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__ECSPI1_SS1			= IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__EPIT1_EPITO			= IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__UART1_CTS			= IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D19__USBOH3_USBH2_OC		= IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__EMI_WEIM_D_20			= IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__GPIO3_20			= IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__IPU_DI0_PIN16			= IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__IPU_SER_DISP0_CS		= IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__CSPI_SS0			= IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__EPIT2_EPITO			= IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__UART1_RTS			= IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D20__USBOH3_USBH2_PWR		= IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__EMI_WEIM_D_21			= IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__GPIO3_21			= IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__IPU_DI0_PIN17			= IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK		= IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__CSPI_SCLK			= IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__I2C1_SCL			= IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__USBOH3_USBOTG_OC		= IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__EMI_WEIM_D_22			= IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__GPIO3_22			= IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__IPU_DI0_PIN1			= IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN		= IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__CSPI_MISO			= IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR		= IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__EMI_WEIM_D_23			= IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__GPIO3_23			= IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__UART3_CTS			= IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D23__UART1_DCD			= IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_DI0_D0_CS			= IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_DI1_PIN2			= IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN		= IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_DI1_PIN14			= IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__EMI_WEIM_EB_3			= IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__GPIO2_31			= IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__UART3_RTS			= IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_EB3__UART1_RI			= IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__IPU_DI1_PIN3			= IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC		= IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__IPU_DI1_PIN16			= IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__EMI_WEIM_D_24			= IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__GPIO3_24			= IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__UART3_TXD_MUX			= IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D24__ECSPI1_SS2			= IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__CSPI_SS2			= IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS		= IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__ECSPI2_SS2			= IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__UART1_DTR			= IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__EMI_WEIM_D_25			= IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__GPIO3_25			= IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__UART3_RXD_MUX			= IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D25__ECSPI1_SS3			= IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__CSPI_SS3			= IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC		= IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__ECSPI2_SS3			= IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__UART1_DSR			= IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__EMI_WEIM_D_26			= IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__GPIO3_26			= IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__UART2_TXD_MUX			= IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D26__FIRI_RXD			= IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_CSI0_D_1			= IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_DI1_PIN11			= IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_SISG_2			= IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_DISP1_DAT_22		= IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__EMI_WEIM_D_27			= IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__GPIO3_27			= IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__UART2_RXD_MUX			= IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D27__FIRI_TXD			= IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_CSI0_D_0			= IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_DI1_PIN13			= IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_SISG_3			= IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_DISP1_DAT_23		= IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__EMI_WEIM_D_28			= IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__GPIO3_28			= IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__UART2_CTS			= IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO		= IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__CSPI_MOSI			= IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__I2C1_SDA			= IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__IPU_EXT_TRIG			= IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__IPU_DI0_PIN13			= IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__EMI_WEIM_D_29			= IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__GPIO3_29			= IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__UART2_RTS			= IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS		= IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__CSPI_SS0			= IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_DI1_PIN15			= IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_CSI1_VSYNC		= IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_DI0_PIN14			= IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__EMI_WEIM_D_30			= IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__GPIO3_30			= IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__UART3_CTS			= IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D30__IPU_CSI0_D_3			= IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__IPU_DI0_PIN11			= IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__IPU_DISP1_DAT_21		= IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__USBOH3_USBH1_OC		= IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__USBOH3_USBH2_OC		= IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__EMI_WEIM_D_31			= IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__GPIO3_31			= IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__UART3_RTS			= IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D31__IPU_CSI0_D_2			= IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__IPU_DI0_PIN12			= IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__IPU_DISP1_DAT_20		= IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__USBOH3_USBH1_PWR		= IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__USBOH3_USBH2_PWR		= IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__EMI_WEIM_A_24			= IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__GPIO5_4			= IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__IPU_DISP1_DAT_19		= IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__IPU_CSI1_D_19			= IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__IPU_SISG_2			= IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__USBPHY2_BVALID		= IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__EMI_WEIM_A_23			= IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__GPIO6_6			= IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__IPU_DISP1_DAT_18		= IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__IPU_CSI1_D_18			= IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__IPU_SISG_3			= IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__USBPHY2_ENDSESSION		= IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__EMI_WEIM_A_22			= IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__GPIO2_16			= IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__IPU_DISP1_DAT_17		= IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__IPU_CSI1_D_17			= IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__SRC_BT_CFG1_7			= IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__EMI_WEIM_A_21			= IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__GPIO2_17			= IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__IPU_DISP1_DAT_16		= IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__IPU_CSI1_D_16			= IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__SRC_BT_CFG1_6			= IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__EMI_WEIM_A_20			= IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__GPIO2_18			= IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__IPU_DISP1_DAT_15		= IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__IPU_CSI1_D_15			= IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__SRC_BT_CFG1_5			= IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__EMI_WEIM_A_19			= IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__GPIO2_19			= IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__IPU_DISP1_DAT_14		= IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__IPU_CSI1_D_14			= IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__SRC_BT_CFG1_4			= IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__EMI_WEIM_A_18			= IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__GPIO2_20			= IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__IPU_DISP1_DAT_13		= IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__IPU_CSI1_D_13			= IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__SRC_BT_CFG1_3			= IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__EMI_WEIM_A_17			= IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__GPIO2_21			= IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__IPU_DISP1_DAT_12		= IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__IPU_CSI1_D_12			= IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__SRC_BT_CFG1_2			= IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__EMI_WEIM_A_16			= IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__GPIO2_22			= IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK		= IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK		= IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__SRC_BT_CFG1_1			= IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__EMI_WEIM_CS_0			= IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__GPIO2_23			= IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__ECSPI2_SCLK			= IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__IPU_DI1_PIN5			= IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__EMI_WEIM_CS_1			= IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__GPIO2_24			= IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__ECSPI2_MOSI			= IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__IPU_DI1_PIN6			= IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__EMI_WEIM_OE			= IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__GPIO2_25			= IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__ECSPI2_MISO			= IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__IPU_DI1_PIN7			= IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__USBPHY2_IDDIG			= IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__EMI_WEIM_RW			= IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__GPIO2_26			= IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__ECSPI2_SS0			= IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__IPU_DI1_PIN8			= IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT		= IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__EMI_WEIM_LBA			= IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__GPIO2_27			= IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__ECSPI2_SS1			= IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__IPU_DI1_PIN17			= IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__SRC_BT_CFG1_0			= IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__EMI_WEIM_EB_0			= IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__GPIO2_28			= IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11		= IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__IPU_CSI1_D_11			= IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__GPC_PMIC_RDY			= IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__SRC_BT_CFG2_7			= IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__EMI_WEIM_EB_1			= IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__GPIO2_29			= IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10		= IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__IPU_CSI1_D_10			= IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__SRC_BT_CFG2_6			= IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0		= IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__GPIO3_0			= IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9		= IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__IPU_CSI1_D_9			= IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__SRC_BT_CFG2_5			= IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1		= IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__GPIO3_1			= IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8		= IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__IPU_CSI1_D_8			= IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__SRC_BT_CFG2_4			= IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2		= IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__GPIO3_2			= IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7		= IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__IPU_CSI1_D_7			= IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__SRC_BT_CFG2_3			= IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3		= IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__GPIO3_3			= IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6		= IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__IPU_CSI1_D_6			= IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__SRC_BT_CFG2_2			= IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4		= IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__GPIO3_4			= IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5		= IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__IPU_CSI1_D_5			= IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__SRC_BT_CFG3_7			= IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5		= IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__GPIO3_5			= IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4		= IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__IPU_CSI1_D_4			= IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__SRC_BT_CFG3_6			= IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6		= IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__GPIO3_6			= IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3		= IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__IPU_CSI1_D_3			= IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__SRC_BT_CFG3_5			= IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7		= IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__GPIO3_7			= IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2		= IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__IPU_CSI1_D_2			= IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__SRC_BT_CFG3_4			= IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8		= IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__GPIO3_8			= IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1		= IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__IPU_CSI1_D_1			= IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__SRC_BT_CFG3_3			= IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9		= IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__GPIO3_9			= IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0		= IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__IPU_CSI1_D_0			= IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__SRC_BT_CFG3_2			= IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10		= IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__GPIO3_10			= IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__IPU_DI1_PIN15		= IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN		= IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__SRC_BT_CFG3_1		= IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11		= IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__GPIO3_11			= IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__IPU_DI1_PIN2			= IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC		= IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12		= IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__GPIO3_12			= IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__IPU_DI1_PIN3			= IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC		= IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13		= IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__GPIO3_13			= IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__IPU_DI1_D0_CS		= IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK		= IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14		= IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__GPIO3_14			= IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__IPU_DI1_D1_CS		= IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK		= IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15		= IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__GPIO3_15			= IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__IPU_DI1_PIN1			= IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__IPU_DI1_PIN4			= IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B		= IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WE_B__GPIO6_12			= IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B		= IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RE_B__GPIO6_13			= IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT		= IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_WAIT__GPIO5_0			= IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B		= IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX3_P__GPIO6_22			= IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3		= IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX2_P__GPIO6_24			= IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2		= IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_CLK_P__GPIO6_26			= IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK		= IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX1_P__GPIO6_28			= IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1		= IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX0_P__GPIO6_30			= IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0		= IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX3_P__GPIO7_22			= IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3		= IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_CLK_P__GPIO7_24			= IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK		= IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX2_P__GPIO7_26			= IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2		= IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX1_P__GPIO7_28			= IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1		= IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX0_P__GPIO7_30			= IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0		= IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_10__GPIO4_0			= IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_10__OSC32k_32K_OUT		= IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_11__GPIO4_1			= IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_12__GPIO4_2			= IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_13__GPIO4_3			= IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_14__GPIO4_4			= IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CLE__EMI_NANDF_CLE		= IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CLE__GPIO6_7			= IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0		= IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_ALE__EMI_NANDF_ALE		= IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_ALE__GPIO6_8			= IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1		= IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B		= IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WP_B__GPIO6_9			= IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2		= IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0		= IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RB0__GPIO6_10			= IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3		= IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0		= IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS0__GPIO6_11			= IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4		= IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1		= IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__GPIO6_14			= IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__MLB_MLBCLK			= IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5		= IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2		= IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__GPIO6_15			= IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__IPU_SISG_0			= IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__ESAI1_TX0			= IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__EMI_WEIM_CRE		= IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK		= IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__MLB_MLBSIG			= IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6		= IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3		= IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__GPIO6_16			= IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__IPU_SISG_1			= IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__ESAI1_TX1			= IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__EMI_WEIM_A_26		= IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__MLB_MLBDAT			= IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7		= IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__FEC_MDIO			= IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__GPIO1_22			= IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__ESAI1_SCKR			= IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__FEC_COL			= IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2		= IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3	= IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49		= IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__FEC_TX_CLK		= IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__GPIO1_23			= IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__ESAI1_FSR			= IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4	= IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50		= IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__FEC_RX_ER			= IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__GPIO1_24			= IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__ESAI1_HCKR			= IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__FEC_RX_CLK			= IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3		= IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_CRS_DV__FEC_RX_DV			= IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_CRS_DV__GPIO1_25			= IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_CRS_DV__ESAI1_SCKT			= IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__FEC_RDATA_1			= IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__GPIO1_26			= IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__ESAI1_FST			= IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__MLB_MLBSIG			= IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1		= IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__FEC_RDATA_0			= IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__GPIO1_27			= IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__ESAI1_HCKT			= IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__OSC32k_32K_OUT		= IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TX_EN__FEC_TX_EN			= IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TX_EN__GPIO1_28			= IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2		= IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__FEC_TDATA_1			= IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__GPIO1_29			= IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3		= IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__MLB_MLBCLK			= IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK		= IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__FEC_TDATA_0			= IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__GPIO1_30			= IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1		= IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0		= IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__FEC_MDC			= IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__GPIO1_31			= IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__ESAI1_TX5_RX0			= IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__MLB_MLBDAT			= IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG	= IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1		= IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__PATA_DIOW			= IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__GPIO6_17			= IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__UART1_TXD_MUX		= IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2		= IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__PATA_DMACK			= IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__GPIO6_18			= IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__UART1_RXD_MUX		= IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3		= IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__PATA_DMARQ			= IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__GPIO7_0			= IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__UART2_TXD_MUX		= IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0		= IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4		= IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN		= IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__GPIO7_1		= IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX		= IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1		= IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5	= IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__PATA_INTRQ			= IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__GPIO7_2			= IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__UART2_CTS			= IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__CAN1_TXCAN			= IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2		= IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6		= IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__PATA_DIOR			= IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__GPIO7_3			= IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__UART2_RTS			= IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__CAN1_RXCAN			= IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7		= IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B	= IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__GPIO7_4			= IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__ESDHC3_CMD		= IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__UART1_CTS		= IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__CAN2_TXCAN		= IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0	= IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__PATA_IORDY			= IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__GPIO7_5			= IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__ESDHC3_CLK			= IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__UART1_RTS			= IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__CAN2_RXCAN			= IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1		= IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__PATA_DA_0			= IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__GPIO7_6			= IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__ESDHC3_RST			= IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__OWIRE_LINE			= IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2		= IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__PATA_DA_1			= IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__GPIO7_7			= IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__ESDHC4_CMD			= IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__UART3_CTS			= IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3		= IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__PATA_DA_2			= IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__GPIO7_8			= IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__ESDHC4_CLK			= IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__UART3_RTS			= IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4		= IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__PATA_CS_0			= IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__GPIO7_9			= IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__UART3_TXD_MUX		= IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5		= IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__PATA_CS_1			= IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__GPIO7_10			= IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__UART3_RXD_MUX		= IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6		= IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__PATA_DATA_0		= IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__GPIO2_0			= IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__EMI_NANDF_D_0		= IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__ESDHC3_DAT4		= IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0	= IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0		= IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7		= IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__PATA_DATA_1		= IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__GPIO2_1			= IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__EMI_NANDF_D_1		= IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__ESDHC3_DAT5		= IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1	= IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1		= IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__PATA_DATA_2		= IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__GPIO2_2			= IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__EMI_NANDF_D_2		= IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__ESDHC3_DAT6		= IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2	= IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2		= IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__PATA_DATA_3		= IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__GPIO2_3			= IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__EMI_NANDF_D_3		= IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__ESDHC3_DAT7		= IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3	= IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3		= IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__PATA_DATA_4		= IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__GPIO2_4			= IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__EMI_NANDF_D_4		= IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__ESDHC4_DAT4		= IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4	= IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4		= IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__PATA_DATA_5		= IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__GPIO2_5			= IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__EMI_NANDF_D_5		= IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__ESDHC4_DAT5		= IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5	= IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5		= IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__PATA_DATA_6		= IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__GPIO2_6			= IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__EMI_NANDF_D_6		= IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__ESDHC4_DAT6		= IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6	= IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6		= IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__PATA_DATA_7		= IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__GPIO2_7			= IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__EMI_NANDF_D_7		= IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__ESDHC4_DAT7		= IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7	= IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7		= IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__PATA_DATA_8		= IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__GPIO2_8			= IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__ESDHC1_DAT4		= IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__EMI_NANDF_D_8		= IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__ESDHC3_DAT0		= IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8	= IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8		= IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__PATA_DATA_9		= IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__GPIO2_9			= IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__ESDHC1_DAT5		= IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__EMI_NANDF_D_9		= IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__ESDHC3_DAT1		= IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9	= IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9		= IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__PATA_DATA_10		= IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__GPIO2_10			= IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__ESDHC1_DAT6		= IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__EMI_NANDF_D_10		= IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__ESDHC3_DAT2		= IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10	= IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10		= IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__PATA_DATA_11		= IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__GPIO2_11			= IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__ESDHC1_DAT7		= IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__EMI_NANDF_D_11		= IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__ESDHC3_DAT3		= IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11	= IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11		= IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__PATA_DATA_12		= IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__GPIO2_12			= IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__ESDHC2_DAT4		= IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__EMI_NANDF_D_12		= IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__ESDHC4_DAT0		= IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12	= IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12		= IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__PATA_DATA_13		= IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__GPIO2_13			= IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__ESDHC2_DAT5		= IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__EMI_NANDF_D_13		= IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__ESDHC4_DAT1		= IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13	= IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13		= IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__PATA_DATA_14		= IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__GPIO2_14			= IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__ESDHC2_DAT6		= IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__EMI_NANDF_D_14		= IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__ESDHC4_DAT2		= IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14	= IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14		= IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__PATA_DATA_15		= IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__GPIO2_15			= IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__ESDHC2_DAT7		= IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__EMI_NANDF_D_15		= IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__ESDHC4_DAT3		= IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15	= IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15		= IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__ESDHC1_DAT0			= IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__GPIO1_16			= IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__GPT_CAPIN1			= IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__CSPI_MISO			= IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__CCM_PLL3_BYP		= IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__ESDHC1_DAT1			= IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__GPIO1_17			= IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__GPT_CAPIN2			= IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__CSPI_SS0			= IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__CCM_PLL4_BYP		= IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__ESDHC1_CMD			= IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_CMD__GPIO1_18			= IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__GPT_CMPOUT1			= IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__CSPI_MOSI			= IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__CCM_PLL1_BYP			= IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__ESDHC1_DAT2			= IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__GPIO1_19			= IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__GPT_CMPOUT2			= IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__PWM2_PWMO			= IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__WDOG1_WDOG_B		= IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__CSPI_SS1			= IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB	= IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__CCM_PLL2_BYP		= IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__ESDHC1_CLK			= IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_CLK__GPIO1_20			= IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__OSC32k_32K_OUT		= IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__GPT_CLKIN			= IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__CSPI_SCLK			= IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__SATA_PHY_DTB_0		= IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__ESDHC1_DAT3			= IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__GPIO1_21			= IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__GPT_CMPOUT3			= IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__PWM1_PWMO			= IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__WDOG2_WDOG_B		= IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__CSPI_SS2			= IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB	= IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1		= IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__ESDHC2_CLK			= IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_CLK__GPIO1_10			= IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__KPP_COL_5			= IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS		= IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__CSPI_SCLK			= IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__SCC_RANDOM_V			= IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__ESDHC2_CMD			= IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_CMD__GPIO1_11			= IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__KPP_ROW_5			= IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC		= IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__CSPI_MOSI			= IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__SCC_RANDOM			= IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__ESDHC2_DAT3			= IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__GPIO1_12			= IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__KPP_COL_6			= IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC		= IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__CSPI_SS2			= IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__SJC_DONE			= IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__ESDHC2_DAT2			= IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__GPIO1_13			= IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__KPP_ROW_6			= IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD		= IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__CSPI_SS1			= IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__SJC_FAIL			= IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__ESDHC2_DAT1			= IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__GPIO1_14			= IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__KPP_COL_7			= IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS		= IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__CSPI_SS0			= IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__RTIC_SEC_VIO		= IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__ESDHC2_DAT0			= IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__GPIO1_15			= IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__KPP_ROW_7			= IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD		= IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__CSPI_MISO			= IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__RTIC_DONE_INT		= IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__CCM_CLKO			= IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__GPIO1_0			= IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__KPP_COL_5			= IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK		= IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__EPIT1_EPITO			= IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__SRTC_ALARM_DEB			= IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__USBOH3_USBH1_PWR		= IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__CSU_TD				= IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__ESAI1_SCKR			= IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__GPIO1_1			= IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__KPP_ROW_5			= IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK		= IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__PWM2_PWMO			= IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__WDOG2_WDOG_B			= IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__ESDHC1_CD			= IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__SRC_TESTER_ACK			= IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__ESAI1_FSR			= IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__GPIO1_9			= IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__KPP_COL_6			= IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__CCM_REF_EN_B			= IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__PWM1_PWMO			= IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__WDOG1_WDOG_B			= IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__ESDHC1_WP			= IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__SCC_FAIL_STATE			= IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__ESAI1_HCKR			= IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__GPIO1_3			= IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__I2C3_SCL			= IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__DPLLIP1_TOG_EN			= IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__CCM_CLKO2			= IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0	= IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__USBOH3_USBH1_OC		= IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__MLB_MLBCLK			= IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__ESAI1_SCKT			= IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__GPIO1_6			= IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__I2C3_SDA			= IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__CCM_CCM_OUT_0			= IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__CSU_CSU_INT_DEB		= IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1	= IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__ESDHC2_LCTL			= IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__MLB_MLBSIG			= IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__ESAI1_FST			= IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__GPIO1_2			= IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__KPP_ROW_6			= IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__CCM_CCM_OUT_1			= IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0		= IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2	= IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__ESDHC2_WP			= IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__MLB_MLBDAT			= IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__ESAI1_HCKT			= IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__GPIO1_4			= IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__KPP_COL_7			= IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__CCM_CCM_OUT_2			= IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1		= IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3	= IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__ESDHC2_CD			= IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__SCC_SEC_STATE			= IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__ESAI1_TX2_RX3			= IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__GPIO1_5			= IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__KPP_ROW_7			= IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__CCM_CLKO			= IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2		= IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4	= IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__I2C3_SCL			= IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__CCM_PLL1_BYP			= IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__ESAI1_TX4_RX1			= IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__GPIO1_7			= IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__EPIT1_EPITO			= IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__CAN1_TXCAN			= IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__UART2_TXD_MUX			= IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_GPIO_7__FIRI_RXD			= IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__SPDIF_PLOCK			= IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__CCM_PLL2_BYP			= IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__ESAI1_TX5_RX0			= IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__GPIO1_8			= IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__EPIT2_EPITO			= IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__CAN1_RXCAN			= IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__UART2_RXD_MUX			= IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL),
+	MX53_PAD_GPIO_8__FIRI_TXD			= IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__SPDIF_SRCLK			= IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__CCM_PLL3_BYP			= IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__ESAI1_TX3_RX2			= IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__GPIO7_11			= IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT		= IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1		= IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__SPDIF_IN1			= IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__I2C3_SDA			= IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__SJC_DE_B			= IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__ESAI1_TX0			= IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__GPIO7_12			= IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0		= IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__GPC_PMIC_RDY			= IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG		= IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__SPDIF_OUT1			= IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__IPU_SNOOP2			= IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__SJC_JTAG_ACT			= IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__ESAI1_TX1			= IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__GPIO7_13			= IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1		= IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__OWIRE_LINE			= IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG	= IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK		= IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__ESDHC1_LCTL			= IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__SRC_SYSTEM_RST		= IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX53_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h
deleted file mode 100644
index e3765a3..0000000
--- a/arch/arm/include/asm/arch-mx5/iomux.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MACH_MX5_IOMUX_H__
-#define __MACH_MX5_IOMUX_H__
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-
-typedef unsigned int iomux_pin_name_t;
-
-/* various IOMUX output functions */
-typedef enum iomux_config {
-	IOMUX_CONFIG_ALT0,	/*!< used as alternate function 0 */
-	IOMUX_CONFIG_ALT1,	/*!< used as alternate function 1 */
-	IOMUX_CONFIG_ALT2,	/*!< used as alternate function 2 */
-	IOMUX_CONFIG_ALT3,	/*!< used as alternate function 3 */
-	IOMUX_CONFIG_ALT4,	/*!< used as alternate function 4 */
-	IOMUX_CONFIG_ALT5,	/*!< used as alternate function 5 */
-	IOMUX_CONFIG_ALT6,	/*!< used as alternate function 6 */
-	IOMUX_CONFIG_ALT7,	/*!< used as alternate function 7 */
-	IOMUX_CONFIG_GPIO,	/*!< added to help user use GPIO mode */
-	IOMUX_CONFIG_SION = 0x1 << 4,	/*!< used as LOOPBACK:MUX SION bit */
-} iomux_pin_cfg_t;
-
-/* various IOMUX pad functions */
-typedef enum iomux_pad_config {
-	PAD_CTL_SRE_SLOW = 0x0 << 0,	/* Slow slew rate */
-	PAD_CTL_SRE_FAST = 0x1 << 0,	/* Fast slew rate */
-	PAD_CTL_DRV_LOW = 0x0 << 1,	/* Low drive strength */
-	PAD_CTL_DRV_MEDIUM = 0x1 << 1,	/* Medium drive strength */
-	PAD_CTL_DRV_HIGH = 0x2 << 1,	/* High drive strength */
-	PAD_CTL_DRV_MAX = 0x3 << 1,	/* Max drive strength */
-	PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,	/* Opendrain disable */
-	PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */
-	PAD_CTL_100K_PD = 0x0 << 4,	/* 100Kohm pulldown */
-	PAD_CTL_47K_PU = 0x1 << 4,	/* 47Kohm pullup */
-	PAD_CTL_100K_PU = 0x2 << 4,	/* 100Kohm pullup */
-	PAD_CTL_22K_PU = 0x3 << 4,	/* 22Kohm pullup */
-	PAD_CTL_PUE_KEEPER = 0x0 << 6,	/* enable pulldown */
-	PAD_CTL_PUE_PULL = 0x1 << 6,	/* enable pullup */
-	PAD_CTL_PKE_NONE = 0x0 << 7,	/* Disable pullup/pulldown */
-	PAD_CTL_PKE_ENABLE = 0x1 << 7,	/* Enable pullup/pulldown */
-	PAD_CTL_HYS_NONE = 0x0 << 8,	/* Hysteresis disabled */
-	PAD_CTL_HYS_ENABLE = 0x1 << 8,	/* Hysteresis enabled */
-	PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */
-	PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */
-	PAD_CTL_DRV_VOT_LOW = 0x1 << 13, /* Low voltage mode */
-	PAD_CTL_DRV_VOT_HIGH = 0x0 << 13,/* High voltage mode */
-} iomux_pad_config_t;
-
-/* various IOMUX input functions */
-typedef enum iomux_input_config {
-	INPUT_CTL_PATH0 = 0x0,
-	INPUT_CTL_PATH1,
-	INPUT_CTL_PATH2,
-	INPUT_CTL_PATH3,
-	INPUT_CTL_PATH4,
-	INPUT_CTL_PATH5,
-	INPUT_CTL_PATH6,
-	INPUT_CTL_PATH7,
-} iomux_input_config_t;
-
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-
-#endif				/*  __MACH_MX5_IOMUX_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/mx5x_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
deleted file mode 100644
index 3457f6a..0000000
--- a/arch/arm/include/asm/arch-mx5/mx5x_pins.h
+++ /dev/null
@@ -1,879 +0,0 @@
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
-#define __ASM_ARCH_MX5_MX5X_PINS_H__
-
-#ifndef __ASSEMBLY__
-
-/*
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 |  23 - 21 | 20  - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P  |  IO_I   | GPIO_I   | PAD_I   | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 9 contains MUX_I used to identify the register
- * offset (0-based. base is IOMUX_module_base) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
- * similar field definitions are used for the pad control register.
- * The IOMUX controller can be split in two parts. At the begeinning,
- * there is the register definitions for the multiplexing each pin.
- * Then there is a set of registers (PAD_I) to configure each pin
- * (pullup, pulldown, etc).
- * PAD_I defines the offset of the pad register for each pin.
- * GPIO_I defines, if available, the number of gpio that can be
- * connected to that pad
- * IO_I defines the multiplexer mode required to set the pad in gpio mode
- * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs
- *
- * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
- *    ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
- * It means the mux control register is at register offset 0x28. The pad control
- * register offset is: 0x250 and also occupy the least significant bits
- * within the register.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I			0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I			10
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent which
- * mux mode is for GPIO (0-based)
- */
-#define GPIO_I			21
-
-#define MUX_IO_P                29
-#define MUX_IO_I                24
-#define IOMUX_TO_GPIO(pin)      ((((unsigned int)pin >> MUX_IO_P) * \
-					GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
-					((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-#define IOMUX_TO_IRQ(pin)       (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-
-#define NON_GPIO_PORT		0x7
-#define PIN_TO_MUX_MASK		((1 << (PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK		((1 << (GPIO_I - PAD_I)) - 1)
-#define PIN_TO_ALT_GPIO_MASK		((1 << (MUX_IO_I - GPIO_I)) - 1)
-
-#define NON_MUX_I              PIN_TO_MUX_MASK
-#define NON_PAD_I              PIN_TO_PAD_MASK
-
-#if defined(CONFIG_MX51)
-#define MUX_I_START		0x001C
-#define PAD_I_START		0x3F0
-#define INPUT_CTL_START		0x8C4
-#define MUX_I_END		(PAD_I_START - 4)
-#elif defined(CONFIG_MX53)
-#define MUX_I_START            0x0020
-#define PAD_I_START            0x348
-#define INPUT_CTL_START        0x730
-#define MUX_I_END              (PAD_I_START - 4)
-#else
-#error "CPU_TYPE not defined"
-#endif
-
-#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
-	(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
-	((mi) << MUX_I) | \
-	((pi - PAD_I_START) << PAD_I) | \
-	((ga) << GPIO_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
-	_MXC_BUILD_PIN(gp, gi, ga, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
-	_MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin)	((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin)	((pin >> PAD_I) & PIN_TO_PAD_MASK)
-#define PIN_TO_ALT_GPIO(pin)	((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
-#define PIN_TO_IOMUX_INDEX(pin)	(PIN_TO_IOMUX_MUX(pin) >> 2)
-
-/*
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-enum {
-	MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
-	MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
-	MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
-	MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
-	MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
-	MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
-	MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
-	MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
-	MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
-	MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
-	MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
-	MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
-	MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
-	MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
-	MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
-	MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
-	MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
-	MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
-	MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
-	MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
-	MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
-	MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
-	MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
-	MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
-	MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
-	MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
-	MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
-	MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
-	MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
-	MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
-	MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
-	MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
-	MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
-	MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
-	MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
-	MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
-	MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
-	MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
-	MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
-	MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
-	MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
-	MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
-	MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
-	MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
-	MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
-	MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
-	MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
-	MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
-	MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
-	MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
-	MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
-	MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
-	MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
-	MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
-	MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
-	MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
-	MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
-	MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
-	MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
-	MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
-	MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
-	MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
-	MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
-	MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
-	MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
-	MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
-	MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
-	MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
-	MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
-	MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
-	MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
-	MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
-	MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
-	MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
-	MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
-	MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
-	MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
-	MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
-	MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
-	MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
-	MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
-	MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
-	MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
-	MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
-	MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
-	MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
-	MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
-	MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
-	MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
-	MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
-	MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
-	MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
-	MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
-	MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
-	MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
-	MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
-	MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
-	MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
-	MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
-	MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
-	MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
-	MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
-	MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
-	MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
-	MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
-	MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
-	MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
-	MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
-	MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
-	MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
-	MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
-	MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
-	MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
-	MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
-	MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
-	MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
-	MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
-	MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
-	MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
-	MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
-	MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
-	MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
-	MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
-	MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
-	MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
-	MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
-	MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
-	MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
-	MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
-	MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
-	MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
-	MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
-	MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
-	MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
-	MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
-	MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
-	MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
-	MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
-	MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
-	MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
-	MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
-	MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
-	MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
-	MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
-	MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
-	MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
-	MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
-	MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
-	MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
-	MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
-	MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
-	MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
-	MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
-	MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
-	MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
-	MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
-	MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
-	MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
-	MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
-	MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
-	MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
-	MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
-	MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
-	MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
-	MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
-	MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
-	MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
-	MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
-	MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
-	MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
-	MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
-	MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
-	MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
-	MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
-	MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
-	MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
-	MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
-	MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
-	MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
-	MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
-	MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
-	MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
-	MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
-	MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
-	MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
-	MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
-	MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
-	MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
-	MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
-	MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
-	MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
-	MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
-	MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
-	MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
-	MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
-	MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
-	MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
-	MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
-	MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
-	MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
-	MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
-	MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
-	MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
-	MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
-	MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
-	MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
-	MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
-	MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
-	MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
-	MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
-	MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
-	MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
-	MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
-	MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
-	MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
-	MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
-	MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
-	MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
-	MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
-	MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
-	MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
-	MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
-	MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
-	MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
-	MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
-	MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
-	MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
-	MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
-	MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
-	MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
-	MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
-	MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
-	MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
-	MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
-	MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
-	MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
-	MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
-	MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
-	MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
-	MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
-	MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
-	MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
-	MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
-	MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
-	MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
-	MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
-	MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
-	MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
-	MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
-	MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
-	MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
-	MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
-
-	/* The following are PADS used for drive strength */
-
-	MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820),
-	MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838),
-	MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890),
-	MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C),
-	MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C),
-	MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884),
-	MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C),
-	MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864),
-	MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C),
-	MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874),
-	MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878),
-	MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880),
-	MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C),
-	MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C),
-	MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4),
-	MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC),
-	MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8),
-	MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C),
-	MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0),
-	MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0),
-	MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4),
-	MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC),
-	MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C),
-	MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848),
-	MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868),
-	MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4),
-	MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8),
-	MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac),
-	MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0),
-	MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4),
-	MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8),
-	MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC),
-	MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0),
-	MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4),
-	MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8),
-	MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC),
-	MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0),
-	MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4),
-	MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8),
-	MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC),
-	MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
-};
-
-enum {
-	MX53_PIN_GPIO_19  = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
-	MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
-	MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
-	MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354),
-	MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358),
-	MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C),
-	MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360),
-	MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364),
-	MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368),
-	MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C),
-	MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370),
-	MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374),
-	MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378),
-	MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C),
-	MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380),
-	MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384),
-	MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388),
-	MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C),
-	MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390),
-	MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394),
-	MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398),
-	MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C),
-	MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0),
-	MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4),
-	MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8),
-	MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC),
-	MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0),
-	MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4),
-	MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8),
-	MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC),
-	MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0),
-	MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4),
-	MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8),
-	MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC),
-	MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0),
-	MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4),
-	MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8),
-	MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC),
-	MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0),
-	MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4),
-	MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8),
-	MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC),
-	MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0),
-	MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4),
-	MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8),
-	MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC),
-	MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400),
-	MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404),
-	MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408),
-	MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C),
-	MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410),
-	MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414),
-	MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418),
-	MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C),
-	MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420),
-	MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424),
-	MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428),
-	MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C),
-	MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430),
-	MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434),
-	MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438),
-	MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C),
-	MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
-	MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
-	MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
-	MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C),
-	MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
-	MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
-	MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458),
-	MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C),
-	MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460),
-	MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464),
-	MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468),
-	MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C),
-	MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470),
-	MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474),
-	MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478),
-	MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C),
-	MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480),
-	MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484),
-	MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488),
-	MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C),
-	MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490),
-	MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494),
-	MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498),
-	MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C),
-	MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0),
-	MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4),
-	MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8),
-	MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC),
-	MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0),
-	MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4),
-	MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8),
-	MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC),
-	MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0),
-	MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4),
-	MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8),
-	MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC),
-	MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0),
-	MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4),
-	MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8),
-	MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC),
-	MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0),
-	MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4),
-	MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8),
-	MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC),
-	MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0),
-	MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4),
-	MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8),
-	MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC),
-	MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500),
-	MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504),
-	MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508),
-	MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C),
-	MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510),
-	MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514),
-	MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518),
-	MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C),
-	MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520),
-	MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524),
-	MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528),
-	MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C),
-	MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530),
-	MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534),
-	MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538),
-	MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C),
-	MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I),
-	MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I),
-	MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I),
-	MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I),
-	MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I),
-	MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I),
-	MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I),
-	MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I),
-	MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I),
-	MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I),
-	MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540),
-	MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544),
-	MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548),
-	MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C),
-	MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550),
-	MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554),
-	MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558),
-	MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C),
-	MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560),
-	MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564),
-	MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568),
-	MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C),
-	MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570),
-	MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574),
-	MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578),
-	MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C),
-	MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580),
-	MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584),
-	MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588),
-	MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C),
-	MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590),
-	MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594),
-	MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598),
-	MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C),
-	MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0),
-	MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4),
-	MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8),
-	MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC),
-	MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0),
-	MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4),
-	MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8),
-	MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC),
-	MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0),
-	MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4),
-	MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8),
-	MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC),
-	MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0),
-	MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4),
-	MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8),
-	MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC),
-	MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0),
-	MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4),
-	MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8),
-	MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC),
-	MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0),
-	MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4),
-	MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8),
-	MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC),
-	MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600),
-	MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604),
-	MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608),
-	MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C),
-	MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610),
-	MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614),
-	MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618),
-	MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C),
-	MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620),
-	MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624),
-	MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628),
-	MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C),
-	MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630),
-	MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634),
-	MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638),
-	MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C),
-	MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640),
-	MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644),
-	MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648),
-	MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C),
-	MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650),
-	MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654),
-	MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658),
-	MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C),
-	MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660),
-	MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664),
-	MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668),
-	MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C),
-	MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670),
-	MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674),
-	MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678),
-	MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C),
-	MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680),
-	MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684),
-	MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688),
-	MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C),
-	MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690),
-	MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694),
-	MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698),
-	MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C),
-	MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0),
-	MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4),
-	MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8),
-	MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC),
-	MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0),
-	MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4),
-	MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8),
-	MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC),
-	MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0),
-	MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4),
-	MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8),
-	MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC),
-	MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0),
-	MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4),
-	MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8),
-	MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC),
-	MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0),
-	MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4),
-	MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8),
-	MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC),
-	MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0),
-	MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4),
-	MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC),
-	MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708),
-	MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C),
-	MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710),
-	MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714),
-	MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718),
-	MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C),
-	MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720),
-	MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724),
-	MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728),
-	MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C),
-};
-/* various IOMUX input select register index */
-typedef enum iomux_input_select {
-	MX51_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
-	MX51_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
-	MX51_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
-	MX51_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX51_CCM_IPP_DI_CLK_SELECT_INPUT,
-	/* TO2 */
-	MX51_CCM_IPP_DI1_CLK_SELECT_INPUT,
-	MX51_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
-	MX51_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
-	MX51_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_MISO_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_MOSI_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
-	MX51_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
-	/* TO2 */
-	MX51_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX51_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
-	MX51_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
-	MX51_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
-	MX51_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
-	MX51_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
-	MX51_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
-	MX51_FEC_FEC_COL_SELECT_INPUT,
-	MX51_FEC_FEC_CRS_SELECT_INPUT,
-	MX51_FEC_FEC_MDI_SELECT_INPUT,
-	MX51_FEC_FEC_RDATA_0_SELECT_INPUT,
-	MX51_FEC_FEC_RDATA_1_SELECT_INPUT,
-	MX51_FEC_FEC_RDATA_2_SELECT_INPUT,
-	MX51_FEC_FEC_RDATA_3_SELECT_INPUT,
-	MX51_FEC_FEC_RX_CLK_SELECT_INPUT,
-	MX51_FEC_FEC_RX_DV_SELECT_INPUT,
-	MX51_FEC_FEC_RX_ER_SELECT_INPUT,
-	MX51_FEC_FEC_TX_CLK_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
-	/* TO2 */
-	MX51_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
-	MX51_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
-	MX51_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
-	/* TO2 */
-	MX51_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
-	/* TO2 */
-	MX51_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
-	MX51_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
-	MX51_I2C1_IPP_SCL_IN_SELECT_INPUT,
-	MX51_I2C1_IPP_SDA_IN_SELECT_INPUT,
-	MX51_I2C2_IPP_SCL_IN_SELECT_INPUT,
-	MX51_I2C2_IPP_SDA_IN_SELECT_INPUT,
-	MX51_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-	MX51_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-	MX51_KPP_IPP_IND_COL_6_SELECT_INPUT,
-	MX51_KPP_IPP_IND_COL_7_SELECT_INPUT,
-	MX51_KPP_IPP_IND_ROW_4_SELECT_INPUT,
-	MX51_KPP_IPP_IND_ROW_5_SELECT_INPUT,
-	MX51_KPP_IPP_IND_ROW_6_SELECT_INPUT,
-	MX51_KPP_IPP_IND_ROW_7_SELECT_INPUT,
-	MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
-	MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX51_UART2_IPP_UART_RTS_B_SELECT_INPUT,
-	MX51_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX51_UART3_IPP_UART_RTS_B_SELECT_INPUT,
-	MX51_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
-	MX51PUT_NUM_MUX,
-	/* MX53 */
-	MX53_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
-	MX53_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
-	MX53_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
-	MX53_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
-	MX53_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX53_CAN1_IPP_IND_CANRX_SELECT_INPUT,
-	MX53_CAN2_IPP_IND_CANRX_SELECT_INPUT,
-	MX53_CCM_IPP_ASRC_EXT_SELECT_INPUT,
-	MX53_CCM_IPP_DI1_CLK_SELECT_INPUT,
-	MX53_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
-	MX53_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
-	MX53_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
-	MX53_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
-	MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_MISO_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_SS_B_0_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
-	MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT,
-	MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
-	MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
-	MX53_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT,
-	MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_FST_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SCKT_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
-	MX53_ESDHC1_IPP_WP_ON_SELECT_INPUT,
-	MX53_FEC_FEC_COL_SELECT_INPUT,
-	MX53_FEC_FEC_MDI_SELECT_INPUT,
-	MX53_FEC_FEC_RX_CLK_SELECT_INPUT,
-	MX53_FIRI_IPP_IND_RXD_SELECT_INPUT,
-	MX53_GPC_PMIC_RDY_SELECT_INPUT,
-	MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
-	MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
-	MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
-	MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
-	MX53_I2C3_IPP_SCL_IN_SELECT_INPUT,
-	MX53_I2C3_IPP_SDA_IN_SELECT_INPUT,
-	MX53_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-	MX53_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-	MX53_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
-	MX53_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
-	MX53_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
-	MX53_KPP_IPP_IND_COL_5_SELECT_INPUT,
-	MX53_KPP_IPP_IND_COL_6_SELECT_INPUT,
-	MX53_KPP_IPP_IND_COL_7_SELECT_INPUT,
-	MX53_KPP_IPP_IND_ROW_5_SELECT_INPUT,
-	MX53_KPP_IPP_IND_ROW_6_SELECT_INPUT,
-	MX53_KPP_IPP_IND_ROW_7_SELECT_INPUT,
-	MX53_MLB_MLBCLK_IN_SELECT_INPUT,
-	MX53_MLB_MLBDAT_IN_SELECT_INPUT,
-	MX53_MLB_MLBSIG_IN_SELECT_INPUT,
-	MX53_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
-	MX53_SDMA_EVENTS_14_SELECT_INPUT,
-	MX53_SDMA_EVENTS_15_SELECT_INPUT,
-	MX53_SPDIF_SPDIF_IN1_SELECT_INPUT,
-	MX53_UART1_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_UART2_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_UART3_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_UART4_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_UART5_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
-	MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
-	MX53_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
-} iomux_input_select_t;
-
-#endif				/* __ASSEMBLY__ */
-#endif				/* __ASM_ARCH_MX5_MX5X_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/spl.h b/arch/arm/include/asm/arch-mx5/spl.h
new file mode 100644
index 0000000..e0b6e3e
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx5/spl.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __ASM_ARCH_SPL_H__
+#define __ASM_ARCH_SPL_H__
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_NAND	1
+
+#endif	/* __ASM_ARCH_SPL_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index db377cc..cfd4edc 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -61,6 +61,7 @@
 u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
+void enable_ocotp_clk(unsigned char enable);
 void enable_usboh3_clk(unsigned char enable);
 int enable_sata_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 7676457..aa9747c 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -20,6 +20,7 @@
 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
 
+#define CCM_CCOSR		0x020c4060
 #define CCM_CCGR0		0x020C4068
 #define CCM_CCGR1		0x020C406c
 #define CCM_CCGR2		0x020C4070
@@ -244,7 +245,12 @@
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
+#ifdef CONFIG_MX6SL
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x1F
+#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
+#else
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x3F
+#endif
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
 
 /* Define the bits in register CS1CDR */
@@ -262,10 +268,13 @@
 /* Define the bits in register CS2CDR */
 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK		(0x3F << 21)
 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET		21
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v)			(((v) & 0x3f) << 21)
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK		(0x7 << 18)
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET		18
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)			(((v) & 0x7) << 18)
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		(0x3 << 16)
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		16
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			(((v) & 0x3) << 16)
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK		(0x7 << 12)
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET		12
 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK		(0x7 << 9)
@@ -412,183 +421,183 @@
 #define MXC_CCM_CCGR_CG_MASK				3
 
 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET			0
-#define MXC_CCM_CCGR0_AIPS_TZ1_MASK			(3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
+#define MXC_CCM_CCGR0_AIPS_TZ1_MASK			(3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET			2
-#define MXC_CCM_CCGR0_AIPS_TZ2_MASK			(3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
-#define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET		4
-#define MXC_CCM_CCGR0_AMASK				(3<<MXC_CCM_CCGR0_APBHDMA)
+#define MXC_CCM_CCGR0_AIPS_TZ2_MASK			(3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
+#define MXC_CCM_CCGR0_APBHDMA_OFFSET			4
+#define MXC_CCM_CCGR0_APBHDMA_MASK			(3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
 #define MXC_CCM_CCGR0_ASRC_OFFSET			6
-#define MXC_CCM_CCGR0_ASRC_MASK				(3<<MXC_CCM_CCGR0_ASRC_OFFSET)
+#define MXC_CCM_CCGR0_ASRC_MASK				(3 << MXC_CCM_CCGR0_ASRC_OFFSET)
 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET		8
-#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK		(3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK		(3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET		10
-#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK		(3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK		(3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET		12
-#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK		(3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK		(3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
 #define MXC_CCM_CCGR0_CAN1_OFFSET			14
-#define MXC_CCM_CCGR0_CAN1_MASK				(3<<MXC_CCM_CCGR0_CAN1_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_MASK				(3 << MXC_CCM_CCGR0_CAN1_OFFSET)
 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET		16
-#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK			(3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK			(3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
 #define MXC_CCM_CCGR0_CAN2_OFFSET			18
-#define MXC_CCM_CCGR0_CAN2_MASK				(3<<MXC_CCM_CCGR0_CAN2_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_MASK				(3 << MXC_CCM_CCGR0_CAN2_OFFSET)
 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET		20
-#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK			(3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK			(3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET		22
-#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK		(3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK		(3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
 #define MXC_CCM_CCGR0_DCIC1_OFFSET			24
-#define MXC_CCM_CCGR0_DCIC1_MASK			(3<<MXC_CCM_CCGR0_DCIC1_OFFSET)
+#define MXC_CCM_CCGR0_DCIC1_MASK			(3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
 #define MXC_CCM_CCGR0_DCIC2_OFFSET			26
-#define MXC_CCM_CCGR0_DCIC2_MASK			(3<<MXC_CCM_CCGR0_DCIC2_OFFSET)
+#define MXC_CCM_CCGR0_DCIC2_MASK			(3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
 #define MXC_CCM_CCGR0_DTCP_OFFSET			28
-#define MXC_CCM_CCGR0_DTCP_MASK				(3<<MXC_CCM_CCGR0_DTCP_OFFSET)
+#define MXC_CCM_CCGR0_DTCP_MASK				(3 << MXC_CCM_CCGR0_DTCP_OFFSET)
 
 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET			0
-#define MXC_CCM_CCGR1_ECSPI1S_MASK			(3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI1S_MASK			(3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET			2
-#define MXC_CCM_CCGR1_ECSPI2S_MASK			(3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI2S_MASK			(3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET			4
-#define MXC_CCM_CCGR1_ECSPI3S_MASK			(3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI3S_MASK			(3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET			6
-#define MXC_CCM_CCGR1_ECSPI4S_MASK			(3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI4S_MASK			(3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET			8
-#define MXC_CCM_CCGR1_ECSPI5S_MASK			(3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI5S_MASK			(3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET		10
-#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK		(3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK		(3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
 #define MXC_CCM_CCGR1_EPIT1S_OFFSET			12
-#define MXC_CCM_CCGR1_EPIT1S_MASK			(3<<MXC_CCM_CCGR1_EPIT1S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT1S_MASK			(3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
 #define MXC_CCM_CCGR1_EPIT2S_OFFSET			14
-#define MXC_CCM_CCGR1_EPIT2S_MASK			(3<<MXC_CCM_CCGR1_EPIT2S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT2S_MASK			(3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
 #define MXC_CCM_CCGR1_ESAIS_OFFSET			16
-#define MXC_CCM_CCGR1_ESAIS_MASK			(3<<MXC_CCM_CCGR1_ESAIS_OFFSET)
+#define MXC_CCM_CCGR1_ESAIS_MASK			(3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET			20
-#define MXC_CCM_CCGR1_GPT_BUS_MASK			(3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_BUS_MASK			(3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET			22
-#define MXC_CCM_CCGR1_GPT_SERIAL_MASK			(3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_GPT_SERIAL_MASK			(3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
 #define MXC_CCM_CCGR1_GPU2D_OFFSET			24
-#define MXC_CCM_CCGR1_GPU2D_MASK			(3<<MXC_CCM_CCGR1_GPU2D_OFFSET)
+#define MXC_CCM_CCGR1_GPU2D_MASK			(3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
 #define MXC_CCM_CCGR1_GPU3D_OFFSET			26
-#define MXC_CCM_CCGR1_GPU3D_MASK			(3<<MXC_CCM_CCGR1_GPU3D_OFFSET)
+#define MXC_CCM_CCGR1_GPU3D_MASK			(3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
 
 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET		0
-#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK		(3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK		(3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET		4
-#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK		(3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK		(3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET		6
-#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK			(3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET		8
-#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK			(3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET		10
-#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK			(3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET			12
-#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK			(3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
+#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK			(3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET		14
-#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK		(3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK		(3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
 #define MXC_CCM_CCGR2_IPMUX1_OFFSET			16
-#define MXC_CCM_CCGR2_IPMUX1_MASK			(3<<MXC_CCM_CCGR2_IPMUX1_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX1_MASK			(3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
 #define MXC_CCM_CCGR2_IPMUX2_OFFSET			18
-#define MXC_CCM_CCGR2_IPMUX2_MASK			(3<<MXC_CCM_CCGR2_IPMUX2_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX2_MASK			(3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
 #define MXC_CCM_CCGR2_IPMUX3_OFFSET			20
-#define MXC_CCM_CCGR2_IPMUX3_MASK			(3<<MXC_CCM_CCGR2_IPMUX3_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX3_MASK			(3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET	22
-#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK	(3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET	24
-#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK	(3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET	26
-#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK	(3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
 
 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET				0
-#define MXC_CCM_CCGR3_IPU1_IPU_MASK				(3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET			2
-#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK				(3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET			4
-#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK				(3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET				6
-#define MXC_CCM_CCGR3_IPU2_IPU_MASK				(3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_MASK				(3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET			8
-#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK				(3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK				(3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET			10
-#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK				(3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK				(3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET				12
-#define MXC_CCM_CCGR3_LDB_DI0_MASK				(3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI0_MASK				(3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET				14
-#define MXC_CCM_CCGR3_LDB_DI1_MASK				(3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI1_MASK				(3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET			16
-#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK			(3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK			(3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
 #define MXC_CCM_CCGR3_MLB_OFFSET				18
-#define MXC_CCM_CCGR3_MLB_MASK					(3<<MXC_CCM_CCGR3_MLB_OFFSET)
+#define MXC_CCM_CCGR3_MLB_MASK					(3 << MXC_CCM_CCGR3_MLB_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET	20
-#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK		(3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK		(3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET	22
-#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK		(3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK		(3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET		24
-#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK			(3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK			(3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET		26
-#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK			(3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK			(3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
 #define MXC_CCM_CCGR3_OCRAM_OFFSET				28
-#define MXC_CCM_CCGR3_OCRAM_MASK				(3<<MXC_CCM_CCGR3_OCRAM_OFFSET)
+#define MXC_CCM_CCGR3_OCRAM_MASK				(3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET			30
-#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK				(3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
+#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK				(3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
 
 #define MXC_CCM_CCGR4_PCIE_OFFSET				0
-#define MXC_CCM_CCGR4_PCIE_MASK					(3<<MXC_CCM_CCGR4_PCIE_OFFSET)
+#define MXC_CCM_CCGR4_PCIE_MASK					(3 << MXC_CCM_CCGR4_PCIE_OFFSET)
 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET		8
-#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK			(3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK			(3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET			12
-#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK			(3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK			(3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET	14
-#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK	(3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK	(3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
 #define MXC_CCM_CCGR4_PWM1_OFFSET				16
-#define MXC_CCM_CCGR4_PWM1_MASK					(3<<MXC_CCM_CCGR4_PWM1_OFFSET)
+#define MXC_CCM_CCGR4_PWM1_MASK					(3 << MXC_CCM_CCGR4_PWM1_OFFSET)
 #define MXC_CCM_CCGR4_PWM2_OFFSET				18
-#define MXC_CCM_CCGR4_PWM2_MASK					(3<<MXC_CCM_CCGR4_PWM2_OFFSET)
+#define MXC_CCM_CCGR4_PWM2_MASK					(3 << MXC_CCM_CCGR4_PWM2_OFFSET)
 #define MXC_CCM_CCGR4_PWM3_OFFSET				20
-#define MXC_CCM_CCGR4_PWM3_MASK					(3<<MXC_CCM_CCGR4_PWM3_OFFSET)
+#define MXC_CCM_CCGR4_PWM3_MASK					(3 << MXC_CCM_CCGR4_PWM3_OFFSET)
 #define MXC_CCM_CCGR4_PWM4_OFFSET				22
-#define MXC_CCM_CCGR4_PWM4_MASK					(3<<MXC_CCM_CCGR4_PWM4_OFFSET)
+#define MXC_CCM_CCGR4_PWM4_MASK					(3 << MXC_CCM_CCGR4_PWM4_OFFSET)
 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET		24
-#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK		(3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK		(3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET	26
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK		(3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK		(3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET	28
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK	(3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK	(3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET		30
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK		(3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK		(3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
 
 #define MXC_CCM_CCGR5_ROM_OFFSET			0
-#define MXC_CCM_CCGR5_ROM_MASK				(3<<MXC_CCM_CCGR5_ROM_OFFSET)
+#define MXC_CCM_CCGR5_ROM_MASK				(3 << MXC_CCM_CCGR5_ROM_OFFSET)
 #define MXC_CCM_CCGR5_SATA_OFFSET			4
-#define MXC_CCM_CCGR5_SATA_MASK				(3<<MXC_CCM_CCGR5_SATA_OFFSET)
+#define MXC_CCM_CCGR5_SATA_MASK				(3 << MXC_CCM_CCGR5_SATA_OFFSET)
 #define MXC_CCM_CCGR5_SDMA_OFFSET			6
-#define MXC_CCM_CCGR5_SDMA_MASK				(3<<MXC_CCM_CCGR5_SDMA_OFFSET)
+#define MXC_CCM_CCGR5_SDMA_MASK				(3 << MXC_CCM_CCGR5_SDMA_OFFSET)
 #define MXC_CCM_CCGR5_SPBA_OFFSET			12
-#define MXC_CCM_CCGR5_SPBA_MASK				(3<<MXC_CCM_CCGR5_SPBA_OFFSET)
+#define MXC_CCM_CCGR5_SPBA_MASK				(3 << MXC_CCM_CCGR5_SPBA_OFFSET)
 #define MXC_CCM_CCGR5_SPDIF_OFFSET			14
-#define MXC_CCM_CCGR5_SPDIF_MASK			(3<<MXC_CCM_CCGR5_SPDIF_OFFSET)
+#define MXC_CCM_CCGR5_SPDIF_MASK			(3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
 #define MXC_CCM_CCGR5_SSI1_OFFSET			18
-#define MXC_CCM_CCGR5_SSI1_MASK				(3<<MXC_CCM_CCGR5_SSI1_OFFSET)
+#define MXC_CCM_CCGR5_SSI1_MASK				(3 << MXC_CCM_CCGR5_SSI1_OFFSET)
 #define MXC_CCM_CCGR5_SSI2_OFFSET			20
-#define MXC_CCM_CCGR5_SSI2_MASK				(3<<MXC_CCM_CCGR5_SSI2_OFFSET)
+#define MXC_CCM_CCGR5_SSI2_MASK				(3 << MXC_CCM_CCGR5_SSI2_OFFSET)
 #define MXC_CCM_CCGR5_SSI3_OFFSET			22
-#define MXC_CCM_CCGR5_SSI3_MASK				(3<<MXC_CCM_CCGR5_SSI3_OFFSET)
+#define MXC_CCM_CCGR5_SSI3_MASK				(3 << MXC_CCM_CCGR5_SSI3_OFFSET)
 #define MXC_CCM_CCGR5_UART_OFFSET			24
-#define MXC_CCM_CCGR5_UART_MASK				(3<<MXC_CCM_CCGR5_UART_OFFSET)
+#define MXC_CCM_CCGR5_UART_MASK				(3 << MXC_CCM_CCGR5_UART_OFFSET)
 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET		26
-#define MXC_CCM_CCGR5_UART_SERIAL_MASK			(3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
+#define MXC_CCM_CCGR5_UART_SERIAL_MASK			(3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
 
 #define MXC_CCM_CCGR6_USBOH3_OFFSET		0
-#define MXC_CCM_CCGR6_USBOH3_MASK		(3<<MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USBOH3_MASK		(3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
 #define MXC_CCM_CCGR6_USDHC1_OFFSET		2
-#define MXC_CCM_CCGR6_USDHC1_MASK		(3<<MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_MASK		(3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
 #define MXC_CCM_CCGR6_USDHC2_OFFSET		4
-#define MXC_CCM_CCGR6_USDHC2_MASK		(3<<MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_MASK		(3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
 #define MXC_CCM_CCGR6_USDHC3_OFFSET		6
-#define MXC_CCM_CCGR6_USDHC3_MASK		(3<<MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC3_MASK		(3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
 #define MXC_CCM_CCGR6_USDHC4_OFFSET		8
-#define MXC_CCM_CCGR6_USDHC4_MASK		(3<<MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_MASK		(3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET		10
-#define MXC_CCM_CCGR6_EMI_SLOW_MASK		(3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK		(3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET		12
-#define MXC_CCM_CCGR6_VDOAXICLK_MASK		(3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK		(3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
 
 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
 #define BP_ANADIG_PLL_SYS_RSVD0      20
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index d79ab2f..03abb2a 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -25,6 +25,13 @@
 
 #define ROMCP_ARB_BASE_ADDR             0x00000000
 #define ROMCP_ARB_END_ADDR              0x000FFFFF
+
+#ifdef CONFIG_MX6SL
+#define GPU_2D_ARB_BASE_ADDR            0x02200000
+#define GPU_2D_ARB_END_ADDR             0x02203FFF
+#define OPENVG_ARB_BASE_ADDR            0x02204000
+#define OPENVG_ARB_END_ADDR             0x02207FFF
+#else
 #define CAAM_ARB_BASE_ADDR              0x00100000
 #define CAAM_ARB_END_ADDR               0x00103FFF
 #define APBH_DMA_ARB_BASE_ADDR          0x00110000
@@ -37,9 +44,19 @@
 #define GPU_2D_ARB_END_ADDR             0x00137FFF
 #define DTCP_ARB_BASE_ADDR              0x00138000
 #define DTCP_ARB_END_ADDR               0x0013BFFF
+#endif	/* CONFIG_MX6SL */
+
+#define MXS_APBH_BASE			APBH_DMA_ARB_BASE_ADDR
+#define MXS_GPMI_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
 
 /* GPV - PL301 configuration ports */
+#ifdef CONFIG_MX6SL
+#define GPV2_BASE_ADDR                  0x00D00000
+#else
 #define GPV2_BASE_ADDR			0x00200000
+#endif
+
 #define GPV3_BASE_ADDR			0x00300000
 #define GPV4_BASE_ADDR			0x00800000
 #define IRAM_BASE_ADDR			0x00900000
@@ -70,10 +87,17 @@
 #define WEIM_ARB_BASE_ADDR              0x08000000
 #define WEIM_ARB_END_ADDR               0x0FFFFFFF
 
+#ifdef CONFIG_MX6SL
+#define MMDC0_ARB_BASE_ADDR             0x80000000
+#define MMDC0_ARB_END_ADDR              0xFFFFFFFF
+#define MMDC1_ARB_BASE_ADDR             0xC0000000
+#define MMDC1_ARB_END_ADDR              0xFFFFFFFF
+#else
 #define MMDC0_ARB_BASE_ADDR             0x10000000
 #define MMDC0_ARB_END_ADDR              0x7FFFFFFF
 #define MMDC1_ARB_BASE_ADDR             0x80000000
 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
+#endif
 
 #define IPU_SOC_BASE_ADDR		IPU1_ARB_BASE_ADDR
 #define IPU_SOC_OFFSET			0x00200000
@@ -89,6 +113,16 @@
 #define ECSPI2_BASE_ADDR            (ATZ1_BASE_ADDR + 0x0C000)
 #define ECSPI3_BASE_ADDR            (ATZ1_BASE_ADDR + 0x10000)
 #define ECSPI4_BASE_ADDR            (ATZ1_BASE_ADDR + 0x14000)
+#ifdef CONFIG_MX6SL
+#define UART5_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x18000)
+#define UART1_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x20000)
+#define UART2_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x24000)
+#define SSI1_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x28000)
+#define SSI2_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x2C000)
+#define SSI3_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x30000)
+#define UART3_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x34000)
+#define UART4_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x38000)
+#else
 #define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
@@ -96,6 +130,8 @@
 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
 #define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
+#endif
+
 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
 #define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
 #define AIPS1_ON_BASE_ADDR          (ATZ1_BASE_ADDR + 0x7C000)
@@ -128,18 +164,35 @@
 #define SRC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x58000)
 #define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
 #define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
+#ifdef CONFIG_MX6SL
+#define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x64000)
+#define SIPIX_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#else
 #define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
 #define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#endif
 
 #define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
 #define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
+#ifdef CONFIG_MX6SL
+#define USBO2H_PL301_IPS_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x0000)
+#define USBO2H_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
+#else
 #define USBOH3_PL301_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x0000)
 #define USBOH3_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
+#endif
+
 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
+#ifdef CONFIG_MX6SL
+#define MSHC_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
+#else
 #define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
+#endif
+
 #define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
 #define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
 #define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
@@ -149,7 +202,12 @@
 #define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
 #define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
+#ifdef CONFIG_MX6SL
+#define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
+#else
 #define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
+#endif
+
 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
@@ -171,7 +229,6 @@
 
 #define CHIP_REV_1_0                 0x10
 #define IRAM_SIZE                    0x00040000
-#define IMX_IIM_BASE                 OCOTP_BASE_ADDR
 #define FEC_QUIRK_ENET_MAC
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
@@ -200,12 +257,6 @@
 	u32     gpr10;
 };
 
-/* OCOTP Registers */
-struct ocotp_regs {
-	u32	reserved[0x198];
-	u32	gp1;	/* 0x660 */
-};
-
 /* GPR3 bitfields */
 #define IOMUXC_GPR3_GPU_DBG_OFFSET		29
 #define IOMUXC_GPR3_GPU_DBG_MASK		(3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
@@ -365,14 +416,22 @@
 #define MXC_CSPICON_POL		4
 #define MXC_CSPICON_PHA		0
 #define MXC_CSPICON_SSPOL	12
+#ifdef CONFIG_MX6SL
+#define MXC_SPI_BASE_ADDRESSES \
+	ECSPI1_BASE_ADDR, \
+	ECSPI2_BASE_ADDR, \
+	ECSPI3_BASE_ADDR, \
+	ECSPI4_BASE_ADDR
+#else
 #define MXC_SPI_BASE_ADDRESSES \
 	ECSPI1_BASE_ADDR, \
 	ECSPI2_BASE_ADDR, \
 	ECSPI3_BASE_ADDR, \
 	ECSPI4_BASE_ADDR, \
 	ECSPI5_BASE_ADDR
+#endif
 
-struct iim_regs {
+struct ocotp_regs {
 	u32	ctrl;
 	u32	ctrl_set;
 	u32     ctrl_clr;
@@ -383,9 +442,9 @@
 	u32     rsvd1[3];
 	u32     read_ctrl;
 	u32     rsvd2[3];
-	u32     fuse_data;
+	u32	read_fuse_data;
 	u32     rsvd3[3];
-	u32     sticky;
+	u32	sw_sticky;
 	u32     rsvd4[3];
 	u32     scs;
 	u32     scs_set;
@@ -400,7 +459,16 @@
 
 	struct fuse_bank {
 		u32	fuse_regs[0x20];
-	} bank[15];
+	} bank[16];
+};
+
+struct fuse_bank0_regs {
+	u32	lock;
+	u32	rsvd0[3];
+	u32	uid_low;
+	u32	rsvd1[3];
+	u32	uid_high;
+	u32	rsvd2[0x17];
 };
 
 struct fuse_bank4_regs {
@@ -411,7 +479,11 @@
 	u32	mac_addr_low;
 	u32     rsvd2[3];
 	u32     mac_addr_high;
-	u32	rsvd3[0x13];
+	u32	rsvd3[0xb];
+	u32	gp1;
+	u32	rsvd4[3];
+	u32	gp2;
+	u32	rsvd5[3];
 };
 
 struct aipstz_regs {
diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h
index 63f4856..ce865a6 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -24,7 +24,11 @@
 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
 #include "mx6dl_pins.h"
 #else
+#if defined(CONFIG_MX6SL)
+#include "mx6sl_pins.h"
+#else
 #error "Please select cpu"
+#endif	/* CONFIG_MX6SL */
 #endif	/* CONFIG_MX6DL or CONFIG_MX6S */
 #endif	/* CONFIG_MX6Q */
 
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index 9846f1b..a4134a0 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -22,33 +22,6 @@
 
 #include <asm/imx-common/iomux-v3.h>
 
-/* Use to set PAD control */
-#define PAD_CTL_HYS		(1 << 16)
-#define PAD_CTL_PUS_100K_DOWN	(0 << 14)
-#define PAD_CTL_PUS_47K_UP	(1 << 14)
-#define PAD_CTL_PUS_100K_UP	(2 << 14)
-#define PAD_CTL_PUS_22K_UP	(3 << 14)
-
-#define PAD_CTL_PUE		(1 << 13)
-#define PAD_CTL_PKE		(1 << 12)
-#define PAD_CTL_ODE		(1 << 11)
-#define PAD_CTL_SPEED_LOW	(1 << 6)
-#define PAD_CTL_SPEED_MED	(2 << 6)
-#define PAD_CTL_SPEED_HIGH	(3 << 6)
-#define PAD_CTL_DSE_DISABLE	(0 << 3)
-#define PAD_CTL_DSE_240ohm	(1 << 3)
-#define PAD_CTL_DSE_120ohm	(2 << 3)
-#define PAD_CTL_DSE_80ohm	(3 << 3)
-#define PAD_CTL_DSE_60ohm	(4 << 3)
-#define PAD_CTL_DSE_48ohm	(5 << 3)
-#define PAD_CTL_DSE_40ohm	(6 << 3)
-#define PAD_CTL_DSE_34ohm	(7 << 3)
-#define PAD_CTL_SRE_FAST	(1 << 0)
-#define PAD_CTL_SRE_SLOW	(0 << 0)
-
-#define IOMUX_CONFIG_SION 0x10
-#define NO_MUX_I                0
-#define NO_PAD_I                0
 enum {
 	MX6_PAD_CSI0_DAT10__UART1_TXD		= IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0),
 	MX6_PAD_CSI0_DAT11__UART1_RXD		= IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0),
@@ -93,6 +66,7 @@
 	MX6_PAD_EIM_D28__I2C1_SDA		= IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
 	MX6_PAD_EIM_D28__GPIO_3_28		= IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
 	MX6_PAD_EIM_D29__GPIO_3_29		= IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0),
+	MX6_PAD_EIM_DA9__GPIO_3_9		= IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET_MDC__ENET_MDC		= IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0,  0),
 	MX6_PAD_ENET_MDIO__ENET_MDIO		= IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	= IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
@@ -102,6 +76,7 @@
 	MX6_PAD_GPIO_17__GPIO_7_12		= IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
 	MX6_PAD_GPIO_18__GPIO_7_13		= IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
 	MX6_PAD_GPIO_19__GPIO_4_5		= IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO_2__GPIO_1_2		= IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
 	MX6_PAD_GPIO_5__GPIO_1_5		= IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
 	MX6_PAD_GPIO_5__I2C3_SCL		= IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
 	MX6_PAD_KEY_COL3__I2C2_SCL		= IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
@@ -134,8 +109,14 @@
 	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	= IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	= IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	= IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__USDHC1_CLK		= IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0),
+	MX6_PAD_SD1_CMD__USDHC1_CMD		= IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
 	MX6_PAD_SD1_CMD__GPIO_1_18		= IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
 	MX6_PAD_SD1_DAT3__GPIO_1_21		= IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT0__USDHC1_DAT0		= IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT1__USDHC1_DAT1		= IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT2__USDHC1_DAT2		= IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT3__USDHC1_DAT3		= IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0),
 	MX6_PAD_SD3_CLK__USDHC3_CLK		= IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
 	MX6_PAD_SD3_CMD__USDHC3_CMD		= IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
 	MX6_PAD_SD3_DAT0__USDHC3_DAT0		= IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 1c1c008..02a40d4 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -24,33 +24,6 @@
 
 #include <asm/imx-common/iomux-v3.h>
 
-/* Use to set PAD control */
-#define PAD_CTL_HYS		(1 << 16)
-#define PAD_CTL_PUS_100K_DOWN	(0 << 14)
-#define PAD_CTL_PUS_47K_UP	(1 << 14)
-#define PAD_CTL_PUS_100K_UP	(2 << 14)
-#define PAD_CTL_PUS_22K_UP	(3 << 14)
-
-#define PAD_CTL_PUE		(1 << 13)
-#define PAD_CTL_PKE		(1 << 12)
-#define PAD_CTL_ODE		(1 << 11)
-#define PAD_CTL_SPEED_LOW	(1 << 6)
-#define PAD_CTL_SPEED_MED	(2 << 6)
-#define PAD_CTL_SPEED_HIGH	(3 << 6)
-#define PAD_CTL_DSE_DISABLE	(0 << 3)
-#define PAD_CTL_DSE_240ohm	(1 << 3)
-#define PAD_CTL_DSE_120ohm	(2 << 3)
-#define PAD_CTL_DSE_80ohm	(3 << 3)
-#define PAD_CTL_DSE_60ohm	(4 << 3)
-#define PAD_CTL_DSE_48ohm	(5 << 3)
-#define PAD_CTL_DSE_40ohm	(6 << 3)
-#define PAD_CTL_DSE_34ohm	(7 << 3)
-#define PAD_CTL_SRE_FAST	(1 << 0)
-#define PAD_CTL_SRE_SLOW	(0 << 0)
-
-#define NO_MUX_I                0
-#define NO_PAD_I                0
-
 enum {
 	MX6_PAD_SD2_DAT1__USDHC2_DAT1		= IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
 	MX6_PAD_SD2_DAT1__ECSPI5_SS0		= IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
new file mode 100644
index 0000000..3c0ede0
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__
+#define __ASM_ARCH_MX6_MX6SL_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+enum {
+	MX6_PAD_SD2_CLK__USDHC2_CLK				= IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_CMD__USDHC2_CMD				= IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT0__USDHC2_DAT0				= IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT1__USDHC2_DAT1				= IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT2__USDHC2_DAT2				= IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT3__USDHC2_DAT3				= IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
+	MX6_PAD_UART1_RXD__UART1_RXD				= IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
+	MX6_PAD_UART1_TXD__UART1_TXD				= IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
+};
+#endif	/* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 3193297..38e4e51 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -24,6 +24,8 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
+#include <asm/imx-common/regs-common.h>
+
 #define MXC_CPU_MX51		0x51
 #define MXC_CPU_MX53		0x53
 #define MXC_CPU_MX6SL		0x60
@@ -46,4 +48,12 @@
 int fecmxc_initialize(bd_t *bis);
 u32 get_ahb_clk(void);
 u32 get_periph_clk(void);
+
+int mxs_reset_block(struct mxs_register_32 *reg);
+int mxs_wait_mask_set(struct mxs_register_32 *reg,
+		       uint32_t mask,
+		       unsigned int timeout);
+int mxs_wait_mask_clr(struct mxs_register_32 *reg,
+		       uint32_t mask,
+		       unsigned int timeout);
 #endif
diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h
index 3f7d3f0..9be53f0 100644
--- a/arch/arm/include/asm/arch-mxs/clock.h
+++ b/arch/arm/include/asm/arch-mxs/clock.h
@@ -59,6 +59,7 @@
 void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
 void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
 void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
+void mxs_set_lcdclk(uint32_t freq);
 
 /* Compatibility with the FEC Ethernet driver */
 #define	imx_get_fecclk()	mxc_get_clock(MXC_AHB_CLK)
diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h
index 8f67497..dc21e34 100644
--- a/arch/arm/include/asm/arch-mxs/imx-regs.h
+++ b/arch/arm/include/asm/arch-mxs/imx-regs.h
@@ -23,11 +23,11 @@
 #ifndef __IMX_REGS_H__
 #define __IMX_REGS_H__
 
-#include <asm/arch/regs-apbh.h>
+#include <asm/imx-common/regs-apbh.h>
 #include <asm/arch/regs-base.h>
-#include <asm/arch/regs-bch.h>
+#include <asm/imx-common/regs-bch.h>
 #include <asm/arch/regs-digctl.h>
-#include <asm/arch/regs-gpmi.h>
+#include <asm/imx-common/regs-gpmi.h>
 #include <asm/arch/regs-i2c.h>
 #include <asm/arch/regs-lcdif.h>
 #include <asm/arch/regs-lradc.h>
diff --git a/arch/arm/include/asm/arch-mxs/iomux.h b/arch/arm/include/asm/arch-mxs/iomux.h
index 4288715..d919fb2 100644
--- a/arch/arm/include/asm/arch-mxs/iomux.h
+++ b/arch/arm/include/asm/arch-mxs/iomux.h
@@ -71,7 +71,11 @@
 #define PAD_16MA		3
 
 #define PAD_1V8			0
+#if defined(CONFIG_MX28)
 #define PAD_3V3			1
+#else
+#define PAD_3V3			0
+#endif
 
 #define PAD_NOPULL		0
 #define PAD_PULLUP		1
diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
index 62810ec..c3cba33 100644
--- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
@@ -26,7 +26,7 @@
 #ifndef __MX23_REGS_CLKCTRL_H__
 #define __MX23_REGS_CLKCTRL_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_clkctrl_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
index 23e9adc..1c2c82e 100644
--- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
@@ -26,7 +26,7 @@
 #ifndef __MX28_REGS_CLKCTRL_H__
 #define __MX28_REGS_CLKCTRL_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_clkctrl_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-digctl.h b/arch/arm/include/asm/arch-mxs/regs-digctl.h
index d043325..d4a3966 100644
--- a/arch/arm/include/asm/arch-mxs/regs-digctl.h
+++ b/arch/arm/include/asm/arch-mxs/regs-digctl.h
@@ -22,7 +22,7 @@
 #ifndef __MX28_REGS_DIGCTL_H__
 #define __MX28_REGS_DIGCTL_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_digctl_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-i2c.h b/arch/arm/include/asm/arch-mxs/regs-i2c.h
index 067cfd3..d062b5b 100644
--- a/arch/arm/include/asm/arch-mxs/regs-i2c.h
+++ b/arch/arm/include/asm/arch-mxs/regs-i2c.h
@@ -23,7 +23,7 @@
 #ifndef __MX28_REGS_I2C_H__
 #define __MX28_REGS_I2C_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_i2c_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-lcdif.h b/arch/arm/include/asm/arch-mxs/regs-lcdif.h
index b90b2d4..59ce236 100644
--- a/arch/arm/include/asm/arch-mxs/regs-lcdif.h
+++ b/arch/arm/include/asm/arch-mxs/regs-lcdif.h
@@ -26,16 +26,23 @@
 #ifndef __MX28_REGS_LCDIF_H__
 #define __MX28_REGS_LCDIF_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_lcdif_regs {
 	mxs_reg_32(hw_lcdif_ctrl)		/* 0x00 */
 	mxs_reg_32(hw_lcdif_ctrl1)		/* 0x10 */
+#if defined(CONFIG_MX28)
 	mxs_reg_32(hw_lcdif_ctrl2)		/* 0x20 */
-	mxs_reg_32(hw_lcdif_transfer_count)	/* 0x30 */
-	mxs_reg_32(hw_lcdif_cur_buf)		/* 0x40 */
-	mxs_reg_32(hw_lcdif_next_buf)		/* 0x50 */
+#endif
+	mxs_reg_32(hw_lcdif_transfer_count)	/* 0x20/0x30 */
+	mxs_reg_32(hw_lcdif_cur_buf)		/* 0x30/0x40 */
+	mxs_reg_32(hw_lcdif_next_buf)		/* 0x40/0x50 */
+
+#if defined(CONFIG_MX23)
+	uint32_t	reserved1[4];
+#endif
+
 	mxs_reg_32(hw_lcdif_timing)		/* 0x60 */
 	mxs_reg_32(hw_lcdif_vdctrl0)		/* 0x70 */
 	mxs_reg_32(hw_lcdif_vdctrl1)		/* 0x80 */
@@ -54,13 +61,19 @@
 	mxs_reg_32(hw_lcdif_csc_coeffctrl4)	/* 0x150 */
 	mxs_reg_32(hw_lcdif_csc_offset)	/* 0x160 */
 	mxs_reg_32(hw_lcdif_csc_limit)		/* 0x170 */
-	mxs_reg_32(hw_lcdif_data)		/* 0x180 */
-	mxs_reg_32(hw_lcdif_bm_error_stat)	/* 0x190 */
+
+#if defined(CONFIG_MX23)
+	uint32_t	reserved2[12];
+#endif
+	mxs_reg_32(hw_lcdif_data)		/* 0x1b0/0x180 */
+	mxs_reg_32(hw_lcdif_bm_error_stat)	/* 0x1c0/0x190 */
+#if defined(CONFIG_MX28)
 	mxs_reg_32(hw_lcdif_crc_stat)		/* 0x1a0 */
-	mxs_reg_32(hw_lcdif_lcdif_stat)	/* 0x1b0 */
-	mxs_reg_32(hw_lcdif_version)		/* 0x1c0 */
-	mxs_reg_32(hw_lcdif_debug0)		/* 0x1d0 */
-	mxs_reg_32(hw_lcdif_debug1)		/* 0x1e0 */
+#endif
+	mxs_reg_32(hw_lcdif_lcdif_stat)		/* 0x1d0/0x1b0 */
+	mxs_reg_32(hw_lcdif_version)		/* 0x1e0/0x1c0 */
+	mxs_reg_32(hw_lcdif_debug0)		/* 0x1f0/0x1d0 */
+	mxs_reg_32(hw_lcdif_debug1)		/* 0x200/0x1e0 */
 	mxs_reg_32(hw_lcdif_debug2)		/* 0x1f0 */
 };
 #endif
@@ -191,8 +204,13 @@
 #define	LCDIF_VDCTRL1_VSYNC_PERIOD_MASK				0xffffffff
 #define	LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET			0
 
+#if defined(CONFIG_MX23)
+#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0xff << 24)
+#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			24
+#elif defined(CONFIG_MX28)
 #define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0x3fff << 18)
 #define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			18
+#endif
 #define	LCDIF_VDCTRL2_HSYNC_PERIOD_MASK				0x3ffff
 #define	LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET			0
 
diff --git a/arch/arm/include/asm/arch-mxs/regs-lradc.h b/arch/arm/include/asm/arch-mxs/regs-lradc.h
index 28d8382..23fd0e3 100644
--- a/arch/arm/include/asm/arch-mxs/regs-lradc.h
+++ b/arch/arm/include/asm/arch-mxs/regs-lradc.h
@@ -26,7 +26,7 @@
 #ifndef __MX28_REGS_LRADC_H__
 #define __MX28_REGS_LRADC_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_lradc_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-ocotp.h b/arch/arm/include/asm/arch-mxs/regs-ocotp.h
index 3269892..5af3855 100644
--- a/arch/arm/include/asm/arch-mxs/regs-ocotp.h
+++ b/arch/arm/include/asm/arch-mxs/regs-ocotp.h
@@ -26,7 +26,7 @@
 #ifndef __MX28_REGS_OCOTP_H__
 #define __MX28_REGS_OCOTP_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_ocotp_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h
index d584170..191093b 100644
--- a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h
+++ b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h
@@ -26,7 +26,7 @@
 #ifndef __MX28_REGS_PINCTRL_H__
 #define __MX28_REGS_PINCTRL_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_pinctrl_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
index 51a981a..a7430c4 100644
--- a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
+++ b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
@@ -22,7 +22,7 @@
 #ifndef __MX23_REGS_POWER_H__
 #define __MX23_REGS_POWER_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_power_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx28.h b/arch/arm/include/asm/arch-mxs/regs-power-mx28.h
index 257ee88..4a73b1c 100644
--- a/arch/arm/include/asm/arch-mxs/regs-power-mx28.h
+++ b/arch/arm/include/asm/arch-mxs/regs-power-mx28.h
@@ -22,7 +22,7 @@
 #ifndef __MX28_REGS_POWER_H__
 #define __MX28_REGS_POWER_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_power_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-rtc.h b/arch/arm/include/asm/arch-mxs/regs-rtc.h
index 6b2dd33..1926546 100644
--- a/arch/arm/include/asm/arch-mxs/regs-rtc.h
+++ b/arch/arm/include/asm/arch-mxs/regs-rtc.h
@@ -23,7 +23,7 @@
 #ifndef __MX28_REGS_RTC_H__
 #define __MX28_REGS_RTC_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_rtc_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h
index 5920f9b..0b61fa9d 100644
--- a/arch/arm/include/asm/arch-mxs/regs-ssp.h
+++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h
@@ -25,7 +25,7 @@
 #ifndef __MX28_REGS_SSP_H__
 #define __MX28_REGS_SSP_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 #if defined(CONFIG_MX23)
diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h
index f8537f1..df343bd 100644
--- a/arch/arm/include/asm/arch-mxs/regs-timrot.h
+++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h
@@ -25,7 +25,7 @@
 #ifndef __MX28_REGS_TIMROT_H__
 #define __MX28_REGS_TIMROT_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_timrot_regs {
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index ad984da..44353a4 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -141,42 +141,7 @@
  */
 #define NON_SECURE_SRAM_START	0x40304000
 #define NON_SECURE_SRAM_END	0x4030E000	/* Not inclusive */
+#define SRAM_SCRATCH_SPACE_ADDR	NON_SECURE_SRAM_START
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4030D000
-/* Temporary SRAM stack used while low level init is done */
-#define SRAM_SCRATCH_SPACE_ADDR		NON_SECURE_SRAM_START
-/* SRAM scratch space entries */
-#define OMAP4_SRAM_SCRATCH_OMAP4_REV	SRAM_SCRATCH_SPACE_ADDR
-#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
-#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
-#define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
-#define OMAP_SRAM_SCRATCH_VCORES_PTR	(SRAM_SCRATCH_SPACE_ADDR + 0x1C)
-#define OMAP4_SRAM_SCRATCH_SYS_CTRL	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
-#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x24)
-
-/* ROM code defines */
-/* Boot device */
-#define BOOT_DEVICE_MASK	0xFF
-#define BOOT_DEVICE_OFFSET	0x8
-#define DEV_DESC_PTR_OFFSET	0x4
-#define DEV_DATA_PTR_OFFSET	0x18
-#define BOOT_MODE_OFFSET	0x8
-#define RESET_REASON_OFFSET	0x9
-#define CH_FLAGS_OFFSET		0xA
-
-#define CH_FLAGS_CHSETTINGS	(0x1 << 0)
-#define CH_FLAGS_CHRAM		(0x1 << 1)
-#define CH_FLAGS_CHFLASH	(0x1 << 2)
-#define CH_FLAGS_CHMMCSD	(0x1 << 3)
-
-#ifndef __ASSEMBLY__
-struct omap_boot_parameters {
-	char *boot_message;
-	unsigned int mem_boot_descriptor;
-	unsigned char omap_bootdevice;
-	unsigned char reset_reason;
-	unsigned char ch_flags;
-};
-#endif
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index d5f1868..ef85594 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -27,6 +27,8 @@
 #include <asm/omap_common.h>
 #include <asm/arch/mux_omap4.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 struct omap_sysinfo {
 	char *board_string;
 };
@@ -52,19 +54,14 @@
 void sdram_init(void);
 u32 omap_sdram_size(void);
 u32 cortex_rev(void);
+void save_omap_boot_params(void);
 void init_omap_revision(void);
 void do_io_settings(void);
 void omap_vc_init(u16 speed_khz);
 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 u32 warm_reset(void);
 void force_emif_self_refresh(void);
-/*
- * This is used to verify if the configuration header
- * was executed by Romcode prior to control of transfer
- * to the bootloader. SPL is responsible for saving and
- * passing this to the u-boot.
- */
-extern struct omap_boot_parameters boot_params;
+void setup_warmreset_time(void);
 
 static inline u32 running_from_sdram(void)
 {
@@ -84,7 +81,7 @@
 	 * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
 	 * mandatory section if CH is present.
 	 */
-	if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
+	if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
 		return 0;
 	else
 		return running_from_sdram();
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index cfde374..68afa76 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -190,6 +190,10 @@
 #define OPTFCLKEN_SRCOMP_FCLK_SHIFT		8
 #define OPTFCLKEN_SRCOMP_FCLK_MASK		(1 << 8)
 
+/* PRM_RSTTIME */
+#define RSTTIME1_SHIFT				0
+#define RSTTIME1_MASK				(0x3ff << 0)
+
 /* Clock frequencies */
 #define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
 #define OMAP_SYS_CLK_IND_38_4_MHZ	6
@@ -251,4 +255,10 @@
 #define DPLL_NO_LOCK	0
 #define DPLL_LOCK	1
 
+/*
+ * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
+ * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
+ * into microsec and passing the value.
+ */
+#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC	31219
 #endif /* _CLOCKS_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index 5e62013..044ab55 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -142,6 +142,8 @@
 #define I2C_BASE1		(OMAP54XX_L4_PER_BASE + 0x70000)
 #define I2C_BASE2		(OMAP54XX_L4_PER_BASE + 0x72000)
 #define I2C_BASE3		(OMAP54XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4		(OMAP54XX_L4_PER_BASE + 0x7A000)
+#define I2C_BASE5		(OMAP54XX_L4_PER_BASE + 0x7C000)
 
 /* MUSB base */
 #define MUSB_BASE		(OMAP54XX_L4_CORE_BASE + 0xAB000)
diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h
index 68be03b..ec39a53 100644
--- a/arch/arm/include/asm/arch-omap5/i2c.h
+++ b/arch/arm/include/asm/arch-omap5/i2c.h
@@ -23,7 +23,7 @@
 #ifndef _OMAP5_I2C_H_
 #define _OMAP5_I2C_H_
 
-#define I2C_BUS_MAX	3
+#define I2C_BUS_MAX	5
 #define I2C_DEFAULT_BASE	I2C_BASE1
 
 struct i2c {
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 887fcaa..04af227 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -188,22 +188,10 @@
  */
 #define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */
+#define SRAM_SCRATCH_SPACE_ADDR	NON_SECURE_SRAM_START
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4031F000
 
-#define SRAM_SCRATCH_SPACE_ADDR		NON_SECURE_SRAM_START
-/*
- * SRAM scratch space entries
- */
-#define OMAP5_SRAM_SCRATCH_OMAP5_REV	SRAM_SCRATCH_SPACE_ADDR
-#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
-#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
-#define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
-#define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
-#define OMAP5_SRAM_SCRATCH_SYS_CTRL	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
-#define OMAP5_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x24)
-
 /* Silicon revisions */
 #define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
 #define OMAP4430_ES1_0	0x44300100
@@ -214,21 +202,6 @@
 #define OMAP4460_ES1_0	0x44600100
 #define OMAP4460_ES1_1	0x44600110
 
-/* ROM code defines */
-/* Boot device */
-#define BOOT_DEVICE_MASK	0xFF
-#define BOOT_DEVICE_OFFSET	0x8
-#define DEV_DESC_PTR_OFFSET	0x4
-#define DEV_DATA_PTR_OFFSET	0x18
-#define BOOT_MODE_OFFSET	0x8
-#define RESET_REASON_OFFSET     0x9
-#define CH_FLAGS_OFFSET         0xA
-
-#define CH_FLAGS_CHSETTINGS	(0x1 << 0)
-#define	CH_FLAGS_CHRAM		(0x1 << 1)
-#define CH_FLAGS_CHFLASH	(0x1 << 2)
-#define CH_FLAGS_CHMMCSD	(0x1 << 3)
-
 /* CONTROL_SRCOMP_XXX_SIDE */
 #define OVERRIDE_XS_SHIFT		30
 #define OVERRIDE_XS_MASK		(1 << 30)
@@ -249,14 +222,6 @@
 	s8 multiply_factor;
 };
 
-struct omap_boot_parameters {
-	char *boot_message;
-	unsigned int mem_boot_descriptor;
-	unsigned char omap_bootdevice;
-	unsigned char reset_reason;
-	unsigned char ch_flags;
-};
-
 struct ctrl_ioregs {
 	u32 ctrl_ddrch;
 	u32 ctrl_lpddr2ch;
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index e66ab44..4d99db9 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -27,6 +27,8 @@
 #include <asm/omap_common.h>
 #include <asm/arch/clocks.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 struct pad_conf_entry {
 	u32 offset;
 	u32 val;
@@ -56,6 +58,7 @@
 void sdram_init(void);
 u32 omap_sdram_size(void);
 u32 cortex_rev(void);
+void save_omap_boot_params(void);
 void init_omap_revision(void);
 void do_io_settings(void);
 void omap_vc_init(u16 speed_khz);
@@ -64,14 +67,7 @@
 void force_emif_self_refresh(void);
 void get_ioregs(const struct ctrl_ioregs **regs);
 void srcomp_enable(void);
-
-/*
- * This is used to verify if the configuration header
- * was executed by Romcode prior to control of transfer
- * to the bootloader. SPL is responsible for saving and
- * passing this to the u-boot.
- */
-extern struct omap_boot_parameters boot_params;
+void setup_warmreset_time(void);
 
 static inline u32 running_from_sdram(void)
 {
@@ -91,7 +87,7 @@
 	 * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
 	 * mandatory section if CH is present.
 	 */
-	if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
+	if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
 		return 0;
 	else
 		return running_from_sdram();
@@ -122,4 +118,13 @@
 #endif
 }
 
+static inline u32 div_round_up(u32 num, u32 den)
+{
+	return (num + den - 1)/den;
+}
+
+static inline u32 usec_to_32k(u32 usec)
+{
+	return div_round_up(32768 * usec, 1000000);
+}
 #endif
diff --git a/arch/arm/include/asm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h
index 44b800f..2397bce 100644
--- a/arch/arm/include/asm/arch-pxa/hardware.h
+++ b/arch/arm/include/asm/arch-pxa/hardware.h
@@ -77,17 +77,6 @@
 #define GPIO_FALLING_EDGE	1
 #define GPIO_RISING_EDGE	2
 #define GPIO_BOTH_EDGES		3
-extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask );
-
-/*
- * Handy routine to set GPIO alternate functions
- */
-extern void set_GPIO_mode( int gpio_mode );
-
-/*
- * return current lclk frequency in units of 10kHz
- */
-extern unsigned int get_lclk_frequency_10khz(void);
 
 #endif
 
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 3e642e9..5fe4838d 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -72,6 +72,7 @@
 
 /* These are the available SKUs (product types) for Tegra */
 enum {
+	SKU_ID_T20_7		= 0x7,
 	SKU_ID_T20		= 0x8,
 	SKU_ID_T25SE		= 0x14,
 	SKU_ID_AP25		= 0x17,
@@ -81,6 +82,7 @@
 	SKU_ID_T33		= 0x80,
 	SKU_ID_T30		= 0x81, /* Cardhu value */
 	SKU_ID_T114_ENG		= 0x00, /* Dalmore value, unfused */
+	SKU_ID_T114_1		= 0x01,
 };
 
 /*
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index d0c69da..8b8a91a 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -23,16 +23,28 @@
 #ifndef _ASM_ARCH_HARDWARE_H
 #define _ASM_ARCH_HARDWARE_H
 
-#define XPSS_SYS_CTRL_BASEADDR		0xF8000000
-#define XPSS_DEV_CFG_APB_BASEADDR	0xF8007000
-#define XPSS_SCU_BASEADDR		0xF8F00000
+#define ZYNQ_SYS_CTRL_BASEADDR		0xF8000000
+#define ZYNQ_DEV_CFG_APB_BASEADDR	0xF8007000
+#define ZYNQ_SCU_BASEADDR		0xF8F00000
+#define ZYNQ_SCUTIMER_BASEADDR		0xF8F00600
+#define ZYNQ_GEM_BASEADDR0		0xE000B000
+#define ZYNQ_GEM_BASEADDR1		0xE000C000
+#define ZYNQ_SDHCI_BASEADDR0		0xE0100000
+#define ZYNQ_SDHCI_BASEADDR1		0xE0101000
+#define ZYNQ_I2C_BASEADDR0		0xE0004000
+#define ZYNQ_I2C_BASEADDR1		0xE0005000
 
 /* Reflect slcr offsets */
 struct slcr_regs {
 	u32 scl; /* 0x0 */
 	u32 slcr_lock; /* 0x4 */
 	u32 slcr_unlock; /* 0x8 */
-	u32 reserved1[125];
+	u32 reserved0[75];
+	u32 gem0_rclk_ctrl; /* 0x138 */
+	u32 gem1_rclk_ctrl; /* 0x13c */
+	u32 gem0_clk_ctrl; /* 0x140 */
+	u32 gem1_clk_ctrl; /* 0x144 */
+	u32 reserved1[46];
 	u32 pss_rst_ctrl; /* 0x200 */
 	u32 reserved2[15];
 	u32 fpga_rst_ctrl; /* 0x240 */
@@ -41,15 +53,21 @@
 	u32 boot_mode; /* 0x25c */
 	u32 reserved4[116];
 	u32 trust_zone; /* 0x430 */ /* FIXME */
-	u32 reserved5[115];
+	u32 reserved5_1[63];
+	u32 pss_idcode; /* 0x530 */
+	u32 reserved5_2[51];
 	u32 ddr_urgent; /* 0x600 */
 	u32 reserved6[6];
 	u32 ddr_urgent_sel; /* 0x61c */
-	u32 reserved7[188];
+	u32 reserved7[56];
+	u32 mio_pin[54]; /* 0x700 - 0x7D4 */
+	u32 reserved8[74];
+	u32 lvl_shftr_en; /* 0x900 */
+	u32 reserved9[3];
 	u32 ocm_cfg; /* 0x910 */
 };
 
-#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
+#define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
 
 struct devcfg_regs {
 	u32 ctrl; /* 0x0 */
@@ -72,7 +90,7 @@
 	u32 read_count; /* 0x8c */
 };
 
-#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR)
+#define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
 
 struct scu_regs {
 	u32 reserved1[16];
@@ -80,6 +98,6 @@
 	u32 filter_end; /* 0x44 */
 };
 
-#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR)
+#define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
 
 #endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index e788900..2317121 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -26,5 +26,12 @@
 extern void zynq_slcr_lock(void);
 extern void zynq_slcr_unlock(void);
 extern void zynq_slcr_cpu_reset(void);
+extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
+extern void zynq_slcr_devcfg_disable(void);
+extern void zynq_slcr_devcfg_enable(void);
+extern u32 zynq_slcr_get_idcode(void);
+
+/* Driver extern functions */
+extern int zynq_sdhci_init(u32 regbase);
 
 #endif /* _SYS_PROTO_H_ */
diff --git a/arch/arm/include/asm/bootm.h b/arch/arm/include/asm/bootm.h
index db2ff94..2c4fa19 100644
--- a/arch/arm/include/asm/bootm.h
+++ b/arch/arm/include/asm/bootm.h
@@ -1,4 +1,7 @@
-/* Copyright (C) 2011
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * Copyright (C) 2011
  * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -19,8 +22,55 @@
 #ifndef ARM_BOOTM_H
 #define ARM_BOOTM_H
 
-#ifdef CONFIG_USB_DEVICE
 extern void udc_disconnect(void);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+		defined(CONFIG_CMDLINE_TAG) || \
+		defined(CONFIG_INITRD_TAG) || \
+		defined(CONFIG_SERIAL_TAG) || \
+		defined(CONFIG_REVISION_TAG)
+# define BOOTM_ENABLE_TAGS		1
+#else
+# define BOOTM_ENABLE_TAGS		0
+#endif
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+# define BOOTM_ENABLE_MEMORY_TAGS	1
+#else
+# define BOOTM_ENABLE_MEMORY_TAGS	0
+#endif
+
+#ifdef CONFIG_CMDLINE_TAG
+ #define BOOTM_ENABLE_CMDLINE_TAG	1
+#else
+ #define BOOTM_ENABLE_CMDLINE_TAG	0
+#endif
+
+#ifdef CONFIG_INITRD_TAG
+ #define BOOTM_ENABLE_INITRD_TAG	1
+#else
+ #define BOOTM_ENABLE_INITRD_TAG	0
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+ #define BOOTM_ENABLE_SERIAL_TAG	1
+void get_board_serial(struct tag_serialnr *serialnr);
+#else
+ #define BOOTM_ENABLE_SERIAL_TAG	0
+static inline void get_board_serial(struct tag_serialnr *serialnr)
+{
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+ #define BOOTM_ENABLE_REVISION_TAG	1
+u32 get_board_rev(void);
+#else
+ #define BOOTM_ENABLE_REVISION_TAG	0
+static inline u32 get_board_rev(void)
+{
+	return 0;
+}
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 37ac0da..7611d0a 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -24,6 +24,10 @@
 #ifndef	__ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
 
+#ifdef CONFIG_OMAP
+#include <asm/omap_boot.h>
+#endif
+
 /* Architecture-specific global data */
 struct arch_global_data {
 #if defined(CONFIG_FSL_ESDHC)
@@ -51,6 +55,10 @@
 	unsigned long tlb_addr;
 	unsigned long tlb_size;
 #endif
+
+#ifdef CONFIG_OMAP
+	struct omap_boot_parameters omap_boot_params;
+#endif
 };
 
 #include <asm-generic/global_data.h>
diff --git a/arch/arm/include/asm/arch-mxs/dma.h b/arch/arm/include/asm/imx-common/dma.h
similarity index 93%
rename from arch/arm/include/asm/arch-mxs/dma.h
rename to arch/arm/include/asm/imx-common/dma.h
index 1ac8696..cb74528 100644
--- a/arch/arm/include/asm/arch-mxs/dma.h
+++ b/arch/arm/include/asm/imx-common/dma.h
@@ -72,6 +72,18 @@
 	MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
 	MXS_MAX_DMA_CHANNELS,
 };
+#elif defined(CONFIG_MX6)
+enum {
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+	MXS_MAX_DMA_CHANNELS,
+};
 #endif
 
 /*
diff --git a/arch/arm/include/asm/imx-common/imximage.cfg b/arch/arm/include/asm/imx-common/imximage.cfg
new file mode 100644
index 0000000..95daa3d
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/imximage.cfg
@@ -0,0 +1,30 @@
+/*
+ * i.MX image header offset values
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ */
+
+/*
+ * NOTE: This file must be kept in sync with tools/imximage.h because
+ *       tools/imximage.c can not cross-include headers from arch/arm/
+ *       and vice-versa.
+ */
+
+#ifndef __ASM_IMX_COMMON_IMXIMAGE_CFG__
+#define __ASM_IMX_COMMON_IMXIMAGE_CFG__
+
+/* Standard image header offset for NAND, SATA, SD, SPI flash. */
+#define FLASH_OFFSET_STANDARD	0x400
+/* Specific image header offset for booting from OneNAND. */
+#define FLASH_OFFSET_ONENAND	0x100
+/* Specific image header offset for booting from memory-mapped NOR. */
+#define FLASH_OFFSET_NOR	0x1000
+
+#endif  /* __ASM_IMX_COMMON_IMXIMAGE_CFG__ */
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index c34bb76..0b4e763 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -23,6 +23,8 @@
 #ifndef __MACH_IOMUX_V3_H__
 #define __MACH_IOMUX_V3_H__
 
+#include <common.h>
+
 /*
  *	build IOMUX_PAD structure
  *
@@ -84,7 +86,68 @@
 	((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)|	\
 	((iomux_v3_cfg_t)(sel_input)     << MUX_SEL_INPUT_SHIFT))
 
+#define NEW_PAD_CTRL(cfg, pad)	(((cfg) & ~MUX_PAD_CTRL_MASK) | \
+					MUX_PAD_CTRL(pad))
+
+#define __NA_			0x000
+#define NO_MUX_I		0
+#define NO_PAD_I		0
+
 #define NO_PAD_CTRL		(1 << 17)
+
+#ifdef CONFIG_MX6
+
+#define PAD_CTL_HYS		(1 << 16)
+
+#define PAD_CTL_PUS_100K_DOWN	(0 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP	(1 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP	(2 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP	(3 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUE		(1 << 13 | PAD_CTL_PKE)
+#define PAD_CTL_PKE		(1 << 12)
+
+#define PAD_CTL_ODE		(1 << 11)
+
+#define PAD_CTL_SPEED_LOW	(1 << 6)
+#define PAD_CTL_SPEED_MED	(2 << 6)
+#define PAD_CTL_SPEED_HIGH	(3 << 6)
+
+#define PAD_CTL_DSE_DISABLE	(0 << 3)
+#define PAD_CTL_DSE_240ohm	(1 << 3)
+#define PAD_CTL_DSE_120ohm	(2 << 3)
+#define PAD_CTL_DSE_80ohm	(3 << 3)
+#define PAD_CTL_DSE_60ohm	(4 << 3)
+#define PAD_CTL_DSE_48ohm	(5 << 3)
+#define PAD_CTL_DSE_40ohm	(6 << 3)
+#define PAD_CTL_DSE_34ohm	(7 << 3)
+
+#else
+
+#define PAD_CTL_DVS		(1 << 13)
+#define PAD_CTL_INPUT_DDR	(1 << 9)
+#define PAD_CTL_HYS		(1 << 8)
+
+#define PAD_CTL_PKE		(1 << 7)
+#define PAD_CTL_PUE		(1 << 6 | PAD_CTL_PKE)
+#define PAD_CTL_PUS_100K_DOWN	(0 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP	(1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP	(2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP	(3 << 4 | PAD_CTL_PUE)
+
+#define PAD_CTL_ODE		(1 << 3)
+
+#define PAD_CTL_DSE_LOW		(0 << 1)
+#define PAD_CTL_DSE_MED		(1 << 1)
+#define PAD_CTL_DSE_HIGH	(2 << 1)
+#define PAD_CTL_DSE_MAX		(3 << 1)
+
+#endif
+
+#define PAD_CTL_SRE_SLOW	(0 << 0)
+#define PAD_CTL_SRE_FAST	(1 << 0)
+
+#define IOMUX_CONFIG_SION	0x10
+
 #define GPIO_PIN_MASK		0x1f
 #define GPIO_PORT_SHIFT		5
 #define GPIO_PORT_MASK		(0x7 << GPIO_PORT_SHIFT)
@@ -95,10 +158,8 @@
 #define GPIO_PORTE		(4 << GPIO_PORT_SHIFT)
 #define GPIO_PORTF		(5 << GPIO_PORT_SHIFT)
 
-#define MUX_CONFIG_SION		(0x1 << 4)
-
-int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 				     unsigned count);
 
 #endif	/* __MACH_IOMUX_V3_H__*/
diff --git a/arch/arm/include/asm/arch-mxs/regs-apbh.h b/arch/arm/include/asm/imx-common/regs-apbh.h
similarity index 96%
rename from arch/arm/include/asm/arch-mxs/regs-apbh.h
rename to arch/arm/include/asm/imx-common/regs-apbh.h
index fcef4b8..bcec6e0 100644
--- a/arch/arm/include/asm/arch-mxs/regs-apbh.h
+++ b/arch/arm/include/asm/imx-common/regs-apbh.h
@@ -26,7 +26,7 @@
 #ifndef __REGS_APBH_H__
 #define __REGS_APBH_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 
@@ -109,7 +109,7 @@
 	mxs_reg_32(hw_apbh_version)
 };
 
-#elif defined(CONFIG_MX28)
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
 struct mxs_apbh_regs {
 	mxs_reg_32(hw_apbh_ctrl0)
 	mxs_reg_32(hw_apbh_ctrl1)
@@ -288,6 +288,17 @@
 #define	APBH_CTRL0_CLKGATE_CHANNEL_NAND7		0x0800
 #define	APBH_CTRL0_CLKGATE_CHANNEL_HSADC		0x1000
 #define	APBH_CTRL0_CLKGATE_CHANNEL_LCDIF		0x2000
+#elif defined(CONFIG_MX6)
+#define	APBH_CTRL0_CLKGATE_CHANNEL_OFFSET		0
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND0		0x0001
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND1		0x0002
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND2		0x0004
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND3		0x0008
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND4		0x0010
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND5		0x0020
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND6		0x0040
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND7		0x0080
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP			0x0100
 #endif
 
 #define	APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN			(1 << 31)
@@ -393,6 +404,10 @@
 #define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF		0x2000
 #endif
 
+#if defined(CONFIG_MX6)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET		16
+#endif
+
 #if defined(CONFIG_MX23)
 #define	APBH_DEVSEL_CH7_MASK				(0xf << 28)
 #define	APBH_DEVSEL_CH7_OFFSET				28
diff --git a/arch/arm/include/asm/arch-mxs/regs-bch.h b/arch/arm/include/asm/imx-common/regs-bch.h
similarity index 96%
rename from arch/arm/include/asm/arch-mxs/regs-bch.h
rename to arch/arm/include/asm/imx-common/regs-bch.h
index 40baa4d..dbe7ac8 100644
--- a/arch/arm/include/asm/arch-mxs/regs-bch.h
+++ b/arch/arm/include/asm/imx-common/regs-bch.h
@@ -26,7 +26,7 @@
 #ifndef __MX28_REGS_BCH_H__
 #define __MX28_REGS_BCH_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_bch_regs {
@@ -136,8 +136,13 @@
 #define	BCH_FLASHLAYOUT0_NBLOCKS_OFFSET			24
 #define	BCH_FLASHLAYOUT0_META_SIZE_MASK			(0xff << 16)
 #define	BCH_FLASHLAYOUT0_META_SIZE_OFFSET		16
+#if defined(CONFIG_MX6)
+#define	BCH_FLASHLAYOUT0_ECC0_MASK			(0x1f << 11)
+#define	BCH_FLASHLAYOUT0_ECC0_OFFSET			11
+#else
 #define	BCH_FLASHLAYOUT0_ECC0_MASK			(0xf << 12)
 #define	BCH_FLASHLAYOUT0_ECC0_OFFSET			12
+#endif
 #define	BCH_FLASHLAYOUT0_ECC0_NONE			(0x0 << 12)
 #define	BCH_FLASHLAYOUT0_ECC0_ECC2			(0x1 << 12)
 #define	BCH_FLASHLAYOUT0_ECC0_ECC4			(0x2 << 12)
@@ -161,8 +166,13 @@
 
 #define	BCH_FLASHLAYOUT1_PAGE_SIZE_MASK			(0xffff << 16)
 #define	BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET		16
+#if defined(CONFIG_MX6)
+#define	BCH_FLASHLAYOUT1_ECCN_MASK			(0x1f << 11)
+#define	BCH_FLASHLAYOUT1_ECCN_OFFSET			11
+#else
 #define	BCH_FLASHLAYOUT1_ECCN_MASK			(0xf << 12)
 #define	BCH_FLASHLAYOUT1_ECCN_OFFSET			12
+#endif
 #define	BCH_FLASHLAYOUT1_ECCN_NONE			(0x0 << 12)
 #define	BCH_FLASHLAYOUT1_ECCN_ECC2			(0x1 << 12)
 #define	BCH_FLASHLAYOUT1_ECCN_ECC4			(0x2 << 12)
diff --git a/arch/arm/include/asm/arch-mxs/regs-common.h b/arch/arm/include/asm/imx-common/regs-common.h
similarity index 100%
rename from arch/arm/include/asm/arch-mxs/regs-common.h
rename to arch/arm/include/asm/imx-common/regs-common.h
diff --git a/arch/arm/include/asm/arch-mxs/regs-gpmi.h b/arch/arm/include/asm/imx-common/regs-gpmi.h
similarity index 99%
rename from arch/arm/include/asm/arch-mxs/regs-gpmi.h
rename to arch/arm/include/asm/imx-common/regs-gpmi.h
index 624d618..3409b94 100644
--- a/arch/arm/include/asm/arch-mxs/regs-gpmi.h
+++ b/arch/arm/include/asm/imx-common/regs-gpmi.h
@@ -26,7 +26,7 @@
 #ifndef __MX28_REGS_GPMI_H__
 #define __MX28_REGS_GPMI_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_gpmi_regs {
diff --git a/arch/arm/include/asm/omap_boot.h b/arch/arm/include/asm/omap_boot.h
new file mode 100644
index 0000000..a803965
--- /dev/null
+++ b/arch/arm/include/asm/omap_boot.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK	0xFF
+#define BOOT_DEVICE_OFFSET	0x8
+#define DEV_DESC_PTR_OFFSET	0x4
+#define DEV_DATA_PTR_OFFSET	0x18
+#define BOOT_MODE_OFFSET	0x8
+#define RESET_REASON_OFFSET	0x9
+#define CH_FLAGS_OFFSET		0xA
+
+#define CH_FLAGS_CHSETTINGS	(0x1 << 0)
+#define CH_FLAGS_CHRAM		(0x1 << 1)
+#define CH_FLAGS_CHFLASH	(0x1 << 2)
+#define CH_FLAGS_CHMMCSD	(0x1 << 3)
+
+#ifndef __ASSEMBLY__
+struct omap_boot_parameters {
+	char *boot_message;
+	unsigned int mem_boot_descriptor;
+	unsigned char omap_bootdevice;
+	unsigned char reset_reason;
+	unsigned char ch_flags;
+	unsigned long omap_bootmode;
+};
+#endif
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 091ddb5..baeef4e 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -25,6 +25,8 @@
 #ifndef	_OMAP_COMMON_H_
 #define	_OMAP_COMMON_H_
 
+#ifndef __ASSEMBLY__
+
 #include <common.h>
 
 #define NUM_SYS_CLKS	8
@@ -316,6 +318,7 @@
 	u32 cm_wkupaon_io_srcomp_clkctrl;
 	u32 prm_rstctrl;
 	u32 prm_rstst;
+	u32 prm_rsttime;
 	u32 prm_vc_val_bypass;
 	u32 prm_vc_cfg_i2c_mode;
 	u32 prm_vc_cfg_i2c_clk;
@@ -557,6 +560,7 @@
 	extern u32 *const omap_si_rev;
 	return *omap_si_rev;
 }
+#endif
 
 /*
  * silicon revisions.
@@ -583,4 +587,19 @@
 
 /* DRA7XX */
 #define DRA752_ES1_0	0x07520100
+
+/*
+ * SRAM scratch space entries
+ */
+#define OMAP_SRAM_SCRATCH_OMAP_REV	SRAM_SCRATCH_SPACE_ADDR
+#define OMAP_SRAM_SCRATCH_EMIF_SIZE	(SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
+#define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP_SRAM_SCRATCH_SYS_CTRL	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP_SRAM_SCRATCH_BOOT_PARAMS	(SRAM_SCRATCH_SPACE_ADDR + 0x24)
+#define OMAP5_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x28)
+
 #endif /* _OMAP_COMMON_H_ */
diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h
index f16861a..c01eef3 100644
--- a/arch/arm/include/asm/u-boot-arm.h
+++ b/arch/arm/include/asm/u-boot-arm.h
@@ -54,8 +54,6 @@
 int	board_init(void);
 int	dram_init (void);
 void	dram_init_banksize (void);
-void	setup_serial_tag (struct tag **params);
-void	setup_revision_tag (struct tag **params);
 
 /* cpu/.../interrupt.c */
 int	arch_interrupt_init	(void);
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 6ae161a..8ad9f66 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -39,12 +39,14 @@
 SOBJS-y += crt0.o
 
 ifndef CONFIG_SPL_BUILD
+SOBJS-y += relocate.o
 ifndef CONFIG_SYS_GENERIC_BOARD
 COBJS-y	+= board.o
 endif
 COBJS-y += bss.o
 
 COBJS-y	+= bootm.o
+COBJS-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
 COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
 SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
 SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
new file mode 100644
index 0000000..93888f8
--- /dev/null
+++ b/arch/arm/lib/bootm-fdt.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *  - Added prep subcommand support
+ *  - Reorganized source - modeled after powerpc version
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2001  Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_fixup_memory_node(void *blob)
+{
+	bd_t *bd = gd->bd;
+	int bank;
+	u64 start[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		start[bank] = bd->bi_dram[bank].start;
+		size[bank] = bd->bi_dram[bank].size;
+	}
+
+	return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
+}
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index f3b30c5..1b6e0ac 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -22,7 +22,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
- *
  */
 
 #include <common.h>
@@ -37,13 +36,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
-	defined(CONFIG_CMDLINE_TAG) || \
-	defined(CONFIG_INITRD_TAG) || \
-	defined(CONFIG_SERIAL_TAG) || \
-	defined(CONFIG_REVISION_TAG)
 static struct tag *params;
-#endif
 
 static ulong get_sp(void)
 {
@@ -75,23 +68,6 @@
 		    gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
 }
 
-#ifdef CONFIG_OF_LIBFDT
-static int fixup_memory_node(void *blob)
-{
-	bd_t	*bd = gd->bd;
-	int bank;
-	u64 start[CONFIG_NR_DRAM_BANKS];
-	u64 size[CONFIG_NR_DRAM_BANKS];
-
-	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		start[bank] = bd->bi_dram[bank].start;
-		size[bank] = bd->bi_dram[bank].size;
-	}
-
-	return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
-}
-#endif
-
 static void announce_and_cleanup(void)
 {
 	printf("\nStarting kernel ...\n\n");
@@ -109,11 +85,6 @@
 	cleanup_before_linux();
 }
 
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
-	defined(CONFIG_CMDLINE_TAG) || \
-	defined(CONFIG_INITRD_TAG) || \
-	defined(CONFIG_SERIAL_TAG) || \
-	defined(CONFIG_REVISION_TAG)
 static void setup_start_tag (bd_t *bd)
 {
 	params = (struct tag *)bd->bi_boot_params;
@@ -127,9 +98,7 @@
 
 	params = tag_next (params);
 }
-#endif
 
-#ifdef CONFIG_SETUP_MEMORY_TAGS
 static void setup_memory_tags(bd_t *bd)
 {
 	int i;
@@ -144,9 +113,7 @@
 		params = tag_next (params);
 	}
 }
-#endif
 
-#ifdef CONFIG_CMDLINE_TAG
 static void setup_commandline_tag(bd_t *bd, char *commandline)
 {
 	char *p;
@@ -171,9 +138,7 @@
 
 	params = tag_next (params);
 }
-#endif
 
-#ifdef CONFIG_INITRD_TAG
 static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
 {
 	/* an ATAG_INITRD node tells the kernel where the compressed
@@ -187,14 +152,11 @@
 
 	params = tag_next (params);
 }
-#endif
 
-#ifdef CONFIG_SERIAL_TAG
-void setup_serial_tag(struct tag **tmp)
+static void setup_serial_tag(struct tag **tmp)
 {
 	struct tag *params = *tmp;
 	struct tag_serialnr serialnr;
-	void get_board_serial(struct tag_serialnr *serialnr);
 
 	get_board_serial(&serialnr);
 	params->hdr.tag = ATAG_SERIAL;
@@ -204,13 +166,10 @@
 	params = tag_next (params);
 	*tmp = params;
 }
-#endif
 
-#ifdef CONFIG_REVISION_TAG
-void setup_revision_tag(struct tag **in_params)
+static void setup_revision_tag(struct tag **in_params)
 {
 	u32 rev = 0;
-	u32 get_board_rev(void);
 
 	rev = get_board_rev();
 	params->hdr.tag = ATAG_REVISION;
@@ -218,106 +177,50 @@
 	params->u.revision.rev = rev;
 	params = tag_next (params);
 }
-#endif
 
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
-	defined(CONFIG_CMDLINE_TAG) || \
-	defined(CONFIG_INITRD_TAG) || \
-	defined(CONFIG_SERIAL_TAG) || \
-	defined(CONFIG_REVISION_TAG)
 static void setup_end_tag(bd_t *bd)
 {
 	params->hdr.tag = ATAG_NONE;
 	params->hdr.size = 0;
 }
-#endif
-
-#ifdef CONFIG_OF_LIBFDT
-static int create_fdt(bootm_headers_t *images)
-{
-	ulong of_size = images->ft_len;
-	char **of_flat_tree = &images->ft_addr;
-	ulong *initrd_start = &images->initrd_start;
-	ulong *initrd_end = &images->initrd_end;
-	struct lmb *lmb = &images->lmb;
-	ulong rd_len;
-	int ret;
-
-	debug("using: FDT\n");
-
-	boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
-
-	rd_len = images->rd_end - images->rd_start;
-	ret = boot_ramdisk_high(lmb, images->rd_start, rd_len,
-			initrd_start, initrd_end);
-	if (ret)
-		return ret;
-
-	ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
-	if (ret)
-		return ret;
-
-	fdt_chosen(*of_flat_tree, 1);
-	fixup_memory_node(*of_flat_tree);
-	fdt_fixup_ethernet(*of_flat_tree);
-	fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
-#ifdef CONFIG_OF_BOARD_SETUP
-	ft_board_setup(*of_flat_tree, gd->bd);
-#endif
-
-	return 0;
-}
-#endif
 
 __weak void setup_board_tags(struct tag **in_params) {}
 
 /* Subcommand: PREP */
 static void boot_prep_linux(bootm_headers_t *images)
 {
-#ifdef CONFIG_CMDLINE_TAG
 	char *commandline = getenv("bootargs");
-#endif
 
+	if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
 #ifdef CONFIG_OF_LIBFDT
-	if (images->ft_len) {
 		debug("using: FDT\n");
-		if (create_fdt(images)) {
+		if (image_setup_linux(images)) {
 			printf("FDT creation failed! hanging...");
 			hang();
 		}
-	} else
 #endif
-	{
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
-	defined(CONFIG_CMDLINE_TAG) || \
-	defined(CONFIG_INITRD_TAG) || \
-	defined(CONFIG_SERIAL_TAG) || \
-	defined(CONFIG_REVISION_TAG)
+	} else if (BOOTM_ENABLE_TAGS) {
 		debug("using: ATAGS\n");
 		setup_start_tag(gd->bd);
-#ifdef CONFIG_SERIAL_TAG
-		setup_serial_tag(&params);
-#endif
-#ifdef CONFIG_CMDLINE_TAG
-		setup_commandline_tag(gd->bd, commandline);
-#endif
-#ifdef CONFIG_REVISION_TAG
-		setup_revision_tag(&params);
-#endif
-#ifdef CONFIG_SETUP_MEMORY_TAGS
-		setup_memory_tags(gd->bd);
-#endif
-#ifdef CONFIG_INITRD_TAG
-		if (images->rd_start && images->rd_end)
-			setup_initrd_tag(gd->bd, images->rd_start,
-			images->rd_end);
-#endif
+		if (BOOTM_ENABLE_SERIAL_TAG)
+			setup_serial_tag(&params);
+		if (BOOTM_ENABLE_CMDLINE_TAG)
+			setup_commandline_tag(gd->bd, commandline);
+		if (BOOTM_ENABLE_REVISION_TAG)
+			setup_revision_tag(&params);
+		if (BOOTM_ENABLE_MEMORY_TAGS)
+			setup_memory_tags(gd->bd);
+		if (BOOTM_ENABLE_INITRD_TAG) {
+			if (images->rd_start && images->rd_end) {
+				setup_initrd_tag(gd->bd, images->rd_start,
+						 images->rd_end);
+			}
+		}
 		setup_board_tags(&params);
 		setup_end_tag(gd->bd);
-#else /* all tags */
+	} else {
 		printf("FDT and ATAGS support not compiled in - hanging\n");
 		hang();
-#endif /* all tags */
 	}
 }
 
@@ -342,11 +245,9 @@
 	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
 	announce_and_cleanup();
 
-#ifdef CONFIG_OF_LIBFDT
-	if (images->ft_len)
+	if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
 		r2 = (unsigned long)images->ft_addr;
 	else
-#endif
 		r2 = gd->bd->bi_boot_params;
 
 	kernel_entry(0, machid, r2);
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
new file mode 100644
index 0000000..4446da9
--- /dev/null
+++ b/arch/arm/lib/relocate.S
@@ -0,0 +1,112 @@
+/*
+ *  relocate - common relocation function for ARM U-Boot
+ *
+ *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * void relocate_code(addr_moni)
+ *
+ * This function relocates the monitor code.
+ *
+ * NOTE:
+ * To prevent the code below from containing references with an R_ARM_ABS32
+ * relocation record type, we never refer to linker-defined symbols directly.
+ * Instead, we declare literals which contain their relative location with
+ * respect to relocate_code, and at run time, add relocate_code back to them.
+ */
+
+ENTRY(relocate_code)
+	mov	r6, r0	/* save addr of destination */
+
+	ldr	r0, =_start		/* r0 <- SRC &_start */
+	subs	r9, r6, r0		/* r9 <- relocation offset */
+	beq	relocate_done		/* skip relocation */
+	mov	r1, r6			/* r1 <- scratch for copy loop */
+	adr	r7, relocate_code	/* r7 <- SRC &relocate_code */
+	ldr	r3, _image_copy_end_ofs	/* r3 <- __image_copy_end local ofs */
+	add	r2, r7, r3		/* r2 <- SRC &__image_copy_end */
+
+copy_loop:
+	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
+	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
+
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- __dynsym_start local ofs */
+	add	r10, r10, r7		/* r10 <- SRC &__dynsym_start */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- __rel_dyn_start local ofs */
+	add	r2, r2, r7		/* r2 <- SRC &__rel_dyn_start */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- __rel_dyn_end local ofs */
+	add	r3, r3, r7		/* r3 <- SRC &__rel_dyn_end */
+fixloop:
+	ldr	r0, [r2]		/* r0 <- SRC location to fix up */
+	add	r0, r0, r9		/* r0 <- DST location to fix up */
+	ldr	r1, [r2, #4]
+	and	r7, r1, #0xff
+	cmp	r7, #23			/* relative fixup? */
+	beq	fixrel
+	cmp	r7, #2			/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r1, r9		/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
+	cmp	r2, r3
+	blo	fixloop
+
+relocate_done:
+
+	/* ARMv4- don't know bx lr but the assembler fails to see that */
+
+#ifdef __ARM_ARCH_4__
+        mov        pc, lr
+#else
+        bx        lr
+#endif
+
+_image_copy_end_ofs:
+	.word __image_copy_end - relocate_code
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - relocate_code
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - relocate_code
+_dynsym_start_ofs:
+	.word __dynsym_start - relocate_code
+
+ENDPROC(relocate_code)
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
index ccf862a..2e79e98 100644
--- a/arch/avr32/lib/board.c
+++ b/arch/avr32/lib/board.c
@@ -116,7 +116,7 @@
 	printf ("\n\n%s\n\n", version_string);
 	printf ("U-Boot code: %08lx -> %08lx  data: %08lx -> %08lx\n",
 		(unsigned long)_text, (unsigned long)_etext,
-		(unsigned long)_data, (unsigned long)__bss_end);
+		(unsigned long)_data, (unsigned long)(&__bss_end));
 	return 0;
 }
 
@@ -183,7 +183,7 @@
 	 *  - stack
 	 */
 	addr = CONFIG_SYS_SDRAM_BASE + sdram_size;
-	monitor_len = (char *)__bss_end - _text;
+	monitor_len = (char *)(&__bss_end) - _text;
 
 	/*
 	 * Reserve memory for u-boot code, data and bss.
diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile
index 0a72ec5..1421cb2 100644
--- a/arch/blackfin/cpu/Makefile
+++ b/arch/blackfin/cpu/Makefile
@@ -18,14 +18,12 @@
 SEXTRA   := start.o
 SOBJS    := interrupt.o cache.o
 COBJS-y  += cpu.o
-COBJS-y  += gpio.o
+COBJS-$(CONFIG_ADI_GPIO1) += gpio.o
 COBJS-y  += interrupts.o
 COBJS-$(CONFIG_JTAG_CONSOLE) += jtag-console.o
 COBJS-y  += os_log.o
 COBJS-y  += reset.o
-COBJS-y  += serial.o
 COBJS-y  += traps.o
-COBJS-$(CONFIG_HW_WATCHDOG)  += watchdog.o
 
 SRCS     := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS     := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c
index 0be2e2b..218f57e 100644
--- a/arch/blackfin/cpu/cpu.c
+++ b/arch/blackfin/cpu/cpu.c
@@ -16,13 +16,39 @@
 #include <asm/mach-common/bits/core.h>
 #include <asm/mach-common/bits/ebiu.h>
 #include <asm/mach-common/bits/trace.h>
+#include <asm/serial.h>
 
 #include "cpu.h"
-#include "serial.h"
 #include "initcode.h"
 
 ulong bfin_poweron_retx;
 
+#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
+void bfin_core1_start(void)
+{
+#ifdef BF561_FAMILY
+	/* Enable core 1 */
+	bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
+#else
+	/* Enable core 1 */
+	bfin_write32(RCU0_SVECT1, COREB_L1_CODE_START);
+	bfin_write32(RCU0_CRCTL, 0);
+
+	bfin_write32(RCU0_CRCTL, 0x2);
+
+	/* Check if core 1 starts */
+	while (!(bfin_read32(RCU0_CRSTAT) & 0x2))
+		continue;
+
+	bfin_write32(RCU0_CRCTL, 0);
+
+	/* flag to notify cces core 1 application */
+	bfin_write32(SDU0_MSG_SET, (1 << 19));
+#endif
+}
+#endif
+
+__attribute__ ((__noreturn__))
 void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
 {
 #ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
@@ -72,6 +98,10 @@
 # endif
 #endif
 
+#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
+	bfin_core1_start();
+#endif
+
 	serial_early_puts("Board init flash\n");
 	board_init_f(bootflag);
 }
diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c
index f684be5..f74a0b7 100644
--- a/arch/blackfin/cpu/gpio.c
+++ b/arch/blackfin/cpu/gpio.c
@@ -1,5 +1,6 @@
 /*
- * GPIO Abstraction Layer
+ * ADI GPIO1 Abstraction Layer
+ * Support BF50x, BF51x, BF52x, BF53x and BF561 only.
  *
  * Copyright 2006-2010 Analog Devices Inc.
  *
@@ -55,25 +56,6 @@
 	(struct gpio_port_t *) FIO0_FLAG_D,
 	(struct gpio_port_t *) FIO1_FLAG_D,
 	(struct gpio_port_t *) FIO2_FLAG_D,
-#elif defined(CONFIG_BF54x)
-	(struct gpio_port_t *)PORTA_FER,
-	(struct gpio_port_t *)PORTB_FER,
-	(struct gpio_port_t *)PORTC_FER,
-	(struct gpio_port_t *)PORTD_FER,
-	(struct gpio_port_t *)PORTE_FER,
-	(struct gpio_port_t *)PORTF_FER,
-	(struct gpio_port_t *)PORTG_FER,
-	(struct gpio_port_t *)PORTH_FER,
-	(struct gpio_port_t *)PORTI_FER,
-	(struct gpio_port_t *)PORTJ_FER,
-#elif defined(CONFIG_BF60x)
-	(struct gpio_port_t *)PORTA_FER,
-	(struct gpio_port_t *)PORTB_FER,
-	(struct gpio_port_t *)PORTC_FER,
-	(struct gpio_port_t *)PORTD_FER,
-	(struct gpio_port_t *)PORTE_FER,
-	(struct gpio_port_t *)PORTF_FER,
-	(struct gpio_port_t *)PORTG_FER,
 #else
 # error no gpio arrays defined
 #endif
@@ -174,12 +156,6 @@
 
 inline int check_gpio(unsigned gpio)
 {
-#if defined(CONFIG_BF54x)
-	if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
-	    || gpio == GPIO_PH14 || gpio == GPIO_PH15
-	    || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
-		return -EINVAL;
-#endif
 	if (gpio >= MAX_BLACKFIN_GPIOS)
 		return -EINVAL;
 	return 0;
@@ -218,18 +194,6 @@
 	else
 		*port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
 	SSYNC();
-#elif defined(CONFIG_BF54x)
-	if (usage == GPIO_USAGE)
-		gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
-	else
-		gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
-	SSYNC();
-#elif defined(CONFIG_BF60x)
-	if (usage == GPIO_USAGE)
-		gpio_array[gpio_bank(gpio)]->port_fer_clear = gpio_bit(gpio);
-	else
-		gpio_array[gpio_bank(gpio)]->port_fer_set = gpio_bit(gpio);
-	SSYNC();
 #endif
 }
 
@@ -304,30 +268,6 @@
 		}
 	}
 }
-#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
-inline void portmux_setup(unsigned short per)
-{
-	u32 pmux;
-	u16 ident = P_IDENT(per);
-	u16 function = P_FUNCT2MUX(per);
-
-	pmux = gpio_array[gpio_bank(ident)]->port_mux;
-
-	pmux &= ~(0x3 << (2 * gpio_sub_n(ident)));
-	pmux |= (function & 0x3) << (2 * gpio_sub_n(ident));
-
-	gpio_array[gpio_bank(ident)]->port_mux = pmux;
-}
-
-inline u16 get_portmux(unsigned short per)
-{
-	u32 pmux;
-	u16 ident = P_IDENT(per);
-
-	pmux = gpio_array[gpio_bank(ident)]->port_mux;
-
-	return (pmux >> (2 * gpio_sub_n(ident)) & 0x3);
-}
 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 inline void portmux_setup(unsigned short per)
 {
@@ -344,7 +284,6 @@
 # define portmux_setup(...)  do { } while (0)
 #endif
 
-#if !defined(CONFIG_BF54x) && !defined(CONFIG_BF60x)
 /***********************************************************
 *
 * FUNCTIONS: Blackfin General Purpose Ports Access Functions
@@ -491,15 +430,6 @@
 GET_GPIO_P(maska)
 GET_GPIO_P(maskb)
 
-#else /* CONFIG_BF54x */
-
-unsigned short get_gpio_dir(unsigned gpio)
-{
-	return (0x01 & (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio)));
-}
-
-#endif /* CONFIG_BF54x */
-
 /***********************************************************
 *
 * FUNCTIONS:	Blackfin Peripheral Resource Allocation
@@ -548,11 +478,7 @@
 		 * be requested and used by several drivers
 		 */
 
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
-		if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
-#else
 		if (!(per & P_MAYSHARE)) {
-#endif
 			/*
 			 * Allow that the identical pin function can
 			 * be requested from the same driver twice
@@ -641,7 +567,7 @@
 * MODIFICATION HISTORY :
 **************************************************************/
 
-int bfin_gpio_request(unsigned gpio, const char *label)
+int gpio_request(unsigned gpio, const char *label)
 {
 	if (check_gpio(gpio) < 0)
 		return -EINVAL;
@@ -665,11 +591,9 @@
 		       gpio, get_label(gpio));
 		return -EBUSY;
 	}
-#if !defined(CONFIG_BF54x) && !defined(CONFIG_BF60x)
 	else {	/* Reset POLAR setting when acquiring a gpio for the first time */
 		set_gpio_polar(gpio, 0);
 	}
-#endif
 
 	reserve(gpio, gpio);
 	set_label(gpio, label);
@@ -679,27 +603,27 @@
 	return 0;
 }
 
-#ifdef CONFIG_BFIN_GPIO_TRACK
-void bfin_gpio_free(unsigned gpio)
+int gpio_free(unsigned gpio)
 {
 	if (check_gpio(gpio) < 0)
-		return;
+		return -1;
 
 	if (unlikely(!is_reserved(gpio, gpio, 0))) {
 		gpio_error(gpio);
-		return;
+		return -1;
 	}
 
 	unreserve(gpio, gpio);
 
 	set_label(gpio, "free");
-}
-#endif
 
-#ifdef BFIN_SPECIAL_GPIO_BANKS
+	return 0;
+}
+
+#ifdef ADI_SPECIAL_GPIO_BANKS
 DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
 
-int bfin_special_gpio_request(unsigned gpio, const char *label)
+int special_gpio_request(unsigned gpio, const char *label)
 {
 	/*
 	 * Allow that the identical GPIO can
@@ -731,7 +655,7 @@
 	return 0;
 }
 
-void bfin_special_gpio_free(unsigned gpio)
+void special_gpio_free(unsigned gpio)
 {
 	if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
 		gpio_error(gpio);
@@ -744,21 +668,13 @@
 }
 #endif
 
-static inline void __bfin_gpio_direction_input(unsigned gpio)
+static inline void __gpio_direction_input(unsigned gpio)
 {
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
-	gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
-#else
 	gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
-#endif
-#if defined(CONFIG_BF60x)
-	gpio_array[gpio_bank(gpio)]->inen_set = gpio_bit(gpio);
-#else
 	gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
-#endif
 }
 
-int bfin_gpio_direction_input(unsigned gpio)
+int gpio_direction_input(unsigned gpio)
 {
 	unsigned long flags;
 
@@ -768,31 +684,24 @@
 	}
 
 	local_irq_save(flags);
-	__bfin_gpio_direction_input(gpio);
+	__gpio_direction_input(gpio);
 	AWA_DUMMY_READ(inen);
 	local_irq_restore(flags);
 
 	return 0;
 }
 
-void bfin_gpio_toggle_value(unsigned gpio)
-{
-#ifdef CONFIG_BF54x
-	gpio_set_value(gpio, !gpio_get_value(gpio));
-#else
-	gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
-#endif
-}
-
-void bfin_gpio_set_value(unsigned gpio, int arg)
+int gpio_set_value(unsigned gpio, int arg)
 {
 	if (arg)
 		gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
 	else
 		gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
+
+	return 0;
 }
 
-int bfin_gpio_direction_output(unsigned gpio, int value)
+int gpio_direction_output(unsigned gpio, int value)
 {
 	unsigned long flags;
 
@@ -803,17 +712,9 @@
 
 	local_irq_save(flags);
 
-#if defined(CONFIG_BF60x)
-	gpio_array[gpio_bank(gpio)]->inen_clear = gpio_bit(gpio);
-#else
 	gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
-#endif
 	gpio_set_value(gpio, value);
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
-	gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
-#else
 	gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
-#endif
 
 	AWA_DUMMY_READ(dir);
 	local_irq_restore(flags);
@@ -821,11 +722,8 @@
 	return 0;
 }
 
-int bfin_gpio_get_value(unsigned gpio)
+int gpio_get_value(unsigned gpio)
 {
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
-	return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
-#else
 	unsigned long flags;
 
 	if (unlikely(get_gpio_edge(gpio))) {
@@ -838,7 +736,6 @@
 		return ret;
 	} else
 		return get_gpio_data(gpio);
-#endif
 }
 
 /* If we are booting from SPI and our board lacks a strong enough pull up,
@@ -860,8 +757,7 @@
 	udelay(1);
 }
 
-#ifdef CONFIG_BFIN_GPIO_TRACK
-void bfin_gpio_labels(void)
+void gpio_labels(void)
 {
 	int c, gpio;
 
@@ -877,4 +773,3 @@
 			continue;
 	}
 }
-#endif
diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c
index 1a06680..ffaf101 100644
--- a/arch/blackfin/cpu/initcode.c
+++ b/arch/blackfin/cpu/initcode.c
@@ -13,12 +13,12 @@
 
 #include <config.h>
 #include <asm/blackfin.h>
+#include <asm/mach-common/bits/watchdog.h>
 #include <asm/mach-common/bits/bootrom.h>
 #include <asm/mach-common/bits/core.h>
+#include <asm/serial.h>
 
-#define BUG() while (1) { asm volatile("emuexcpt;"); }
-
-#include "serial.h"
+#define BUG() while (1) asm volatile("emuexcpt;");
 
 #ifndef __ADSPBF60x__
 #include <asm/mach-common/bits/ebiu.h>
@@ -193,17 +193,12 @@
 	}
 #endif
 
+#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS
 	if (BFIN_DEBUG_EARLY_SERIAL) {
-		int enabled = serial_early_enabled(uart_base);
-
 		serial_early_init(uart_base);
-
-		/* If the UART is off, that means we need to program
-		 * the baud rate ourselves initially.
-		 */
-		if (!enabled)
-			serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
+		serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
 	}
+#endif
 }
 
 __attribute__((always_inline))
@@ -262,7 +257,8 @@
 		"%1 = RETS;" /* Load addr of NMI handler */
 		"RETS = %0;" /* Restore RETS */
 		"[%2] = %1;" /* Write NMI handler */
-		: "=r"(tmp1), "=r"(tmp2) : "ab"(EVT2)
+		: "=d"(tmp1), "=d"(tmp2)
+		: "ab"(EVT2)
 	);
 }
 
@@ -462,19 +458,29 @@
 	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
 		serial_putc('e');
 #ifdef __ADSPBF60x__
+		/* Reset system event controller */
 		bfin_write_SEC_GCTL(0x2);
-		SSYNC();
-		bfin_write_SEC_FCTL(0xc1);
-		bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
-
 		bfin_write_SEC_CCTL(0x2);
 		SSYNC();
+
+		/* Enable fault event input and system reset action in fault
+		 * controller. Route watchdog timeout event to fault interface.
+		 */
+		bfin_write_SEC_FCTL(0xc1);
+		/* Enable watchdog interrupt source */
+		bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
+		SSYNC();
+
+		/* Enable system event controller */
 		bfin_write_SEC_GCTL(0x1);
 		bfin_write_SEC_CCTL(0x1);
+		SSYNC();
 #endif
+		bfin_write_WDOG_CTL(WDDIS);
+		SSYNC();
 		bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
 #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART
-		bfin_write_WDOG_CTL(0);
+		bfin_write_WDOG_CTL(WDEN);
 #endif
 		serial_putc('f');
 	}
@@ -713,37 +719,32 @@
 __attribute__((always_inline)) static inline void
 update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
 {
-	serial_putc('a');
-
 	/* Since we've changed the SCLK above, we may need to update
 	 * the UART divisors (UART baud rates are based on SCLK).
 	 * Do the division by hand as there are no native instructions
 	 * for dividing which means we'd generate a libgcc reference.
 	 */
-	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
-		unsigned int sdivR, vcoR;
-		int dividend = sdivB * divB * vcoR;
-		int divisor = vcoB * sdivR;
-		unsigned int quotient;
+	unsigned int sdivR, vcoR;
+	unsigned int dividend;
+	unsigned int divisor;
+	unsigned int quotient;
 
-		serial_putc('b');
+	serial_putc('a');
 
 #ifdef __ADSPBF60x__
-		sdivR = bfin_read_CGU_DIV();
-		sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
-		vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
+	sdivR = bfin_read_CGU_DIV();
+	sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
+	vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
 #else
-		sdivR = bfin_read_PLL_DIV() & 0xf;
-		vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
+	sdivR = bfin_read_PLL_DIV() & 0xf;
+	vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
 #endif
 
-		for (quotient = 0; dividend > 0; ++quotient)
-			dividend -= divisor;
-		serial_early_put_div(quotient - ANOMALY_05000230);
-		serial_putc('c');
-	}
-
-	serial_putc('d');
+	dividend = sdivB * divB * vcoR;
+	divisor = vcoB * sdivR;
+	quotient = early_division(dividend, divisor);
+	serial_early_put_div(quotient - ANOMALY_05000230);
+	serial_putc('c');
 }
 
 __attribute__((always_inline)) static inline void
diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S
index 7155fc8..da084a8 100644
--- a/arch/blackfin/cpu/start.S
+++ b/arch/blackfin/cpu/start.S
@@ -32,10 +32,10 @@
 
 #include <config.h>
 #include <asm/blackfin.h>
+#include <asm/mach-common/bits/watchdog.h>
 #include <asm/mach-common/bits/core.h>
 #include <asm/mach-common/bits/pll.h>
-
-#include "serial.h"
+#include <asm/serial.h>
 
 /* It may seem odd that we make calls to functions even though we haven't
  * relocated ourselves yet out of {flash,ram,wherever}.  This is OK because
@@ -65,20 +65,29 @@
 	p5.h = HI(COREMMR_BASE);
 
 #ifdef CONFIG_HW_WATCHDOG
-#ifndef __ADSPBF60x__
-# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START
-#  define CONFIG_HW_WATCHDOG_TIMEOUT_START 5000
-# endif
-	/* Program the watchdog with an initial timeout of ~5 seconds.
+	/* Program the watchdog with default timeout of ~5 seconds.
 	 * That should be long enough to bootstrap ourselves up and
 	 * then the common u-boot code can take over.
 	 */
+	r1 = WDDIS;
+# ifdef __ADSPBF60x__
+	[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
+# else
+	W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
+# endif
+	SSYNC;
 	r0 = 0;
-	r0.h = HI(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_START));
+	r0.h = HI(MSEC_TO_SCLK(CONFIG_WATCHDOG_TIMEOUT_MSECS));
 	[p4 + (WDOG_CNT - SYSMMR_BASE)] = r0;
+	SSYNC;
+	r1 = WDEN;
 	/* fire up the watchdog - R0.L above needs to be 0x0000 */
-	W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r0;
-#endif
+# ifdef __ADSPBF60x__
+	[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
+# else
+	W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
+# endif
+	SSYNC;
 #endif
 
 	/* Turn on the serial for debugging the init process */
diff --git a/arch/blackfin/include/asm/clock.h b/arch/blackfin/include/asm/clock.h
new file mode 100644
index 0000000..f1fcd40
--- /dev/null
+++ b/arch/blackfin/include/asm/clock.h
@@ -0,0 +1,78 @@
+
+/*
+ * Copyright (C) 2012 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __CLOCK_H__
+#define __CLOCK_H__
+
+#include <asm/blackfin.h>
+#ifdef PLL_CTL
+#include <asm/mach-common/bits/pll.h>
+# define pll_is_bypassed() (bfin_read_PLL_CTL() & BYPASS)
+#else
+#include <asm/mach-common/bits/cgu.h>
+# define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP)
+# define bfin_read_PLL_CTL() bfin_read_CGU_CTL()
+# define bfin_read_PLL_DIV() bfin_read_CGU_DIV()
+# define SSEL SYSSEL
+# define SSEL_P SYSSEL_P
+#endif
+
+__attribute__((always_inline))
+static inline uint32_t early_division(uint32_t dividend, uint32_t divisor)
+{
+	uint32_t quotient;
+	uint32_t i, j;
+
+	for (quotient = 1, i = 1; dividend > divisor; ++i) {
+		j = divisor << i;
+		if (j > dividend || (j & 0x80000000)) {
+			--i;
+			quotient += (1 << i);
+			dividend -= (divisor << i);
+			i = 0;
+		}
+	}
+
+	return quotient;
+}
+
+__attribute__((always_inline))
+static inline uint32_t early_get_uart_clk(void)
+{
+	uint32_t msel, pll_ctl, vco;
+	uint32_t div, ssel, sclk, uclk;
+
+	pll_ctl = bfin_read_PLL_CTL();
+	msel = (pll_ctl & MSEL) >> MSEL_P;
+	if (msel == 0)
+		msel = (MSEL >> MSEL_P) + 1;
+
+	vco = (CONFIG_CLKIN_HZ >> (pll_ctl & DF)) * msel;
+	sclk = vco;
+	if (!pll_is_bypassed()) {
+		div = bfin_read_PLL_DIV();
+		ssel = (div & SSEL) >> SSEL_P;
+#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
+		sclk = vco/ssel;
+#else
+		sclk = early_division(vco, ssel);
+#endif
+	}
+	uclk = sclk;
+#ifdef CGU_DIV
+	ssel = (div & S0SEL) >> S0SEL_P;
+	uclk = early_division(sclk, ssel);
+#endif
+	return uclk;
+}
+
+#ifdef CGU_DIV
+# define get_uart_clk get_sclk0
+#else
+# define get_uart_clk get_sclk
+#endif
+
+#endif
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index ef1db6e..8a7c079 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -17,21 +17,21 @@
 
 struct dmasg_large {
 	void *next_desc_addr;
-	unsigned long start_addr;
-	unsigned short cfg;
-	unsigned short x_count;
-	short x_modify;
-	unsigned short y_count;
-	short y_modify;
+	u32 start_addr;
+	u16 cfg;
+	u16 x_count;
+	s16 x_modify;
+	u16 y_count;
+	s16 y_modify;
 } __attribute__((packed));
 
 struct dmasg {
-	unsigned long start_addr;
-	unsigned short cfg;
-	unsigned short x_count;
-	short x_modify;
-	unsigned short y_count;
-	short y_modify;
+	u32 start_addr;
+	u16 cfg;
+	u16 x_count;
+	s16 x_modify;
+	u16 y_count;
+	s16 y_modify;
 } __attribute__((packed));
 
 struct dma_register {
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 05131b5..58a6191 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -7,6 +7,8 @@
 #ifndef __ARCH_BLACKFIN_GPIO_H__
 #define __ARCH_BLACKFIN_GPIO_H__
 
+#include <asm-generic/gpio.h>
+
 #define gpio_bank(x)	((x) >> 4)
 #define gpio_bit(x)	(1<<((x) & 0xF))
 #define gpio_sub_n(x)	((x) & 0xF)
@@ -65,10 +67,11 @@
 
 #define PERIPHERAL_USAGE 1
 #define GPIO_USAGE 0
+#define MAX_GPIOS MAX_BLACKFIN_GPIOS
 
 #ifndef __ASSEMBLY__
 
-#if !defined(CONFIG_BF54x) && !defined(CONFIG_BF60x)
+#ifdef CONFIG_ADI_GPIO1
 void set_gpio_dir(unsigned, unsigned short);
 void set_gpio_inen(unsigned, unsigned short);
 void set_gpio_polar(unsigned, unsigned short);
@@ -140,61 +143,16 @@
 };
 #endif
 
-#ifdef CONFIG_BFIN_GPIO_TRACK
-void bfin_gpio_labels(void);
-void bfin_gpio_free(unsigned gpio);
-#else
-#define bfin_gpio_labels()
-#define bfin_gpio_free(gpio)
-#define bfin_gpio_request(gpio, label) bfin_gpio_request(gpio)
-#define bfin_special_gpio_request(gpio, label) bfin_special_gpio_request(gpio)
+#ifdef ADI_SPECIAL_GPIO_BANKS
+void special_gpio_free(unsigned gpio);
+int special_gpio_request(unsigned gpio, const char *label);
 #endif
 
-#ifdef BFIN_SPECIAL_GPIO_BANKS
-void bfin_special_gpio_free(unsigned gpio);
-int bfin_special_gpio_request(unsigned gpio, const char *label);
-#endif
-
-int bfin_gpio_request(unsigned gpio, const char *label);
-int bfin_gpio_direction_input(unsigned gpio);
-int bfin_gpio_direction_output(unsigned gpio, int value);
-int bfin_gpio_get_value(unsigned gpio);
-void bfin_gpio_set_value(unsigned gpio, int value);
-void bfin_gpio_toggle_value(unsigned gpio);
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-	return bfin_gpio_request(gpio, label);
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-	return bfin_gpio_free(gpio);
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
-	return bfin_gpio_direction_input(gpio);
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-	return bfin_gpio_direction_output(gpio, value);
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
-	return bfin_gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-	return bfin_gpio_set_value(gpio, value);
-}
+void gpio_labels(void);
 
 static inline int gpio_is_valid(int number)
 {
-	return number >= 0 && number < MAX_BLACKFIN_GPIOS;
+	return number >= 0 && number < MAX_GPIOS;
 }
 
 #include <linux/ctype.h>
@@ -248,7 +206,7 @@
 }
 #define name_to_gpio(n) name_to_gpio(n)
 
-#define gpio_status() bfin_gpio_labels()
+#define gpio_status() gpio_labels()
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_def.h b/arch/blackfin/include/asm/mach-bf561/BF561_def.h
index a7ff5a3..8fd552f 100644
--- a/arch/blackfin/include/asm/mach-bf561/BF561_def.h
+++ b/arch/blackfin/include/asm/mach-bf561/BF561_def.h
@@ -714,4 +714,6 @@
 #define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1)
 #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
 
+#define COREB_L1_CODE_START       0xFF600000
+
 #endif /* __BFIN_DEF_ADSP_BF561_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h
index 8c1dcd0..02b81d3 100644
--- a/arch/blackfin/include/asm/mach-bf609/BF609_def.h
+++ b/arch/blackfin/include/asm/mach-bf609/BF609_def.h
@@ -128,6 +128,9 @@
 #define EMAC0_MACCFG      0xFFC20000 /* EMAC0 MAC Configuration Register */
 #define EMAC1_MACCFG      0xFFC22000 /* EMAC1 MAC Configuration Register */
 
+#define SPI0_REGBASE      0xFFC40400 /* SPI0 Base Address */
+#define SPI1_REGBASE      0xFFC40500 /* SPI1 Base Address */
+
 #define DMA10_DSCPTR_NXT  0xFFC05000 /* DMA10 Pointer to Next Initial Desc */
 #define DMA10_ADDRSTART   0xFFC05004 /* DMA10 Start Address of Current Buf */
 #define DMA10_CFG         0xFFC05008 /* DMA10 Configuration Register */
@@ -244,4 +247,6 @@
 #define L1_INST_SRAM_SIZE 0x8000
 #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
 
+#define COREB_L1_CODE_START       0xFF600000
+
 #endif /* __BFIN_DEF_ADSP_BF609_proc__ */
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
index 300ef44..003694b 100644
--- a/arch/blackfin/include/asm/portmux.h
+++ b/arch/blackfin/include/asm/portmux.h
@@ -17,11 +17,6 @@
 #define P_MAYSHARE	0x2000
 #define P_DONTCARE	0x1000
 
-#ifndef CONFIG_BFIN_GPIO_TRACK
-#define peripheral_request(per, label) peripheral_request(per)
-#define peripheral_request_list(per, label) peripheral_request_list(per)
-#endif
-
 #ifndef __ASSEMBLY__
 
 int peripheral_request(unsigned short per, const char *label);
diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/include/asm/serial.h
similarity index 82%
rename from arch/blackfin/cpu/serial.h
rename to arch/blackfin/include/asm/serial.h
index 9200339..87a337d 100644
--- a/arch/blackfin/cpu/serial.h
+++ b/arch/blackfin/include/asm/serial.h
@@ -78,19 +78,31 @@
 #else
 
 .macro serial_early_init
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-	call _serial_initialize;
+#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM)
+	call __serial_early_init;
 #endif
 .endm
 
 .macro serial_early_set_baud
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
+#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM)
 	R0.L = LO(CONFIG_BAUDRATE);
 	R0.H = HI(CONFIG_BAUDRATE);
-	call _serial_set_baud;
+	call __serial_early_set_baud;
 #endif
 .endm
 
+#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
+#define update_serial_early_string_addr \
+	R1.L = _start; \
+	R1.H = _start; \
+	R0 = R0 - R1; \
+	R1.L = 0; \
+	R1.H = 0x2000; \
+	R0 = R0 + R1;
+#else
+#define update_serial_early_string_addr
+#endif
+
 /* Since we embed the string right into our .text section, we need
  * to find its address.  We do this by getting our PC and adding 2
  * bytes (which is the length of the jump instruction).  Then we
@@ -108,7 +120,8 @@
 	.previous; \
 	R0.L = 7b; \
 	R0.H = 7b; \
-	call _serial_puts;
+	update_serial_early_string_addr \
+	call _uart_early_puts;
 #else
 # define serial_early_puts(str)
 #endif
diff --git a/arch/blackfin/cpu/serial1.h b/arch/blackfin/include/asm/serial1.h
similarity index 94%
rename from arch/blackfin/cpu/serial1.h
rename to arch/blackfin/include/asm/serial1.h
index a20175b..467d381 100644
--- a/arch/blackfin/cpu/serial1.h
+++ b/arch/blackfin/include/asm/serial1.h
@@ -15,6 +15,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <asm/clock.h>
+
 #define MMR_UART(n) _PASTE_UART(n, UART, DLL)
 #ifdef UART_DLL
 # define UART0_DLL UART_DLL
@@ -230,19 +232,6 @@
 }
 
 __attribute__((always_inline))
-static inline uint32_t uart_sclk(void)
-{
-#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL)
-	/* We cannot use get_sclk() early on as it uses
-	 * caches in external memory
-	 */
-	return CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV;
-#else
-	return get_sclk();
-#endif
-}
-
-__attribute__((always_inline))
 static inline int uart_init(uint32_t uart_base)
 {
 	/* always enable UART -- avoids anomalies 05000309 and 05000350 */
@@ -275,21 +264,8 @@
 }
 
 __attribute__((always_inline))
-static inline int serial_early_enabled(uint32_t uart_base)
+static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor)
 {
-	return bfin_read(&pUART->gctl) & UCEN;
-}
-
-__attribute__((always_inline))
-static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
-{
-	/* Translate from baud into divisor in terms of SCLK.  The
-	 * weird multiplication is to make sure we over sample just
-	 * a little rather than under sample the incoming signals.
-	 */
-	uint16_t divisor = (uart_sclk() + (baud * 8)) / (baud * 16) -
-			ANOMALY_05000230;
-
 	/* Set DLAB in LCR to Access DLL and DLH */
 	ACCESS_LATCH();
 	SSYNC();
@@ -305,6 +281,24 @@
 }
 
 __attribute__((always_inline))
+static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
+{
+	/* Translate from baud into divisor in terms of SCLK.  The
+	 * weird multiplication is to make sure we over sample just
+	 * a little rather than under sample the incoming signals.
+	 */
+#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
+	uint16_t divisor = (early_get_uart_clk() + baud * 8) / (baud * 16)
+			- ANOMALY_05000230;
+#else
+	uint16_t divisor = early_division(early_get_uart_clk() + (baud * 8),
+			baud * 16) - ANOMALY_05000230;
+#endif
+
+	serial_set_divisor(uart_base, divisor);
+}
+
+__attribute__((always_inline))
 static inline void serial_early_put_div(uint16_t divisor)
 {
 	uint32_t uart_base = UART_BASE;
diff --git a/arch/blackfin/cpu/serial4.h b/arch/blackfin/include/asm/serial4.h
similarity index 86%
rename from arch/blackfin/cpu/serial4.h
rename to arch/blackfin/include/asm/serial4.h
index 887845c..6548396 100644
--- a/arch/blackfin/cpu/serial4.h
+++ b/arch/blackfin/include/asm/serial4.h
@@ -15,6 +15,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <asm/clock.h>
+
 #define MMR_UART(n) _PASTE_UART(n, UART, REVID)
 #define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
 
@@ -84,20 +86,6 @@
 }
 
 __attribute__((always_inline))
-static inline uint32_t uart_sclk(void)
-{
-#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL)
-	/* We cannot use get_sclk() early on as it uses caches in
-	 * external memory
-	 */
-	return CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV /
-		CONFIG_SCLK0_DIV;
-#else
-	return get_sclk0();
-#endif
-}
-
-__attribute__((always_inline))
 static inline int uart_init(uint32_t uart_base)
 {
 	/* always enable UART to 8-bit mode */
@@ -127,19 +115,20 @@
 }
 
 __attribute__((always_inline))
-static inline int serial_early_enabled(uint32_t uart_base)
+static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor)
 {
-	return bfin_read(&pUART->control) & UEN;
+	/* Program the divisor to get the baud rate we want */
+	bfin_write(&pUART->clock, divisor);
+	SSYNC();
 }
 
 __attribute__((always_inline))
 static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
 {
-	uint32_t divisor = uart_sclk() / (baud * 16);
+	uint16_t divisor = early_division(early_get_uart_clk(), baud * 16);
 
 	/* Program the divisor to get the baud rate we want */
-	bfin_write(&pUART->clock, divisor);
-	SSYNC();
+	serial_set_divisor(uart_base, divisor);
 }
 
 __attribute__((always_inline))
diff --git a/arch/blackfin/include/asm/soft_switch.h b/arch/blackfin/include/asm/soft_switch.h
new file mode 100644
index 0000000..ff8e44d
--- /dev/null
+++ b/arch/blackfin/include/asm/soft_switch.h
@@ -0,0 +1,18 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2012 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __SOFT_SWITCH_H__
+#define __SOFT_SWITCH_H__
+
+#define IO_PORT_A              0
+#define IO_PORT_B              1
+#define IO_PORT_INPUT          0
+#define IO_PORT_OUTPUT         1
+
+int config_switch_bit(int num, int port, int bit, int dir, uchar value);
+#endif
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
index ccea3b9..f1d5547 100644
--- a/arch/blackfin/lib/board.c
+++ b/arch/blackfin/lib/board.c
@@ -231,6 +231,8 @@
 	bd->bi_sclk = get_sclk();
 	bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
 	bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+	bd->bi_baudrate = (gd->baudrate > 0)
+		? simple_strtoul(gd->baudrate, NULL, 10) : CONFIG_BAUDRATE;
 
 	return 0;
 }
@@ -277,9 +279,9 @@
 	dcache_enable();
 #endif
 
-#ifdef CONFIG_WATCHDOG
+#ifdef CONFIG_HW_WATCHDOG
 	serial_early_puts("Setting up external watchdog\n");
-	watchdog_init();
+	hw_watchdog_init();
 #endif
 
 #ifdef DEBUG
diff --git a/arch/blackfin/lib/clocks.c b/arch/blackfin/lib/clocks.c
index d852f5e..97795e1 100644
--- a/arch/blackfin/lib/clocks.c
+++ b/arch/blackfin/lib/clocks.c
@@ -7,17 +7,7 @@
  */
 
 #include <common.h>
-#include <asm/blackfin.h>
-
-#ifdef PLL_CTL
-# include <asm/mach-common/bits/pll.h>
-# define pll_is_bypassed() (bfin_read_PLL_STAT() & DF)
-#else
-# include <asm/mach-common/bits/cgu.h>
-# define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP)
-# define bfin_read_PLL_CTL() bfin_read_CGU_CTL()
-# define bfin_read_PLL_DIV() bfin_read_CGU_DIV()
-#endif
+#include <asm/clock.h>
 
 /* Get the voltage input multiplier */
 u_long get_vco(void)
diff --git a/arch/blackfin/lib/string.c b/arch/blackfin/lib/string.c
index 44d8c6d..5b7ac0b 100644
--- a/arch/blackfin/lib/string.c
+++ b/arch/blackfin/lib/string.c
@@ -128,10 +128,12 @@
 	unsigned long limit;
 
 #ifdef MSIZE
-	limit = 6;
+	/* The max memory DMA memory transfer size is 32 bytes. */
+	limit = 5;
 	*dshift = MSIZE_P;
 #else
-	limit = 3;
+	/* The max memory DMA memory transfer size is 4 bytes. */
+	limit = 2;
 	*dshift = WDSIZE_P;
 #endif
 
@@ -170,7 +172,8 @@
 	mod = 1 << bpos;
 
 #ifdef PSIZE
-	dsize |= min(3, bpos) << PSIZE_P;
+	/* The max memory DMA peripheral transfer size is 4 bytes. */
+	dsize |= min(2, bpos) << PSIZE_P;
 #endif
 
 	/* Copy sram functions from sdram to sram */
diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c
index d506d0c..56b6512 100644
--- a/arch/m68k/lib/bootm.c
+++ b/arch/m68k/lib/bootm.c
@@ -78,13 +78,6 @@
 	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
 		return 1;
 
-	/* allocate space and init command line */
-	ret = boot_get_cmdline (lmb, &cmd_start, &cmd_end);
-	if (ret) {
-		puts("ERROR with allocation of cmdline\n");
-		goto error;
-	}
-
 	/* allocate space for kernel copy of board info */
 	ret = boot_get_kbd (lmb, &kbd);
 	if (ret) {
@@ -93,14 +86,12 @@
 	}
 	set_clocks_in_mhz(kbd);
 
-	kernel = (void (*)(bd_t *, ulong, ulong, ulong, ulong))images->ep;
-
-	rd_len = images->rd_end - images->rd_start;
-	ret = boot_ramdisk_high (lmb, images->rd_start, rd_len,
-			&initrd_start, &initrd_end);
+	ret = image_setup_linux(images);
 	if (ret)
 		goto error;
 
+	kernel = (void (*)(bd_t *, ulong, ulong, ulong, ulong))images->ep;
+
 	debug("## Transferring control to Linux (at address %08lx) ...\n",
 	      (ulong) kernel);
 
diff --git a/arch/microblaze/include/asm/gpio.h b/arch/microblaze/include/asm/gpio.h
index 883f4d4..f5cad56 100644
--- a/arch/microblaze/include/asm/gpio.h
+++ b/arch/microblaze/include/asm/gpio.h
@@ -1,41 +1,15 @@
 #ifndef _ASM_MICROBLAZE_GPIO_H_
 #define _ASM_MICROBLAZE_GPIO_H_
 
-#include <asm/io.h>
+#include <asm-generic/gpio.h>
 
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-	return 0;
-}
+/* Allocation functions */
+extern int gpio_alloc_dual(u32 baseaddr, const char *name, u32 gpio_no0,
+			   u32 gpio_no1);
+extern int gpio_alloc(u32 baseaddr, const char *name, u32 gpio_no);
 
-static inline int gpio_free(unsigned gpio)
-{
-	return 0;
-}
+#define gpio_status()	gpio_info()
+extern void gpio_info(void);
 
-static inline int gpio_direction_input(unsigned gpio)
-{
-	return 0;
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-	return 0;
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
-	return 0;
-}
-
-static inline int gpio_set_value(unsigned gpio, int value)
-{
-	return 0;
-}
-
-static inline int gpio_is_valid(int number)
-{
-	return 0;
-}
 #endif
 
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 66d21f4..3842709 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -32,11 +32,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
+int do_bootm_linux(int flag, int argc, char * const argv[],
+		   bootm_headers_t *images)
 {
 	/* First parameter is mapped to $r5 for kernel boot args */
-	void	(*theKernel) (char *, ulong, ulong);
-	char	*commandline = getenv ("bootargs");
+	void	(*thekernel) (char *, ulong, ulong);
+	char	*commandline = getenv("bootargs");
 	ulong	rd_data_start, rd_data_end;
 
 	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
@@ -51,10 +52,10 @@
 		of_flat_tree = images->ft_addr;
 #endif
 
-	theKernel = (void (*)(char *, ulong, ulong))images->ep;
+	thekernel = (void (*)(char *, ulong, ulong))images->ep;
 
 	/* find ramdisk */
-	ret = boot_get_ramdisk (argc, argv, images, IH_ARCH_MICROBLAZE,
+	ret = boot_get_ramdisk(argc, argv, images, IH_ARCH_MICROBLAZE,
 			&rd_data_start, &rd_data_end);
 	if (ret)
 		return 1;
@@ -63,10 +64,19 @@
 
 	if (!of_flat_tree && argc > 3)
 		of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16);
+
+	/* fixup the initrd now that we know where it should be */
+	if (images->rd_start && images->rd_end && of_flat_tree)
+		ret = fdt_initrd(of_flat_tree, images->rd_start,
+				 images->rd_end, 1);
+		if (ret)
+			return 1;
+
 #ifdef DEBUG
-	printf ("## Transferring control to Linux (at address 0x%08lx) " \
-				"ramdisk 0x%08lx, FDT 0x%08lx...\n",
-		(ulong) theKernel, rd_data_start, (ulong) of_flat_tree);
+	printf("## Transferring control to Linux (at address 0x%08lx) ",
+	       (ulong)thekernel);
+	printf("ramdisk 0x%08lx, FDT 0x%08lx...\n",
+	       rd_data_start, (ulong) of_flat_tree);
 #endif
 
 #ifdef XILINX_USE_DCACHE
@@ -78,7 +88,7 @@
 	 * r6: pointer to ramdisk
 	 * r7: pointer to the fdt, followed by the board info data
 	 */
-	theKernel (commandline, rd_data_start, (ulong) of_flat_tree);
+	thekernel(commandline, rd_data_start, (ulong)of_flat_tree);
 	/* does not return */
 
 	return 1;
diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h
index f3c7b27..d22eb5b 100644
--- a/arch/nds32/include/asm/u-boot-nds32.h
+++ b/arch/nds32/include/asm/u-boot-nds32.h
@@ -30,11 +30,6 @@
 #define _U_BOOT_NDS32_H_	1
 
 /* for the following variables, see start.S */
-extern char __bss_start[];	/* BSS start relative to _start */
-extern ulong __bss_end;		/* BSS end relative to _start */
-extern char _end[];		/* end of image relative to _start */
-extern void _start(void);	/* start of image relative to _start */
-extern ulong _TEXT_BASE;	/* code start */
 extern ulong IRQ_STACK_START;	/* top of IRQ stack */
 extern ulong FIQ_STACK_START;	/* top of FIQ stack */
 
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
index 57af1be..1157d8c 100644
--- a/arch/nds32/lib/board.c
+++ b/arch/nds32/lib/board.c
@@ -36,6 +36,7 @@
 #include <nand.h>
 #include <onenand_uboot.h>
 #include <mmc.h>
+#include <asm/sections.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -300,7 +301,7 @@
 
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
 
-	monitor_flash_len = &_end - &_start;
+	monitor_flash_len = (ulong)&_end - (ulong)&_start;
 	debug("monitor flash len: %08lX\n", monitor_flash_len);
 
 	board_init();	/* Setup chipselects */
diff --git a/arch/openrisc/config.mk b/arch/openrisc/config.mk
index 521e73a..01c0f77 100644
--- a/arch/openrisc/config.mk
+++ b/arch/openrisc/config.mk
@@ -25,3 +25,5 @@
 PLATFORM_CPPFLAGS += -DCONFIG_OPENRISC -D__OR1K__ -ffixed-r10
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
+
+LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
diff --git a/board/openrisc/openrisc-generic/u-boot.lds b/arch/openrisc/cpu/u-boot.lds
similarity index 98%
rename from board/openrisc/openrisc-generic/u-boot.lds
rename to arch/openrisc/cpu/u-boot.lds
index 9024f30..d9bb7b7 100644
--- a/board/openrisc/openrisc-generic/u-boot.lds
+++ b/arch/openrisc/cpu/u-boot.lds
@@ -30,7 +30,7 @@
 	 . = ALIGN(4);
 	 .u_boot_list : {
 		KEEP(*(SORT(.u_boot_list*)));
-	 }
+	 } > ram
 
 	.rodata : {
 		*(.rodata);
diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile
index b53232f..4f4c9ec 100644
--- a/arch/powerpc/cpu/mpc512x/Makefile
+++ b/arch/powerpc/cpu/mpc512x/Makefile
@@ -38,7 +38,6 @@
 COBJS-y += speed.o
 COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
 COBJS-$(CONFIG_CMD_IDE) += ide.o
-COBJS-$(CONFIG_IIM) += iim.o
 COBJS-$(CONFIG_PCI) += pci.o
 
 # Stub implementations of cache management functions for USB
diff --git a/arch/powerpc/cpu/mpc512x/cpu_init.c b/arch/powerpc/cpu/mpc512x/cpu_init.c
index b308cb4..0e20ded 100644
--- a/arch/powerpc/cpu/mpc512x/cpu_init.c
+++ b/arch/powerpc/cpu/mpc512x/cpu_init.c
@@ -201,7 +201,7 @@
 	 */
 	out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
 	out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
-#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+#if defined(CONFIG_FSL_IIM) || defined(CONFIG_CMD_FUSE)
 	setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
 #endif
 }
diff --git a/arch/powerpc/cpu/mpc512x/iim.c b/arch/powerpc/cpu/mpc512x/iim.c
deleted file mode 100644
index abec8f6..0000000
--- a/arch/powerpc/cpu/mpc512x/iim.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * Copyright 2008 Silicon Turnkey Express, Inc.
- * Martha Marx <mmarx@silicontkx.com>
- *
- * ADS5121 IIM (Fusebox) Interface
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_CMD_FUSE
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static char cur_bank = '1';
-
-char *iim_err_msg(u32 err)
-{
-	static char *IIM_errs[] = {
-		"Parity Error in cache",
-		"Explicit Sense Cycle Error",
-		"Write to Locked Register Error",
-		"Read Protect Error",
-		"Override Protect Error",
-		"Write Protect Error"};
-
-	int i;
-
-	if (!err)
-		return "";
-	for (i = 1; i < 8; i++)
-		if (err & (1 << i))
-			printf("IIM - %s\n", IIM_errs[i-1]);
-	return "";
-}
-
-int in_range(int n, int min, int max, char *err, char *usg)
-{
-	if (n > max || n < min) {
-		printf(err);
-		printf("Usage:\n%s\n", usg);
-		return 0;
-	}
-	return 1;
-}
-
-int ads5121_fuse_read(int bank, int fstart, int num)
-{
-	iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
-	u32 *iim_fb, dummy;
-	int f, ctr;
-
-	out_be32(&iim->err, in_be32(&iim->err));
-	if (bank == 0)
-		iim_fb = (u32 *)&(iim->fbac0);
-	else
-		iim_fb = (u32 *)&(iim->fbac1);
-/* try a read to see if Read Protect is set */
-	dummy = in_be32(&iim_fb[0]);
-	if (in_be32(&iim->err) & IIM_ERR_RPE) {
-		printf("\tRead protect fuse is set\n");
-		out_be32(&iim->err, IIM_ERR_RPE);
-		return 0;
-	}
-	printf("Reading Bank %d cache\n", bank);
-	for (f = fstart, ctr = 0; num > 0; ctr++, num--, f++) {
-		if (ctr % 4 == 0)
-			printf("F%2d:", f);
-		printf("\t%#04x", (u8)(iim_fb[f]));
-		if (ctr % 4 == 3)
-			printf("\n");
-	}
-	if (ctr % 4 != 0)
-		printf("\n");
-}
-
-int ads5121_fuse_override(int bank, int f, u8 val)
-{
-	iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
-	u32 *iim_fb;
-	u32 iim_stat;
-	int i;
-
-	out_be32(&iim->err, in_be32(&iim->err));
-	if (bank == 0)
-		iim_fb = (u32 *)&(iim->fbac0);
-	else
-		iim_fb = (u32 *)&(iim->fbac1);
-/* try a read to see if Read Protect is set */
-	iim_stat = in_be32(&iim_fb[0]);
-	if (in_be32(&iim->err) & IIM_ERR_RPE) {
-		printf("Read protect fuse is set on bank %d;"
-			"Override protect may also be set\n", bank);
-		printf("An attempt will be made to override\n");
-		out_be32(&iim->err, IIM_ERR_RPE);
-	}
-	if (iim_stat & IIM_FBAC_FBOP) {
-		printf("Override protect fuse is set on bank %d\n", bank);
-		return 1;
-	}
-	if (f > IIM_FMAX) /* reset the entire bank */
-		for (i = 0; i < IIM_FMAX + 1; i++)
-			out_be32(&iim_fb[i],  0);
-	else
-		out_be32(&iim_fb[f], val);
-	return 0;
-}
-
-int ads5121_fuse_prog(cmd_tbl_t *cmdtp, int bank, char *fuseno_bitno)
-{
-	iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
-	int f, i, bitno;
-	u32 stat, err;
-
-	f = simple_strtol(fuseno_bitno, NULL, 10);
-	if (f == 0 && fuseno_bitno[0] != '0')
-		f = -1;
-	if (!in_range(f, 0, IIM_FMAX,
-		"<frow> must be between 0-31\n\n", cmdtp->usage))
-		return 1;
-	bitno = -1;
-	for (i = 0; i < 6; i++) {
-		if (fuseno_bitno[i] == '_') {
-			bitno = simple_strtol(&(fuseno_bitno[i+1]), NULL, 10);
-			if (bitno == 0 && fuseno_bitno[i+1] != '0')
-				bitno = -1;
-			break;
-		}
-	}
-	if (!in_range(bitno, 0, 7, "Bit number ranges from 0-7\n"
-		"Example of <frow_bitno>: \"18_4\" sets bit 4 of row 18\n",
-		cmdtp->usage))
-		return 1;
-	out_be32(&iim->err, in_be32(&iim->err));
-	out_be32(&iim->prg_p, IIM_PRG_P_SET);
-	out_be32(&iim->ua, IIM_SET_UA(bank, f));
-	out_be32(&iim->la, IIM_SET_LA(f, bitno));
-#ifdef DEBUG
-	printf("Programming disabled with DEBUG defined \n");
-	printf(""Set up to pro
-	printf("iim.ua = %x; iim.la = %x\n", iim->ua, iim->la);
-#else
-	out_be32(&iim->fctl, IIM_FCTL_PROG_PULSE | IIM_FCTL_PROG);
-	do
-		udelay(20);
-	while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY);
-	out_be32(&iim->prg_p, 0);
-	err = in_be32(&iim->err);
-	if (stat & IIM_STAT_PRGD) {
-		if (!(err & (IIM_ERR_WPE | IIM_ERR_WPE))) {
-			printf("Fuse is successfully set");
-			if (err)
-				printf(" - however there are other errors");
-			printf("\n");
-		}
-		iim->stat = 0;
-	}
-	if (err) {
-		iim_err_msg(err);
-		out_be32(&iim->err, in_be32(&iim->err));
-	}
-#endif
-}
-
-int ads5121_fuse_sense(int bank, int fstart, int num)
-{
-	iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
-	u32 iim_fbac;
-	u32 stat, err, err_hold = 0;
-	int f, ctr;
-
-	out_be32(&iim->err, in_be32(&iim->err));
-	if (bank == 0)
-		iim_fbac = in_be32(&iim->fbac0);
-	else
-		iim_fbac = in_be32(&iim->fbac1);
-	if (iim_fbac & IIM_FBAC_FBESP) {
-		printf("\tSense Protect disallows this operation\n");
-		out_be32(&iim->err, IIM_FBAC_FBESP);
-		return 1;
-	}
-	err = in_be32(&iim->err);
-	if (err) {
-		iim_err_msg(err);
-		err_hold |= err;
-	}
-	if (err & IIM_ERR_RPE)
-		printf("\tRead protect fuse is set; "
-			"Sense Protect may be set but will be attempted\n");
-	if (err)
-		out_be32(&iim->err, err);
-	printf("Sensing fuse(s) on Bank %d\n", bank);
-	for (f = fstart, ctr = 0; num > 0; ctr++, f++, num--) {
-		out_be32(&iim->ua, IIM_SET_UA(bank, f));
-		out_be32(&iim->la, IIM_SET_LA(f, 0));
-		out_be32(&iim->fctl,  IIM_FCTL_ESNS_N);
-		do
-			udelay(20);
-		while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY);
-		err = in_be32(&iim->err);
-		if (err & IIM_ERR_SNSE) {
-			iim_err_msg(err);
-			out_be32(&iim->err, IIM_ERR_SNSE);
-			return 1;
-		}
-		if (stat & IIM_STAT_SNSD) {
-			out_be32(&iim->stat, 0);
-			if (ctr % 4 == 0)
-				printf("F%2d:", f);
-			printf("\t%#04x", (u8)iim->sdat);
-			if (ctr % 4 == 3)
-				printf("\n");
-		}
-		if (err) {
-			err_hold |= err;
-			out_be32(&iim->err, err);
-		}
-	}
-	if (ctr % 4 != 0)
-		printf("\n");
-	if (err_hold)
-		iim_err_msg(err_hold);
-
-	return 0;
-}
-
-int ads5121_fuse_stat(int bank)
-{
-	iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
-	u32 iim_fbac;
-	u32 err;
-
-	out_be32(&iim->err, in_be32(&iim->err));
-	if (bank == 0)
-		iim_fbac = in_be32(&iim->fbac0);
-	else
-		iim_fbac = in_be32(&iim->fbac1);
-	err = in_be32(&iim->err);
-	if (err)
-		iim_err_msg(err);
-	if (err & IIM_ERR_RPE  || iim_fbac & IIM_FBAC_FBRP) {
-		if (iim_fbac == 0)
-			printf("Since protection settings can't be read - "
-				"try sensing fuse row 0;\n");
-		return 0;
-	}
-	if (iim_fbac & IIM_PROTECTION)
-		printf("Protection Fuses Bank %d = %#04x:\n", bank, iim_fbac);
-	else if (!(err & IIM_ERR_RPE))
-		printf("No Protection fuses are set\n");
-	if (iim_fbac & IIM_FBAC_FBWP)
-		printf("\tWrite Protect fuse is set\n");
-	if (iim_fbac & IIM_FBAC_FBOP)
-		printf("\tOverride Protect fuse is set\n");
-	if (iim_fbac & IIM_FBAC_FBESP)
-		printf("\tSense Protect Fuse is set\n");
-	out_be32(&iim->err, in_be32(&iim->err));
-
-	return 0;
-}
-
-int do_ads5121_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int frow, n, v, bank;
-
-	if (cur_bank == '0')
-		bank = 0;
-	else
-		bank = 1;
-
-	switch (argc) {
-	case 0:
-	case 1:
-		printf("Usage:\n%s\n", cmdtp->usage);
-		return 1;
-	case 2:
-		if (strncmp(argv[1], "stat", 4) == 0)
-			return ads5121_fuse_stat(bank);
-		if (strncmp(argv[1], "read", 4) == 0)
-			return ads5121_fuse_read(bank, 0, IIM_FMAX + 1);
-		if (strncmp(argv[1], "sense", 5) == 0)
-			return ads5121_fuse_sense(bank, 0, IIM_FMAX + 1);
-		if (strncmp(argv[1], "ovride", 6) == 0)
-			return ads5121_fuse_override(bank, IIM_FMAX + 1, 0);
-		if (strncmp(argv[1], "bank", 4) == 0) {
-			printf("Active Fuse Bank is %c\n", cur_bank);
-			return 0;
-		}
-		printf("Usage:\n%s\n", cmdtp->usage);
-		return 1;
-	case 3:
-		if (strncmp(argv[1], "bank", 4) == 0) {
-			if (argv[2][0] == '0')
-				cur_bank = '0';
-			else if (argv[2][0] == '1')
-				cur_bank = '1';
-			else {
-				printf("Usage:\n%s\n", cmdtp->usage);
-				return 1;
-			}
-
-			printf("Setting Active Fuse Bank to %c\n", cur_bank);
-			return 0;
-		}
-		if (strncmp(argv[1], "prog", 4) == 0)
-			return ads5121_fuse_prog(cmdtp, bank, argv[2]);
-
-		frow = (int)simple_strtol(argv[2], NULL, 10);
-		if (frow == 0 && argv[2][0] != '0')
-			frow = -1;
-		if (!in_range(frow, 0, IIM_FMAX,
-			"<frow> must be between 0-31\n\n", cmdtp->usage))
-			return 1;
-		if (strncmp(argv[1], "read", 4) == 0)
-			return ads5121_fuse_read(bank, frow, 1);
-		if (strncmp(argv[1], "ovride", 6) == 0)
-			return ads5121_fuse_override(bank, frow, 0);
-		if (strncmp(argv[1], "sense", 5) == 0)
-			return ads5121_fuse_sense(bank, frow, 1);
-		printf("Usage:\n%s\n", cmdtp->usage);
-		return 1;
-	case 4:
-		frow = (int)simple_strtol(argv[2], NULL, 10);
-		if (frow == 0 && argv[2][0] != '0')
-			frow = -1;
-		if (!in_range(frow, 0, IIM_FMAX,
-			"<frow> must be between 0-31\n\n", cmdtp->usage))
-			return 1;
-		if (strncmp(argv[1], "read", 4) == 0) {
-			n = (int)simple_strtol(argv[3], NULL, 10);
-			if (!in_range(frow + n, frow + 1, IIM_FMAX + 1,
-				"<frow>+<n> must be between 1-32\n\n",
-				cmdtp->usage))
-				return 1;
-			return ads5121_fuse_read(bank, frow, n);
-		}
-		if (strncmp(argv[1], "ovride", 6) == 0) {
-			v = (int)simple_strtol(argv[3], NULL, 10);
-			return ads5121_fuse_override(bank, frow, v);
-		}
-		if (strncmp(argv[1], "sense", 5) == 0) {
-			n = (int)simple_strtol(argv[3], NULL, 10);
-			if (!in_range(frow + n, frow + 1, IIM_FMAX + 1,
-				"<frow>+<n> must be between 1-32\n\n",
-				cmdtp->usage))
-				return 1;
-			return ads5121_fuse_sense(bank, frow, n);
-		}
-		printf("Usage:\n%s\n", cmdtp->usage);
-		return 1;
-	default: /* at least 5 args */
-		printf("Usage:\n%s\n", cmdtp->usage);
-		return 1;
-	}
-}
-
-U_BOOT_CMD(
-	fuse, CONFIG_SYS_MAXARGS, 0, do_ads5121_fuse,
-	"   - Read, Sense, Override or Program Fuses\n",
-	"bank <n>		- sets active Fuse Bank to 0 or 1\n"
-	"			    no args shows current active bank\n"
-	"fuse stat		- print active fuse bank's protection status\n"
-	"fuse read [<frow> [<n>]] - print <n> fuse rows starting at <frow>\n"
-	"			    no args to print entire bank's fuses\n"
-	"fuse ovride [<frow> [<v>]]- override fuses at <frow> with <v>\n"
-	"			    no <v> defaults to 0 for the row\n"
-	"			    no args resets entire bank to 0\n"
-	"			  NOTE - settings persist until hard reset\n"
-	"fuse sense [<frow>]	- senses current fuse at <frow>\n"
-	"			    no args for entire bank\n"
-	"fuse prog <frow_bit> 	- program fuse at row <frow>, bit <_bit>\n"
-	"			    <frow> is 0-31, <bit> is 0-7; eg. 13_2 \n"
-	"			  WARNING - this is permanent"
-);
-#endif /* CONFIG_CMD_FUSE */
diff --git a/arch/powerpc/cpu/mpc8220/Makefile b/arch/powerpc/cpu/mpc8220/Makefile
deleted file mode 100644
index b8529ef..0000000
--- a/arch/powerpc/cpu/mpc8220/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-SOBJS	= io.o fec_dma_tasks.o
-COBJS	= cpu.o cpu_init.o dramSetup.o fec.o i2c.o \
-	  interrupts.o loadtask.o speed.o \
-	  traps.o uart.o pci.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/powerpc/cpu/mpc8220/config.mk b/arch/powerpc/cpu/mpc8220/config.mk
deleted file mode 100644
index 2c638b5..0000000
--- a/arch/powerpc/cpu/mpc8220/config.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# (C) Copyright 2003-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -meabi
-
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 \
-		     -mstring -mcpu=603e -mmultiple
diff --git a/arch/powerpc/cpu/mpc8220/cpu.c b/arch/powerpc/cpu/mpc8220/cpu.c
deleted file mode 100644
index 64e0526..0000000
--- a/arch/powerpc/cpu/mpc8220/cpu.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code for the MPC8220 CPUs
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <mpc8220.h>
-#include <netdev.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkcpu (void)
-{
-	ulong clock = gd->cpu_clk;
-	char buf[32];
-
-	puts ("CPU:   ");
-
-	printf (CPU_ID_STR);
-
-	printf (" (JTAG ID %08lx)", *(vu_long *) (CONFIG_SYS_MBAR + 0x50));
-
-	printf (" at %s MHz\n", strmhz (buf, clock));
-
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	volatile gptmr8220_t *gptmr = (volatile gptmr8220_t *) MMAP_GPTMR;
-	ulong msr;
-
-	/* Interrupts and MMU off */
-	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
-
-	msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
-	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
-
-	/* Charge the watchdog timer */
-	gptmr->Prescl = 10;
-	gptmr->Count = 1;
-
-	gptmr->Mode = GPT_TMS_SGPIO;
-
-	gptmr->Control = GPT_CTRL_WDEN | GPT_CTRL_CE;
-
-	return 1;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Get timebase clock frequency (like cpu_clk in Hz)
- *
- */
-unsigned long get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = (gd->bus_clk + 3L) / 4L;
-
-	return (tbclk);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_MPC8220_FEC)
-	mpc8220_fec_initialize(bis);
-#endif
-	return 0;
-}
diff --git a/arch/powerpc/cpu/mpc8220/cpu_init.c b/arch/powerpc/cpu/mpc8220/cpu_init.c
deleted file mode 100644
index 8f52c7d..0000000
--- a/arch/powerpc/cpu/mpc8220/cpu_init.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8220.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers.
- */
-void cpu_init_f (void)
-{
-	volatile flexbus8220_t *flexbus = (volatile flexbus8220_t *) MMAP_FB;
-	volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG;
-	volatile xlbarb8220_t *xlbarb = (volatile xlbarb8220_t *) MMAP_XLBARB;
-
-	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
-	/* Clear initial global data */
-	memset ((void *) gd, 0, sizeof (gd_t));
-
-	/* Clear all port configuration */
-	portcfg->pcfg0 = 0;
-	portcfg->pcfg1 = 0;
-	portcfg->pcfg2 = 0;
-	portcfg->pcfg3 = 0;
-	portcfg->pcfg2 = CONFIG_SYS_GP1_PORT2_CONFIG;
-	portcfg->pcfg3 = CONFIG_SYS_PCI_PORT3_CONFIG | CONFIG_SYS_GP2_PORT3_CONFIG;
-
-	/*
-	 * Flexbus Controller: configure chip selects and enable them
-	 */
-#if defined (CONFIG_SYS_CS0_BASE)
-	flexbus->csar0 = CONFIG_SYS_CS0_BASE;
-
-/* Sorcery-C can hang-up after CTRL reg initialization */
-#if defined (CONFIG_SYS_CS0_CTRL)
-	flexbus->cscr0 = CONFIG_SYS_CS0_CTRL;
-#endif
-	flexbus->csmr0 = ((CONFIG_SYS_CS0_MASK - 1) & 0xffff0000) | 1;
-	__asm__ volatile ("sync");
-#endif
-#if defined (CONFIG_SYS_CS1_BASE)
-	flexbus->csar1 = CONFIG_SYS_CS1_BASE;
-	flexbus->cscr1 = CONFIG_SYS_CS1_CTRL;
-	flexbus->csmr1 = ((CONFIG_SYS_CS1_MASK - 1) & 0xffff0000) | 1;
-	__asm__ volatile ("sync");
-#endif
-#if defined (CONFIG_SYS_CS2_BASE)
-	flexbus->csar2 = CONFIG_SYS_CS2_BASE;
-	flexbus->cscr2 = CONFIG_SYS_CS2_CTRL;
-	flexbus->csmr2 = ((CONFIG_SYS_CS2_MASK - 1) & 0xffff0000) | 1;
-	portcfg->pcfg3 |= CONFIG_SYS_CS2_PORT3_CONFIG;
-	__asm__ volatile ("sync");
-#endif
-#if defined (CONFIG_SYS_CS3_BASE)
-	flexbus->csar3 = CONFIG_SYS_CS3_BASE;
-	flexbus->cscr3 = CONFIG_SYS_CS3_CTRL;
-	flexbus->csmr3 = ((CONFIG_SYS_CS3_MASK - 1) & 0xffff0000) | 1;
-	portcfg->pcfg3 |= CONFIG_SYS_CS3_PORT3_CONFIG;
-	__asm__ volatile ("sync");
-#endif
-#if defined (CONFIG_SYS_CS4_BASE)
-	flexbus->csar4 = CONFIG_SYS_CS4_BASE;
-	flexbus->cscr4 = CONFIG_SYS_CS4_CTRL;
-	flexbus->csmr4 = ((CONFIG_SYS_CS4_MASK - 1) & 0xffff0000) | 1;
-	portcfg->pcfg3 |= CONFIG_SYS_CS4_PORT3_CONFIG;
-	__asm__ volatile ("sync");
-#endif
-#if defined (CONFIG_SYS_CS5_BASE)
-	flexbus->csar5 = CONFIG_SYS_CS5_BASE;
-	flexbus->cscr5 = CONFIG_SYS_CS5_CTRL;
-	flexbus->csmr5 = ((CONFIG_SYS_CS5_MASK - 1) & 0xffff0000) | 1;
-	portcfg->pcfg3 |= CONFIG_SYS_CS5_PORT3_CONFIG;
-	__asm__ volatile ("sync");
-#endif
-
-	/* This section of the code cannot place in cpu_init_r(),
-	   it will cause the system to hang */
-	/* enable timebase */
-	xlbarb->addrTenTimeOut = 0x1000;
-	xlbarb->dataTenTimeOut = 0x1000;
-	xlbarb->busActTimeOut = 0x2000;
-
-	xlbarb->config = 0x00002000;
-
-	/* Master Priority Enable */
-	xlbarb->mastPriority = 0;
-	xlbarb->mastPriEn = 0xff;
-}
-
-/*
- * initialize higher level parts of CPU like time base and timers
- */
-int cpu_init_r (void)
-{
-	/* this may belongs to disable interrupt section */
-	/* mask all interrupts */
-	*(vu_long *) 0xf0000700 = 0xfffffc00;
-	*(vu_long *) 0xf0000714 |= 0x0001ffff;
-	*(vu_long *) 0xf0000710 &= ~0x00000f00;
-
-	/* route critical ints to normal ints */
-	*(vu_long *) 0xf0000710 |= 0x00000001;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC8220_FEC)
-	/* load FEC microcode */
-	loadtask (0, 2);
-#endif
-	return (0);
-}
diff --git a/arch/powerpc/cpu/mpc8220/dma.h b/arch/powerpc/cpu/mpc8220/dma.h
deleted file mode 100644
index d06ee63..0000000
--- a/arch/powerpc/cpu/mpc8220/dma.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on code
- * (C) Copyright Motorola, Inc., 2000
- *
- * MPC8220 dma header file
- */
-
-#ifndef __MPC8220_DMA_H
-#define __MPC8220_DMA_H
-
-#include <common.h>
-#include <mpc8220.h>
-
-/* Task number assignment */
-#define FEC_RECV_TASK_NO            0
-#define FEC_XMIT_TASK_NO            1
-
-/*---------------------------------------------------------------------
- * Stuff for Ethernet Tx/Rx tasks
- *---------------------------------------------------------------------
- */
-
-/* Layout of Ethernet controller Parameter SRAM area:
- * ----------------------------------------------------------------
- * 0x00: TBD_BASE, base address of TX BD ring
- * 0x04: TBD_NEXT, address of next TX BD to be processed
- * 0x08: RBD_BASE, base address of RX BD ring
- * 0x0C: RBD_NEXT, address of next RX BD to be processed
- * ---------------------------------------------------------------
- * ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH).
- */
-
-/* base address of SRAM area to store parameters used by Ethernet tasks */
-#define FEC_PARAM_BASE  (MMAP_SRAM + 0x5b00)
-
-/* base address of SRAM area for buffer descriptors */
-#define FEC_BD_BASE     (MMAP_SRAM + 0x5b20)
-
-/*---------------------------------------------------------------------
- * common shortcuts  used  by driver C code
- *---------------------------------------------------------------------
- */
-
-/* Disable SmartDMA task */
-#define DMA_TASK_DISABLE(tasknum)						\
-{										\
-	volatile ushort *tcr = (ushort *)(MMAP_DMA + 0x0000001c + 2 * tasknum); \
-	*tcr = (*tcr) & (~0x8000);						\
-}
-
-/* Enable SmartDMA task */
-#define DMA_TASK_ENABLE(tasknum)						\
-{										\
-	volatile ushort *tcr = (ushort *) (MMAP_DMA + 0x0000001c + 2 * tasknum);\
-	*tcr = (*tcr)  | 0x8000;						\
-}
-
-/* Clear interrupt pending bits */
-#define DMA_CLEAR_IEVENT(tasknum)						\
-{										\
-	struct mpc8220_dma *dma = (struct mpc8220_dma *)MMAP_DMA;		\
-	dma->IntPend = (1 << tasknum);						\
-}
-
-#endif  /* __MPC8220_DMA_H */
diff --git a/arch/powerpc/cpu/mpc8220/dramSetup.c b/arch/powerpc/cpu/mpc8220/dramSetup.c
deleted file mode 100644
index 52cf133..0000000
--- a/arch/powerpc/cpu/mpc8220/dramSetup.c
+++ /dev/null
@@ -1,752 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale, Inc
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-DESCRIPTION
-Read Dram spd and base on its information to calculate the memory size,
-characteristics to initialize the dram on MPC8220
-*/
-
-#include <common.h>
-#include <mpc8220.h>
-#include "i2cCore.h"
-#include "dramSetup.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define SPD_SIZE	CONFIG_SYS_SDRAM_SPD_SIZE
-#define DRAM_SPD	(CONFIG_SYS_SDRAM_SPD_I2C_ADDR)<<1	/* on Board SPD eeprom */
-#define TOTAL_BANK	CONFIG_SYS_SDRAM_TOTAL_BANKS
-
-int spd_status (volatile i2c8220_t * pi2c, u8 sta_bit, u8 truefalse)
-{
-	int i;
-
-	for (i = 0; i < I2C_POLL_COUNT; i++) {
-		if ((pi2c->sr & sta_bit) == (truefalse ? sta_bit : 0))
-			return (OK);
-	}
-
-	return (ERROR);
-}
-
-int spd_clear (volatile i2c8220_t * pi2c)
-{
-	pi2c->adr = 0;
-	pi2c->fdr = 0;
-	pi2c->cr = 0;
-	pi2c->sr = 0;
-
-	return (OK);
-}
-
-int spd_stop (volatile i2c8220_t * pi2c)
-{
-	pi2c->cr &= ~I2C_CTL_STA;	/* Generate stop signal         */
-	if (spd_status (pi2c, I2C_STA_BB, 0) != OK)
-		return ERROR;
-
-	return (OK);
-}
-
-int spd_readbyte (volatile i2c8220_t * pi2c, u8 * readb, int *index)
-{
-	pi2c->sr &= ~I2C_STA_IF;	/* Clear Interrupt Bit          */
-	*readb = pi2c->dr;	/* Read a byte                  */
-
-	/*
-	   Set I2C_CTRL_TXAK will cause Transfer pending and
-	   set I2C_CTRL_STA will cause Interrupt pending
-	 */
-	if (*index != 2) {
-		if (spd_status (pi2c, I2C_STA_CF, 1) != OK)	/* Transfer not complete?       */
-			return ERROR;
-	}
-
-	if (*index != 1) {
-		if (spd_status (pi2c, I2C_STA_IF, 1) != OK)
-			return ERROR;
-	}
-
-	return (OK);
-}
-
-int readSpdData (u8 * spdData)
-{
-	volatile i2c8220_t *pi2cReg;
-	volatile pcfg8220_t *pcfg;
-	u8 slvAdr = DRAM_SPD;
-	u8 Tmp;
-	int Length = SPD_SIZE;
-	int i = 0;
-
-	/* Enable Port Configuration for SDA and SDL signals */
-	pcfg = (volatile pcfg8220_t *) (MMAP_PCFG);
-	__asm__ ("sync");
-	pcfg->pcfg3 &= ~CONFIG_SYS_I2C_PORT3_CONFIG;
-	__asm__ ("sync");
-
-	/* Points the structure to I2c mbar memory offset */
-	pi2cReg = (volatile i2c8220_t *) (MMAP_I2C);
-
-
-	/* Clear FDR, ADR, SR and CR reg */
-	pi2cReg->adr = 0;
-	pi2cReg->fdr = 0;
-	pi2cReg->cr = 0;
-	pi2cReg->sr = 0;
-
-	/* Set for fix XLB Bus Frequency */
-	switch (gd->bus_clk) {
-	case 60000000:
-		pi2cReg->fdr = 0x15;
-		break;
-	case 70000000:
-		pi2cReg->fdr = 0x16;
-		break;
-	case 80000000:
-		pi2cReg->fdr = 0x3a;
-		break;
-	case 90000000:
-		pi2cReg->fdr = 0x17;
-		break;
-	case 100000000:
-		pi2cReg->fdr = 0x3b;
-		break;
-	case 110000000:
-		pi2cReg->fdr = 0x18;
-		break;
-	case 120000000:
-		pi2cReg->fdr = 0x19;
-		break;
-	case 130000000:
-		pi2cReg->fdr = 0x1a;
-		break;
-	}
-
-	pi2cReg->adr = CONFIG_SYS_I2C_SLAVE<<1;
-
-	pi2cReg->cr = I2C_CTL_EN;	/* Set Enable         */
-
-	/*
-	   The I2C bus should be in Idle state. If the bus is busy,
-	   clear the STA bit in control register
-	 */
-	if (spd_status (pi2cReg, I2C_STA_BB, 0) != OK) {
-		if ((pi2cReg->cr & I2C_CTL_STA) == I2C_CTL_STA)
-			pi2cReg->cr &= ~I2C_CTL_STA;
-
-		/* Check again if it is still busy, return error if found */
-		if (spd_status (pi2cReg, I2C_STA_BB, 1) == OK)
-			return ERROR;
-	}
-
-	pi2cReg->cr |= I2C_CTL_TX;	/* Enable the I2c for TX, Ack   */
-	pi2cReg->cr |= I2C_CTL_STA;	/* Generate start signal        */
-
-	if (spd_status (pi2cReg, I2C_STA_BB, 1) != OK)
-		return ERROR;
-
-
-	/* Write slave address */
-	pi2cReg->sr &= ~I2C_STA_IF;	/* Clear Interrupt              */
-	pi2cReg->dr = slvAdr;	/* Write a byte                 */
-
-	if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) {	/* Transfer not complete?       */
-		spd_stop (pi2cReg);
-		return ERROR;
-	}
-
-	if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) {
-		spd_stop (pi2cReg);
-		return ERROR;
-	}
-
-
-	/* Issue the offset to start */
-	pi2cReg->sr &= ~I2C_STA_IF;	/* Clear Interrupt              */
-	pi2cReg->dr = 0;	/* Write a byte                 */
-
-	if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) {	/* Transfer not complete?       */
-		spd_stop (pi2cReg);
-		return ERROR;
-	}
-
-	if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) {
-		spd_stop (pi2cReg);
-		return ERROR;
-	}
-
-
-	/* Set repeat start */
-	pi2cReg->cr |= I2C_CTL_RSTA;	/* Repeat Start                 */
-
-	pi2cReg->sr &= ~I2C_STA_IF;	/* Clear Interrupt              */
-	pi2cReg->dr = slvAdr | 1;	/* Write a byte                 */
-
-	if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) {	/* Transfer not complete?       */
-		spd_stop (pi2cReg);
-		return ERROR;
-	}
-
-	if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) {
-		spd_stop (pi2cReg);
-		return ERROR;
-	}
-
-	if (((pi2cReg->sr & 0x07) == 0x07) || (pi2cReg->sr & 0x01))
-		return ERROR;
-
-	pi2cReg->cr &= ~I2C_CTL_TX;	/* Set receive mode             */
-
-	if (((pi2cReg->sr & 0x07) == 0x07) || (pi2cReg->sr & 0x01))
-		return ERROR;
-
-	/* Dummy Read */
-	if (spd_readbyte (pi2cReg, &Tmp, &i) != OK) {
-		spd_stop (pi2cReg);
-		return ERROR;
-	}
-
-	i = 0;
-	while (Length) {
-		if (Length == 2)
-			pi2cReg->cr |= I2C_CTL_TXAK;
-
-		if (Length == 1)
-			pi2cReg->cr &= ~I2C_CTL_STA;
-
-		if (spd_readbyte (pi2cReg, spdData, &Length) != OK) {
-			return spd_stop (pi2cReg);
-		}
-		i++;
-		Length--;
-		spdData++;
-	}
-
-	/* Stop the service */
-	spd_stop (pi2cReg);
-
-	return OK;
-}
-
-int getBankInfo (int bank, draminfo_t * pBank)
-{
-	int status;
-	int checksum;
-	int count;
-	u8 spdData[SPD_SIZE];
-
-
-	if (bank > 2 || pBank == 0) {
-		/* illegal values */
-		return (-42);
-	}
-
-	status = readSpdData (&spdData[0]);
-	if (status < 0)
-		return (-1);
-
-	/* check the checksum */
-	for (count = 0, checksum = 0; count < LOC_CHECKSUM; count++)
-		checksum += spdData[count];
-
-	checksum = checksum - ((checksum / 256) * 256);
-
-	if (checksum != spdData[LOC_CHECKSUM])
-		return (-2);
-
-	/* Get the memory type */
-	if (!
-	    ((spdData[LOC_TYPE] == TYPE_DDR)
-	     || (spdData[LOC_TYPE] == TYPE_SDR)))
-		/* not one of the types we support */
-		return (-3);
-
-	pBank->type = spdData[LOC_TYPE];
-
-	/* Set logical banks */
-	pBank->banks = spdData[LOC_LOGICAL_BANKS];
-
-	/* Check that we have enough physical banks to cover the bank we are
-	 * figuring out.  Odd-numbered banks correspond to the second bank
-	 * on the device.
-	 */
-	if (bank & 1) {
-		/* Second bank of a "device" */
-		if (spdData[LOC_PHYS_BANKS] < 2)
-			/* this bank doesn't exist on the "device" */
-			return (-4);
-
-		if (spdData[LOC_ROWS] & 0xf0)
-			/* Two asymmetric banks */
-			pBank->rows = spdData[LOC_ROWS] >> 4;
-		else
-			pBank->rows = spdData[LOC_ROWS];
-
-		if (spdData[LOC_COLS] & 0xf0)
-			/* Two asymmetric banks */
-			pBank->cols = spdData[LOC_COLS] >> 4;
-		else
-			pBank->cols = spdData[LOC_COLS];
-	} else {
-		/* First bank of a "device" */
-		pBank->rows = spdData[LOC_ROWS];
-		pBank->cols = spdData[LOC_COLS];
-	}
-
-	pBank->width = spdData[LOC_WIDTH_HIGH] << 8 | spdData[LOC_WIDTH_LOW];
-	pBank->bursts = spdData[LOC_BURSTS];
-	pBank->CAS = spdData[LOC_CAS];
-	pBank->CS = spdData[LOC_CS];
-	pBank->WE = spdData[LOC_WE];
-	pBank->Trp = spdData[LOC_Trp];
-	pBank->Trcd = spdData[LOC_Trcd];
-	pBank->buffered = spdData[LOC_Buffered] & 1;
-	pBank->refresh = spdData[LOC_REFRESH];
-
-	return (0);
-}
-
-
-/* checkMuxSetting -- given a row/column device geometry, return a mask
- *                    of the valid DRAM controller addr_mux settings for
- *                    that geometry.
- *
- *  Arguments:        u8 rows:     number of row addresses in this device
- *                    u8 columns:  number of column addresses in this device
- *
- *  Returns:          a mask of the allowed addr_mux settings for this
- *                    geometry.  Each bit in the mask represents a
- *                    possible addr_mux settings (for example, the
- *                    (1<<2) bit in the mask represents the 0b10 setting)/
- *
- */
-u8 checkMuxSetting (u8 rows, u8 columns)
-{
-	muxdesc_t *pIdx, *pMux;
-	u8 mask;
-	int lrows, lcolumns;
-	u32 mux[4] = { 0x00080c04, 0x01080d03, 0x02080e02, 0xffffffff };
-
-	/* Setup MuxDescriptor in SRAM space */
-	/* MUXDESC AddressRuns [] = {
-	   { 0, 8, 12, 4 },         / setting, columns, rows, extra columns /
-	   { 1, 8, 13, 3 },         / setting, columns, rows, extra columns /
-	   { 2, 8, 14, 2 },         / setting, columns, rows, extra columns /
-	   { 0xff }                 / list terminator /
-	   }; */
-
-	pIdx = (muxdesc_t *) & mux[0];
-
-	/* Check rows x columns against each possible address mux setting */
-	for (pMux = pIdx, mask = 0;; pMux++) {
-		lrows = rows;
-		lcolumns = columns;
-
-		if (pMux->MuxValue == 0xff)
-			break;	/* end of list */
-
-		/* For a given mux setting, since we want all the memory in a
-		 * device to be contiguous, we want the device "use up" the
-		 * address lines such that there are no extra column or row
-		 * address lines on the device.
-		 */
-
-		lcolumns -= pMux->Columns;
-		if (lcolumns < 0)
-			/* Not enough columns to get to the rows */
-			continue;
-
-		lrows -= pMux->Rows;
-		if (lrows > 0)
-			/* we have extra rows left -- can't do that! */
-			continue;
-
-		/* At this point, we either have to have used up all the
-		 * rows or we have to have no columns left.
-		 */
-
-		if (lcolumns != 0 && lrows != 0)
-			/* rows AND columns are left.  Bad! */
-			continue;
-
-		lcolumns -= pMux->MoreColumns;
-
-		if (lcolumns <= 0)
-			mask |= (1 << pMux->MuxValue);
-	}
-
-	return (mask);
-}
-
-
-u32 dramSetup (void)
-{
-	draminfo_t DramInfo[TOTAL_BANK];
-	draminfo_t *pDramInfo;
-	u32 size, temp, cfg_value, mode_value, refresh;
-	u8 *ptr;
-	u8 bursts, Trp, Trcd, type, buffered;
-	u8 muxmask, rows, columns;
-	int count, banknum;
-	u32 *prefresh, *pIdx;
-	u32 refrate[8] = { 15625, 3900, 7800, 31300,
-		62500, 125000, 0xffffffff, 0xffffffff
-	};
-	volatile sysconf8220_t *sysconf;
-	volatile memctl8220_t *memctl;
-
-	sysconf = (volatile sysconf8220_t *) MMAP_MBAR;
-	memctl = (volatile memctl8220_t *) MMAP_MEMCTL;
-
-	/* Set everything in the descriptions to zero */
-	ptr = (u8 *) & DramInfo[0];
-	for (count = 0; count < sizeof (DramInfo); count++)
-		*ptr++ = 0;
-
-	for (banknum = 0; banknum < TOTAL_BANK; banknum++)
-		sysconf->cscfg[banknum];
-
-	/* Descriptions of row/column address muxing for various
-	 * addr_mux settings.
-	 */
-
-	pIdx = prefresh = (u32 *) & refrate[0];
-
-	/* Get all the info for all three logical banks */
-	bursts = 0xff;
-	Trp = 0;
-	Trcd = 0;
-	type = 0;
-	buffered = 0xff;
-	refresh = 0xffffffff;
-	muxmask = 0xff;
-
-	/* Two bank, CS0 and CS1 */
-	for (banknum = 0, pDramInfo = &DramInfo[0];
-	     banknum < TOTAL_BANK; banknum++, pDramInfo++) {
-		pDramInfo->ordinal = banknum;	/* initial sorting */
-		if (getBankInfo (banknum, pDramInfo) < 0)
-			continue;
-
-		/* get cumulative parameters of all three banks */
-		if (type && pDramInfo->type != type)
-			return 0;
-
-		type = pDramInfo->type;
-		rows = pDramInfo->rows;
-		columns = pDramInfo->cols;
-
-		/* This chip only supports 13 DRAM memory lines, but some devices
-		 * have 14 rows.  To deal with this, ignore the 14th address line
-		 * by limiting the number of rows (and columns) to 13.  This will
-		 * mean that for 14-row devices we will only be able to use
-		 * half of the memory, but it's better than nothing.
-		 */
-		if (rows > 13)
-			rows = 13;
-		if (columns > 13)
-			columns = 13;
-
-		pDramInfo->size =
-			((1 << (rows + columns)) * pDramInfo->width);
-		pDramInfo->size *= pDramInfo->banks;
-		pDramInfo->size >>= 3;
-
-		/* figure out which addr_mux configurations will support this device */
-		muxmask &= checkMuxSetting (rows, columns);
-		if (muxmask == 0)
-			return 0;
-
-		buffered = pDramInfo->buffered;
-		bursts &= pDramInfo->bursts;	/* union of all bursts */
-		if (pDramInfo->Trp > Trp)	/* worst case (longest) Trp */
-			Trp = pDramInfo->Trp;
-
-		if (pDramInfo->Trcd > Trcd)	/* worst case (longest) Trcd */
-			Trcd = pDramInfo->Trcd;
-
-		prefresh = pIdx;
-		/* worst case (shortest) Refresh period */
-		if (refresh > prefresh[pDramInfo->refresh & 7])
-			refresh = prefresh[pDramInfo->refresh & 7];
-
-	}			/* for loop */
-
-
-	/* We only allow a burst length of 8! */
-	if (!(bursts & 8))
-		bursts = 8;
-
-	/* Sort the devices.  In order to get each chip select region
-	 * aligned properly, put the biggest device at the lowest address.
-	 * A simple bubble sort will do the trick.
-	 */
-	for (banknum = 0, pDramInfo = &DramInfo[0];
-	     banknum < TOTAL_BANK; banknum++, pDramInfo++) {
-		int i;
-
-		for (i = 0; i < TOTAL_BANK; i++) {
-			if (pDramInfo->size < DramInfo[i].size &&
-			    pDramInfo->ordinal < DramInfo[i].ordinal) {
-				/* If the current bank is smaller, but if the ordinal is also
-				 * smaller, swap the ordinals
-				 */
-				u8 temp8;
-
-				temp8 = DramInfo[i].ordinal;
-				DramInfo[i].ordinal = pDramInfo->ordinal;
-				pDramInfo->ordinal = temp8;
-			}
-		}
-	}
-
-
-	/* Now figure out the base address for each bank.  While
-	 * we're at it, figure out how much memory there is.
-	 *
-	 */
-	size = 0;
-	for (banknum = 0; banknum < TOTAL_BANK; banknum++) {
-		int i;
-
-		for (i = 0; i < TOTAL_BANK; i++) {
-			if (DramInfo[i].ordinal == banknum
-			    && DramInfo[i].size != 0) {
-				DramInfo[i].base = size;
-				size += DramInfo[i].size;
-			}
-		}
-	}
-
-	/* Set up the Drive Strength register */
-	sysconf->sdramds = CONFIG_SYS_SDRAM_DRIVE_STRENGTH;
-
-	/* ********************** Cfg 1 ************************* */
-
-	/* Set the single read to read/write/precharge delay */
-	cfg_value = CFG1_SRD2RWP ((type == TYPE_DDR) ? 7 : 0xb);
-
-	/* Set the single write to read/write/precharge delay.
-	 * This may or may not be correct.  The controller spec
-	 * says "tWR", but "tWR" does not appear in the SPD.  It
-	 * always seems to be 15nsec for the class of device we're
-	 * using, which turns out to be 2 clock cycles at 133MHz,
-	 * so that's what we're going to use.
-	 *
-	 * HOWEVER, because of a bug in the controller, for DDR
-	 * we need to set this to be the same as the value
-	 * calculated for bwt2rwp.
-	 */
-	cfg_value |= CFG1_SWT2RWP ((type == TYPE_DDR) ? 7 : 2);
-
-	/* Set the Read CAS latency.  We're going to use a CL of
-	 * 2.5 for DDR and 2 SDR.
-	 */
-	cfg_value |= CFG1_RLATENCY ((type == TYPE_DDR) ? 7 : 2);
-
-
-	/* Set the Active to Read/Write delay.  This depends
-	 * on Trcd which is reported as nanoseconds times 4.
-	 * We want to calculate Trcd (in nanoseconds) times XLB clock (in Hz)
-	 * which gives us a dimensionless quantity.  Play games with
-	 * the divisions so we don't run out of dynamic ranges.
-	 */
-	/* account for megaherz and the times 4 */
-	temp = (Trcd * (gd->bus_clk / 1000000)) / 4;
-
-	/* account for nanoseconds and round up, with a minimum value of 2 */
-	temp = ((temp + 999) / 1000) - 1;
-	if (temp < 2)
-		temp = 2;
-
-	cfg_value |= CFG1_ACT2WR (temp);
-
-	/* Set the precharge to active delay.  This depends
-	 * on Trp which is reported as nanoseconds times 4.
-	 * We want to calculate Trp (in nanoseconds) times XLB clock (in Hz)
-	 * which gives us a dimensionless quantity.  Play games with
-	 * the divisions so we don't run out of dynamic ranges.
-	 */
-	/* account for megaherz and the times 4 */
-	temp = (Trp * (gd->bus_clk / 1000000)) / 4;
-
-	/* account for nanoseconds and round up, then subtract 1, with a
-	 * minumum value of 1 and a maximum value of 7.
-	 */
-	temp = (((temp + 999) / 1000) - 1) & 7;
-	if (temp < 1)
-		temp = 1;
-
-	cfg_value |= CFG1_PRE2ACT (temp);
-
-	/* Set refresh to active delay.  This depends
-	 * on Trfc which is not reported in the SPD.
-	 * We'll use a nominal value of 75nsec which is
-	 * what the controller spec uses.
-	 */
-	temp = (75 * (gd->bus_clk / 1000000));
-	/* account for nanoseconds and round up, then subtract 1 */
-	cfg_value |= CFG1_REF2ACT (((temp + 999) / 1000) - 1);
-
-	/* Set the write latency, using the values given in the controller spec */
-	cfg_value |= CFG1_WLATENCY ((type == TYPE_DDR) ? 3 : 0);
-	memctl->cfg1 = cfg_value;	/* cfg 1 */
-	asm volatile ("sync");
-
-
-	/* ********************** Cfg 2 ************************* */
-
-	/* Set the burst read to read/precharge delay */
-	cfg_value = CFG2_BRD2RP ((type == TYPE_DDR) ? 5 : 8);
-
-	/* Set the burst write to read/precharge delay.  Semi-magic numbers
-	 * based on the controller spec recommendations, assuming tWR is
-	 * two clock cycles.
-	 */
-	cfg_value |= CFG2_BWT2RWP ((type == TYPE_DDR) ? 7 : 10);
-
-	/* Set the Burst read to write delay.  Semi-magic numbers
-	 * based on the DRAM controller documentation.
-	 */
-	cfg_value |= CFG2_BRD2WT ((type == TYPE_DDR) ? 7 : 0xb);
-
-	/* Set the burst length -- must be 8!! Well, 7, actually, becuase
-	 * it's burst lenght minus 1.
-	 */
-	cfg_value |= CFG2_BURSTLEN (7);
-	memctl->cfg2 = cfg_value;	/* cfg 2 */
-	asm volatile ("sync");
-
-
-	/* ********************** mode ************************* */
-
-	/* Set enable bit, CKE high/low bits, and the DDR/SDR mode bit,
-	 * disable automatic refresh.
-	 */
-	cfg_value = CTL_MODE_ENABLE | CTL_CKE_HIGH |
-		((type == TYPE_DDR) ? CTL_DDR_MODE : 0);
-
-	/* Set the address mux based on whichever setting(s) is/are common
-	 * to all the devices we have.  If there is more than one, choose
-	 * one arbitrarily.
-	 */
-	if (muxmask & 0x4)
-		cfg_value |= CTL_ADDRMUX (2);
-	else if (muxmask & 0x2)
-		cfg_value |= CTL_ADDRMUX (1);
-	else
-		cfg_value |= CTL_ADDRMUX (0);
-
-	/* Set the refresh interval. */
-	temp = ((refresh * (gd->bus_clk / 1000000)) / (1000 * 64)) - 1;
-	cfg_value |= CTL_REFRESH_INTERVAL (temp);
-
-	/* Set buffered/non-buffered memory */
-	if (buffered)
-		cfg_value |= CTL_BUFFERED;
-
-	memctl->ctrl = cfg_value;	/* ctrl */
-	asm volatile ("sync");
-
-	if (type == TYPE_DDR) {
-		/* issue precharge all */
-		temp = cfg_value | CTL_PRECHARGE_CMD;
-		memctl->ctrl = temp;	/* ctrl */
-		asm volatile ("sync");
-	}
-
-
-	/* Set up mode value for CAS latency */
-#if (CONFIG_SYS_SDRAM_CAS_LATENCY==5) /* CL=2.5 */
-	mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) |
-		MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2p5) | MODE_CMD);
-#else
-	mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) |
-		      MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2) | MODE_CMD);
-#endif
-	asm volatile ("sync");
-
-	/* Write Extended Mode  - enable DLL */
-	if (type == TYPE_DDR) {
-		temp = MODE_EXTENDED | MODE_X_DLL_ENABLE |
-			MODE_X_DS_NORMAL | MODE_CMD;
-		memctl->mode = (temp >> 16);	/* mode */
-		asm volatile ("sync");
-
-		/* Write Mode - reset DLL, set CAS latency */
-		temp = mode_value | MODE_OPMODE (MODE_OPMODE_RESETDLL);
-		memctl->mode = (temp >> 16);	/* mode */
-		asm volatile ("sync");
-	}
-
-	/* Program the chip selects. */
-	for (banknum = 0; banknum < TOTAL_BANK; banknum++) {
-		if (DramInfo[banknum].size != 0) {
-			u32 mask;
-			int i;
-
-			for (i = 0, mask = 1; i < 32; mask <<= 1, i++) {
-				if (DramInfo[banknum].size & mask)
-					break;
-			}
-			temp = (DramInfo[banknum].base & 0xfff00000) | (i -
-									1);
-
-			sysconf->cscfg[banknum] = temp;
-			asm volatile ("sync");
-		}
-	}
-
-	/* Wait for DLL lock */
-	udelay (200);
-
-	temp = cfg_value | CTL_PRECHARGE_CMD;	/* issue precharge all */
-	memctl->ctrl = temp;	/* ctrl */
-	asm volatile ("sync");
-
-	temp = cfg_value | CTL_REFRESH_CMD;	/* issue precharge all */
-	memctl->ctrl = temp;	/* ctrl */
-	asm volatile ("sync");
-
-	memctl->ctrl = temp;	/* ctrl */
-	asm volatile ("sync");
-
-	/* Write Mode - DLL normal */
-	temp = mode_value | MODE_OPMODE (MODE_OPMODE_NORMAL);
-	memctl->mode = (temp >> 16);	/* mode */
-	asm volatile ("sync");
-
-	/* Enable refresh, enable DQS's (if DDR), and lock the control register */
-	cfg_value &= ~CTL_MODE_ENABLE;	/* lock register */
-	cfg_value |= CTL_REFRESH_ENABLE;	/* enable refresh */
-
-	if (type == TYPE_DDR)
-		cfg_value |= CTL_DQSOEN (0xf);	/* enable DQS's for DDR */
-
-	memctl->ctrl = cfg_value;	/* ctrl */
-	asm volatile ("sync");
-
-	return size;
-}
diff --git a/arch/powerpc/cpu/mpc8220/dramSetup.h b/arch/powerpc/cpu/mpc8220/dramSetup.h
deleted file mode 100644
index 3b64e08..0000000
--- a/arch/powerpc/cpu/mpc8220/dramSetup.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * dramSetup.h
- *
- * Prototypes, etc. for the Motorola MPC8220
- * embedded cpu chips
- *
- * 2004 (c) Freescale, Inc.
- * Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __INCdramsetuph
-#define __INCdramsetuph
-#ifndef __ASSEMBLY__
-/* Where various things are in the SPD */
-#define LOC_TYPE                    2
-#define LOC_CHECKSUM                63
-#define LOC_PHYS_BANKS              5
-#define LOC_LOGICAL_BANKS           17
-#define LOC_ROWS                    3
-#define LOC_COLS                    4
-#define LOC_WIDTH_HIGH              7
-#define LOC_WIDTH_LOW               6
-#define LOC_REFRESH                 12
-#define LOC_BURSTS                  16
-#define LOC_CAS                     18
-#define LOC_CS                      19
-#define LOC_WE                      20
-#define LOC_Tcyc                    9
-#define LOC_Tac                     10
-#define LOC_Trp                     27
-#define LOC_Trrd                    28
-#define LOC_Trcd                    29
-#define LOC_Tras                    30
-#define LOC_Buffered                21
-/* Types of memory the SPD can tell us about.
- * We can actually only use SDRAM and DDR.
- */
-#define TYPE_DRAM                   1	/* plain old dram */
-#define TYPE_EDO                    2	/* EDO dram */
-#define TYPE_Nibble                 3	/* serial nibble memory */
-#define TYPE_SDR                    4	/* SDRAM */
-#define TYPE_ROM                    5	/*  */
-#define TYPE_SGRRAM                 6	/* graphics memory */
-#define TYPE_DDR                    7	/* DDR sdram */
-#define SDRAMDS_MASK        0x3	/* each field is 2 bits wide */
-#define SDRAMDS_SBE_SHIFT     8	/* Clock enable drive strength */
-#define SDRAMDS_SBC_SHIFT     6	/* Clocks drive strength */
-#define SDRAMDS_SBA_SHIFT     4	/* Address drive strength */
-#define SDRAMDS_SBS_SHIFT     2	/* SDR DQS drive strength */
-#define SDRAMDS_SBD_SHIFT     0	/* Data and DQS drive strength */
-#define  DRIVE_STRENGTH_HIGH 0
-#define  DRIVE_STRENGTH_MED  1
-#define  DRIVE_STRENGTH_LOW  2
-#define  DRIVE_STRENGTH_OFF  3
-
-#define OK      0
-#define ERROR   -1
-/* Structure to hold information about address muxing. */
-	typedef struct tagMuxDescriptor {
-	u8 MuxValue;
-	u8 Columns;
-	u8 Rows;
-	u8 MoreColumns;
-} muxdesc_t;
-
-/* Structure to define one physical bank of
- * memory.  Note that dram size in bytes is
- * (2^^(rows+columns)) * width * banks / 8
-*/
-typedef struct tagDramInfo {
-	u32 size;		/* size in bytes */
-	u32 base;		/* base address */
-	u8 ordinal;		/* where in the memory map will we put this */
-	u8 type;
-	u8 rows;
-	u8 cols;
-	u16 width;		/* width of each chip in bits */
-	u8 banks;		/* number of chips, aka logical banks */
-	u8 bursts;		/* bit-encoded allowable burst length */
-	u8 CAS;			/* bit-encoded CAS latency values */
-	u8 CS;			/* bit-encoded CS latency values */
-	u8 WE;			/* bit-encoded WE latency values */
-	u8 Trp;			/* bit-encoded row precharge time */
-	u8 Trcd;		/* bit-encoded RAS to CAS delay */
-	u8 buffered;		/* buffered or not */
-	u8 refresh;		/* encoded refresh rate */
-} draminfo_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __INCdramsetuph */
diff --git a/arch/powerpc/cpu/mpc8220/fec.c b/arch/powerpc/cpu/mpc8220/fec.c
deleted file mode 100644
index 43fa802..0000000
--- a/arch/powerpc/cpu/mpc8220/fec.c
+++ /dev/null
@@ -1,961 +0,0 @@
-/*
- * (C) Copyright 2003-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on mpc4200fec.c,
- * (C) Copyright Motorola, Inc., 2000
- */
-
-#include <common.h>
-#include <mpc8220.h>
-#include <malloc.h>
-#include <net.h>
-#include <miiphy.h>
-#include "dma.h"
-#include "fec.h"
-
-#undef  DEBUG
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC8220_FEC)
-
-#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
-#error "CONFIG_MII has to be defined!"
-#endif
-
-#ifdef DEBUG
-static void tfifo_print (char *devname, mpc8220_fec_priv * fec);
-static void rfifo_print (char *devname, mpc8220_fec_priv * fec);
-#endif /* DEBUG */
-
-typedef struct {
-	u8 data[1500];		/* actual data */
-	int length;		/* actual length */
-	int used;		/* buffer in use or not */
-	u8 head[16];		/* MAC header(6 + 6 + 2) + 2(aligned) */
-} NBUF;
-
-int fec8220_miiphy_read (const char *devname, u8 phyAddr, u8 regAddr, u16 *retVal);
-int fec8220_miiphy_write (const char *devname, u8 phyAddr, u8 regAddr, u16 data);
-
-/********************************************************************/
-#ifdef DEBUG
-static void mpc8220_fec_phydump (char *devname)
-{
-	u16 phyStatus, i;
-	u8 phyAddr = CONFIG_PHY_ADDR;
-	u8 reg_mask[] = {
-#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
-		/* regs to print: 0...7, 16...19, 21, 23, 24 */
-		1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
-		1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
-#else
-		/* regs to print: 0...8, 16...20 */
-		1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
-		1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-#endif
-	};
-
-	for (i = 0; i < 32; i++) {
-		if (reg_mask[i]) {
-			miiphy_read (devname, phyAddr, i, &phyStatus);
-			printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
-		}
-	}
-}
-#endif
-
-/********************************************************************/
-static int mpc8220_fec_rbd_init (mpc8220_fec_priv * fec)
-{
-	int ix;
-	char *data;
-	static int once = 0;
-
-	for (ix = 0; ix < FEC_RBD_NUM; ix++) {
-		if (!once) {
-			data = (char *) malloc (FEC_MAX_PKT_SIZE);
-			if (data == NULL) {
-				printf ("RBD INIT FAILED\n");
-				return -1;
-			}
-			fec->rbdBase[ix].dataPointer = (u32) data;
-		}
-		fec->rbdBase[ix].status = FEC_RBD_EMPTY;
-		fec->rbdBase[ix].dataLength = 0;
-	}
-	once++;
-
-	/*
-	 * have the last RBD to close the ring
-	 */
-	fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
-	fec->rbdIndex = 0;
-
-	return 0;
-}
-
-/********************************************************************/
-static void mpc8220_fec_tbd_init (mpc8220_fec_priv * fec)
-{
-	int ix;
-
-	for (ix = 0; ix < FEC_TBD_NUM; ix++) {
-		fec->tbdBase[ix].status = 0;
-	}
-
-	/*
-	 * Have the last TBD to close the ring
-	 */
-	fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
-
-	/*
-	 * Initialize some indices
-	 */
-	fec->tbdIndex = 0;
-	fec->usedTbdIndex = 0;
-	fec->cleanTbdNum = FEC_TBD_NUM;
-}
-
-/********************************************************************/
-static void mpc8220_fec_rbd_clean (mpc8220_fec_priv * fec, FEC_RBD * pRbd)
-{
-	/*
-	 * Reset buffer descriptor as empty
-	 */
-	if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
-		pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
-	else
-		pRbd->status = FEC_RBD_EMPTY;
-
-	pRbd->dataLength = 0;
-
-	/*
-	 * Now, we have an empty RxBD, restart the SmartDMA receive task
-	 */
-	DMA_TASK_ENABLE (FEC_RECV_TASK_NO);
-
-	/*
-	 * Increment BD count
-	 */
-	fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
-}
-
-/********************************************************************/
-static void mpc8220_fec_tbd_scrub (mpc8220_fec_priv * fec)
-{
-	FEC_TBD *pUsedTbd;
-
-#ifdef DEBUG
-	printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
-		fec->cleanTbdNum, fec->usedTbdIndex);
-#endif
-
-	/*
-	 * process all the consumed TBDs
-	 */
-	while (fec->cleanTbdNum < FEC_TBD_NUM) {
-		pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
-		if (pUsedTbd->status & FEC_TBD_READY) {
-#ifdef DEBUG
-			printf ("Cannot clean TBD %d, in use\n",
-				fec->cleanTbdNum);
-#endif
-			return;
-		}
-
-		/*
-		 * clean this buffer descriptor
-		 */
-		if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
-			pUsedTbd->status = FEC_TBD_WRAP;
-		else
-			pUsedTbd->status = 0;
-
-		/*
-		 * update some indeces for a correct handling of the TBD ring
-		 */
-		fec->cleanTbdNum++;
-		fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
-	}
-}
-
-/********************************************************************/
-static void mpc8220_fec_set_hwaddr (mpc8220_fec_priv * fec, char *mac)
-{
-	u8 currByte;		/* byte for which to compute the CRC */
-	int byte;		/* loop - counter */
-	int bit;		/* loop - counter */
-	u32 crc = 0xffffffff;	/* initial value */
-
-	/*
-	 * The algorithm used is the following:
-	 * we loop on each of the six bytes of the provided address,
-	 * and we compute the CRC by left-shifting the previous
-	 * value by one position, so that each bit in the current
-	 * byte of the address may contribute the calculation. If
-	 * the latter and the MSB in the CRC are different, then
-	 * the CRC value so computed is also ex-ored with the
-	 * "polynomium generator". The current byte of the address
-	 * is also shifted right by one bit at each iteration.
-	 * This is because the CRC generatore in hardware is implemented
-	 * as a shift-register with as many ex-ores as the radixes
-	 * in the polynomium. This suggests that we represent the
-	 * polynomiumm itself as a 32-bit constant.
-	 */
-	for (byte = 0; byte < 6; byte++) {
-		currByte = mac[byte];
-		for (bit = 0; bit < 8; bit++) {
-			if ((currByte & 0x01) ^ (crc & 0x01)) {
-				crc >>= 1;
-				crc = crc ^ 0xedb88320;
-			} else {
-				crc >>= 1;
-			}
-			currByte >>= 1;
-		}
-	}
-
-	crc = crc >> 26;
-
-	/*
-	 * Set individual hash table register
-	 */
-	if (crc >= 32) {
-		fec->eth->iaddr1 = (1 << (crc - 32));
-		fec->eth->iaddr2 = 0;
-	} else {
-		fec->eth->iaddr1 = 0;
-		fec->eth->iaddr2 = (1 << crc);
-	}
-
-	/*
-	 * Set physical address
-	 */
-	fec->eth->paddr1 =
-		(mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
-	fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
-}
-
-/********************************************************************/
-static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
-{
-	mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv;
-	struct mpc8220_dma *dma = (struct mpc8220_dma *) MMAP_DMA;
-	const u8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
-
-#ifdef DEBUG
-	printf ("mpc8220_fec_init... Begin\n");
-#endif
-
-	/*
-	 * Initialize RxBD/TxBD rings
-	 */
-	mpc8220_fec_rbd_init (fec);
-	mpc8220_fec_tbd_init (fec);
-
-	/*
-	 * Set up Pin Muxing for FEC 1
-	 */
-	*(vu_long *) MMAP_PCFG = 0;
-	*(vu_long *) (MMAP_PCFG + 4) = 0;
-	/*
-	 * Clear FEC-Lite interrupt event register(IEVENT)
-	 */
-	fec->eth->ievent = 0xffffffff;
-
-	/*
-	 * Set interrupt mask register
-	 */
-	fec->eth->imask = 0x00000000;
-
-	/*
-	 * Set FEC-Lite receive control register(R_CNTRL):
-	 */
-	if (fec->xcv_type == SEVENWIRE) {
-		/*
-		 * Frame length=1518; 7-wire mode
-		 */
-		fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
-	} else {
-		/*
-		 * Frame length=1518; MII mode;
-		 */
-		fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
-	}
-
-	fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
-	if (fec->xcv_type != SEVENWIRE) {
-		/*
-		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
-		 * and do not drop the Preamble.
-		 */
-		/*
-		 * tbd - rtm
-		 * fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
-		 * No MII for 7-wire mode
-		 */
-		fec->eth->mii_speed = 0x00000030;
-	}
-
-	/*
-	 * Set Opcode/Pause Duration Register
-	 */
-	fec->eth->op_pause = 0x00010020;	/*FIXME0xffff0020; */
-
-	/*
-	 * Set Rx FIFO alarm and granularity value
-	 */
-	fec->eth->rfifo_cntrl = 0x0c000000;
-	fec->eth->rfifo_alarm = 0x0000030c;
-#ifdef DEBUG
-	if (fec->eth->rfifo_status & 0x00700000) {
-		printf ("mpc8220_fec_init() RFIFO error\n");
-	}
-#endif
-
-	/*
-	 * Set Tx FIFO granularity value
-	 */
-	/*fec->eth->tfifo_cntrl = 0x0c000000; */ /*tbd - rtm */
-	fec->eth->tfifo_cntrl = 0x0e000000;
-#ifdef DEBUG
-	printf ("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
-	printf ("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
-#endif
-
-	/*
-	 * Set transmit fifo watermark register(X_WMRK), default = 64
-	 */
-	fec->eth->tfifo_alarm = 0x00000080;
-	fec->eth->x_wmrk = 0x2;
-
-	/*
-	 * Set individual address filter for unicast address
-	 * and set physical address registers.
-	 */
-	mpc8220_fec_set_hwaddr (fec, (char *)(dev->enetaddr));
-
-	/*
-	 * Set multicast address filter
-	 */
-	fec->eth->gaddr1 = 0x00000000;
-	fec->eth->gaddr2 = 0x00000000;
-
-	/*
-	 * Turn ON cheater FSM: ????
-	 */
-	fec->eth->xmit_fsm = 0x03000000;
-
-#if 1
-/*#if defined(CONFIG_MPC5200)*/
-	/*
-	 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
-	 * work w/ the current receive task.
-	 */
-	dma->PtdCntrl |= 0x00000001;
-#endif
-
-	/*
-	 * Set priority of different initiators
-	 */
-	dma->IPR0 = 7;		/* always */
-	dma->IPR3 = 6;		/* Eth RX */
-	dma->IPR4 = 5;		/* Eth Tx */
-
-	/*
-	 * Clear SmartDMA task interrupt pending bits
-	 */
-	DMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
-
-	/*
-	 * Initialize SmartDMA parameters stored in SRAM
-	 */
-	*(int *) FEC_TBD_BASE = (int) fec->tbdBase;
-	*(int *) FEC_RBD_BASE = (int) fec->rbdBase;
-	*(int *) FEC_TBD_NEXT = (int) fec->tbdBase;
-	*(int *) FEC_RBD_NEXT = (int) fec->rbdBase;
-
-	if (fec->xcv_type != SEVENWIRE) {
-		/*
-		 * Initialize PHY(LXT971A):
-		 *
-		 *   Generally, on power up, the LXT971A reads its configuration
-		 *   pins to check for forced operation, If not cofigured for
-		 *   forced operation, it uses auto-negotiation/parallel detection
-		 *   to automatically determine line operating conditions.
-		 *   If the PHY device on the other side of the link supports
-		 *   auto-negotiation, the LXT971A auto-negotiates with it
-		 *   using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
-		 *   support auto-negotiation, the LXT971A automatically detects
-		 *   the presence of either link pulses(10Mbps PHY) or Idle
-		 *   symbols(100Mbps) and sets its operating conditions accordingly.
-		 *
-		 *   When auto-negotiation is controlled by software, the following
-		 *   steps are recommended.
-		 *
-		 * Note:
-		 *   The physical address is dependent on hardware configuration.
-		 *
-		 */
-		int timeout = 1;
-		u16 phyStatus;
-
-		/*
-		 * Reset PHY, then delay 300ns
-		 */
-		miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
-		udelay (1000);
-
-		if (fec->xcv_type == MII10) {
-			/*
-			 * Force 10Base-T, FDX operation
-			 */
-#ifdef DEBUG
-			printf ("Forcing 10 Mbps ethernet link... ");
-#endif
-			miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
-			/*
-			   miiphy_write(fec, phyAddr, 0x0, 0x0100);
-			 */
-			miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
-
-			timeout = 20;
-			do {	/* wait for link status to go down */
-				udelay (10000);
-				if ((timeout--) == 0) {
-#ifdef DEBUG
-					printf ("hmmm, should not have waited...");
-#endif
-					break;
-				}
-				miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
-#ifdef DEBUG
-				printf ("=");
-#endif
-			} while ((phyStatus & 0x0004)); /* !link up */
-
-			timeout = 1000;
-			do {	/* wait for link status to come back up */
-				udelay (10000);
-				if ((timeout--) == 0) {
-					printf ("failed. Link is down.\n");
-					break;
-				}
-				miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
-#ifdef DEBUG
-				printf ("+");
-#endif
-			} while (!(phyStatus & 0x0004));	/* !link up */
-
-#ifdef DEBUG
-			printf ("done.\n");
-#endif
-		} else {	/* MII100 */
-			/*
-			 * Set the auto-negotiation advertisement register bits
-			 */
-			miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
-
-			/*
-			 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
-			 */
-			miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
-
-			/*
-			 * Wait for AN completion
-			 */
-			timeout = 5000;
-			do {
-				udelay (1000);
-
-				if ((timeout--) == 0) {
-#ifdef DEBUG
-					printf ("PHY auto neg 0 failed...\n");
-#endif
-					return -1;
-				}
-
-				if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) !=
-				    0) {
-#ifdef DEBUG
-					printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
-#endif
-					return -1;
-				}
-			} while (!(phyStatus & 0x0004));
-
-#ifdef DEBUG
-			printf ("PHY auto neg complete! \n");
-#endif
-		}
-
-	}
-
-	/*
-	 * Enable FEC-Lite controller
-	 */
-	fec->eth->ecntrl |= 0x00000006;
-
-#ifdef DEBUG
-	if (fec->xcv_type != SEVENWIRE)
-		mpc8220_fec_phydump (dev->name);
-#endif
-
-	/*
-	 * Enable SmartDMA receive task
-	 */
-	DMA_TASK_ENABLE (FEC_RECV_TASK_NO);
-
-#ifdef DEBUG
-	printf ("mpc8220_fec_init... Done \n");
-#endif
-
-	return 1;
-}
-
-/********************************************************************/
-static void mpc8220_fec_halt (struct eth_device *dev)
-{
-	mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv;
-	int counter = 0xffff;
-
-#ifdef DEBUG
-	if (fec->xcv_type != SEVENWIRE)
-		mpc8220_fec_phydump (dev->name);
-#endif
-
-	/*
-	 * mask FEC chip interrupts
-	 */
-	fec->eth->imask = 0;
-
-	/*
-	 * issue graceful stop command to the FEC transmitter if necessary
-	 */
-	fec->eth->x_cntrl |= 0x00000001;
-
-	/*
-	 * wait for graceful stop to register
-	 */
-	while ((counter--) && (!(fec->eth->ievent & 0x10000000)));
-
-	/*
-	 * Disable SmartDMA tasks
-	 */
-	DMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
-	DMA_TASK_DISABLE (FEC_RECV_TASK_NO);
-
-	/*
-	 * Disable the Ethernet Controller
-	 */
-	fec->eth->ecntrl &= 0xfffffffd;
-
-	/*
-	 * Clear FIFO status registers
-	 */
-	fec->eth->rfifo_status &= 0x00700000;
-	fec->eth->tfifo_status &= 0x00700000;
-
-	fec->eth->reset_cntrl = 0x01000000;
-
-	/*
-	 * Issue a reset command to the FEC chip
-	 */
-	fec->eth->ecntrl |= 0x1;
-
-	/*
-	 * wait at least 16 clock cycles
-	 */
-	udelay (10);
-
-#ifdef DEBUG
-	printf ("Ethernet task stopped\n");
-#endif
-}
-
-#ifdef DEBUG
-/********************************************************************/
-
-static void tfifo_print (char *devname, mpc8220_fec_priv * fec)
-{
-	u16 phyAddr = CONFIG_PHY_ADDR;
-	u16 phyStatus;
-
-	if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
-	    || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
-
-		miiphy_read (devname, phyAddr, 0x1, &phyStatus);
-		printf ("\nphyStatus: 0x%04x\n", phyStatus);
-		printf ("ecntrl:   0x%08x\n", fec->eth->ecntrl);
-		printf ("ievent:   0x%08x\n", fec->eth->ievent);
-		printf ("x_status: 0x%08x\n", fec->eth->x_status);
-		printf ("tfifo: status	0x%08x\n", fec->eth->tfifo_status);
-
-		printf ("	control 0x%08x\n", fec->eth->tfifo_cntrl);
-		printf ("	lrfp	0x%08x\n", fec->eth->tfifo_lrf_ptr);
-		printf ("	lwfp	0x%08x\n", fec->eth->tfifo_lwf_ptr);
-		printf ("	alarm	0x%08x\n", fec->eth->tfifo_alarm);
-		printf ("	readptr 0x%08x\n", fec->eth->tfifo_rdptr);
-		printf ("	writptr 0x%08x\n", fec->eth->tfifo_wrptr);
-	}
-}
-
-static void rfifo_print (char *devname, mpc8220_fec_priv * fec)
-{
-	u16 phyAddr = CONFIG_PHY_ADDR;
-	u16 phyStatus;
-
-	if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
-	    || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
-
-		miiphy_read (devname, phyAddr, 0x1, &phyStatus);
-		printf ("\nphyStatus: 0x%04x\n", phyStatus);
-		printf ("ecntrl:   0x%08x\n", fec->eth->ecntrl);
-		printf ("ievent:   0x%08x\n", fec->eth->ievent);
-		printf ("x_status: 0x%08x\n", fec->eth->x_status);
-		printf ("rfifo: status	0x%08x\n", fec->eth->rfifo_status);
-
-		printf ("	control 0x%08x\n", fec->eth->rfifo_cntrl);
-		printf ("	lrfp	0x%08x\n", fec->eth->rfifo_lrf_ptr);
-		printf ("	lwfp	0x%08x\n", fec->eth->rfifo_lwf_ptr);
-		printf ("	alarm	0x%08x\n", fec->eth->rfifo_alarm);
-		printf ("	readptr 0x%08x\n", fec->eth->rfifo_rdptr);
-		printf ("	writptr 0x%08x\n", fec->eth->rfifo_wrptr);
-	}
-}
-#endif /* DEBUG */
-
-/********************************************************************/
-
-static int mpc8220_fec_send(struct eth_device *dev, void *eth_data,
-			     int data_length)
-{
-	/*
-	 * This routine transmits one frame.  This routine only accepts
-	 * 6-byte Ethernet addresses.
-	 */
-	mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv;
-	FEC_TBD *pTbd;
-
-#ifdef DEBUG
-	printf ("tbd status: 0x%04x\n", fec->tbdBase[0].status);
-	tfifo_print (dev->name, fec);
-#endif
-
-	/*
-	 * Clear Tx BD ring at first
-	 */
-	mpc8220_fec_tbd_scrub (fec);
-
-	/*
-	 * Check for valid length of data.
-	 */
-	if ((data_length > 1500) || (data_length <= 0)) {
-		return -1;
-	}
-
-	/*
-	 * Check the number of vacant TxBDs.
-	 */
-	if (fec->cleanTbdNum < 1) {
-#ifdef DEBUG
-		printf ("No available TxBDs ...\n");
-#endif
-		return -1;
-	}
-
-	/*
-	 * Get the first TxBD to send the mac header
-	 */
-	pTbd = &fec->tbdBase[fec->tbdIndex];
-	pTbd->dataLength = data_length;
-	pTbd->dataPointer = (u32) eth_data;
-	pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
-	fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
-
-#ifdef DEBUG
-	printf ("DMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
-#endif
-
-	/*
-	 * Kick the MII i/f
-	 */
-	if (fec->xcv_type != SEVENWIRE) {
-		u16 phyStatus;
-
-		miiphy_read (dev->name, 0, 0x1, &phyStatus);
-	}
-
-	/*
-	 * Enable SmartDMA transmit task
-	 */
-
-#ifdef DEBUG
-	tfifo_print (dev->name, fec);
-#endif
-
-	DMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
-
-#ifdef DEBUG
-	tfifo_print (dev->name, fec);
-#endif
-
-#ifdef DEBUG
-	printf ("+");
-#endif
-
-	fec->cleanTbdNum -= 1;
-
-#ifdef DEBUG
-	printf ("smartDMA ethernet Tx task enabled\n");
-#endif
-	/*
-	 * wait until frame is sent .
-	 */
-	while (pTbd->status & FEC_TBD_READY) {
-		udelay (10);
-#ifdef DEBUG
-		printf ("TDB status = %04x\n", pTbd->status);
-#endif
-	}
-
-	return 0;
-}
-
-
-/********************************************************************/
-static int mpc8220_fec_recv (struct eth_device *dev)
-{
-	/*
-	 * This command pulls one frame from the card
-	 */
-	mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv;
-	FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
-	unsigned long ievent;
-	int frame_length, len = 0;
-	NBUF *frame;
-
-#ifdef DEBUG
-	printf ("mpc8220_fec_recv %d Start...\n", fec->rbdIndex);
-	printf ("-");
-#endif
-
-	/*
-	 * Check if any critical events have happened
-	 */
-	ievent = fec->eth->ievent;
-	fec->eth->ievent = ievent;
-	if (ievent & 0x20060000) {
-		/* BABT, Rx/Tx FIFO errors */
-		mpc8220_fec_halt (dev);
-		mpc8220_fec_init (dev, NULL);
-		return 0;
-	}
-	if (ievent & 0x80000000) {
-		/* Heartbeat error */
-		fec->eth->x_cntrl |= 0x00000001;
-	}
-	if (ievent & 0x10000000) {
-		/* Graceful stop complete */
-		if (fec->eth->x_cntrl & 0x00000001) {
-			mpc8220_fec_halt (dev);
-			fec->eth->x_cntrl &= ~0x00000001;
-			mpc8220_fec_init (dev, NULL);
-		}
-	}
-
-	if (!(pRbd->status & FEC_RBD_EMPTY)) {
-		if ((pRbd->status & FEC_RBD_LAST)
-		    && !(pRbd->status & FEC_RBD_ERR)
-		    && ((pRbd->dataLength - 4) > 14)) {
-
-			/*
-			 * Get buffer address and size
-			 */
-			frame = (NBUF *) pRbd->dataPointer;
-			frame_length = pRbd->dataLength - 4;
-
-			/* DEBUG code */
-			if (_DEBUG) {
-				int i;
-
-				printf ("recv data hdr:");
-				for (i = 0; i < 14; i++)
-					printf ("%x ", *(frame->head + i));
-				printf ("\n");
-			}
-
-			/*
-			 *  Fill the buffer and pass it to upper layers
-			 */
-/*			memcpy(buff, frame->head, 14);
-			memcpy(buff + 14, frame->data, frame_length);*/
-			NetReceive((uchar *)pRbd->dataPointer, frame_length);
-			len = frame_length;
-		}
-		/*
-		 * Reset buffer descriptor as empty
-		 */
-		mpc8220_fec_rbd_clean (fec, pRbd);
-	}
-	DMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
-	return len;
-}
-
-
-/********************************************************************/
-int mpc8220_fec_initialize (bd_t * bis)
-{
-	mpc8220_fec_priv *fec;
-
-#ifdef CONFIG_HAS_ETH1
-	mpc8220_fec_priv *fec2;
-#endif
-	struct eth_device *dev;
-	char *tmp, *end;
-	char env_enetaddr[6];
-
-#ifdef CONFIG_HAS_ETH1
-	char env_enet1addr[6];
-#endif
-	int i;
-
-	fec = (mpc8220_fec_priv *) malloc (sizeof (*fec));
-	dev = (struct eth_device *) malloc (sizeof (*dev));
-	memset (dev, 0, sizeof *dev);
-
-	fec->eth = (ethernet_regs *) MMAP_FEC1;
-#ifdef CONFIG_HAS_ETH1
-	fec2 = (mpc8220_fec_priv *) malloc (sizeof (*fec));
-	fec2->eth = (ethernet_regs *) MMAP_FEC2;
-#endif
-	fec->tbdBase = (FEC_TBD *) FEC_BD_BASE;
-	fec->rbdBase =
-		(FEC_RBD *) (FEC_BD_BASE + FEC_TBD_NUM * sizeof (FEC_TBD));
-	fec->xcv_type = MII100;
-
-	dev->priv = (void *) fec;
-	dev->iobase = MMAP_FEC1;
-	dev->init = mpc8220_fec_init;
-	dev->halt = mpc8220_fec_halt;
-	dev->send = mpc8220_fec_send;
-	dev->recv = mpc8220_fec_recv;
-
-	sprintf (dev->name, "FEC");
-	eth_register (dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-	miiphy_register (dev->name,
-			fec8220_miiphy_read, fec8220_miiphy_write);
-#endif
-
-	/*
-	 * Try to set the mac address now. The fec mac address is
-	 * a garbage after reset. When not using fec for booting
-	 * the Linux fec driver will try to work with this garbage.
-	 */
-	tmp = getenv ("ethaddr");
-	if (tmp) {
-		for (i = 0; i < 6; i++) {
-			env_enetaddr[i] =
-				tmp ? simple_strtoul (tmp, &end, 16) : 0;
-			if (tmp)
-				tmp = (*end) ? end + 1 : end;
-		}
-		mpc8220_fec_set_hwaddr (fec, env_enetaddr);
-	}
-#ifdef CONFIG_HAS_ETH1
-	tmp = getenv ("eth1addr");
-	if (tmp) {
-		for (i = 0; i < 6; i++) {
-			env_enet1addr[i] =
-				tmp ? simple_strtoul (tmp, &end, 16) : 0;
-			if (tmp)
-				tmp = (*end) ? end + 1 : end;
-		}
-		mpc8220_fec_set_hwaddr (fec2, env_enet1addr);
-	}
-#endif
-
-	return 1;
-}
-
-/* MII-interface related functions */
-/********************************************************************/
-int fec8220_miiphy_read (const char *devname, u8 phyAddr, u8 regAddr, u16 *retVal)
-{
-	ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1;
-	u32 reg;		/* convenient holder for the PHY register */
-	u32 phy;		/* convenient holder for the PHY */
-	int timeout = 0xffff;
-
-	/*
-	 * reading from any PHY's register is done by properly
-	 * programming the FEC's MII data register.
-	 */
-	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
-	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
-
-	eth->mii_data =
-		(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy
-		 | reg);
-
-	/*
-	 * wait for the related interrupt
-	 */
-	while ((timeout--) && (!(eth->ievent & 0x00800000)));
-
-	if (timeout == 0) {
-#ifdef DEBUG
-		printf ("Read MDIO failed...\n");
-#endif
-		return -1;
-	}
-
-	/*
-	 * clear mii interrupt bit
-	 */
-	eth->ievent = 0x00800000;
-
-	/*
-	 * it's now safe to read the PHY's register
-	 */
-	*retVal = (u16) eth->mii_data;
-
-	return 0;
-}
-
-/********************************************************************/
-int fec8220_miiphy_write(const char *devname, u8 phyAddr, u8 regAddr, u16 data)
-{
-	ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1;
-	u32 reg;		/* convenient holder for the PHY register */
-	u32 phy;		/* convenient holder for the PHY */
-	int timeout = 0xffff;
-
-	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
-	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
-
-	eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
-			 FEC_MII_DATA_TA | phy | reg | data);
-
-	/*
-	 * wait for the MII interrupt
-	 */
-	while ((timeout--) && (!(eth->ievent & 0x00800000)));
-
-	if (timeout == 0) {
-#ifdef DEBUG
-		printf ("Write MDIO failed...\n");
-#endif
-		return -1;
-	}
-
-	/*
-	 * clear MII interrupt bit
-	 */
-	eth->ievent = 0x00800000;
-
-	return 0;
-}
-
-#endif /* CONFIG_MPC8220_FEC */
diff --git a/arch/powerpc/cpu/mpc8220/fec.h b/arch/powerpc/cpu/mpc8220/fec.h
deleted file mode 100644
index a8927fc..0000000
--- a/arch/powerpc/cpu/mpc8220/fec.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on mpc4200fec.h
- * (C) Copyright Motorola, Inc., 2000
- *
- * odin ethernet header file
- */
-
-#ifndef __MPC8220_FEC_H
-#define __MPC8220_FEC_H
-
-#include <common.h>
-#include <mpc8220.h>
-#include "dma.h"
-
-typedef struct ethernet_register_set {
-
-/* [10:2]addr = 00 */
-
-/*  Control and status Registers (offset 000-1FF) */
-
-	volatile u32 fec_id;		/* MBAR_ETH + 0x000 */
-	volatile u32 ievent;		/* MBAR_ETH + 0x004 */
-	volatile u32 imask;		/* MBAR_ETH + 0x008 */
-
-	volatile u32 RES0[1];		/* MBAR_ETH + 0x00C */
-	volatile u32 r_des_active;	/* MBAR_ETH + 0x010 */
-	volatile u32 x_des_active;	/* MBAR_ETH + 0x014 */
-	volatile u32 r_des_active_cl;	/* MBAR_ETH + 0x018 */
-	volatile u32 x_des_active_cl;	/* MBAR_ETH + 0x01C */
-	volatile u32 ivent_set;		/* MBAR_ETH + 0x020 */
-	volatile u32 ecntrl;		/* MBAR_ETH + 0x024 */
-
-	volatile u32 RES1[6];		/* MBAR_ETH + 0x028-03C */
-	volatile u32 mii_data;		/* MBAR_ETH + 0x040 */
-	volatile u32 mii_speed;		/* MBAR_ETH + 0x044 */
-	volatile u32 mii_status;	/* MBAR_ETH + 0x048 */
-
-	volatile u32 RES2[5];		/* MBAR_ETH + 0x04C-05C */
-	volatile u32 mib_data;		/* MBAR_ETH + 0x060 */
-	volatile u32 mib_control;	/* MBAR_ETH + 0x064 */
-
-	volatile u32 RES3[6];		/* MBAR_ETH + 0x068-7C */
-	volatile u32 r_activate;	/* MBAR_ETH + 0x080 */
-	volatile u32 r_cntrl;		/* MBAR_ETH + 0x084 */
-	volatile u32 r_hash;		/* MBAR_ETH + 0x088 */
-	volatile u32 r_data;		/* MBAR_ETH + 0x08C */
-	volatile u32 ar_done;		/* MBAR_ETH + 0x090 */
-	volatile u32 r_test;		/* MBAR_ETH + 0x094 */
-	volatile u32 r_mib;		/* MBAR_ETH + 0x098 */
-	volatile u32 r_da_low;		/* MBAR_ETH + 0x09C */
-	volatile u32 r_da_high;		/* MBAR_ETH + 0x0A0 */
-
-	volatile u32 RES4[7];		/* MBAR_ETH + 0x0A4-0BC */
-	volatile u32 x_activate;	/* MBAR_ETH + 0x0C0 */
-	volatile u32 x_cntrl;		/* MBAR_ETH + 0x0C4 */
-	volatile u32 backoff;		/* MBAR_ETH + 0x0C8 */
-	volatile u32 x_data;		/* MBAR_ETH + 0x0CC */
-	volatile u32 x_status;		/* MBAR_ETH + 0x0D0 */
-	volatile u32 x_mib;		/* MBAR_ETH + 0x0D4 */
-	volatile u32 x_test;		/* MBAR_ETH + 0x0D8 */
-	volatile u32 fdxfc_da1;		/* MBAR_ETH + 0x0DC */
-	volatile u32 fdxfc_da2;		/* MBAR_ETH + 0x0E0 */
-	volatile u32 paddr1;		/* MBAR_ETH + 0x0E4 */
-	volatile u32 paddr2;		/* MBAR_ETH + 0x0E8 */
-	volatile u32 op_pause;		/* MBAR_ETH + 0x0EC */
-
-	volatile u32 RES5[4];		/* MBAR_ETH + 0x0F0-0FC */
-	volatile u32 instr_reg;		/* MBAR_ETH + 0x100 */
-	volatile u32 context_reg;	/* MBAR_ETH + 0x104 */
-	volatile u32 test_cntrl;	/* MBAR_ETH + 0x108 */
-	volatile u32 acc_reg;		/* MBAR_ETH + 0x10C */
-	volatile u32 ones;		/* MBAR_ETH + 0x110 */
-	volatile u32 zeros;		/* MBAR_ETH + 0x114 */
-	volatile u32 iaddr1;		/* MBAR_ETH + 0x118 */
-	volatile u32 iaddr2;		/* MBAR_ETH + 0x11C */
-	volatile u32 gaddr1;		/* MBAR_ETH + 0x120 */
-	volatile u32 gaddr2;		/* MBAR_ETH + 0x124 */
-	volatile u32 random;		/* MBAR_ETH + 0x128 */
-	volatile u32 rand1;		/* MBAR_ETH + 0x12C */
-	volatile u32 tmp;		/* MBAR_ETH + 0x130 */
-
-	volatile u32 RES6[3];		/* MBAR_ETH + 0x134-13C */
-	volatile u32 fifo_id;		/* MBAR_ETH + 0x140 */
-	volatile u32 x_wmrk;		/* MBAR_ETH + 0x144 */
-	volatile u32 fcntrl;		/* MBAR_ETH + 0x148 */
-	volatile u32 r_bound;		/* MBAR_ETH + 0x14C */
-	volatile u32 r_fstart;		/* MBAR_ETH + 0x150 */
-	volatile u32 r_count;		/* MBAR_ETH + 0x154 */
-	volatile u32 r_lag;		/* MBAR_ETH + 0x158 */
-	volatile u32 r_read;		/* MBAR_ETH + 0x15C */
-	volatile u32 r_write;		/* MBAR_ETH + 0x160 */
-	volatile u32 x_count;		/* MBAR_ETH + 0x164 */
-	volatile u32 x_lag;		/* MBAR_ETH + 0x168 */
-	volatile u32 x_retry;		/* MBAR_ETH + 0x16C */
-	volatile u32 x_write;		/* MBAR_ETH + 0x170 */
-	volatile u32 x_read;		/* MBAR_ETH + 0x174 */
-
-	volatile u32 RES7[2];		/* MBAR_ETH + 0x178-17C */
-	volatile u32 fm_cntrl;		/* MBAR_ETH + 0x180 */
-	volatile u32 rfifo_data;	/* MBAR_ETH + 0x184 */
-	volatile u32 rfifo_status;	/* MBAR_ETH + 0x188 */
-	volatile u32 rfifo_cntrl;	/* MBAR_ETH + 0x18C */
-	volatile u32 rfifo_lrf_ptr;	/* MBAR_ETH + 0x190 */
-	volatile u32 rfifo_lwf_ptr;	/* MBAR_ETH + 0x194 */
-	volatile u32 rfifo_alarm;	/* MBAR_ETH + 0x198 */
-	volatile u32 rfifo_rdptr;	/* MBAR_ETH + 0x19C */
-	volatile u32 rfifo_wrptr;	/* MBAR_ETH + 0x1A0 */
-	volatile u32 tfifo_data;	/* MBAR_ETH + 0x1A4 */
-	volatile u32 tfifo_status;	/* MBAR_ETH + 0x1A8 */
-	volatile u32 tfifo_cntrl;	/* MBAR_ETH + 0x1AC */
-	volatile u32 tfifo_lrf_ptr;	/* MBAR_ETH + 0x1B0 */
-	volatile u32 tfifo_lwf_ptr;	/* MBAR_ETH + 0x1B4 */
-	volatile u32 tfifo_alarm;	/* MBAR_ETH + 0x1B8 */
-	volatile u32 tfifo_rdptr;	/* MBAR_ETH + 0x1BC */
-	volatile u32 tfifo_wrptr;	/* MBAR_ETH + 0x1C0 */
-
-	volatile u32 reset_cntrl;	/* MBAR_ETH + 0x1C4 */
-	volatile u32 xmit_fsm;		/* MBAR_ETH + 0x1C8 */
-
-	volatile u32 RES8[3];		/* MBAR_ETH + 0x1CC-1D4 */
-	volatile u32 rdes_data0;	/* MBAR_ETH + 0x1D8 */
-	volatile u32 rdes_data1;	/* MBAR_ETH + 0x1DC */
-	volatile u32 r_length;		/* MBAR_ETH + 0x1E0 */
-	volatile u32 x_length;		/* MBAR_ETH + 0x1E4 */
-	volatile u32 x_addr;		/* MBAR_ETH + 0x1E8 */
-	volatile u32 cdes_data;		/* MBAR_ETH + 0x1EC */
-	volatile u32 status;		/* MBAR_ETH + 0x1F0 */
-	volatile u32 dma_control;	/* MBAR_ETH + 0x1F4 */
-	volatile u32 des_cmnd;		/* MBAR_ETH + 0x1F8 */
-	volatile u32 data;		/* MBAR_ETH + 0x1FC */
-
-	/*  MIB COUNTERS (Offset 200-2FF) */
-
-	volatile u32 rmon_t_drop;	/* MBAR_ETH + 0x200 */
-	volatile u32 rmon_t_packets;	/* MBAR_ETH + 0x204 */
-	volatile u32 rmon_t_bc_pkt;	/* MBAR_ETH + 0x208 */
-	volatile u32 rmon_t_mc_pkt;	/* MBAR_ETH + 0x20C */
-	volatile u32 rmon_t_crc_align;	/* MBAR_ETH + 0x210 */
-	volatile u32 rmon_t_undersize;	/* MBAR_ETH + 0x214 */
-	volatile u32 rmon_t_oversize;	/* MBAR_ETH + 0x218 */
-	volatile u32 rmon_t_frag;	/* MBAR_ETH + 0x21C */
-	volatile u32 rmon_t_jab;	/* MBAR_ETH + 0x220 */
-	volatile u32 rmon_t_col;	/* MBAR_ETH + 0x224 */
-	volatile u32 rmon_t_p64;	/* MBAR_ETH + 0x228 */
-	volatile u32 rmon_t_p65to127;	/* MBAR_ETH + 0x22C */
-	volatile u32 rmon_t_p128to255;	/* MBAR_ETH + 0x230 */
-	volatile u32 rmon_t_p256to511;	/* MBAR_ETH + 0x234 */
-	volatile u32 rmon_t_p512to1023;	/* MBAR_ETH + 0x238 */
-	volatile u32 rmon_t_p1024to2047;/* MBAR_ETH + 0x23C */
-	volatile u32 rmon_t_p_gte2048;	/* MBAR_ETH + 0x240 */
-	volatile u32 rmon_t_octets;	/* MBAR_ETH + 0x244 */
-	volatile u32 ieee_t_drop;	/* MBAR_ETH + 0x248 */
-	volatile u32 ieee_t_frame_ok;	/* MBAR_ETH + 0x24C */
-	volatile u32 ieee_t_1col;	/* MBAR_ETH + 0x250 */
-	volatile u32 ieee_t_mcol;	/* MBAR_ETH + 0x254 */
-	volatile u32 ieee_t_def;	/* MBAR_ETH + 0x258 */
-	volatile u32 ieee_t_lcol;	/* MBAR_ETH + 0x25C */
-	volatile u32 ieee_t_excol;	/* MBAR_ETH + 0x260 */
-	volatile u32 ieee_t_macerr;	/* MBAR_ETH + 0x264 */
-	volatile u32 ieee_t_cserr;	/* MBAR_ETH + 0x268 */
-	volatile u32 ieee_t_sqe;	/* MBAR_ETH + 0x26C */
-	volatile u32 t_fdxfc;		/* MBAR_ETH + 0x270 */
-	volatile u32 ieee_t_octets_ok;	/* MBAR_ETH + 0x274 */
-
-	volatile u32 RES9[2];		/* MBAR_ETH + 0x278-27C */
-	volatile u32 rmon_r_drop;	/* MBAR_ETH + 0x280 */
-	volatile u32 rmon_r_packets;	/* MBAR_ETH + 0x284 */
-	volatile u32 rmon_r_bc_pkt;	/* MBAR_ETH + 0x288 */
-	volatile u32 rmon_r_mc_pkt;	/* MBAR_ETH + 0x28C */
-	volatile u32 rmon_r_crc_align;	/* MBAR_ETH + 0x290 */
-	volatile u32 rmon_r_undersize;	/* MBAR_ETH + 0x294 */
-	volatile u32 rmon_r_oversize;	/* MBAR_ETH + 0x298 */
-	volatile u32 rmon_r_frag;	/* MBAR_ETH + 0x29C */
-	volatile u32 rmon_r_jab;	/* MBAR_ETH + 0x2A0 */
-
-	volatile u32 rmon_r_resvd_0;	/* MBAR_ETH + 0x2A4 */
-
-	volatile u32 rmon_r_p64;	/* MBAR_ETH + 0x2A8 */
-	volatile u32 rmon_r_p65to127;	/* MBAR_ETH + 0x2AC */
-	volatile u32 rmon_r_p128to255;	/* MBAR_ETH + 0x2B0 */
-	volatile u32 rmon_r_p256to511;	/* MBAR_ETH + 0x2B4 */
-	volatile u32 rmon_r_p512to1023;	/* MBAR_ETH + 0x2B8 */
-	volatile u32 rmon_r_p1024to2047;/* MBAR_ETH + 0x2BC */
-	volatile u32 rmon_r_p_gte2048;	/* MBAR_ETH + 0x2C0 */
-	volatile u32 rmon_r_octets;	/* MBAR_ETH + 0x2C4 */
-	volatile u32 ieee_r_drop;	/* MBAR_ETH + 0x2C8 */
-	volatile u32 ieee_r_frame_ok;	/* MBAR_ETH + 0x2CC */
-	volatile u32 ieee_r_crc;	/* MBAR_ETH + 0x2D0 */
-	volatile u32 ieee_r_align;	/* MBAR_ETH + 0x2D4 */
-	volatile u32 r_macerr;		/* MBAR_ETH + 0x2D8 */
-	volatile u32 r_fdxfc;		/* MBAR_ETH + 0x2DC */
-	volatile u32 ieee_r_octets_ok;	/* MBAR_ETH + 0x2E0 */
-
-	volatile u32 RES10[6];		/* MBAR_ETH + 0x2E4-2FC */
-
-	volatile u32 RES11[64];		/* MBAR_ETH + 0x300-3FF */
-} ethernet_regs;
-
-/* Receive & Transmit Buffer Descriptor definitions */
-typedef struct BufferDescriptor {
-	u16 status;
-	u16 dataLength;
-	u32 dataPointer;
-} FEC_RBD;
-
-typedef struct {
-	u16 status;
-	u16 dataLength;
-	u32 dataPointer;
-} FEC_TBD;
-
-/* private structure */
-typedef enum {
-	SEVENWIRE,		/* 7-wire       */
-	MII10,			/* MII 10Mbps   */
-	MII100			/* MII 100Mbps  */
-} xceiver_type;
-
-typedef struct {
-	ethernet_regs *eth;
-	xceiver_type xcv_type;	/* transceiver type */
-	FEC_RBD *rbdBase;	/* RBD ring */
-	FEC_TBD *tbdBase;	/* TBD ring */
-	u16 rbdIndex;		/* next receive BD to read */
-	u16 tbdIndex;		/* next transmit BD to send */
-	u16 usedTbdIndex;	/* next transmit BD to clean */
-	u16 cleanTbdNum;	/* the number of available transmit BDs */
-} mpc8220_fec_priv;
-
-/* Ethernet parameter area */
-#define FEC_TBD_BASE	    (FEC_PARAM_BASE + 0x00)
-#define FEC_TBD_NEXT	    (FEC_PARAM_BASE + 0x04)
-#define FEC_RBD_BASE	    (FEC_PARAM_BASE + 0x08)
-#define FEC_RBD_NEXT	    (FEC_PARAM_BASE + 0x0c)
-
-/* BD Numer definitions */
-#define FEC_TBD_NUM	   48	/* The user can adjust this value */
-#define FEC_RBD_NUM	   32	/* The user can adjust this value */
-
-/* packet size limit */
-#define FEC_MAX_PKT_SIZE   1536
-
-/* RBD bits definitions */
-#define FEC_RBD_EMPTY	0x8000	/* Buffer is empty */
-#define FEC_RBD_WRAP	0x2000	/* Last BD in ring */
-#define FEC_RBD_INT	0x1000	/* Interrupt */
-#define FEC_RBD_LAST	0x0800	/* Buffer is last in frame(useless) */
-#define FEC_RBD_MISS	0x0100	/* Miss bit for prom mode */
-#define FEC_RBD_BC	0x0080	/* The received frame is broadcast frame */
-#define FEC_RBD_MC	0x0040	/* The received frame is multicast frame */
-#define FEC_RBD_LG	0x0020	/* Frame length violation */
-#define FEC_RBD_NO	0x0010	/* Nonoctet align frame */
-#define FEC_RBD_SH	0x0008	/* Short frame */
-#define FEC_RBD_CR	0x0004	/* CRC error */
-#define FEC_RBD_OV	0x0002	/* Receive FIFO overrun */
-#define FEC_RBD_TR	0x0001	/* Frame is truncated */
-#define FEC_RBD_ERR	(FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
-			 FEC_RBD_OV | FEC_RBD_TR)
-
-/* TBD bits definitions */
-#define FEC_TBD_READY	0x8000	/* Buffer is ready */
-#define FEC_TBD_WRAP	0x2000	/* Last BD in ring */
-#define FEC_TBD_INT	0x1000	/* Interrupt */
-#define FEC_TBD_LAST	0x0800	/* Buffer is last in frame */
-#define FEC_TBD_TC	0x0400	/* Transmit the CRC */
-#define FEC_TBD_ABC	0x0200	/* Append bad CRC */
-
-/* MII-related definitios */
-#define FEC_MII_DATA_ST		0x40000000	/* Start of frame delimiter */
-#define FEC_MII_DATA_OP_RD	0x20000000	/* Perform a read operation */
-#define FEC_MII_DATA_OP_WR	0x10000000	/* Perform a write operation */
-#define FEC_MII_DATA_PA_MSK	0x0f800000	/* PHY Address field mask */
-#define FEC_MII_DATA_RA_MSK	0x007c0000	/* PHY Register field mask */
-#define FEC_MII_DATA_TA		0x00020000	/* Turnaround */
-#define FEC_MII_DATA_DATAMSK	0x0000ffff	/* PHY data field */
-
-#define FEC_MII_DATA_RA_SHIFT	18	/* MII Register address bits */
-#define FEC_MII_DATA_PA_SHIFT	23	/* MII PHY address bits */
-
-#endif /* __MPC8220_FEC_H */
diff --git a/arch/powerpc/cpu/mpc8220/fec_dma_tasks.S b/arch/powerpc/cpu/mpc8220/fec_dma_tasks.S
deleted file mode 100644
index 3f8a03b..0000000
--- a/arch/powerpc/cpu/mpc8220/fec_dma_tasks.S
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * Copyright (C) 2004, Freescale Semiconductor, Inc.
- *
- * This file contains microcode for the FEC controller of the MPC8220.
- */
-
-#include <config.h>
-
-#if defined(CONFIG_MPC8220)
-
-/* sas/sccg, gas target */
-.section        smartdmaInitData,"aw",@progbits	/* Initialized data for task variables */
-.section        smartdmaTaskTable,"aw",@progbits	/* Task tables */
-.align  9
-.globl taskTable
-taskTable:
-.globl scEthernetRecv_Entry
-scEthernetRecv_Entry:		/* Task 0 */
-.long   scEthernetRecv_TDT - taskTable	/* Task 0 Descriptor Table */
-.long   scEthernetRecv_TDT - taskTable + 0x00000094
-.long   scEthernetRecv_VarTab - taskTable	/* Task 0 Variable Table */
-.long   scEthernetRecv_FDT - taskTable + 0x03	/* Task 0 Function Descriptor Table & Flags */
-.long   0x00000000
-.long   0x00000000
-.long   scEthernetRecv_CSave - taskTable	/* Task 0 context save space */
-.long   0xf0000000
-.globl scEthernetXmit_Entry
-scEthernetXmit_Entry:		/* Task 1 */
-.long   scEthernetXmit_TDT - taskTable	/* Task 1 Descriptor Table */
-.long   scEthernetXmit_TDT - taskTable + 0x000000e0
-.long   scEthernetXmit_VarTab - taskTable	/* Task 1 Variable Table */
-.long   scEthernetXmit_FDT - taskTable + 0x03	/* Task 1 Function Descriptor Table & Flags */
-.long   0x00000000
-.long   0x00000000
-.long   scEthernetXmit_CSave - taskTable	/* Task 1 context save space */
-.long   0xf0000000
-
-
-.globl scEthernetRecv_TDT
-scEthernetRecv_TDT:	/* Task 0 Descriptor Table */
-.long   0xc4c50000	/* 0000(153):  LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */
-.long   0x84c5e000	/* 0004(153):  LCD: idx1 = var9 + var11; ; idx1 += inc0 */
-.long   0x10001f08	/* 0008(156):    DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x10000380	/* 000C(157):    DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x00000f88	/* 0010(158):    DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */
-.long   0x81980000	/* 0014(162):  LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
-.long   0x10000780	/* 0018(164):    DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x60000000	/* 001C(165):    DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long   0x010cf04c	/* 0020(165):    DRD2B1: var4 = EU3(); EU3(var1,var12)  */
-.long   0x82180349	/* 0024(169):  LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */
-.long   0x81c68004	/* 0028(172):    LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */
-.long   0x70000000	/* 002C(174):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long   0x018cf04e	/* 0030(174):      DRD2B1: var6 = EU3(); EU3(var1,var14)  */
-.long   0x70000000	/* 0034(175):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long   0x020cf04f	/* 0038(175):      DRD2B1: var8 = EU3(); EU3(var1,var15)  */
-.long   0x00000b88	/* 003C(176):      DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */
-.long   0x80025184	/* 0040(205):    LCDEXT: idx1 = 0xf0009184; ; */
-.long   0x86810412	/* 0044(205):    LCD: idx2 = var13, idx3 = var2; idx2 < var16; idx2 += inc2, idx3 += inc2 */
-.long   0x0200cf88	/* 0048(209):      DRD1A: *idx3 = *idx1; FN=0 init=16 WS=0 RS=0 */
-.long   0x80025184	/* 004C(217):    LCDEXT: idx1 = 0xf0009184; ; */
-.long   0x8681845b	/* 0050(217):    LCD: idx2 = var13, idx3 = var3; idx2 < var17; idx2 += inc3, idx3 += inc3 */
-.long   0x0000cf88	/* 0054(221):      DRD1A: *idx3 = *idx1; FN=0 init=0 WS=0 RS=0 */
-.long   0xc31883a4	/* 0058(225):    LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc4 */
-.long   0x80190000	/* 005C(225):    LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
-.long   0x04008468	/* 0060(227):      DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */
-.long   0xc4038360	/* 0064(232):    LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc4, idx2 += inc0 */
-.long   0x81c50000	/* 0068(233):    LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */
-.long   0x1000cb18	/* 006C(235):      DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x00000f18	/* 0070(236):      DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
-.long   0xc418836d	/* 0074(238):    LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc5 */
-.long   0x83990000	/* 0078(238):    LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */
-.long   0x10000c00	/* 007C(240):      DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x0000c800	/* 0080(241):      DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */
-.long   0x81988000	/* 0084(245):    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
-.long   0x10000788	/* 0088(247):      DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x60000000	/* 008C(248):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long   0x080cf04c	/* 0090(248):      DRD2B1: idx0 = EU3(); EU3(var1,var12)  */
-.long   0x000001f8	/* 0094(:0):    NOP */
-
-
-.globl scEthernetXmit_TDT
-scEthernetXmit_TDT:	/* Task 1 Descriptor Table */
-.long   0x80095b00	/* 0000(280):  LCDEXT: idx0 = 0xf0025b00; ; */
-.long   0x85c60004	/* 0004(280):  LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */
-.long   0x10002308	/* 0008(283):    DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x10000f88	/* 000C(284):    DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x00000380	/* 0010(285):    DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */
-.long   0x81980000	/* 0014(288):  LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
-.long   0x10000780	/* 0018(290):    DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x60000000	/* 001C(291):    DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long   0x024cf04d	/* 0020(291):    DRD2B1: var9 = EU3(); EU3(var1,var13)  */
-.long   0x84980309	/* 0024(294):  LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */
-.long   0xc0004003	/* 0028(297):    LCDEXT: idx1 = 0x00000003; ; */
-.long   0x81c60004	/* 002C(297):    LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */
-.long   0x70000000	/* 0030(299):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long   0x010cf04e	/* 0034(299):      DRD2B1: var4 = EU3(); EU3(var1,var14)  */
-.long   0x70000000	/* 0038(300):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long   0x014cf04f	/* 003C(300):      DRD2B1: var5 = EU3(); EU3(var1,var15)  */
-.long   0x70000000	/* 0040(301):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long   0x028cf050	/* 0044(301):      DRD2B1: var10 = EU3(); EU3(var1,var16)  */
-.long   0x70000000	/* 0048(302):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long   0x018cf051	/* 004C(302):      DRD2B1: var6 = EU3(); EU3(var1,var17)  */
-.long   0x10000b90	/* 0050(303):      DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x60000000	/* 0054(304):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long   0x01ccf0a1	/* 0058(304):      DRD2B1: var7 = EU3(); EU3(var2,idx1)  */
-.long   0xc2988312	/* 005C(308):    LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */
-.long   0x83490000	/* 0060(308):    LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */
-.long   0x00001b10	/* 0064(310):      DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */
-.long   0x800251a4	/* 0068(315):    LCDEXT: idx1 = 0xf00091a4; ; */
-.long   0xc30104dc	/* 006C(315):    LCDEXT: idx2 = var6, idx3 = var2; idx2 >= var19; idx2 += inc3, idx3 += inc4 */
-.long   0x839a032d	/* 0070(316):    LCD: idx4 = var7; idx4 == var12; idx4 += inc5 */
-.long   0x0220c798	/* 0074(321):      DRD1A: *idx1 = *idx3; FN=0 init=17 WS=0 RS=0 */
-.long   0x800251a4	/* 0078(329):    LCDEXT: idx1 = 0xf00091a4; ; */
-.long   0x99198337	/* 007C(329):    LCD: idx2 = idx2, idx3 = idx3; idx2 > var12; idx2 += inc6, idx3 += inc7 */
-.long   0x022ac798	/* 0080(333):      DRD1A: *idx1 = *idx3; FN=0 init=17 WS=1 RS=1 */
-.long   0x800251a4	/* 0084(350):    LCDEXT: idx1 = 0xf00091a4; ; */
-.long   0xc1430000	/* 0088(350):    LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */
-.long   0x82998312	/* 008C(351):    LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */
-.long   0x0a2ac790	/* 0090(354):      DRD1A: *idx1 = *idx2; FN=0 TFD init=17 WS=1 RS=1 */
-.long   0x81988000	/* 0094(359):    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
-.long   0x60000002	/* 0098(361):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=0 RS=0 */
-.long   0x0c4cfc4d	/* 009C(361):      DRD2B1: *idx1 = EU3(); EU3(*idx1,var13)  */
-.long   0xc21883ad	/* 00A0(365):    LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */
-.long   0x80190000	/* 00A4(365):    LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
-.long   0x04008460	/* 00A8(367):      DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */
-.long   0xc4052305	/* 00AC(371):    LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */
-.long   0x81ca0000	/* 00B0(372):    LCD: idx3 = var3 + var20; idx3 once var0; idx3 += inc0 */
-.long   0x1000c718	/* 00B4(374):      DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x00000f18	/* 00B8(375):      DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
-.long   0xc4188000	/* 00BC(378):    LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */
-.long   0x85190312	/* 00C0(378):    LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */
-.long   0x10000c00	/* 00C4(380):      DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x1000c400	/* 00C8(381):      DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x00008860	/* 00CC(382):      DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */
-.long   0x81988000	/* 00D0(386):    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
-.long   0x10000788	/* 00D4(388):      DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x60000000	/* 00D8(389):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long   0x080cf04d	/* 00DC(389):      DRD2B1: idx0 = EU3(); EU3(var1,var13)  */
-.long   0x000001f8	/* 00E0(:0):    NOP */
-
-.align 8
-
-.globl scEthernetRecv_VarTab
-scEthernetRecv_VarTab:	/* Task 0 Variable Table */
-.long   0x00000000	/* var[0] */
-.long   0x00000000	/* var[1] */
-.long   0x00000000	/* var[2] */
-.long   0x00000000	/* var[3] */
-.long   0x00000000	/* var[4] */
-.long   0x00000000	/* var[5] */
-.long   0x00000000	/* var[6] */
-.long   0x00000000	/* var[7] */
-.long   0x00000000	/* var[8] */
-.long   0xf0025b00	/* var[9] */
-.long   0x00000008	/* var[10] */
-.long   0x0000000c	/* var[11] */
-.long   0x80000000	/* var[12] */
-.long   0x00000000	/* var[13] */
-.long   0x10000000	/* var[14] */
-.long   0x20000000	/* var[15] */
-.long   0x00000800	/* var[16] */
-.long   0x00000001	/* var[17] */
-.long   0x00000000	/* var[18] */
-.long   0x00000000	/* var[19] */
-.long   0x00000000	/* var[20] */
-.long   0x00000000	/* var[21] */
-.long   0x00000000	/* var[22] */
-.long   0x00000000	/* var[23] */
-.long   0x00000000	/* inc[0] */
-.long   0x60000000	/* inc[1] */
-.long   0x20000004	/* inc[2] */
-.long   0x20000001	/* inc[3] */
-.long   0x80000000	/* inc[4] */
-.long   0x40000000	/* inc[5] */
-.long   0x00000000	/* inc[6] */
-.long   0x00000000	/* inc[7] */
-
-.align  8
-
-.globl scEthernetXmit_VarTab
-scEthernetXmit_VarTab:	/* Task 1 Variable Table */
-.long   0x00000000	/* var[0] */
-.long   0x00000000	/* var[1] */
-.long   0x00000000	/* var[2] */
-.long   0x00000000	/* var[3] */
-.long   0x00000000	/* var[4] */
-.long   0x00000000	/* var[5] */
-.long   0x00000000	/* var[6] */
-.long   0x00000000	/* var[7] */
-.long   0x00000000	/* var[8] */
-.long   0x00000000	/* var[9] */
-.long   0x00000000	/* var[10] */
-.long   0xf0025b00	/* var[11] */
-.long   0x00000000	/* var[12] */
-.long   0x80000000	/* var[13] */
-.long   0x10000000	/* var[14] */
-.long   0x08000000	/* var[15] */
-.long   0x20000000	/* var[16] */
-.long   0x0000ffff	/* var[17] */
-.long   0xffffffff	/* var[18] */
-.long   0x00000004	/* var[19] */
-.long   0x00000008	/* var[20] */
-.long   0x00000000	/* var[21] */
-.long   0x00000000	/* var[22] */
-.long   0x00000000	/* var[23] */
-.long   0x00000000	/* inc[0] */
-.long   0x60000000	/* inc[1] */
-.long   0x40000000	/* inc[2] */
-.long   0xc000fffc	/* inc[3] */
-.long   0xe0000004	/* inc[4] */
-.long   0x80000000	/* inc[5] */
-.long   0x4000ffff	/* inc[6] */
-.long   0xe0000001	/* inc[7] */
-
-.align 8
-
-.globl scEthernetRecv_FDT
-scEthernetRecv_FDT:	/* Task 0 Function Descriptor Table */
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x21800000	/* and(), EU# 3 */
-.long   0x21e00000	/* or(), EU# 3 */
-.long   0x21400000	/* andn(), EU# 3 */
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-
-.align 8
-
-.globl scEthernetXmit_FDT
-scEthernetXmit_FDT:	/* Task 1 Function Descriptor Table */
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x21800000	/* and(), EU# 3 */
-.long   0x21e00000	/* or(), EU# 3 */
-.long   0x21400000	/* andn(), EU# 3 */
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-
-
-.globl scEthernetRecv_CSave
-scEthernetRecv_CSave:	/* Task 0 context save space */
-.space  128, 0x0
-
-
-.globl scEthernetXmit_CSave
-scEthernetXmit_CSave:	/* Task 1 context save space */
-.space  128, 0x0
-
-#endif
diff --git a/arch/powerpc/cpu/mpc8220/i2c.c b/arch/powerpc/cpu/mpc8220/i2c.c
deleted file mode 100644
index 2f35d20..0000000
--- a/arch/powerpc/cpu/mpc8220/i2c.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale, Inc
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_HARD_I2C
-
-#include <mpc8220.h>
-#include <i2c.h>
-
-typedef struct mpc8220_i2c {
-	volatile u32 adr;	/* I2Cn + 0x00 */
-	volatile u32 fdr;	/* I2Cn + 0x04 */
-	volatile u32 cr;	/* I2Cn + 0x08 */
-	volatile u32 sr;	/* I2Cn + 0x0C */
-	volatile u32 dr;	/* I2Cn + 0x10 */
-} i2c_t;
-
-/* I2Cn control register bits */
-#define I2C_EN      0x80
-#define I2C_IEN     0x40
-#define I2C_STA     0x20
-#define I2C_TX      0x10
-#define I2C_TXAK    0x08
-#define I2C_RSTA    0x04
-#define I2C_INIT_MASK   (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
-
-/* I2Cn status register bits */
-#define I2C_CF      0x80
-#define I2C_AAS     0x40
-#define I2C_BB      0x20
-#define I2C_AL      0x10
-#define I2C_SRW     0x04
-#define I2C_IF      0x02
-#define I2C_RXAK    0x01
-
-#define I2C_TIMEOUT 100
-#define I2C_RETRIES 1
-
-struct mpc8220_i2c_tap {
-	int scl2tap;
-	int tap2tap;
-};
-
-static int mpc_reg_in (volatile u32 * reg);
-static void mpc_reg_out (volatile u32 * reg, int val, int mask);
-static int wait_for_bb (void);
-static int wait_for_pin (int *status);
-static int do_address (uchar chip, char rdwr_flag);
-static int send_bytes (uchar chip, char *buf, int len);
-static int receive_bytes (uchar chip, char *buf, int len);
-static int mpc_get_fdr (int);
-
-static int mpc_reg_in (volatile u32 * reg)
-{
-	int ret;
-	ret = *reg >> 24;
-	__asm__ __volatile__ ("eieio");
-	return ret;
-}
-
-static void mpc_reg_out (volatile u32 * reg, int val, int mask)
-{
-	int tmp;
-
-	if (!mask) {
-		*reg = val << 24;
-	} else {
-		tmp = mpc_reg_in (reg);
-		*reg = ((tmp & ~mask) | (val & mask)) << 24;
-	}
-	__asm__ __volatile__ ("eieio");
-
-	return;
-}
-
-static int wait_for_bb (void)
-{
-	i2c_t *regs = (i2c_t *) MMAP_I2C;
-	int timeout = I2C_TIMEOUT;
-	int status;
-
-	status = mpc_reg_in (&regs->sr);
-
-	while (timeout-- && (status & I2C_BB)) {
-
-		mpc_reg_out (&regs->cr, I2C_STA, I2C_STA);
-		(void)mpc_reg_in (&regs->dr);
-		mpc_reg_out (&regs->cr, 0, I2C_STA);
-		mpc_reg_out (&regs->cr, 0, 0);
-		mpc_reg_out (&regs->cr, I2C_EN, 0);
-
-		udelay (1000);
-		status = mpc_reg_in (&regs->sr);
-	}
-
-	return (status & I2C_BB);
-}
-
-static int wait_for_pin (int *status)
-{
-	i2c_t *regs = (i2c_t *) MMAP_I2C;
-	int timeout = I2C_TIMEOUT;
-
-	*status = mpc_reg_in (&regs->sr);
-
-	while (timeout-- && !(*status & I2C_IF)) {
-		udelay (1000);
-		*status = mpc_reg_in (&regs->sr);
-	}
-
-	if (!(*status & I2C_IF)) {
-		return -1;
-	}
-
-	mpc_reg_out (&regs->sr, 0, I2C_IF);
-	return 0;
-}
-
-static int do_address (uchar chip, char rdwr_flag)
-{
-	i2c_t *regs = (i2c_t *) MMAP_I2C;
-	int status;
-
-	chip <<= 1;
-
-	if (rdwr_flag)
-		chip |= 1;
-
-	mpc_reg_out (&regs->cr, I2C_TX, I2C_TX);
-	mpc_reg_out (&regs->dr, chip, 0);
-
-	if (wait_for_pin (&status))
-		return -2;
-	if (status & I2C_RXAK)
-		return -3;
-	return 0;
-}
-
-static int send_bytes (uchar chip, char *buf, int len)
-{
-	i2c_t *regs = (i2c_t *) MMAP_I2C;
-	int wrcount;
-	int status;
-
-	for (wrcount = 0; wrcount < len; ++wrcount) {
-
-		mpc_reg_out (&regs->dr, buf[wrcount], 0);
-
-		if (wait_for_pin (&status))
-			break;
-
-		if (status & I2C_RXAK)
-			break;
-
-	}
-
-	return !(wrcount == len);
-	return 0;
-}
-
-static int receive_bytes (uchar chip, char *buf, int len)
-{
-	i2c_t *regs = (i2c_t *) MMAP_I2C;
-	int dummy = 1;
-	int rdcount = 0;
-	int status;
-	int i;
-
-	mpc_reg_out (&regs->cr, 0, I2C_TX);
-
-	for (i = 0; i < len; ++i) {
-		buf[rdcount] = mpc_reg_in (&regs->dr);
-
-		if (dummy)
-			dummy = 0;
-		else
-			rdcount++;
-
-		if (wait_for_pin (&status))
-			return -4;
-	}
-
-	mpc_reg_out (&regs->cr, I2C_TXAK, I2C_TXAK);
-	buf[rdcount++] = mpc_reg_in (&regs->dr);
-
-	if (wait_for_pin (&status))
-		return -5;
-
-	mpc_reg_out (&regs->cr, 0, I2C_TXAK);
-	return 0;
-}
-
-/**************** I2C API ****************/
-
-void i2c_init (int speed, int saddr)
-{
-	i2c_t *regs = (i2c_t *) MMAP_I2C;
-
-	mpc_reg_out (&regs->cr, 0, 0);
-	mpc_reg_out (&regs->adr, saddr << 1, 0);
-
-	/* Set clock
-	 */
-	mpc_reg_out (&regs->fdr, mpc_get_fdr (speed), 0);
-
-	/* Enable module
-	 */
-	mpc_reg_out (&regs->cr, I2C_EN, I2C_INIT_MASK);
-	mpc_reg_out (&regs->sr, 0, I2C_IF);
-	return;
-}
-
-static int mpc_get_fdr (int speed)
-{
-	static int fdr = -1;
-
-	if (fdr == -1) {
-		ulong best_speed = 0;
-		ulong divider;
-		ulong ipb, scl;
-		ulong bestmatch = 0xffffffffUL;
-		int best_i = 0, best_j = 0, i, j;
-		int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8 };
-		struct mpc8220_i2c_tap scltap[] = {
-			{4, 1},
-			{4, 2},
-			{6, 4},
-			{6, 8},
-			{14, 16},
-			{30, 32},
-			{62, 64},
-			{126, 128}
-		};
-
-		ipb = gd->bus_clk;
-		for (i = 7; i >= 0; i--) {
-			for (j = 7; j >= 0; j--) {
-				scl = 2 * (scltap[j].scl2tap +
-					   (SCL_Tap[i] -
-					    1) * scltap[j].tap2tap + 2);
-				if (ipb <= speed * scl) {
-					if ((speed * scl - ipb) < bestmatch) {
-						bestmatch = speed * scl - ipb;
-						best_i = i;
-						best_j = j;
-						best_speed = ipb / scl;
-					}
-				}
-			}
-		}
-		divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2);
-		if (gd->flags & GD_FLG_RELOC) {
-			fdr = divider;
-		} else {
-			printf ("%ld kHz, ", best_speed / 1000);
-			return divider;
-		}
-	}
-
-	return fdr;
-}
-
-int i2c_probe (uchar chip)
-{
-	i2c_t *regs = (i2c_t *) MMAP_I2C;
-	int i;
-
-	for (i = 0; i < I2C_RETRIES; i++) {
-		mpc_reg_out (&regs->cr, I2C_STA, I2C_STA);
-
-		if (!do_address (chip, 0)) {
-			mpc_reg_out (&regs->cr, 0, I2C_STA);
-			break;
-		}
-
-		mpc_reg_out (&regs->cr, 0, I2C_STA);
-		udelay (50);
-	}
-
-	return (i == I2C_RETRIES);
-}
-
-int i2c_read (uchar chip, uint addr, int alen, uchar * buf, int len)
-{
-	uchar xaddr[4];
-	i2c_t *regs = (i2c_t *) MMAP_I2C;
-	int ret = -1;
-
-	xaddr[0] = (addr >> 24) & 0xFF;
-	xaddr[1] = (addr >> 16) & 0xFF;
-	xaddr[2] = (addr >> 8) & 0xFF;
-	xaddr[3] = addr & 0xFF;
-
-	if (wait_for_bb ()) {
-		printf ("i2c_read: bus is busy\n");
-		goto Done;
-	}
-
-	mpc_reg_out (&regs->cr, I2C_STA, I2C_STA);
-	if (do_address (chip, 0)) {
-		printf ("i2c_read: failed to address chip\n");
-		goto Done;
-	}
-
-	if (send_bytes (chip, (char *)&xaddr[4 - alen], alen)) {
-		printf ("i2c_read: send_bytes failed\n");
-		goto Done;
-	}
-
-	mpc_reg_out (&regs->cr, I2C_RSTA, I2C_RSTA);
-	if (do_address (chip, 1)) {
-		printf ("i2c_read: failed to address chip\n");
-		goto Done;
-	}
-
-	if (receive_bytes (chip, (char *)buf, len)) {
-		printf ("i2c_read: receive_bytes failed\n");
-		goto Done;
-	}
-
-	ret = 0;
-      Done:
-	mpc_reg_out (&regs->cr, 0, I2C_STA);
-	return ret;
-}
-
-int i2c_write (uchar chip, uint addr, int alen, uchar * buf, int len)
-{
-	uchar xaddr[4];
-	i2c_t *regs = (i2c_t *) MMAP_I2C;
-	int ret = -1;
-
-	xaddr[0] = (addr >> 24) & 0xFF;
-	xaddr[1] = (addr >> 16) & 0xFF;
-	xaddr[2] = (addr >> 8) & 0xFF;
-	xaddr[3] = addr & 0xFF;
-
-	if (wait_for_bb ()) {
-		printf ("i2c_write: bus is busy\n");
-		goto Done;
-	}
-
-	mpc_reg_out (&regs->cr, I2C_STA, I2C_STA);
-	if (do_address (chip, 0)) {
-		printf ("i2c_write: failed to address chip\n");
-		goto Done;
-	}
-
-	if (send_bytes (chip, (char *)&xaddr[4 - alen], alen)) {
-		printf ("i2c_write: send_bytes failed\n");
-		goto Done;
-	}
-
-	if (send_bytes (chip, (char *)buf, len)) {
-		printf ("i2c_write: send_bytes failed\n");
-		goto Done;
-	}
-
-	ret = 0;
-      Done:
-	mpc_reg_out (&regs->cr, 0, I2C_STA);
-	return ret;
-}
-
-#endif /* CONFIG_HARD_I2C */
diff --git a/arch/powerpc/cpu/mpc8220/i2cCore.c b/arch/powerpc/cpu/mpc8220/i2cCore.c
deleted file mode 100644
index b89ad03..0000000
--- a/arch/powerpc/cpu/mpc8220/i2cCore.c
+++ /dev/null
@@ -1,627 +0,0 @@
-/* I2cCore.c - MPC8220 PPC I2C Library */
-
-/* Copyright 2004      Freescale Semiconductor, Inc. */
-
-/*
-modification history
---------------------
-01c,29jun04,tcl	 1.3	removed CR. Added two bytes offset support.
-01b,19jan04,tcl	 1.2	removed i2cMsDelay and sysDecGet. renamed i2cMsDelay
-			back to sysMsDelay
-01a,19jan04,tcl	 1.1	created and seperated from i2c.c
-*/
-
-/*
-DESCRIPTION
-This file contain I2C low level handling library functions
-*/
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <vxWorks.h>
-#include <sysLib.h>
-#include <iosLib.h>
-#include <logLib.h>
-#include <tickLib.h>
-
-/* BSP Includes */
-#include "config.h"
-#include "mpc8220.h"
-#include "i2cCore.h"
-
-#ifdef DEBUG_I2CCORE
-int I2CCDbg = 0;
-#endif
-
-#define ABS(x)	((x < 0)? -x : x)
-
-char *I2CERR[16] = {
-	"Transfer in Progress\n",	/* 0 */
-	"Transfer complete\n",
-	"Not Addressed\n",		/* 2 */
-	"Addressed as a slave\n",
-	"Bus is Idle\n",		/* 4 */
-	"Bus is busy\n",
-	"Arbitration Lost\n",		/* 6 */
-	"Arbitration on Track\n",
-	"Slave receive, master writing to slave\n",	/* 8 */
-	"Slave transmit, master reading from slave\n",
-	"Interrupt is pending\n",	/* 10 */
-	"Interrupt complete\n",
-	"Acknowledge received\n",	/* 12 */
-	"No acknowledge received\n",
-	"Unknown status\n",		/* 14 */
-	"\n"
-};
-
-/******************************************************************************
- *
- * chk_status - Check I2C status bit
- *
- * RETURNS: OK, or ERROR if the bit encounter
- *
- */
-
-STATUS chk_status (PSI2C pi2c, UINT8 sta_bit, UINT8 truefalse)
-{
-	int i, status = 0;
-
-	for (i = 0; i < I2C_POLL_COUNT; i++) {
-		if ((pi2c->sr & sta_bit) == (truefalse ? sta_bit : 0))
-			return (OK);
-	}
-
-	I2CCDBG (L2, ("--- sr %x stabit %x truefalse %d\n",
-		      pi2c->sr, sta_bit, truefalse, 0, 0, 0));
-
-	if (i == I2C_POLL_COUNT) {
-		switch (sta_bit) {
-		case I2C_STA_CF:
-			status = 0;
-			break;
-		case I2C_STA_AAS:
-			status = 2;
-			break;
-		case I2C_STA_BB:
-			status = 4;
-			break;
-		case I2C_STA_AL:
-			status = 6;
-			break;
-		case I2C_STA_SRW:
-			status = 8;
-			break;
-		case I2C_STA_IF:
-			status = 10;
-			break;
-		case I2C_STA_RXAK:
-			status = 12;
-			break;
-		default:
-			status = 14;
-			break;
-		}
-
-		if (!truefalse)
-			status++;
-
-		I2CCDBG (NO, ("--- status %d\n", status, 0, 0, 0, 0, 0));
-		I2CCDBG (NO, (I2CERR[status], 0, 0, 0, 0, 0, 0));
-	}
-
-	return (ERROR);
-}
-
-/******************************************************************************
- *
- * I2C Enable - Enable the I2C Controller
- *
- */
-STATUS i2c_enable (SI2C * pi2c, PI2CSET pi2cSet)
-{
-	int fdr = pi2cSet->bit_rate;
-	UINT8 adr = pi2cSet->i2c_adr;
-
-	I2CCDBG (L2, ("i2c_enable fdr %d adr %x\n", fdr, adr, 0, 0, 0, 0));
-
-	i2c_clear (pi2c);	/* Clear FDR, ADR, SR and CR reg */
-
-	SetI2cFDR (pi2c, fdr);	/* Frequency			*/
-	pi2c->adr = adr;
-
-	pi2c->cr = I2C_CTL_EN;	/* Set Enable			*/
-
-	/*
-	   The I2C bus should be in Idle state. If the bus is busy,
-	   clear the STA bit in control register
-	 */
-	if (chk_status (pi2c, I2C_STA_BB, 0) != OK) {
-		if ((pi2c->cr & I2C_CTL_STA) == I2C_CTL_STA)
-			pi2c->cr &= ~I2C_CTL_STA;
-
-		/* Check again if it is still busy, return error if found */
-		if (chk_status (pi2c, I2C_STA_BB, 1) == OK)
-			return ERROR;
-	}
-
-	return (OK);
-}
-
-/******************************************************************************
- *
- * I2C Disable - Disable the I2C Controller
- *
- */
-STATUS i2c_disable (PSI2C pi2c)
-{
-	i2c_clear (pi2c);
-
-	pi2c->cr &= I2C_CTL_EN; /* Disable I2c			*/
-
-	if ((pi2c->cr & I2C_CTL_STA) == I2C_CTL_STA)
-		pi2c->cr &= ~I2C_CTL_STA;
-
-	if (chk_status (pi2c, I2C_STA_BB, 0) != OK)
-		return ERROR;
-
-	return (OK);
-}
-
-/******************************************************************************
- *
- * I2C Clear - Clear the I2C Controller
- *
- */
-STATUS i2c_clear (PSI2C pi2c)
-{
-	pi2c->adr = 0;
-	pi2c->fdr = 0;
-	pi2c->cr = 0;
-	pi2c->sr = 0;
-
-	return (OK);
-}
-
-
-STATUS i2c_start (PSI2C pi2c, PI2CSET pi2cSet)
-{
-#ifdef TWOBYTES
-	UINT16 ByteOffset = pi2cSet->str_adr;
-#else
-	UINT8 ByteOffset = pi2cSet->str_adr;
-#endif
-#if 1
-	UINT8 tmp = 0;
-#endif
-	UINT8 Addr = pi2cSet->slv_adr;
-
-	pi2c->cr |= I2C_CTL_STA;	/* Generate start signal	*/
-
-	if (chk_status (pi2c, I2C_STA_BB, 1) != OK)
-		return ERROR;
-
-	/* Write slave address */
-	if (i2c_writebyte (pi2c, &Addr) != OK) {
-		i2c_stop (pi2c);	/* Disable I2c			*/
-		return ERROR;
-	}
-#ifdef TWOBYTES
-#   if 0
-	/* Issue the offset to start */
-	if (i2c_write2byte (pi2c, &ByteOffset) != OK) {
-		i2c_stop (pi2c);	/* Disable I2c			*/
-		return ERROR;
-	}
-#endif
-	tmp = (ByteOffset >> 8) & 0xff;
-	if (i2c_writebyte (pi2c, &tmp) != OK) {
-		i2c_stop (pi2c);	/* Disable I2c			*/
-		return ERROR;
-	}
-	tmp = ByteOffset & 0xff;
-	if (i2c_writebyte (pi2c, &tmp) != OK) {
-		i2c_stop (pi2c);	/* Disable I2c			*/
-		return ERROR;
-	}
-#else
-	if (i2c_writebyte (pi2c, &ByteOffset) != OK) {
-		i2c_stop (pi2c);	/* Disable I2c			*/
-		return ERROR;
-	}
-#endif
-
-	return (OK);
-}
-
-STATUS i2c_stop (PSI2C pi2c)
-{
-	pi2c->cr &= ~I2C_CTL_STA;	/* Generate stop signal		*/
-	if (chk_status (pi2c, I2C_STA_BB, 0) != OK)
-		return ERROR;
-
-	return (OK);
-}
-
-/******************************************************************************
- *
- * Read Len bytes to the location pointed to by *Data from the device
- * with address Addr.
- */
-int i2c_readblock (SI2C * pi2c, PI2CSET pi2cSet, UINT8 * Data)
-{
-	int i = 0;
-	UINT8 Tmp;
-
-/*    UINT8 ByteOffset = pi2cSet->str_adr; not used? */
-	UINT8 Addr = pi2cSet->slv_adr;
-	int Length = pi2cSet->xfer_size;
-
-	I2CCDBG (L1, ("i2c_readblock addr %x data 0x%08x len %d offset %d\n",
-		      Addr, (int) Data, Length, ByteOffset, 0, 0));
-
-	if (pi2c->sr & I2C_STA_AL) {	/* Check if Arbitration lost	*/
-		I2CCDBG (FN, ("Arbitration lost\n", 0, 0, 0, 0, 0, 0));
-		pi2c->sr &= ~I2C_STA_AL;	/* Clear Arbitration status bit */
-		return ERROR;
-	}
-
-	pi2c->cr |= I2C_CTL_TX; /* Enable the I2c for TX, Ack	*/
-
-	if (i2c_start (pi2c, pi2cSet) == ERROR)
-		return ERROR;
-
-	pi2c->cr |= I2C_CTL_RSTA;	/* Repeat Start */
-
-	Tmp = Addr | 1;
-
-	if (i2c_writebyte (pi2c, &Tmp) != OK) {
-		i2c_stop (pi2c);	/* Disable I2c	*/
-		return ERROR;
-	}
-
-	if (((pi2c->sr & 0x07) == 0x07) || (pi2c->sr & 0x01))
-		return ERROR;
-
-	pi2c->cr &= ~I2C_CTL_TX;	/* Set receive mode	*/
-
-	if (((pi2c->sr & 0x07) == 0x07) || (pi2c->sr & 0x01))
-		return ERROR;
-
-	/* Dummy Read */
-	if (i2c_readbyte (pi2c, &Tmp, &i) != OK) {
-		i2c_stop (pi2c);	/* Disable I2c	*/
-		return ERROR;
-	}
-
-	i = 0;
-	while (Length) {
-		if (Length == 2)
-			pi2c->cr |= I2C_CTL_TXAK;
-
-		if (Length == 1)
-			pi2c->cr &= ~I2C_CTL_STA;
-
-		if (i2c_readbyte (pi2c, Data, &Length) != OK) {
-			return i2c_stop (pi2c);
-		}
-		i++;
-		Length--;
-		Data++;
-	}
-
-	if (i2c_stop (pi2c) == ERROR)
-		return ERROR;
-
-	return i;
-}
-
-STATUS i2c_writeblock (SI2C * pi2c, PI2CSET pi2cSet, UINT8 * Data)
-{
-	int Length = pi2cSet->xfer_size;
-
-#ifdef TWOBYTES
-	UINT16 ByteOffset = pi2cSet->str_adr;
-#else
-	UINT8 ByteOffset = pi2cSet->str_adr;
-#endif
-	int j, k;
-
-	I2CCDBG (L2, ("i2c_writeblock\n", 0, 0, 0, 0, 0, 0));
-
-	if (pi2c->sr & I2C_STA_AL) {
-		/* Check if arbitration lost */
-		I2CCDBG (L2, ("Arbitration lost\n", 0, 0, 0, 0, 0, 0));
-		pi2c->sr &= ~I2C_STA_AL;	/* Clear the condition	*/
-		return ERROR;
-	}
-
-	pi2c->cr |= I2C_CTL_TX; /* Enable the I2c for TX, Ack	*/
-
-	/* Do the not even offset first */
-	if ((ByteOffset % 8) != 0) {
-		int remain;
-
-		if (Length > 8) {
-			remain = 8 - (ByteOffset % 8);
-			Length -= remain;
-
-			pi2cSet->str_adr = ByteOffset;
-
-			if (i2c_start (pi2c, pi2cSet) == ERROR)
-				return ERROR;
-
-			for (j = ByteOffset; j < remain; j++) {
-				if (i2c_writebyte (pi2c, Data++) != OK)
-					return ERROR;
-			}
-
-			if (i2c_stop (pi2c) == ERROR)
-				return ERROR;
-
-			sysMsDelay (32);
-
-			/* Update the new ByteOffset */
-			ByteOffset += remain;
-		}
-	}
-
-	for (j = ByteOffset, k = 0; j < (Length + ByteOffset); j++) {
-		if ((j % 8) == 0) {
-			pi2cSet->str_adr = j;
-			if (i2c_start (pi2c, pi2cSet) == ERROR)
-				return ERROR;
-		}
-
-		k++;
-
-		if (i2c_writebyte (pi2c, Data++) != OK)
-			return ERROR;
-
-		if ((j == (Length - 1)) || ((k % 8) == 0)) {
-			if (i2c_stop (pi2c) == ERROR)
-				return ERROR;
-
-			sysMsDelay (50);
-		}
-
-	}
-
-	return k;
-}
-
-STATUS i2c_readbyte (SI2C * pi2c, UINT8 * readb, int *index)
-{
-	pi2c->sr &= ~I2C_STA_IF;	/* Clear Interrupt Bit	*/
-	*readb = pi2c->dr;		/* Read a byte		*/
-
-	/*
-	   Set I2C_CTRL_TXAK will cause Transfer pending and
-	   set I2C_CTRL_STA will cause Interrupt pending
-	 */
-	if (*index != 2) {
-		if (chk_status (pi2c, I2C_STA_CF, 1) != OK)	/* Transfer not complete?	*/
-			return ERROR;
-	}
-
-	if (*index != 1) {
-		if (chk_status (pi2c, I2C_STA_IF, 1) != OK)
-			return ERROR;
-	}
-
-	return (OK);
-}
-
-
-STATUS i2c_writebyte (SI2C * pi2c, UINT8 * writeb)
-{
-	pi2c->sr &= ~I2C_STA_IF;	/* Clear Interrupt	*/
-	pi2c->dr = *writeb;		/* Write a byte		*/
-
-	if (chk_status (pi2c, I2C_STA_CF, 1) != OK)	/* Transfer not complete?	*/
-		return ERROR;
-
-	if (chk_status (pi2c, I2C_STA_IF, 1) != OK)
-		return ERROR;
-
-	return OK;
-}
-
-STATUS i2c_write2byte (SI2C * pi2c, UINT16 * writeb)
-{
-	UINT8 data;
-
-	data = (UINT8) ((*writeb >> 8) & 0xff);
-	if (i2c_writebyte (pi2c, &data) != OK)
-		return ERROR;
-	data = (UINT8) (*writeb & 0xff);
-	if (i2c_writebyte (pi2c, &data) != OK)
-		return ERROR;
-	return OK;
-}
-
-/* FDR table base on 33MHz - more detail please refer to Odini2c_dividers.xls
-FDR FDR scl sda scl2tap2
-510 432 tap tap tap tap scl_per	    sda_hold	I2C Freq    0	1   2	3   4	5
-000 000 9   3	4   1	28 Clocks   9 Clocks	1190 KHz    0	0   0	0   0	0
-000 001 9   3	4   2	44 Clocks   11 Clocks	758 KHz	    0	0   1	0   0	0
-000 010 9   3	6   4	80 Clocks   17 Clocks	417 KHz	    0	0   0	1   0	0
-000 011 9   3	6   8	144 Clocks  25 Clocks	231 KHz	    0	0   1	1   0	0
-000 100 9   3	14  16	288 Clocks  49 Clocks	116 KHz	    0	0   0	0   1	0
-000 101 9   3	30  32	576 Clocks  97 Clocks	58 KHz	    0	0   1	0   1	0
-000 110 9   3	62  64	1152 Clocks 193 Clocks	29 KHz	    0	0   0	1   1	0
-000 111 9   3	126 128 2304 Clocks 385 Clocks	14 KHz	    0	0   1	1   1	0
-001 000 10  3	4   1	30 Clocks   9 Clocks	1111 KHz1   0	0   0	0   0
-001 001 10  3	4   2	48 Clocks   11 Clocks	694 KHz	    1	0   1	0   0	0
-001 010 10  3	6   4	88 Clocks   17 Clocks	379 KHz	    1	0   0	1   0	0
-001 011 10  3	6   8	160 Clocks  25 Clocks	208 KHz	    1	0   1	1   0	0
-001 100 10  3	14  16	320 Clocks  49 Clocks	104 KHz	    1	0   0	0   1	0
-001 101 10  3	30  32	640 Clocks  97 Clocks	52 KHz	    1	0   1	0   1	0
-001 110 10  3	62  64	1280 Clocks 193 Clocks	26 KHz	    1	0   0	1   1	0
-001 111 10  3	126 128 2560 Clocks 385 Clocks	13 KHz	    1	0   1	1   1	0
-010 000 12  4	4   1	34 Clocks   10 Clocks	980 KHz	    0	1   0	0   0	0
-010 001 12  4	4   2	56 Clocks   13 Clocks	595 KHz	    0	1   1	0   0	0
-010 010 12  4	6   4	104 Clocks  21 Clocks	321 KHz	    0	1   0	1   0	0
-010 011 12  4	6   8	192 Clocks  33 Clocks	174 KHz	    0	1   1	1   0	0
-010 100 12  4	14  16	384 Clocks  65 Clocks	87 KHz	    0	1   0	0   1	0
-010 101 12  4	30  32	768 Clocks  129 Clocks	43 KHz	    0	1   1	0   1	0
-010 110 12  4	62  64	1536 Clocks 257 Clocks	22 KHz	    0	1   0	1   1	0
-010 111 12  4	126 128 3072 Clocks 513 Clocks	11 KHz	    0	1   1	1   1	0
-011 000 15  4	4   1	40 Clocks   10 Clocks	833 KHz	    1	1   0	0   0	0
-011 001 15  4	4   2	68 Clocks   13 Clocks	490 KHz	    1	1   1	0   0	0
-011 010 15  4	6   4	128 Clocks  21 Clocks	260 KHz	    1	1   0	1   0	0
-011 011 15  4	6   8	240 Clocks  33 Clocks	139 KHz	    1	1   1	1   0	0
-011 100 15  4	14  16	480 Clocks  65 Clocks	69 KHz	    1	1   0	0   1	0
-011 101 15  4	30  32	960 Clocks  129 Clocks	35 KHz	    1	1   1	0   1	0
-011 110 15  4	62  64	1920 Clocks 257 Clocks	17 KHz	    1	1   0	1   1	0
-011 111 15  4	126 128 3840 Clocks 513 Clocks	9 KHz	    1	1   1	1   1	0
-100 000 5   1	4   1	20 Clocks   7 Clocks	1667 KHz    0	0   0	0   0	1
-100 001 5   1	4   2	28 Clocks   7 Clocks	1190 KHz    0	0   1	0   0	1
-100 010 5   1	6   4	48 Clocks   9 Clocks	694 KHz	    0	0   0	1   0	1
-100 011 5   1	6   8	80 Clocks   9 Clocks	417 KHz	    0	0   1	1   0	1
-100 100 5   1	14  16	160 Clocks  17 Clocks	208 KHz	    0	0   0	0   1	1
-100 101 5   1	30  32	320 Clocks  33 Clocks	104 KHz	    0	0   1	0   1	1
-100 110 5   1	62  64	640 Clocks  65 Clocks	52 KHz	    0	0   0	1   1	1
-100 111 5   1	126 128 1280 Clocks 129 Clocks	26 KHz	    0	0   1	1   1	1
-101 000 6   1	4   1	22 Clocks   7 Clocks	1515 KHz    1	0   0	0   0	1
-101 001 6   1	4   2	32 Clocks   7 Clocks	1042 KHz    1	0   1	0   0	1
-101 010 6   1	6   4	56 Clocks   9 Clocks	595 KHz	    1	0   0	1   0	1
-101 011 6   1	6   8	96 Clocks   9 Clocks	347 KHz	    1	0   1	1   0	1
-101 100 6   1	14  16	192 Clocks  17 Clocks	174 KHz	    1	0   0	0   1	1
-101 101 6   1	30  32	384 Clocks  33 Clocks	87 KHz	    1	0   1	0   1	1
-101 110 6   1	62  64	768 Clocks  65 Clocks	43 KHz	    1	0   0	1   1	1
-101 111 6   1	126 128 1536 Clocks 129 Clocks	22 KHz	    1	0   1	1   1	1
-110 000 7   2	4   1	24 Clocks   8 Clocks	1389 KHz    0	1   0	0   0	1
-110 001 7   2	4   2	36 Clocks   9 Clocks	926 KHz	    0	1   1	0   0	1
-110 010 7   2	6   4	64 Clocks   13 Clocks	521 KHz	    0	1   0	1   0	1
-110 011 7   2	6   8	112 Clocks  17 Clocks	298 KHz	    0	1   1	1   0	1
-110 100 7   2	14  16	224 Clocks  33 Clocks	149 KHz	    0	1   0	0   1	1
-110 101 7   2	30  32	448 Clocks  65 Clocks	74 KHz	    0	1   1	0   1	1
-110 110 7   2	62  64	896 Clocks  129 Clocks	37 KHz	    0	1   0	1   1	1
-110 111 7   2	126 128 1792 Clocks 257 Clocks	19 KHz	    0	1   1	1   1	1
-111 000 8   2	4   1	26 Clocks   8 Clocks	1282 KHz    1	1   0	0   0	1
-111 001 8   2	4   2	40 Clocks   9 Clocks	833 KHz	    1	1   1	0   0	1
-111 010 8   2	6   4	72 Clocks   13 Clocks	463 KHz	    1	1   0	1   0	1
-111 011 8   2	6   8	128 Clocks  17 Clocks	260 KHz	    1	1   1	1   0	1
-111 100 8   2	14  16	256 Clocks  33 Clocks	130 KHz	    1	1   0	0   1	1
-111 101 8   2	30  32	512 Clocks  65 Clocks	65 KHz	    1	1   1	0   1	1
-111 110 8   2	62  64	1024 Clocks 129 Clocks	33 KHz	    1	1   0	1   1	1
-111 111 8   2	126 128 2048 Clocks 257 Clocks	16 KHz	    1	1   1	1   1	1
-*/
-STATUS SetI2cFDR (PSI2C pi2cRegs, int bitrate)
-{
-/* Constants */
-	const UINT8 div_hold[8][3] = { {9, 3}, {10, 3},
-	{12, 4}, {15, 4},
-	{5, 1}, {6, 1},
-	{7, 2}, {8, 2}
-	};
-
-	const UINT8 scl_tap[8][2] = { {4, 1}, {4, 2},
-	{6, 4}, {6, 8},
-	{14, 16}, {30, 32},
-	{62, 64}, {126, 128}
-	};
-
-	UINT8 mfdr_bits;
-
-	int i = 0;
-	int j = 0;
-
-	int Diff, min;
-	int WhichFreq, iRec, jRec;
-	int SCL_Period;
-	int SCL_Hold;
-	int I2C_Freq;
-
-	I2CCDBG (L2, ("Entering getBitRate: bitrate %d pi2cRegs 0x%08x\n",
-		      bitrate, (int) pi2cRegs, 0, 0, 0, 0));
-
-	if (bitrate < 0) {
-		I2CCDBG (NO, ("Invalid bitrate\n", 0, 0, 0, 0, 0, 0));
-		return ERROR;
-	}
-
-	/* Initialize */
-	mfdr_bits = 0;
-	min = 0x7fffffff;
-	WhichFreq = iRec = jRec = 0;
-
-	for (i = 0; i < 8; i++) {
-		for (j = 0; j < 8; j++) {
-			/* SCL Period = 2 * (scl2tap + [(SCL_Tap - 1) * tap2tap] + 2)
-			 * SCL Hold   = scl2tap + ((SDA_Tap - 1) * tap2tap) + 3
-			 * Bit Rate (I2C Freq) = System Freq / SCL Period
-			 */
-			SCL_Period =
-				2 * (scl_tap[i][0] +
-				     ((div_hold[j][0] - 1) * scl_tap[i][1]) +
-				     2);
-
-			/* Now get the I2C Freq */
-			I2C_Freq = DEV_CLOCK_FREQ / SCL_Period;
-
-			/* Take equal or slower */
-			if (I2C_Freq > bitrate)
-				continue;
-
-			/* Take the differences */
-			Diff = I2C_Freq - bitrate;
-
-			Diff = ABS (Diff);
-
-			/* Find the closer value */
-			if (Diff < min) {
-				min = Diff;
-				WhichFreq = I2C_Freq;
-				iRec = i;
-				jRec = j;
-			}
-
-			I2CCDBG (L2,
-				 ("--- (%d,%d) I2C_Freq %d minDiff %d min %d\n",
-				  i, j, I2C_Freq, Diff, min, 0));
-		}
-	}
-
-	SCL_Period =
-		2 * (scl_tap[iRec][0] +
-		     ((div_hold[jRec][0] - 1) * scl_tap[iRec][1]) + 2);
-
-	I2CCDBG (L2, ("\nmin %d WhichFreq %d iRec %d jRec %d\n",
-		      min, WhichFreq, iRec, jRec, 0, 0));
-	I2CCDBG (L2, ("--- scl2tap %d SCL_Tap %d tap2tap %d\n",
-		      scl_tap[iRec][0], div_hold[jRec][0], scl_tap[iRec][1],
-		      0, 0, 0));
-
-	/* This may no require */
-	SCL_Hold =
-		scl_tap[iRec][0] +
-		((div_hold[jRec][1] - 1) * scl_tap[iRec][1]) + 3;
-	I2CCDBG (L2,
-		 ("--- SCL_Period %d SCL_Hold %d\n", SCL_Period, SCL_Hold, 0,
-		  0, 0, 0));
-
-	I2CCDBG (L2, ("--- mfdr_bits %x\n", mfdr_bits, 0, 0, 0, 0, 0));
-
-	/* FDR 4,3,2 */
-	if ((iRec & 1) == 1)
-		mfdr_bits |= 0x04;	/* FDR 2 */
-	if ((iRec & 2) == 2)
-		mfdr_bits |= 0x08;	/* FDR 3 */
-	if ((iRec & 4) == 4)
-		mfdr_bits |= 0x10;	/* FDR 4 */
-	/* FDR 5,1,0 */
-	if ((jRec & 1) == 1)
-		mfdr_bits |= 0x01;	/* FDR 0 */
-	if ((jRec & 2) == 2)
-		mfdr_bits |= 0x02;	/* FDR 1 */
-	if ((jRec & 4) == 4)
-		mfdr_bits |= 0x20;	/* FDR 5 */
-
-	I2CCDBG (L2, ("--- mfdr_bits %x\n", mfdr_bits, 0, 0, 0, 0, 0));
-
-	pi2cRegs->fdr = mfdr_bits;
-
-	return OK;
-}
diff --git a/arch/powerpc/cpu/mpc8220/i2cCore.h b/arch/powerpc/cpu/mpc8220/i2cCore.h
deleted file mode 100644
index 72783fd..0000000
--- a/arch/powerpc/cpu/mpc8220/i2cCore.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * i2cCore.h
- *
- * Prototypes, etc. for the Motorola MPC8220
- * embedded cpu chips
- *
- * 2004 (c) Freescale, Inc.
- * Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __INCi2ccoreh
-#define __INCi2ccoreh
-#ifndef __ASSEMBLY__
-/* device types */
-#define I2C_DEVICE_TYPE_EEPROM 0
-#define I2C_EEPROM_ADRS 0xa0
-#define I2C_CTRL_ADRS   I2C_EEPROM_ADRS
-#define EEPROM_ADDR0    0xA2	/* on Dimm SPD eeprom */
-#define EEPROM_ADDR1    0xA4	/* on Board SPD eeprom */
-#define EEPROM_ADDR2    0xD2	/* non-standard eeprom - clock generator */
-/* Control Register */
-#define I2C_CTL_EN      0x80	/* I2C Enable                   */
-#define I2C_CTL_IEN     0x40	/* I2C Interrupt Enable         */
-#define I2C_CTL_STA     0x20	/* Master/Slave Mode select     */
-#define I2C_CTL_TX      0x10	/* Transmit/Receive Mode Select */
-#define I2C_CTL_TXAK    0x08	/* Transmit Acknowledge Enable  */
-#define I2C_CTL_RSTA    0x04	/* Repeat Start                 */
-/* Status Register */
-#define I2C_STA_CF      0x80	/* Data Transfer       */
-#define I2C_STA_AAS     0x40	/* Adressed As Slave   */
-#define I2C_STA_BB      0x20	/* Bus Busy            */
-#define I2C_STA_AL      0x10	/* Arbitration Lost    */
-#define I2C_STA_SRW     0x04	/* Slave Read/Write    */
-#define I2C_STA_IF      0x02	/* I2C Interrupt       */
-#define I2C_STA_RXAK    0x01	/* Receive Acknowledge */
-/* Interrupt Contol Register */
-#define I2C_INT_BNBE2   0x80	/* Bus Not Busy Enable 2 */
-#define I2C_INT_TE2     0x40	/* Transmit Enable 2     */
-#define I2C_INT_RE2     0x20	/* Receive Enable 2      */
-#define I2C_INT_IE2     0x10	/* Interrupt Enable 2    */
-#define I2C_INT_BNBE1   0x08	/* Bus Not Busy Enable 1 */
-#define I2C_INT_TE1     0x04	/* Transmit Enable 1     */
-#define I2C_INT_RE1     0x02	/* Receive Enable 1      */
-#define I2C_INT_IE1     0x01	/* Interrupt Enable 1    */
-#define I2C_POLL_COUNT 0x100000
-#define I2C_ENABLE      0x00000001
-#define I2C_DISABLE     0x00000002
-#define I2C_START       0x00000004
-#define I2C_REPSTART    0x00000008
-#define I2C_STOP        0x00000010
-#define I2C_BITRATE     0x00000020
-#define I2C_SLAVEADR    0x00000040
-#define I2C_STARTADR    0x00000080
-#undef TWOBYTES
-typedef struct i2c_settings {
-	/* Device settings */
-	int bit_rate;		/* Device bit rate */
-	u8 i2c_adr;		/* I2C address */
-	u8 slv_adr;		/* Slave address */
-#ifdef TWOBYTES
-	u16 str_adr;		/* Start address */
-#else
-	u8 str_adr;		/* Start address */
-#endif
-	int xfer_size;		/* Transfer Size */
-
-	int bI2c_en;		/* Enable or Disable */
-	int cmdFlag;		/* I2c Command Flags */
-} i2cset_t;
-
-/*
-int check_status(PSI2C pi2c, u8 sta_bit, u8 truefalse);
-int i2c_enable(PSI2C pi2c, PI2CSET pi2cSet);
-int i2c_disable(PSI2C pi2c);
-int i2c_start(PSI2C pi2c, PI2CSET pi2cSet);
-int i2c_stop(PSI2C pi2c);
-int i2c_clear(PSI2C pi2c);
-int i2c_readblock (PSI2C pi2c, PI2CSET pi2cSet, u8 *Data);
-int i2c_writeblock (PSI2C pi2c, PI2CSET pi2cSet, u8 *Data);
-int i2c_readbyte(PSI2C pi2c, u8 *readb, int *index);
-int i2c_writebyte(PSI2C pi2c, u8 *writeb);
-int SetI2cFDR( PSI2C pi2cRegs, int bitrate );
-*/
-#endif /* __ASSEMBLY__ */
-
-#endif /* __INCi2ccoreh */
diff --git a/arch/powerpc/cpu/mpc8220/interrupts.c b/arch/powerpc/cpu/mpc8220/interrupts.c
deleted file mode 100644
index 9544d85..0000000
--- a/arch/powerpc/cpu/mpc8220/interrupts.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * (C) Copyright -2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * interrupts.c - just enough support for the decrementer/timer
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <command.h>
-
-int interrupt_init_cpu (ulong * decrementer_count)
-{
-	*decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
-
-	return (0);
-}
-
-/****************************************************************************/
-
-/*
- * Handle external interrupts
- */
-void external_interrupt (struct pt_regs *regs)
-{
-	puts ("external_interrupt (oops!)\n");
-}
-
-void timer_interrupt_cpu (struct pt_regs *regs)
-{
-	/* nothing to do here */
-	return;
-}
-
-/****************************************************************************/
-
-/*
- * Install and free a interrupt handler.
- */
-
-void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
-{
-
-}
-
-void irq_free_handler (int vec)
-{
-
-}
-
-/****************************************************************************/
-
-void
-do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
-{
-	puts ("IRQ related functions are unimplemented currently.\n");
-}
diff --git a/arch/powerpc/cpu/mpc8220/io.S b/arch/powerpc/cpu/mpc8220/io.S
deleted file mode 100644
index 5ecdf55..0000000
--- a/arch/powerpc/cpu/mpc8220/io.S
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
- *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- *  Copyright (C) 2001	Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- *			Andreas Heppel <aheppel@sysgo.de>
- *  Copyright (C) 2003	Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <ppc_asm.tmpl>
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:	  in8 */
-/*  Description:  Input 8 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl	in8
-in8:
-	lbz	r3,0(r3)
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:	  in16 */
-/*  Description:  Input 16 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl	in16
-in16:
-	lhz	r3,0(r3)
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:	  in16r */
-/*  Description:  Input 16 bits and byte reverse */
-/* ------------------------------------------------------------------------------- */
-	.globl	in16r
-in16r:
-	lhbrx	r3,0,r3
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:	  in32 */
-/*  Description:  Input 32 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl	in32
-in32:
-	lwz	3,0(3)
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:	  in32r */
-/*  Description:  Input 32 bits and byte reverse */
-/* ------------------------------------------------------------------------------- */
-	.globl	in32r
-in32r:
-	lwbrx	r3,0,r3
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:	  out8 */
-/*  Description:  Output 8 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl	out8
-out8:
-	stb	r4,0(r3)
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:	  out16 */
-/*  Description:  Output 16 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl	out16
-out16:
-	sth	r4,0(r3)
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:	  out16r */
-/*  Description:  Byte reverse and output 16 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl	out16r
-out16r:
-	sthbrx	r4,0,r3
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:	  out32 */
-/*  Description:  Output 32 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl	out32
-out32:
-	stw	r4,0(r3)
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:	  out32r */
-/*  Description:  Byte reverse and output 32 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl	out32r
-out32r:
-	stwbrx	r4,0,r3
-	sync
-	blr
diff --git a/arch/powerpc/cpu/mpc8220/loadtask.c b/arch/powerpc/cpu/mpc8220/loadtask.c
deleted file mode 100644
index 6d8b627..0000000
--- a/arch/powerpc/cpu/mpc8220/loadtask.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on code
- * (C) Copyright Motorola, Inc., 2000
- */
-
-#include <common.h>
-#include <mpc8220.h>
-
-/* Multichannel DMA microcode */
-extern int taskTable;
-
-void loadtask (int basetask, int tasks)
-{
-	int *sram = (int *) (MMAP_SRAM + 512);
-	int *task_org = &taskTable;
-	unsigned int start, offset, end;
-	int i;
-
-#ifdef DEBUG
-	printf ("basetask = %d, tasks = %d\n", basetask, tasks);
-	printf ("task_org = 0x%08x\n", (unsigned int) task_org);
-#endif
-
-	/* setup TaskBAR register */
-	*(vu_long *) MMAP_DMA = (MMAP_SRAM + 512);
-
-	/* relocate task table entries */
-	offset = (unsigned int) sram;
-	for (i = basetask; i < basetask + tasks; i++) {
-		sram[i * 8 + 0] = task_org[i * 8 + 0] + offset;
-		sram[i * 8 + 1] = task_org[i * 8 + 1] + offset;
-		sram[i * 8 + 2] = task_org[i * 8 + 2] + offset;
-		sram[i * 8 + 3] = task_org[i * 8 + 3] + offset;
-		sram[i * 8 + 4] = task_org[i * 8 + 4];
-		sram[i * 8 + 5] = task_org[i * 8 + 5];
-		sram[i * 8 + 6] = task_org[i * 8 + 6] + offset;
-		sram[i * 8 + 7] = task_org[i * 8 + 7];
-	}
-
-	/* relocate task descriptors */
-	start = (sram[basetask * 8] - (unsigned int) sram);
-	end = (sram[(basetask + tasks - 1) * 8 + 1] - (unsigned int) sram);
-
-#ifdef DEBUG
-	printf ("TDT start = 0x%08x, end = 0x%08x\n", start, end);
-#endif
-
-	start /= 4;
-	end /= 4;
-	for (i = start; i <= end; i++) {
-		sram[i] = task_org[i];
-	}
-
-	/* relocate variables */
-	start = (sram[basetask * 8 + 2] - (unsigned int) sram);
-	end = (sram[(basetask + tasks - 1) * 8 + 2] + 256 -
-	       (unsigned int) sram);
-	start /= 4;
-	end /= 4;
-	for (i = start; i < end; i++) {
-		sram[i] = task_org[i];
-	}
-
-	/* relocate function decriptors */
-	start = ((sram[basetask * 8 + 3] & 0xfffffffc) - (unsigned int) sram);
-	end = ((sram[(basetask + tasks - 1) * 8 + 3] & 0xfffffffc) + 256 -
-	       (unsigned int) sram);
-	start /= 4;
-	end /= 4;
-	for (i = start; i < end; i++) {
-		sram[i] = task_org[i];
-	}
-
-	asm volatile ("sync");
-}
diff --git a/arch/powerpc/cpu/mpc8220/pci.c b/arch/powerpc/cpu/mpc8220/pci.c
deleted file mode 100644
index 7ef43b7..0000000
--- a/arch/powerpc/cpu/mpc8220/pci.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright (C) 2003 Motorola Inc.
- * Xianghua Xiao (x.xiao@motorola.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * PCI Configuration space access support for MPC8220 PCI Bridge
- */
-#include <common.h>
-#include <mpc8220.h>
-#include <pci.h>
-#include <asm/io.h>
-
-#if defined(CONFIG_PCI)
-
-/* System RAM mapped over PCI */
-#define CONFIG_PCI_SYS_MEM_BUS	 CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	 CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_SIZE	 (1024 * 1024 * 1024)
-
-#define cfg_read(val, addr, type, op)		*val = op((type)(addr));
-#define cfg_write(val, addr, type, op)		op((type *)(addr), (val));
-
-#define PCI_OP(rw, size, type, op, mask)				\
-int mpc8220_pci_##rw##_config_##size(struct pci_controller *hose,	\
-	pci_dev_t dev, int offset, type val)				\
-{									\
-	u32 addr = 0;							\
-	u16 cfg_type = 0;						\
-	addr = ((offset & 0xfc) | cfg_type | (dev)  | 0x80000000);	\
-	out_be32(hose->cfg_addr, addr);					\
-	__asm__ __volatile__("sync");					\
-	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	\
-	out_be32(hose->cfg_addr, addr & 0x7fffffff);			\
-	__asm__ __volatile__("sync");					\
-	return 0;							\
-}
-
-PCI_OP(read, byte, u8 *, in_8, 3)
-PCI_OP(read, word, u16 *, in_le16, 2)
-PCI_OP(write, byte, u8, out_8, 3)
-PCI_OP(write, word, u16, out_le16, 2)
-PCI_OP(write, dword, u32, out_le32, 0)
-
-int mpc8220_pci_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
-	int offset, u32 *val)
-{
-	u32 addr;
-	u32 tmpv;
-	u32 mask = 2;	 /* word access */
-	/* Read lower 16 bits */
-	addr = ((offset & 0xfc) | (dev) | 0x80000000);
-	out_be32(hose->cfg_addr, addr);
-	__asm__ __volatile__("sync");
-	*val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
-	out_be32(hose->cfg_addr, addr & 0x7fffffff);
-	__asm__ __volatile__("sync");
-
-	/* Read upper 16 bits */
-	offset += 2;
-	addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
-	out_be32(hose->cfg_addr, addr);
-	__asm__ __volatile__("sync");
-	tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
-	out_be32(hose->cfg_addr, addr & 0x7fffffff);
-	__asm__ __volatile__("sync");
-
-	/* combine results into dword value */
-	*val = (tmpv << 16) | *val;
-
-	return 0;
-}
-
-void
-pci_mpc8220_init(struct pci_controller *hose)
-{
-	u32 win0, win1, win2;
-	volatile mpc8220_xcpci_t *xcpci =
-		(volatile mpc8220_xcpci_t *) MMAP_XCPCI;
-
-	volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG;
-
-	win0 = (u32) CONFIG_PCI_MEM_PHYS;
-	win1 = (u32) CONFIG_PCI_IO_PHYS;
-	win2 = (u32) CONFIG_PCI_CFG_PHYS;
-
-	/* Assert PCI reset */
-	out_be32 (&xcpci->glb_stat_ctl, PCI_GLB_STAT_CTRL_PR);
-
-	/* Disable prefetching but read-multiples will still prefetch */
-	out_be32 (&xcpci->target_ctrl, 0x00000000);
-
-	/* Initiator windows */
-	out_be32 (&xcpci->init_win0,  (win0 >> 16) | win0 | 0x003f0000);
-	out_be32 (&xcpci->init_win1, ((win1 >> 16) | win1 ));
-	out_be32 (&xcpci->init_win2, ((win2 >> 16) | win2 ));
-
-	out_be32 (&xcpci->init_win_cfg,
-		PCI_INIT_WIN_CFG_WIN0_CTRL_EN |
-		PCI_INIT_WIN_CFG_WIN1_CTRL_EN | PCI_INIT_WIN_CFG_WIN1_CTRL_IO |
-		PCI_INIT_WIN_CFG_WIN2_CTRL_EN | PCI_INIT_WIN_CFG_WIN2_CTRL_IO);
-
-	out_be32 (&xcpci->init_ctrl, 0x00000000);
-
-	/* Enable bus master and mem access */
-	out_be32 (&xcpci->stat_cmd_reg, PCI_STAT_CMD_B | PCI_STAT_CMD_M);
-
-	/* Cache line size and master latency */
-	out_be32 (&xcpci->bist_htyp_lat_cshl, (0xf8 << PCI_CFG1_LT_SHIFT));
-
-	out_be32 (&xcpci->base0, PCI_BASE_ADDR_REG0); /* 256MB - MBAR space */
-	out_be32 (&xcpci->base1, PCI_BASE_ADDR_REG1); /* 1GB - SDRAM space */
-
-	out_be32 (&xcpci->target_bar0,
-		PCI_TARGET_BASE_ADDR_REG0 | PCI_TARGET_BASE_ADDR_EN);
-	out_be32 (&xcpci->target_bar1,
-		PCI_TARGET_BASE_ADDR_REG1 | PCI_TARGET_BASE_ADDR_EN);
-
-	/* Deassert reset bit */
-	out_be32 (&xcpci->glb_stat_ctl, 0x00000000);
-
-	/* Enable PCI bus master support */
-	/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
-	       PCIREQ2, PCIGNT2 */
-	out_be32((volatile u32 *)&portcfg->pcfg3,
-		(in_be32((volatile u32 *)&portcfg->pcfg3) & 0xFC3FCE7F));
-	out_be32((volatile u32 *)&portcfg->pcfg3,
-		(in_be32((volatile u32 *)&portcfg->pcfg3) | 0x01400180));
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	pci_set_region(hose->regions + 0,
-		CONFIG_PCI_MEM_BUS,
-		CONFIG_PCI_MEM_PHYS,
-		CONFIG_PCI_MEM_SIZE,
-		PCI_REGION_MEM);
-
-	pci_set_region(hose->regions + 1,
-		CONFIG_PCI_IO_BUS,
-		CONFIG_PCI_IO_PHYS,
-		CONFIG_PCI_IO_SIZE,
-		PCI_REGION_IO);
-
-	pci_set_region(hose->regions + 2,
-		CONFIG_PCI_SYS_MEM_BUS,
-		CONFIG_PCI_SYS_MEM_PHYS,
-		CONFIG_PCI_SYS_MEM_SIZE,
-		PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	hose->region_count = 3;
-
-	hose->cfg_addr = &(xcpci->cfg_adr);
-	hose->cfg_data = (volatile unsigned char *)CONFIG_PCI_CFG_BUS;
-
-	pci_set_ops(hose,
-		mpc8220_pci_read_config_byte,
-		mpc8220_pci_read_config_word,
-		mpc8220_pci_read_config_dword,
-		mpc8220_pci_write_config_byte,
-		mpc8220_pci_write_config_word,
-		mpc8220_pci_write_config_dword);
-
-	/* Hose scan */
-	pci_register_hose(hose);
-	hose->last_busno = pci_hose_scan(hose);
-
-	out_be32 (&xcpci->base0, PCI_BASE_ADDR_REG0); /* 256MB - MBAR space */
-	out_be32 (&xcpci->base1, PCI_BASE_ADDR_REG1); /* 1GB - SDRAM space */
-}
-
-#endif /* CONFIG_PCI */
diff --git a/arch/powerpc/cpu/mpc8220/speed.c b/arch/powerpc/cpu/mpc8220/speed.c
deleted file mode 100644
index bb72e5c..0000000
--- a/arch/powerpc/cpu/mpc8220/speed.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale, Inc
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8220.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-typedef struct pllmultiplier {
-	u8 hid1;
-	int multi;
-	int vco_div;
-} pllcfg_t;
-
-/* ------------------------------------------------------------------------- */
-
-/*
- *
- */
-
-int get_clocks (void)
-{
-	pllcfg_t bus2core[] = {
-		{0x02, 2, 8},	/* 1 */
-		{0x01, 2, 4},
-		{0x0C, 3, 8},	/* 1.5 */
-		{0x00, 3, 4},
-		{0x18, 3, 2},
-		{0x05, 4, 4},	/* 2 */
-		{0x04, 4, 2},
-		{0x11, 5, 4},	/* 2.5 */
-		{0x06, 5, 2},
-		{0x10, 6, 4},	/* 3 */
-		{0x08, 6, 2},
-		{0x0E, 7, 2},	/* 3.5 */
-		{0x0A, 8, 2},	/* 4 */
-		{0x07, 9, 2},	/* 4.5 */
-		{0x0B, 10, 2},	/* 5 */
-		{0x09, 11, 2},	/* 5.5 */
-		{0x0D, 12, 2},	/* 6 */
-		{0x12, 13, 2},	/* 6.5 */
-		{0x14, 14, 2},	/* 7 */
-		{0x16, 15, 2},	/* 7.5 */
-		{0x1C, 16, 2}	/* 8 */
-	};
-	u32 hid1;
-	int i, size, pci2bus;
-
-#if !defined(CONFIG_SYS_MPC8220_CLKIN)
-#error clock measuring not implemented yet - define CONFIG_SYS_MPC8220_CLKIN
-#endif
-
-	gd->arch.inp_clk = CONFIG_SYS_MPC8220_CLKIN;
-
-	/* Read XLB to PCI(INP) clock multiplier */
-	pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) &
-		PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK)>>PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT;
-
-	/* XLB bus clock */
-	gd->bus_clk = CONFIG_SYS_MPC8220_CLKIN * pci2bus;
-
-	/* PCI clock is same as input clock */
-	gd->pci_clk = CONFIG_SYS_MPC8220_CLKIN;
-
-	/* FlexBus is temporary set as the same as input clock */
-	/* will do dynamic in the future */
-	gd->arch.flb_clk = CONFIG_SYS_MPC8220_CLKIN;
-
-	/* CPU Clock - Read HID1 */
-	asm volatile ("mfspr %0, 1009":"=r" (hid1):);
-
-	size = sizeof (bus2core) / sizeof (pllcfg_t);
-
-	hid1 >>= 27;
-
-	for (i = 0; i < size; i++)
-		if (hid1 == bus2core[i].hid1) {
-			gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1;
-			gd->arch.vco_clk =
-				CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER *
-				(gd->pci_clk * bus2core[i].vco_div) / 2;
-			break;
-		}
-
-	/* hardcoded 81MHz for now */
-	gd->arch.pev_clk = 81000000;
-
-	return (0);
-}
-
-int prt_mpc8220_clks (void)
-{
-	char buf1[32], buf2[32], buf3[32], buf4[32];
-
-	printf ("       Bus %s MHz, CPU %s MHz, PCI %s MHz, VCO %s MHz\n",
-		strmhz(buf1, gd->bus_clk),
-		strmhz(buf2, gd->cpu_clk),
-		strmhz(buf3, gd->pci_clk),
-		strmhz(buf4, gd->arch.vco_clk)
-	);
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/arch/powerpc/cpu/mpc8220/start.S b/arch/powerpc/cpu/mpc8220/start.S
deleted file mode 100644
index 6295631..0000000
--- a/arch/powerpc/cpu/mpc8220/start.S
+++ /dev/null
@@ -1,734 +0,0 @@
-/*
- *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
- *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- *  Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- *  U-Boot - Startup Code for MPC8220 CPUs
- */
-#include <asm-offsets.h>
-#include <config.h>
-#include <mpc8220.h>
-#include <version.h>
-
-#define _LINUX_CONFIG_H 1   /* avoid reading Linux autoconf.h file  */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <asm/u-boot.h>
-
-/* We don't want the  MMU yet.
-*/
-#undef	MSR_KERNEL
-/* Floating Point enable, Machine Check and Recoverable Interr. */
-#ifdef DEBUG
-#define MSR_KERNEL (MSR_FP|MSR_RI)
-#else
-#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
-#endif
-
-/*
- * Set up GOT: Global Offset Table
- *
- * Use r12 to access the GOT
- */
-	START_GOT
-	GOT_ENTRY(_GOT2_TABLE_)
-	GOT_ENTRY(_FIXUP_TABLE_)
-
-	GOT_ENTRY(_start)
-	GOT_ENTRY(_start_of_vectors)
-	GOT_ENTRY(_end_of_vectors)
-	GOT_ENTRY(transfer_to_handler)
-
-	GOT_ENTRY(__init_end)
-	GOT_ENTRY(__bss_end)
-	GOT_ENTRY(__bss_start)
-	END_GOT
-
-/*
- * Version string
- */
-	.data
-	.globl	version_string
-version_string:
-	.ascii U_BOOT_VERSION_STRING, "\0"
-
-/*
- * Exception vectors
- */
-	.text
-	. = EXC_OFF_SYS_RESET
-	.globl	_start
-_start:
-	mfmsr	r5		    /* save msr contents    */
-
-	/* replace default MBAR base address from 0x80000000
-	    to 0xf0000000 */
-
-#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
-	lis	r3, CONFIG_SYS_MBAR@h
-	ori	r3, r3, CONFIG_SYS_MBAR@l
-
-	/* MBAR is mirrored into the MBAR SPR */
-	mtspr	MBAR,r3
-	mtspr	SPRN_SPRG7W,r3
-	lis	r4, CONFIG_SYS_DEFAULT_MBAR@h
-	stw	r3, 0(r4)
-#endif /* CONFIG_SYS_DEFAULT_MBAR */
-
-	/* Initialise the MPC8220 processor core			*/
-	/*--------------------------------------------------------------*/
-
-	bl  init_8220_core
-
-	/* initialize some things that are hard to access from C	*/
-	/*--------------------------------------------------------------*/
-
-	/* set up stack in on-chip SRAM */
-	lis	r3, CONFIG_SYS_INIT_RAM_ADDR@h
-	ori	r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
-	ori	r1, r3, CONFIG_SYS_INIT_SP_OFFSET
-
-	li	r0, 0		/* Make room for stack frame header and */
-	stwu	r0, -4(r1)	/* clear final stack frame so that	*/
-	stwu	r0, -4(r1)	/* stack backtraces terminate cleanly	*/
-
-	/* let the C-code set up the rest				*/
-	/*								*/
-	/* Be careful to keep code relocatable !			*/
-	/*--------------------------------------------------------------*/
-
-	GET_GOT			/* initialize GOT access		*/
-
-	/* r3: IMMR */
-	bl	cpu_init_f	/* run low-level CPU init code (in Flash)*/
-
-	bl	board_init_f	/* run 1st part of board init code (in Flash)*/
-
-	/* NOTREACHED - board_init_f() does not return */
-
-/*
- * Vector Table
- */
-
-	.globl	_start_of_vectors
-_start_of_vectors:
-
-/* Machine check */
-	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
-
-/* Data Storage exception. */
-	STD_EXCEPTION(0x300, DataStorage, UnknownException)
-
-/* Instruction Storage exception. */
-	STD_EXCEPTION(0x400, InstStorage, UnknownException)
-
-/* External Interrupt exception. */
-	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
-
-/* Alignment exception. */
-	. = 0x600
-Alignment:
-	EXCEPTION_PROLOG(SRR0, SRR1)
-	mfspr	r4,DAR
-	stw	r4,_DAR(r21)
-	mfspr	r5,DSISR
-	stw	r5,_DSISR(r21)
-	addi	r3,r1,STACK_FRAME_OVERHEAD
-	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-
-/* Program check exception */
-	. = 0x700
-ProgramCheck:
-	EXCEPTION_PROLOG(SRR0, SRR1)
-	addi	r3,r1,STACK_FRAME_OVERHEAD
-	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-		MSR_KERNEL, COPY_EE)
-
-	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
-
-	/* I guess we could implement decrementer, and may have
-	 * to someday for timekeeping.
-	 */
-	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
-
-	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
-	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
-	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
-	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
-
-	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
-	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
-
-	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
-	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
-	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
-#ifdef DEBUG
-	. = 0x1300
-	/*
-	 * This exception occurs when the program counter matches the
-	 * Instruction Address Breakpoint Register (IABR).
-	 *
-	 * I want the cpu to halt if this occurs so I can hunt around
-	 * with the debugger and look at things.
-	 *
-	 * When DEBUG is defined, both machine check enable (in the MSR)
-	 * and checkstop reset enable (in the reset mode register) are
-	 * turned off and so a checkstop condition will result in the cpu
-	 * halting.
-	 *
-	 * I force the cpu into a checkstop condition by putting an illegal
-	 * instruction here (at least this is the theory).
-	 *
-	 * well - that didnt work, so just do an infinite loop!
-	 */
-1:	b	1b
-#else
-	STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
-#endif
-	STD_EXCEPTION(0x1400, SMI, UnknownException)
-
-	STD_EXCEPTION(0x1500, Trap_15, UnknownException)
-	STD_EXCEPTION(0x1600, Trap_16, UnknownException)
-	STD_EXCEPTION(0x1700, Trap_17, UnknownException)
-	STD_EXCEPTION(0x1800, Trap_18, UnknownException)
-	STD_EXCEPTION(0x1900, Trap_19, UnknownException)
-	STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
-	STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
-	STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
-	STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
-	STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
-	STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
-	STD_EXCEPTION(0x2000, Trap_20, UnknownException)
-	STD_EXCEPTION(0x2100, Trap_21, UnknownException)
-	STD_EXCEPTION(0x2200, Trap_22, UnknownException)
-	STD_EXCEPTION(0x2300, Trap_23, UnknownException)
-	STD_EXCEPTION(0x2400, Trap_24, UnknownException)
-	STD_EXCEPTION(0x2500, Trap_25, UnknownException)
-	STD_EXCEPTION(0x2600, Trap_26, UnknownException)
-	STD_EXCEPTION(0x2700, Trap_27, UnknownException)
-	STD_EXCEPTION(0x2800, Trap_28, UnknownException)
-	STD_EXCEPTION(0x2900, Trap_29, UnknownException)
-	STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
-	STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
-	STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
-	STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
-	STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
-	STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
-
-
-	.globl	_end_of_vectors
-_end_of_vectors:
-
-	. = 0x3000
-
-/*
- * This code finishes saving the registers to the exception frame
- * and jumps to the appropriate handler for the exception.
- * Register r21 is pointer into trap frame, r1 has new stack pointer.
- */
-	.globl	transfer_to_handler
-transfer_to_handler:
-	stw	r22,_NIP(r21)
-	lis	r22,MSR_POW@h
-	andc	r23,r23,r22
-	stw	r23,_MSR(r21)
-	SAVE_GPR(7, r21)
-	SAVE_4GPRS(8, r21)
-	SAVE_8GPRS(12, r21)
-	SAVE_8GPRS(24, r21)
-	mflr	r23
-	andi.	r24,r23,0x3f00	    /* get vector offset */
-	stw	r24,TRAP(r21)
-	li	r22,0
-	stw	r22,RESULT(r21)
-	lwz	r24,0(r23)		/* virtual address of handler */
-	lwz	r23,4(r23)		/* where to go when done */
-	mtspr	SRR0,r24
-	mtspr	SRR1,r20
-	mtlr	r23
-	SYNC
-	rfi			    /* jump to handler, enable MMU */
-
-int_return:
-	mfmsr	r28		    /* Disable interrupts */
-	li	r4,0
-	ori	r4,r4,MSR_EE
-	andc	r28,r28,r4
-	SYNC			    /* Some chip revs need this... */
-	mtmsr	r28
-	SYNC
-	lwz	r2,_CTR(r1)
-	lwz	r0,_LINK(r1)
-	mtctr	r2
-	mtlr	r0
-	lwz	r2,_XER(r1)
-	lwz	r0,_CCR(r1)
-	mtspr	XER,r2
-	mtcrf	0xFF,r0
-	REST_10GPRS(3, r1)
-	REST_10GPRS(13, r1)
-	REST_8GPRS(23, r1)
-	REST_GPR(31, r1)
-	lwz	r2,_NIP(r1)	    /* Restore environment */
-	lwz	r0,_MSR(r1)
-	mtspr	SRR0,r2
-	mtspr	SRR1,r0
-	lwz	r0,GPR0(r1)
-	lwz	r2,GPR2(r1)
-	lwz	r1,GPR1(r1)
-	SYNC
-	rfi
-
-/*
- * This code initialises the MPC8220 processor core
- * (conforms to PowerPC 603e spec)
- * Note: expects original MSR contents to be in r5.
- */
-
-	.globl	init_8220_core
-init_8220_core:
-
-	/* Initialize machine status; enable machine check interrupt	*/
-	/*--------------------------------------------------------------*/
-
-	li	r3, MSR_KERNEL	    /* Set ME and RI flags		*/
-	rlwimi	r3, r5, 0, 25, 25   /* preserve IP bit set by HRCW	*/
-#ifdef DEBUG
-	rlwimi	r3, r5, 0, 21, 22   /* debugger might set SE & BE bits	*/
-#endif
-	SYNC			    /* Some chip revs need this...	*/
-	mtmsr	r3
-	SYNC
-	mtspr	SRR1, r3	    /* Make SRR1 match MSR		*/
-
-	/* Initialize the Hardware Implementation-dependent Registers	*/
-	/* HID0 also contains cache control				*/
-	/*--------------------------------------------------------------*/
-
-	lis	r3, CONFIG_SYS_HID0_INIT@h
-	ori	r3, r3, CONFIG_SYS_HID0_INIT@l
-	SYNC
-	mtspr	HID0, r3
-
-	lis	r3, CONFIG_SYS_HID0_FINAL@h
-	ori	r3, r3, CONFIG_SYS_HID0_FINAL@l
-	SYNC
-	mtspr	HID0, r3
-
-	/* Enable Extra BATs */
-	mfspr	r3, 1011    /* HID2 */
-	lis	r4, 0x0004
-	ori	r4, r4, 0x0000
-	or	r4, r4, r3
-	mtspr	1011, r4
-	sync
-
-	/* clear all BAT's						*/
-	/*--------------------------------------------------------------*/
-
-	li	r0, 0
-	mtspr	DBAT0U, r0
-	mtspr	DBAT0L, r0
-	mtspr	DBAT1U, r0
-	mtspr	DBAT1L, r0
-	mtspr	DBAT2U, r0
-	mtspr	DBAT2L, r0
-	mtspr	DBAT3U, r0
-	mtspr	DBAT3L, r0
-	mtspr	DBAT4U, r0
-	mtspr	DBAT4L, r0
-	mtspr	DBAT5U, r0
-	mtspr	DBAT5L, r0
-	mtspr	DBAT6U, r0
-	mtspr	DBAT6L, r0
-	mtspr	DBAT7U, r0
-	mtspr	DBAT7L, r0
-	mtspr	IBAT0U, r0
-	mtspr	IBAT0L, r0
-	mtspr	IBAT1U, r0
-	mtspr	IBAT1L, r0
-	mtspr	IBAT2U, r0
-	mtspr	IBAT2L, r0
-	mtspr	IBAT3U, r0
-	mtspr	IBAT3L, r0
-	mtspr	IBAT4U, r0
-	mtspr	IBAT4L, r0
-	mtspr	IBAT5U, r0
-	mtspr	IBAT5L, r0
-	mtspr	IBAT6U, r0
-	mtspr	IBAT6L, r0
-	mtspr	IBAT7U, r0
-	mtspr	IBAT7L, r0
-	SYNC
-
-	/* invalidate all tlb's						*/
-	/*								*/
-	/* From the 603e User Manual: "The 603e provides the ability to */
-	/* invalidate a TLB entry. The TLB Invalidate Entry (tlbie)	*/
-	/* instruction invalidates the TLB entry indexed by the EA, and */
-	/* operates on both the instruction and data TLBs simultaneously*/
-	/* invalidating four TLB entries (both sets in each TLB). The	*/
-	/* index corresponds to bits 15-19 of the EA. To invalidate all */
-	/* entries within both TLBs, 32 tlbie instructions should be	*/
-	/* issued, incrementing this field by one each time."		*/
-	/*								*/
-	/* "Note that the tlbia instruction is not implemented on the	*/
-	/* 603e."							*/
-	/*								*/
-	/* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000	*/
-	/* incrementing by 0x1000 each time. The code below is sort of	*/
-	/* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S	*/
-	/*								*/
-	/*--------------------------------------------------------------*/
-
-	li	r3, 32
-	mtctr	r3
-	li	r3, 0
-1:	tlbie	r3
-	addi	r3, r3, 0x1000
-	bdnz	1b
-	SYNC
-
-	/* Done!							*/
-	/*--------------------------------------------------------------*/
-
-	blr
-
-/* Cache functions.
- *
- * Note: requires that all cache bits in
- * HID0 are in the low half word.
- */
-	.globl	icache_enable
-icache_enable:
-	lis	r4, 0
-	ori	r4, r4, CONFIG_SYS_HID0_INIT /* set ICE & ICFI bit		*/
-	rlwinm	r3, r4, 0, 21, 19     /* clear the ICFI bit		*/
-
-	/*
-	 * The setting of the instruction cache enable (ICE) bit must be
-	 * preceded by an isync instruction to prevent the cache from being
-	 * enabled or disabled while an instruction access is in progress.
-	 */
-	isync
-	mtspr	HID0, r4	      /* Enable Instr Cache & Inval cache */
-	mtspr	HID0, r3	      /* using 2 consec instructions	*/
-	isync
-	blr
-
-	.globl	icache_disable
-icache_disable:
-	mfspr	r3, HID0
-	rlwinm	r3, r3, 0, 17, 15     /* clear the ICE bit		*/
-	mtspr	HID0, r3
-	isync
-	blr
-
-	.globl	icache_status
-icache_status:
-	mfspr	r3, HID0
-	rlwinm	r3, r3, HID0_ICE_BITPOS + 1, 31, 31
-	blr
-
-	.globl	dcache_enable
-dcache_enable:
-	lis	r4, 0
-	ori	r4, r4, HID0_DCE|HID0_DCFI /* set DCE & DCFI bit	*/
-	rlwinm	r3, r4, 0, 22, 20     /* clear the DCFI bit		*/
-
-	/* Enable address translation in MSR bit */
-	mfmsr	r5
-	ori	r5, r5, 0x
-
-
-	/*
-	 * The setting of the instruction cache enable (ICE) bit must be
-	 * preceded by an isync instruction to prevent the cache from being
-	 * enabled or disabled while an instruction access is in progress.
-	 */
-	isync
-	mtspr	HID0, r4	      /* Enable Data Cache & Inval cache*/
-	mtspr	HID0, r3	      /* using 2 consec instructions	*/
-	isync
-	blr
-
-	.globl	dcache_disable
-dcache_disable:
-	mfspr	r3, HID0
-	rlwinm	r3, r3, 0, 18, 16     /* clear the DCE bit */
-	mtspr	HID0, r3
-	isync
-	blr
-
-	.globl	dcache_status
-dcache_status:
-	mfspr	r3, HID0
-	rlwinm	r3, r3, HID0_DCE_BITPOS + 1, 31, 31
-	blr
-
-	.globl	get_pvr
-get_pvr:
-	mfspr	r3, PVR
-	blr
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * r3 = dest
- * r4 = src
- * r5 = length in bytes
- * r6 = cachelinesize
- */
-	.globl	relocate_code
-relocate_code:
-	mr	r1,  r3	    /* Set new stack pointer		*/
-	mr	r9,  r4	    /* Save copy of Global Data pointer */
-	mr	r10, r5	    /* Save copy of Destination Address */
-
-	GET_GOT
-	mr	r3,  r5	    /* Destination Address		*/
-	lis	r4, CONFIG_SYS_MONITOR_BASE@h	/* Source Address	*/
-	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
-	lwz	r5, GOT(__init_end)
-	sub	r5, r5, r4
-	li	r6, CONFIG_SYS_CACHELINE_SIZE	/* Cache Line Size	*/
-
-	/*
-	 * Fix GOT pointer:
-	 *
-	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
-	 *
-	 * Offset:
-	 */
-	sub	r15, r10, r4
-
-	/* First our own GOT */
-	add	r12, r12, r15
-	/* then the one used by the C code */
-	add	r30, r30, r15
-
-	/*
-	 * Now relocate code
-	 */
-
-	cmplw	cr1,r3,r4
-	addi	r0,r5,3
-	srwi.	r0,r0,2
-	beq	cr1,4f	    /* In place copy is not necessary	*/
-	beq	7f	    /* Protect against 0 count		*/
-	mtctr	r0
-	bge	cr1,2f
-
-	la	r8,-4(r4)
-	la	r7,-4(r3)
-1:	lwzu	r0,4(r8)
-	stwu	r0,4(r7)
-	bdnz	1b
-	b	4f
-
-2:	slwi	r0,r0,2
-	add	r8,r4,r0
-	add	r7,r3,r0
-3:	lwzu	r0,-4(r8)
-	stwu	r0,-4(r7)
-	bdnz	3b
-
-/*
- * Now flush the cache: note that we must start from a cache aligned
- * address. Otherwise we might miss one cache line.
- */
-4:	cmpwi	r6,0
-	add	r5,r3,r5
-	beq	7f	    /* Always flush prefetch queue in any case	*/
-	subi	r0,r6,1
-	andc	r3,r3,r0
-	mfspr	r7,HID0	    /* don't do dcbst if dcache is disabled	*/
-	rlwinm	r7,r7,HID0_DCE_BITPOS+1,31,31
-	cmpwi	r7,0
-	beq	9f
-	mr	r4,r3
-5:	dcbst	0,r4
-	add	r4,r4,r6
-	cmplw	r4,r5
-	blt	5b
-	sync		    /* Wait for all dcbst to complete on bus	*/
-9:	mfspr	r7,HID0	    /* don't do icbi if icache is disabled	*/
-	rlwinm	r7,r7,HID0_ICE_BITPOS+1,31,31
-	cmpwi	r7,0
-	beq	7f
-	mr	r4,r3
-6:	icbi	0,r4
-	add	r4,r4,r6
-	cmplw	r4,r5
-	blt	6b
-7:	sync		    /* Wait for all icbi to complete on bus	*/
-	isync
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-
-	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
-	mtlr	r0
-	blr
-
-in_ram:
-
-	/*
-	 * Relocation Function, r12 point to got2+0x8000
-	 *
-	 * Adjust got2 pointers, no need to check for 0, this code
-	 * already puts a few entries in the table.
-	 */
-	li	r0,__got2_entries@sectoff@l
-	la	r3,GOT(_GOT2_TABLE_)
-	lwz	r11,GOT(_GOT2_TABLE_)
-	mtctr	r0
-	sub	r11,r3,r11
-	addi	r3,r3,-4
-1:	lwzu	r0,4(r3)
-	cmpwi	r0,0
-	beq-	2f
-	add	r0,r0,r11
-	stw	r0,0(r3)
-2:	bdnz	1b
-
-	/*
-	 * Now adjust the fixups and the pointers to the fixups
-	 * in case we need to move ourselves again.
-	 */
-	li	r0,__fixup_entries@sectoff@l
-	lwz	r3,GOT(_FIXUP_TABLE_)
-	cmpwi	r0,0
-	mtctr	r0
-	addi	r3,r3,-4
-	beq	4f
-3:	lwzu	r4,4(r3)
-	lwzux	r0,r4,r11
-	cmpwi	r0,0
-	add	r0,r0,r11
-	stw	r4,0(r3)
-	beq-	5f
-	stw	r0,0(r4)
-5:	bdnz	3b
-4:
-clear_bss:
-	/*
-	 * Now clear BSS segment
-	 */
-	lwz	r3,GOT(__bss_start)
-	lwz	r4,GOT(__bss_end)
-
-	cmplw	0, r3, r4
-	beq	6f
-
-	li	r0, 0
-5:
-	stw	r0, 0(r3)
-	addi	r3, r3, 4
-	cmplw	0, r3, r4
-	bne	5b
-6:
-
-	mr	r3, r9	    /* Global Data pointer	*/
-	mr	r4, r10	    /* Destination Address	*/
-	bl	board_init_r
-
-	/*
-	 * Copy exception vector code to low memory
-	 *
-	 * r3: dest_addr
-	 * r7: source address, r8: end address, r9: target address
-	 */
-	.globl	trap_init
-trap_init:
-	mflr	r4	    /* save link register		*/
-	GET_GOT
-	lwz	r7, GOT(_start)
-	lwz	r8, GOT(_end_of_vectors)
-
-	li	r9, 0x100   /* reset vector always at 0x100	*/
-
-	cmplw	0, r7, r8
-	bgelr		    /* return if r7>=r8 - just in case	*/
-1:
-	lwz	r0, 0(r7)
-	stw	r0, 0(r9)
-	addi	r7, r7, 4
-	addi	r9, r9, 4
-	cmplw	0, r7, r8
-	bne	1b
-
-	/*
-	 * relocate `hdlr' and `int_return' entries
-	 */
-	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
-	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
-2:
-	bl	trap_reloc
-	addi	r7, r7, 0x100	    /* next exception vector	    */
-	cmplw	0, r7, r8
-	blt	2b
-
-	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
-	bl	trap_reloc
-
-	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
-	bl	trap_reloc
-
-	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
-	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
-3:
-	bl	trap_reloc
-	addi	r7, r7, 0x100	    /* next exception vector	    */
-	cmplw	0, r7, r8
-	blt	3b
-
-	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
-	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
-4:
-	bl	trap_reloc
-	addi	r7, r7, 0x100	    /* next exception vector	    */
-	cmplw	0, r7, r8
-	blt	4b
-
-	mfmsr	r3		    /* now that the vectors have    */
-	lis	r7, MSR_IP@h	    /* relocated into low memory    */
-	ori	r7, r7, MSR_IP@l    /* MSR[IP] can be turned off    */
-	andc	r3, r3, r7	    /* (if it was on)		    */
-	SYNC			    /* Some chip revs need this...  */
-	mtmsr	r3
-	SYNC
-
-	mtlr	r4		    /* restore link register	    */
-	blr
diff --git a/arch/powerpc/cpu/mpc8220/traps.c b/arch/powerpc/cpu/mpc8220/traps.c
deleted file mode 100644
index 19d6cb5..0000000
--- a/arch/powerpc/cpu/mpc8220/traps.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * linux/arch/powerpc/kernel/traps.c
- *
- * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
- *
- * Modified by Cort Dougan (cort@cs.nmt.edu)
- * and Paul Mackerras (paulus@cs.anu.edu.au)
- * fixed Machine Check Reasons by Reinhard Meyer (r.meyer@emk-elektronik.de)
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This file handles the architecture-dependent parts of hardware exceptions
- */
-
-#include <common.h>
-#include <command.h>
-#include <kgdb.h>
-#include <asm/processor.h>
-
-/* Returns 0 if exception not found and fixup otherwise.  */
-extern unsigned long search_exception_table(unsigned long);
-
-/* THIS NEEDS CHANGING to use the board info structure.
-*/
-#define END_OF_MEM      0x02000000
-
-/*
- * Trap & Exception support
- */
-
-static void print_backtrace(unsigned long *sp)
-{
-	int cnt = 0;
-	unsigned long i;
-
-	printf("Call backtrace: ");
-	while (sp) {
-		if ((uint) sp > END_OF_MEM)
-			break;
-
-		i = sp[1];
-		if (cnt++ % 7 == 0)
-			printf("\n");
-		printf("%08lX ", i);
-		if (cnt > 32)
-			break;
-		sp = (unsigned long *) *sp;
-	}
-	printf("\n");
-}
-
-void show_regs(struct pt_regs *regs)
-{
-	int i;
-
-	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
-		regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
-	printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
-		regs->msr,
-		regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0,
-		regs->msr & MSR_FP ? 1 : 0, regs->msr & MSR_ME ? 1 : 0,
-		regs->msr & MSR_IR ? 1 : 0, regs->msr & MSR_DR ? 1 : 0);
-
-	printf("\n");
-	for (i = 0; i < 32; i++) {
-		if ((i % 8) == 0) {
-			printf("GPR%02d: ", i);
-		}
-
-		printf("%08lX ", regs->gpr[i]);
-		if ((i % 8) == 7) {
-			printf("\n");
-		}
-	}
-}
-
-
-static void _exception(int signr, struct pt_regs *regs)
-{
-	show_regs(regs);
-	print_backtrace((unsigned long *) regs->gpr[1]);
-	panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
-}
-
-void MachineCheckException(struct pt_regs *regs)
-{
-	unsigned long fixup = search_exception_table(regs->nip);
-
-	/* Probing PCI using config cycles cause this exception
-	 * when a device is not present.  Catch it and return to
-	 * the PCI exception handler.
-	 */
-	if (fixup) {
-		regs->nip = fixup;
-		return;
-	}
-#if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-
-	printf("Machine check in kernel mode.\n");
-	printf("Caused by (from msr): ");
-	printf("regs %p ", regs);
-	/* refer to 603e Manual (MPC603EUM/AD), chapter 4.5.2.1 */
-	switch (regs->msr & 0x000F0000) {
-	case (0x80000000 >> 12):
-		printf("Machine check signal - probably due to mm fault\n"
-			"with mmu off\n");
-		break;
-	case (0x80000000 >> 13):
-		printf("Transfer error ack signal\n");
-		break;
-	case (0x80000000 >> 14):
-		printf("Data parity signal\n");
-		break;
-	case (0x80000000 >> 15):
-		printf("Address parity signal\n");
-		break;
-	default:
-		printf("Unknown values in msr\n");
-	}
-	show_regs(regs);
-	print_backtrace((unsigned long *) regs->gpr[1]);
-	panic("machine check");
-}
-
-void AlignmentException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-	show_regs(regs);
-	print_backtrace((unsigned long *) regs->gpr[1]);
-	panic("Alignment Exception");
-}
-
-void ProgramCheckException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-	show_regs(regs);
-	print_backtrace((unsigned long *) regs->gpr[1]);
-	panic("Program Check Exception");
-}
-
-void SoftEmuException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-	show_regs(regs);
-	print_backtrace((unsigned long *) regs->gpr[1]);
-	panic("Software Emulation Exception");
-}
-
-
-void UnknownException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-	printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
-		regs->nip, regs->msr, regs->trap);
-	_exception(0, regs);
-}
-
-#if defined(CONFIG_CMD_BEDBUG)
-extern void do_bedbug_breakpoint(struct pt_regs *);
-#endif
-
-void DebugException(struct pt_regs *regs)
-{
-
-	printf("Debugger trap at @ %lx\n", regs->nip);
-	show_regs(regs);
-#if defined(CONFIG_CMD_BEDBUG)
-	do_bedbug_breakpoint(regs);
-#endif
-}
-
-/* Probe an address by reading.  If not present, return -1, otherwise
- * return 0.
- */
-int addr_probe(uint *addr)
-{
-#if 0
-	int retval;
-
-	__asm__ __volatile__ ("1: lwz %0,0(%1)\n"
-			      "   eieio\n"
-			      "   li %0,0\n"
-			      "2:\n"
-			      ".section .fixup,\"ax\"\n"
-			      "3: li %0,-1\n"
-			      "   b 2b\n"
-			      ".section __ex_table,\"a\"\n"
-			      "   .align 2\n"
-			      "   .long 1b,3b\n"
-			      ".text":"=r" (retval):"r" (addr));
-
-	return (retval);
-#endif
-	return 0;
-}
diff --git a/arch/powerpc/cpu/mpc8220/u-boot.lds b/arch/powerpc/cpu/mpc8220/u-boot.lds
deleted file mode 100644
index dc63d20..0000000
--- a/arch/powerpc/cpu/mpc8220/u-boot.lds
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2003-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  .text      :
-  {
-    arch/powerpc/cpu/mpc8220/start.o	(.text*)
-    *(.text*)
-    . = ALIGN(16);
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/arch/powerpc/cpu/mpc8220/uart.c b/arch/powerpc/cpu/mpc8220/uart.c
deleted file mode 100644
index 772528f..0000000
--- a/arch/powerpc/cpu/mpc8220/uart.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale, Inc
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/*
- * Minimal serial functions needed to use one of the PSC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <mpc8220.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define PSC_BASE   MMAP_PSC1
-
-#if defined(CONFIG_PSC_CONSOLE)
-static int mpc8220_serial_init(void)
-{
-	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
-	u32 counter;
-
-	/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
-	psc->cr = 0;
-	psc->ipcr_acr = 0;
-	psc->isr_imr = 0;
-
-	/* write to CSR: RX/TX baud rate from timers */
-	psc->sr_csr = 0xdd000000;
-
-	psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1;
-
-	/* Setting up BaudRate */
-	counter = ((gd->bus_clk / gd->baudrate)) >> 5;
-	counter++;
-
-	/* write to CTUR: divide counter upper byte */
-	psc->ctur = ((counter & 0xff00) << 16);
-	/* write to CTLR: divide counter lower byte */
-	psc->ctlr = ((counter & 0x00ff) << 24);
-
-	psc->cr = PSC_CR_RST_RX_CMD;
-	psc->cr = PSC_CR_RST_TX_CMD;
-	psc->cr = PSC_CR_RST_ERR_STS_CMD;
-	psc->cr = PSC_CR_RST_BRK_INT_CMD;
-	psc->cr = PSC_CR_RST_MR_PTR_CMD;
-
-	psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE;
-	return (0);
-}
-
-static void mpc8220_serial_putc(const char c)
-{
-	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
-
-	if (c == '\n')
-		serial_putc ('\r');
-
-	/* Wait for last character to go. */
-	while (!(psc->sr_csr & PSC_SR_TXRDY));
-
-	psc->xmitbuf[0] = c;
-}
-
-static int mpc8220_serial_getc(void)
-{
-	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
-
-	/* Wait for a character to arrive. */
-	while (!(psc->sr_csr & PSC_SR_RXRDY));
-	return psc->xmitbuf[2];
-}
-
-static int mpc8220_serial_tstc(void)
-{
-	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
-
-	return (psc->sr_csr & PSC_SR_RXRDY);
-}
-
-static void mpc8220_serial_setbrg(void)
-{
-	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
-	u32 counter;
-
-	counter = ((gd->bus_clk / gd->baudrate)) >> 5;
-	counter++;
-
-	/* write to CTUR: divide counter upper byte */
-	psc->ctur = ((counter & 0xff00) << 16);
-	/* write to CTLR: divide counter lower byte */
-	psc->ctlr = ((counter & 0x00ff) << 24);
-
-	psc->cr = PSC_CR_RST_RX_CMD;
-	psc->cr = PSC_CR_RST_TX_CMD;
-
-	psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE;
-}
-
-static struct serial_device mpc8220_serial_drv = {
-	.name	= "mpc8220_serial",
-	.start	= mpc8220_serial_init,
-	.stop	= NULL,
-	.setbrg	= mpc8220_serial_setbrg,
-	.putc	= mpc8220_serial_putc,
-	.puts	= default_serial_puts,
-	.getc	= mpc8220_serial_getc,
-	.tstc	= mpc8220_serial_tstc,
-};
-
-void mpc8220_serial_initialize(void)
-{
-	serial_register(&mpc8220_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &mpc8220_serial_drv;
-}
-#endif /* CONFIG_PSC_CONSOLE */
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 6776c85..2318064 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -83,10 +83,12 @@
 COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5040)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_T4240)	+= ddr-gen3.o
+COBJS-$(CONFIG_PPC_T4160)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_B4420)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_B4860)	+= ddr-gen3.o
 COBJS-$(CONFIG_BSC9131)		+= ddr-gen3.o
 COBJS-$(CONFIG_BSC9132)		+= ddr-gen3.o
+COBJS-$(CONFIG_PPC_T1040)	+= ddr-gen3.o
 
 COBJS-$(CONFIG_CPM2)	+= ether_fcc.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
@@ -102,8 +104,10 @@
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
 COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
 COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
+COBJS-$(CONFIG_PPC_T4160) += t4240_ids.o
 COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o
 COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
+COBJS-$(CONFIG_PPC_T1040) += t1040_ids.o
 
 COBJS-$(CONFIG_QE)	+= qe_io.o
 COBJS-$(CONFIG_CPM2)	+= serial_scc.o
@@ -137,9 +141,11 @@
 COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
 COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
 COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
+COBJS-$(CONFIG_PPC_T4160) += t4240_serdes.o
 COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o
 COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
 COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o
+COBJS-$(CONFIG_PPC_T1040) += t1040_serdes.o
 
 COBJS-y	+= cpu.o
 COBJS-y	+= cpu_init.o
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 53713e3..4067f05 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -337,7 +337,7 @@
 			while ((in_be32(&l2cache->l2csr0)
 				& (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
 					;
-			out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+			out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
 		}
 		i++;
 	} while (!(cluster & TP_CLUSTER_EOC));
@@ -637,6 +637,28 @@
 	}
 #endif
 
+#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
+		ccsr_usb_phy_t *usb_phy =
+			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+		setbits_be32(&usb_phy->pllprg[1],
+			     CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
+			     CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
+			     CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
+			     CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+		setbits_be32(&usb_phy->port1.ctrl,
+			     CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
+		setbits_be32(&usb_phy->port1.drvvbuscfg,
+			     CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
+		setbits_be32(&usb_phy->port1.pwrfltcfg,
+			     CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+		setbits_be32(&usb_phy->port2.ctrl,
+			     CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
+		setbits_be32(&usb_phy->port2.drvvbuscfg,
+			     CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
+		setbits_be32(&usb_phy->port2.pwrfltcfg,
+			     CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+#endif
+
 #ifdef CONFIG_FMAN_ENET
 	fman_enet_init();
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index dacfdd1..234fde4 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -180,12 +180,5 @@
 
 	invalidate_tlb(1);
 
-#if defined(CONFIG_SECURE_BOOT)
-	/* Disable the TLBs created by ISBC */
-	for (i = CONFIG_SYS_ISBC_START_TLB;
-	     i < CONFIG_SYS_ISBC_START_TLB + CONFIG_SYS_ISBC_NUM_TLBS; i++)
-			disable_tlb(i);
-#endif
-
 	init_tlbs();
 }
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index ef0dd1d..c5b4720 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -142,7 +142,7 @@
 		}
 	}
 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
-	out_be32(&ddr->debug[28], 0x00003000);
+	out_be32(&ddr->debug[28], 0x30003000);
 #endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 01dcdf6..93eca76 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -164,7 +164,7 @@
 	}
 
 	cfg >>= sd_prctl_shift;
-	printf("Using SERDES%d Protocol: 0x%x\n", sd + 1, cfg);
+	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 	if (!is_serdes_prtcl_valid(sd, cfg))
 		printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
 
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 43d4836..861c8e0 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -80,6 +80,8 @@
 	if (nr == id) {
 		table = (u32 *)&__spin_table;
 		printf("table base @ 0x%p\n", table);
+	} else if (is_core_disabled(nr)) {
+		puts("Disabled\n");
 	} else {
 		table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
 		printf("Running on cpu %d\n", id);
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index d529095..672edde 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -128,24 +128,32 @@
 
 	childoff = fdt_subnode_offset(blob, off, name);
 	if (create) {
+		char handle[64], *p;
+
+		strncpy(handle, name, sizeof(handle));
+		p = strchr(handle, '@');
+		if (!strncmp(name, "fman", 4)) {
+			*p = *(p + 1);
+			p++;
+		}
+		*p = '\0';
+
+		dev_off = fdt_path_offset(blob, handle);
+		/* skip this node if alias is not found */
+		if (dev_off == -FDT_ERR_BADPATH)
+			return 0;
+		if (dev_off < 0)
+			return dev_off;
+
 		if (childoff <= 0)
 			childoff = fdt_add_subnode(blob, off, name);
 
+		/* need to update the dev_off after adding a subnode */
+		dev_off = fdt_path_offset(blob, handle);
+		if (dev_off < 0)
+			return dev_off;
+
 		if (childoff > 0) {
-			char handle[64], *p;
-
-			strncpy(handle, name, sizeof(handle));
-			p = strchr(handle, '@');
-			if (!strncmp(name, "fman", 4)) {
-				*p = *(p + 1);
-				p++;
-			}
-			*p = '\0';
-
-			dev_off = fdt_path_offset(blob, handle);
-			if (dev_off < 0)
-				return dev_off;
-
 			dev_handle = fdt_get_phandle(blob, dev_off);
 			if (dev_handle <= 0) {
 				dev_handle = fdt_alloc_phandle(blob);
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 5c4b1e3..a4a21b0 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -69,9 +69,9 @@
 #endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-	mfspr	r3,977
+	mfspr	r3,SPRN_HDBCR1
 	oris	r3,r3,0x0100
-	mtspr	977,r3
+	mtspr	SPRN_HDBCR1,r3
 #endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
@@ -93,10 +93,10 @@
 1:	/* Erratum says set bits 55:60 to 001001 */
 	msync
 	isync
-	mfspr	r3,976
+	mfspr	r3,SPRN_HDBCR0
 	li	r4,0x48
 	rlwimi	r3,r4,0,0x1f8
-	mtspr	976,r3
+	mtspr	SPRN_HDBCR0,r3
 	isync
 2:
 #endif
@@ -154,16 +154,12 @@
 	ori	r3,r3,toreset(__spin_table_addr)@l
 	lwz	r3,0(r3)
 
-	/*
-	 * r10 has the base address for the entry.
-	 * we cannot access it yet before setting up a new TLB
-	 */
 	mfspr	r0,SPRN_PIR
-#if	defined(CONFIG_E6500)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 /*
- * PIR definition for E6500
+ * PIR definition for Chassis 2
  * 0-17 Reserved (logic 0s)
- * 8-19 CHIP_ID,    2'b00      - SoC 1
+ * 18-19 CHIP_ID,    2'b00      - SoC 1
  *                  all others - reserved
  * 20-24 CLUSTER_ID 5'b00000   - CCM 1
  *                  all others - reserved
@@ -177,32 +173,33 @@
  *                       2'b11 - core 3
  * 29-31 THREAD_ID       3'b000 - thread 0
  *                       3'b001 - thread 1
+ *
+ * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08
+ * and clusters by 0x20.
+ *
+ * We renumber PIR so that all threads in the system are consecutive.
  */
-	rlwinm  r4,r0,29,25,31
+
+	rlwinm	r8,r0,29,0x03	/* r8 = core within cluster */
+	srwi	r10,r0,5	/* r10 = cluster */
+
+	mulli	r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER
+	add	r5,r5,r8	/* for spin table index */
+	mulli	r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE	/* for PIR */
 #elif	defined(CONFIG_E500MC)
 	rlwinm	r4,r0,27,27,31
+	mr	r5,r4
 #else
 	mr	r4,r0
+	mr	r5,r4
 #endif
-	slwi	r8,r4,6	/* spin table is padded to 64 byte */
-	add	r10,r3,r8
 
-#ifdef CONFIG_E6500
-	mfspr	r0,SPRN_PIR
 	/*
-	 * core 0 thread 0: pir reset value 0x00, new pir 0
-	 * core 0 thread 1: pir reset value 0x01, new pir 1
-	 * core 1 thread 0: pir reset value 0x08, new pir 2
-	 * core 1 thread 1: pir reset value 0x09, new pir 3
-	 * core 2 thread 0: pir reset value 0x10, new pir 4
-	 * core 2 thread 1: pir reset value 0x11, new pir 5
-	 * etc.
-	 *
-	 * Only thread 0 of each core will be running, updating PIR doesn't
-	 * need to deal with the thread bits.
+	 * r10 has the base address for the entry.
+	 * we cannot access it yet before setting up a new TLB
 	 */
-	rlwinm	r4,r0,30,24,30
-#endif
+	slwi	r8,r5,6	/* spin table is padded to 64 byte */
+	add	r10,r3,r8
 
 	mtspr	SPRN_PIR,r4	/* write to PIR register */
 
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 297f2ed..a4d6e9c 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -112,30 +112,32 @@
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 	/*
 	 * Each cluster has up to 4 cores, sharing the same PLL selection.
-	 * The cluster assignment is fixed per SoC. There is no way identify the
-	 * assignment so far, presuming the "first configuration" which is to
-	 * fill the lower cluster group first before moving up to next group.
-	 * PLL1, PLL2, PLL3 are cluster group A, feeding core 0~3 on cluster 1
-	 * and core 4~7 on cluster 2
-	 * PLL4, PLL5, PLL6 are cluster group B, feeding core 8~11 on cluster 3
-	 * and core 12~15 on cluster 4 if existing
+	 * The cluster assignment is fixed per SoC. PLL1, PLL2, PLL3 are
+	 * cluster group A, feeding cores on cluster 1 and cluster 2.
+	 * PLL4, PLL5, PLL6 are cluster group B, feeding cores on cluster 3
+	 * and cluster 4 if existing.
 	 */
 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
-		u32 c_pll_sel = (in_be32(&clk->clkc0csr + (cpu / 4) * 8) >> 27)
+		int cluster = fsl_qoriq_core_to_cluster(cpu);
+		u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
 				& 0xf;
 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
 		if (cplx_pll > 3)
 			printf("Unsupported architecture configuration"
 				" in function %s\n", __func__);
-		cplx_pll += (cpu / 8) * 3;
-
+		cplx_pll += (cluster / 2) * 3;
 		sysInfo->freqProcessor[cpu] =
 			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
 	}
+#ifdef CONFIG_PPC_B4860
+#define FM1_CLK_SEL	0xe0000000
+#define FM1_CLK_SHIFT	29
+#else
 #define PME_CLK_SEL	0xe0000000
 #define PME_CLK_SHIFT	29
 #define FM1_CLK_SEL	0x1c000000
 #define FM1_CLK_SHIFT	26
+#endif
 	rcw_tmp = in_be32(&gur->rcwsr[7]);
 
 #ifdef CONFIG_SYS_DPAA_PME
@@ -185,6 +187,9 @@
 	case 4:
 		sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
 		break;
+	case 5:
+		sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
+		break;
 	case 6:
 		sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
 		break;
@@ -232,7 +237,8 @@
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
-		u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
+		u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
+				& 0xf;
 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
 
 		sysInfo->freqProcessor[cpu] =
@@ -285,6 +291,10 @@
 #endif
 #endif
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
+#endif
+
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
 #else /* CONFIG_FSL_CORENET */
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 3f76ee6..4f0480b 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -116,10 +116,10 @@
 	/* Erratum says set bits 55:60 to 001001 */
 	msync
 	isync
-	mfspr	r3,976
+	mfspr	r3,SPRN_HDBCR0
 	li	r4,0x48
 	rlwimi	r3,r4,0,0x1f8
-	mtspr	976,r3
+	mtspr	SPRN_HDBCR0,r3
 	isync
 2:
 #endif
@@ -173,52 +173,6 @@
 	mfspr	r1,DBSR
 	mtspr	DBSR,r1		/* Clear all valid bits */
 
-	/*
-	 *	Enable L1 Caches early
-	 *
-	 */
-
-#ifdef CONFIG_SYS_CACHE_STASHING
-	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
-	li	r2,(32 + 0)
-	mtspr	L1CSR2,r2
-#endif
-
-	/* Enable/invalidate the I-Cache */
-	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
-	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
-	mtspr	SPRN_L1CSR1,r2
-1:
-	mfspr	r3,SPRN_L1CSR1
-	and.	r1,r3,r2
-	bne	1b
-
-	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
-	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
-	mtspr	SPRN_L1CSR1,r3
-	isync
-2:
-	mfspr	r3,SPRN_L1CSR1
-	andi.	r1,r3,L1CSR1_ICE@l
-	beq	2b
-
-	/* Enable/invalidate the D-Cache */
-	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
-	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
-	mtspr	SPRN_L1CSR0,r2
-1:
-	mfspr	r3,SPRN_L1CSR0
-	and.	r1,r3,r2
-	bne	1b
-
-	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
-	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
-	mtspr	SPRN_L1CSR0,r3
-	isync
-2:
-	mfspr	r3,SPRN_L1CSR0
-	andi.	r1,r3,L1CSR0_DCE@l
-	beq	2b
 
 	.macro	create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
 	lis	\scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
@@ -372,9 +326,9 @@
 #endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-	mfspr	r3,977
+	mfspr	r3,SPRN_HDBCR1
 	oris	r3,r3,0x0100
-	mtspr	977,r3
+	mtspr	SPRN_HDBCR1,r3
 #endif
 
 	/* Enable Branch Prediction */
@@ -780,13 +734,60 @@
 	isync
 	and.	r1, r0, r4
 	bne	1b
-	lis	r4, L2CSR0_L2E@h
+	lis	r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
+	ori	r4, r4, (L2CSR0_L2REP_MODE)@l
 	sync
-	stw	r4, 0(r3)	/* eanble L2 */
+	stw	r4, 0(r3)	/* enable L2 */
 delete_ccsr_l2_tlb:
 	delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
 #endif
 
+	/*
+	 * Enable the L1. On e6500, this has to be done
+	 * after the L2 is up.
+	 */
+
+#ifdef CONFIG_SYS_CACHE_STASHING
+	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
+	li	r2,(32 + 0)
+	mtspr	L1CSR2,r2
+#endif
+
+	/* Enable/invalidate the I-Cache */
+	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
+	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
+	mtspr	SPRN_L1CSR1,r2
+1:
+	mfspr	r3,SPRN_L1CSR1
+	and.	r1,r3,r2
+	bne	1b
+
+	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
+	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
+	mtspr	SPRN_L1CSR1,r3
+	isync
+2:
+	mfspr	r3,SPRN_L1CSR1
+	andi.	r1,r3,L1CSR1_ICE@l
+	beq	2b
+
+	/* Enable/invalidate the D-Cache */
+	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
+	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
+	mtspr	SPRN_L1CSR0,r2
+1:
+	mfspr	r3,SPRN_L1CSR0
+	and.	r1,r3,r2
+	bne	1b
+
+	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
+	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
+	mtspr	SPRN_L1CSR0,r3
+	isync
+2:
+	mfspr	r3,SPRN_L1CSR0
+	andi.	r1,r3,L1CSR0_DCE@l
+	beq	2b
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
 #define DCSR_LAWBARH0	(CONFIG_SYS_CCSRBAR + 0x1000)
 #define LAW_SIZE_1M	0x13
@@ -1905,6 +1906,7 @@
 	slwi	r4,r4,(10 - 1 - L1_CACHE_SHIFT)
 	mtctr	r4
 1:	dcbi	r0,r3
+	dcblc	r0,r3
 	addi	r3,r3,CONFIG_SYS_CACHELINE_SIZE
 	bdnz	1b
 	sync
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
new file mode 100644
index 0000000..ed61599
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	/* dqrr liodn, frame data liodn, liodn off, sdest */
+	SET_QP_INFO(1, 27, 1, 0),
+	SET_QP_INFO(2, 28, 1, 0),
+	SET_QP_INFO(3, 29, 1, 1),
+	SET_QP_INFO(4, 30, 1, 1),
+	SET_QP_INFO(5, 31, 1, 2),
+	SET_QP_INFO(6, 32, 1, 2),
+	SET_QP_INFO(7, 33, 1, 3),
+	SET_QP_INFO(8, 34, 1, 3),
+	SET_QP_INFO(9, 35, 1, 0),
+	SET_QP_INFO(10, 36, 1, 0),
+	SET_QP_INFO(11, 37, 1, 1),
+	SET_QP_INFO(12, 38, 1, 1),
+	SET_QP_INFO(13, 39, 1, 2),
+	SET_QP_INFO(14, 40, 1, 2),
+	SET_QP_INFO(15, 41, 1, 3),
+	SET_QP_INFO(16, 42, 1, 3),
+	SET_QP_INFO(17, 43, 1, 0),
+	SET_QP_INFO(18, 44, 1, 0),
+	SET_QP_INFO(19, 45, 1, 1),
+	SET_QP_INFO(20, 46, 1, 1),
+	SET_QP_INFO(21, 47, 1, 2),
+	SET_QP_INFO(22, 48, 1, 2),
+	SET_QP_INFO(23, 49, 1, 3),
+	SET_QP_INFO(24, 50, 1, 3),
+	SET_QP_INFO(25, 51, 1, 0),
+};
+#endif
+
+struct srio_liodn_id_table srio_liodn_tbl[] = {
+	SET_SRIO_LIODN_1(1, 307),
+	SET_SRIO_LIODN_1(2, 387),
+};
+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	SET_QMAN_LIODN(62),
+	SET_BMAN_LIODN(63),
+#endif
+
+	SET_SDHC_LIODN(1, 552),
+
+	SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+
+	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 148),
+
+	SET_DMA_LIODN(1, 147),
+	SET_DMA_LIODN(2, 227),
+
+	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+
+	/* SET_NEXUS_LIODN(557), -- not yet implemented */
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(1, 0, 88),
+	SET_FMAN_RX_1G_LIODN(1, 1, 89),
+	SET_FMAN_RX_1G_LIODN(1, 2, 90),
+	SET_FMAN_RX_1G_LIODN(1, 3, 91),
+	SET_FMAN_RX_1G_LIODN(1, 4, 92),
+	SET_FMAN_RX_1G_LIODN(1, 5, 93),
+	SET_FMAN_RX_10G_LIODN(1, 0, 94),
+	SET_FMAN_RX_10G_LIODN(1, 1, 95),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+	SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+	SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+	SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+	SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+	SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct liodn_id_table rman_liodn_tbl[] = {
+	/* Set RMan block 0-3 liodn offset */
+	SET_RMAN_LIODN(0, 678),
+	SET_RMAN_LIODN(1, 679),
+	SET_RMAN_LIODN(2, 680),
+	SET_RMAN_LIODN(3, 681),
+};
+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+	[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
new file mode 100644
index 0000000..8261e03
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet2_serdes.h"
+
+static u8 serdes_cfg_tbl[MAX_SERDES][0xC4][SRDS_MAX_LANES] = {
+	{	/* SerDes 1 */
+	[0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
+		PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
+	[0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
+		PCIE2, PCIE3, PCIE4, SATA1},
+	[0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
+		PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
+	[0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
+		PCIE2, PCIE2, PCIE2, PCIE2},
+	[0x8D] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2,
+		PCIE2, SGMII_SW1_DTSEC6, SGMII_SW1_DTSEC4, SGMII_SW1_DTSEC5},
+	[0x89] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2,
+		PCIE2, PCIE3, SGMII_SW1_DTSEC4, SATA1},
+	[0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE2, PCIE3, PCIE4, SATA1},
+	[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
+	[0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
+	[0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		 PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
+	[0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE2, PCIE2, PCIE2, PCIE2},
+	[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
+		PCIE2, PCIE3, PCIE4, SATA1},
+	[0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
+		PCIE2, PCIE3, SATA2, SATA1},
+	[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
+	[0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
+	[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
+	[0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
+		PCIE2, PCIE2, PCIE2, PCIE2},
+	},
+	{
+	},
+	{
+	},
+	{
+	},
+};
+
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	return serdes_cfg_tbl[serdes][cfg][lane];
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+
+	if (prtcl > (ARRAY_SIZE(serdes_cfg_tbl[serdes])))
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (serdes_cfg_tbl[serdes][prtcl][i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 102defa..c001780 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -31,7 +31,8 @@
 	u8 lanes[SRDS_MAX_LANES];
 };
 
-static struct serdes_config serdes1_cfg_tbl[] = {
+#ifdef CONFIG_PPC_T4240
+static const struct serdes_config serdes1_cfg_tbl[] = {
 	/* SerDes 1 */
 	{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
@@ -66,7 +67,7 @@
 		NONE, NONE, QSGMII_FM1_A, NONE}},
 	{}
 };
-static struct serdes_config serdes2_cfg_tbl[] = {
+static const struct serdes_config serdes2_cfg_tbl[] = {
 	/* SerDes 2 */
 	{1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
@@ -150,7 +151,7 @@
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
 	{}
 };
-static struct serdes_config serdes3_cfg_tbl[] = {
+static const struct serdes_config serdes3_cfg_tbl[] = {
 	/* SerDes 3 */
 	{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
 	{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
@@ -174,20 +175,151 @@
 		SRIO1, SRIO1, SRIO1, SRIO1}},
 	{}
 };
-static struct serdes_config serdes4_cfg_tbl[] = {
+static const struct serdes_config serdes4_cfg_tbl[] = {
 	/* SerDes 4 */
 	{2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
 	{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
 	{6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
 	{8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
-	{10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA1}},
-	{12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA1}},
+	{10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
+	{12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
 	{14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
 	{16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
 	{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
 	{}
 };
-static struct serdes_config *serdes_cfg_tbl[] = {
+#elif defined(CONFIG_PPC_T4160)
+static const struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
+	{2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
+	{4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
+	{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+	{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+	{38, {NONE, NONE, QSGMII_FM1_B, NONE,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
+	{}
+};
+static const struct serdes_config serdes2_cfg_tbl[] = {
+	/* SerDes 2 */
+	{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		NONE, NONE} },
+	{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{38, {NONE, NONE, QSGMII_FM2_B, NONE,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		NONE, NONE, NONE, NONE} },
+	{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, NONE, NONE} },
+	{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, NONE, NONE} },
+	{56, {NONE, XFI_FM1_MAC10,
+		XFI_FM2_MAC10, NONE,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{57, {NONE, XFI_FM1_MAC10,
+		XFI_FM2_MAC10, NONE,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		NONE, NONE} },
+	{}
+};
+static const struct serdes_config serdes3_cfg_tbl[] = {
+	/* SerDes 3 */
+	{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+	{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
+	{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+	{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
+	{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
+	{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
+	{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2} },
+	{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2} },
+	{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
+	{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
+	{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
+	{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+			NONE, NONE, NONE, NONE} },
+	{}
+};
+static const struct serdes_config serdes4_cfg_tbl[] = {
+	/* SerDes 4 */
+	{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
+	{6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
+	{12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
+	{14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
+	{}
+}
+;
+#else
+#error "Need to define SerDes protocol"
+#endif
+static const struct serdes_config *serdes_cfg_tbl[] = {
 	serdes1_cfg_tbl,
 	serdes2_cfg_tbl,
 	serdes3_cfg_tbl,
@@ -196,7 +328,7 @@
 
 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
 {
-	struct serdes_config *ptr;
+	const struct serdes_config *ptr;
 
 	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
 		return 0;
@@ -213,7 +345,7 @@
 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
 {
 	int i;
-	struct serdes_config *ptr;
+	const struct serdes_config *ptr;
 
 	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
 		return 0;
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 39525fb..bc26855 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -77,6 +77,7 @@
 	CPU_TYPE_ENTRY(P5040, P5040, 4),
 	CPU_TYPE_ENTRY(T4240, T4240, 0),
 	CPU_TYPE_ENTRY(T4120, T4120, 0),
+	CPU_TYPE_ENTRY(T4160, T4160, 0),
 	CPU_TYPE_ENTRY(B4860, B4860, 0),
 	CPU_TYPE_ENTRY(G4860, G4860, 0),
 	CPU_TYPE_ENTRY(G4060, G4060, 0),
@@ -84,6 +85,12 @@
 	CPU_TYPE_ENTRY(G4440, G4440, 0),
 	CPU_TYPE_ENTRY(B4420, B4420, 0),
 	CPU_TYPE_ENTRY(B4220, B4220, 0),
+	CPU_TYPE_ENTRY(T1040, T1040, 0),
+	CPU_TYPE_ENTRY(T1041, T1041, 0),
+	CPU_TYPE_ENTRY(T1042, T1042, 0),
+	CPU_TYPE_ENTRY(T1020, T1020, 0),
+	CPU_TYPE_ENTRY(T1021, T1021, 0),
+	CPU_TYPE_ENTRY(T1022, T1022, 0),
 	CPU_TYPE_ENTRY(BSC9130, 9130, 1),
 	CPU_TYPE_ENTRY(BSC9131, 9131, 1),
 	CPU_TYPE_ENTRY(BSC9132, 9132, 2),
@@ -96,35 +103,70 @@
 };
 
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+static inline u32 init_type(u32 cluster, int init_id)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
+	u32 type = in_be32(&gur->tp_ityp[idx]);
+
+	if (type & TP_ITYP_AV)
+		return type;
+
+	return 0;
+}
+
 u32 compute_ppc_cpumask(void)
 {
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	int i = 0, count = 0;
-	u32 cluster, mask = 0;
+	u32 cluster, type, mask = 0;
 
 	do {
 		int j;
-		cluster = in_be32(&gur->tp_cluster[i++].lower);
-		for (j = 0; j < 4; j++) {
-			u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
-			u32 type = in_be32(&gur->tp_ityp[idx]);
-
-			if (type & TP_ITYP_AV) {
+		cluster = in_be32(&gur->tp_cluster[i].lower);
+		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+			type = init_type(cluster, j);
+			if (type) {
 				if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
 					mask |= 1 << count;
+				count++;
 			}
-			count++;
 		}
+		i++;
 	} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
 
 	return mask;
 }
+
+int fsl_qoriq_core_to_cluster(unsigned int core)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int i = 0, count = 0;
+	u32 cluster;
+
+	do {
+		int j;
+		cluster = in_be32(&gur->tp_cluster[i].lower);
+		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+			if (init_type(cluster, j)) {
+				if (count == core)
+					return i;
+				count++;
+			}
+		}
+		i++;
+	} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+
+	return -1;	/* cannot identify the cluster */
+}
+
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 /*
  * Before chassis genenration 2, the cpumask should be hard-coded.
  * In case of cpu type unknown or cpumask unset, use 1 as fail save.
  */
 #define compute_ppc_cpumask()	1
+#define fsl_qoriq_core_to_cluster(x) x
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
 static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index 9adde31..e958e13 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -44,7 +44,6 @@
 		printf("DDR clock (MCLK cycle %u ps) is faster than "
 			"the slowest DIMM(s) (tCKmin %u ps) can support.\n",
 			mclk_ps, tCKmin_X_ps);
-		return 1;
 	}
 	/* determine the acutal cas latency */
 	caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps;
@@ -60,7 +59,6 @@
 	if (caslat_actual * mclk_ps > 20000) {
 		printf("The choosen cas latency %d is too large\n",
 			caslat_actual);
-		return 1;
 	}
 	outpdimm->lowest_common_SPD_caslat = caslat_actual;
 
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 5311a26..7a8636d 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -186,7 +186,7 @@
 	return step_string_tbl[s];
 }
 
-unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
+static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 			  unsigned int dbw_cap_adj[])
 {
 	int i, j;
@@ -354,6 +354,11 @@
 	return total_mem;
 }
 
+/* Use weak function to allow board file to override the address assignment */
+__attribute__((weak, alias("__step_assign_addresses")))
+unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
+			  unsigned int dbw_cap_adj[]);
+
 unsigned long long
 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 				       unsigned int size_only)
@@ -541,14 +546,17 @@
 		total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
 
 	/* setup 3-way interleaving before enabling DDRC */
-	switch (info.memctl_opts[0].memctl_interleaving_mode) {
-	case FSL_DDR_3WAY_1KB_INTERLEAVING:
-	case FSL_DDR_3WAY_4KB_INTERLEAVING:
-	case FSL_DDR_3WAY_8KB_INTERLEAVING:
-		fsl_ddr_set_intl3r(info.memctl_opts[0].memctl_interleaving_mode);
-		break;
-	default:
-		break;
+	if (info.memctl_opts[0].memctl_interleaving) {
+		switch (info.memctl_opts[0].memctl_interleaving_mode) {
+		case FSL_DDR_3WAY_1KB_INTERLEAVING:
+		case FSL_DDR_3WAY_4KB_INTERLEAVING:
+		case FSL_DDR_3WAY_8KB_INTERLEAVING:
+			fsl_ddr_set_intl3r(
+				info.memctl_opts[0].memctl_interleaving_mode);
+			break;
+		default:
+			break;
+		}
 	}
 
 	/* Program configuration registers. */
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 7267611..1009a31 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -512,23 +512,34 @@
 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 
-#elif defined(CONFIG_PPC_T4240)
+#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#define CONFIG_E6500
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
+#ifdef CONFIG_PPC_T4240
 #define CONFIG_MAX_CPUS			12
+#define CONFIG_SYS_NUM_FM1_DTSEC	8
+#define CONFIG_SYS_NUM_FM1_10GEC	2
+#define CONFIG_SYS_NUM_FM2_DTSEC	8
+#define CONFIG_SYS_NUM_FM2_10GEC	2
+#define CONFIG_NUM_DDR_CONTROLLERS	3
+#else
+#define CONFIG_MAX_CPUS			8
+#define CONFIG_SYS_NUM_FM1_DTSEC	7
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_SYS_NUM_FM2_DTSEC	7
+#define CONFIG_SYS_NUM_FM2_10GEC	1
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#endif
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	5
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SRDS_3
 #define CONFIG_SYS_FSL_SRDS_4
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		2
-#define CONFIG_SYS_NUM_FM1_DTSEC	8
-#define CONFIG_SYS_NUM_FM1_10GEC	2
-#define CONFIG_SYS_NUM_FM2_DTSEC	8
-#define CONFIG_SYS_NUM_FM2_10GEC	2
-#define CONFIG_NUM_DDR_CONTROLLERS	3
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
@@ -537,26 +548,23 @@
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_A004468
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_PCI_VER_3_X
 
-#elif defined(CONFIG_PPC_B4420)
+#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
+#define CONFIG_E6500
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
-#define CONFIG_MAX_CPUS			2
-#define CONFIG_SYS_FSL_NUM_CC_PLLS	4
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
-#define CONFIG_SYS_NUM_FM1_DTSEC	4
-#define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
@@ -567,30 +575,50 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
-#elif defined(CONFIG_PPC_B4860)
-#define CONFIG_SYS_PPC64		/* 64-bit core */
-#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
-#define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
+#ifdef CONFIG_PPC_B4860
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
-#define CONFIG_SYS_FSL_NUM_LAWS		32
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
-#define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	6
 #define CONFIG_SYS_NUM_FM1_10GEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#else
+#define CONFIG_MAX_CPUS			2
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	4
+#define CONFIG_SYS_NUM_FM1_DTSEC	4
+#define CONFIG_SYS_NUM_FM1_10GEC	0
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#endif
+
+#elif defined(CONFIG_PPC_T1040)
+#define CONFIG_E5500
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
+#define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
+#define CONFIG_MAX_CPUS			4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	5
+#define CONFIG_SYS_FSL_NUM_LAWS		16
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_FMAN_V3
-#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
-#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_ERRATUM_A_004934
-#define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
 #else
@@ -601,4 +629,10 @@
 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
 #endif
 
+#ifdef CONFIG_E6500
+#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
+#else
+#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
+#endif
+
 #endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index f9cec8e..90b264d 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -70,6 +70,8 @@
 	LAW_TRGT_IF_DCSR = 0x1d,
 	LAW_TRGT_IF_LBC = 0x1f,
 	LAW_TRGT_IF_QMAN = 0x3c,
+
+	LAW_TRGT_IF_MAPLE = 0x50,
 };
 #define LAW_TRGT_IF_DDR		LAW_TRGT_IF_DDR_1
 #define LAW_TRGT_IF_IFC		LAW_TRGT_IF_LBC
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index d1c1967..2bc6ed1 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -23,16 +23,6 @@
 #ifndef __FSL_SECURE_BOOT_H
 #define __FSL_SECURE_BOOT_H
 
-/* Starting TLB number for the TLB entried for 3.5 G space created by ISBC */
-#if defined(CONFIG_FSL_CORENET)
-#define CONFIG_SYS_ISBC_START_TLB		3
-#else
-#define CONFIG_SYS_ISBC_START_TLB		0
-#endif
-
-/* Number fo TLB's created by ISBC */
-#define CONFIG_SYS_ISBC_NUM_TLBS		5
-
 #if defined(CONFIG_FSL_CORENET)
 #define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
 #else
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 6cd7379..ccb91fb 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -80,6 +80,14 @@
 	XFI_FM2_MAC9,
 	XFI_FM2_MAC10,
 	INTERLAKEN,
+	SGMII_SW1_DTSEC1,	/* SW indicates on L2 switch */
+	SGMII_SW1_DTSEC2,
+	SGMII_SW1_DTSEC3,
+	SGMII_SW1_DTSEC4,
+	SGMII_SW1_DTSEC5,
+	SGMII_SW1_DTSEC6,
+	QSGMII_SW1_A,		/* SW indicates on L2 swtich */
+	QSGMII_SW1_B,
 };
 
 enum srds {
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index d5db854..c02447f 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -104,12 +104,6 @@
 	u32 ips_clk;
 	u32 csb_clk;
 #endif /* CONFIG_MPC512X */
-#if defined(CONFIG_MPC8220)
-	unsigned long inp_clk;
-	unsigned long vco_clk;
-	unsigned long pev_clk;
-	unsigned long flb_clk;
-#endif
 	unsigned long reset_status;	/* reset status register at boot */
 #if defined(CONFIG_MPC83xx)
 	unsigned long arbiter_event_attributes;
diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h
index d96e536..8248219 100644
--- a/arch/powerpc/include/asm/immap_512x.h
+++ b/arch/powerpc/include/asm/immap_512x.h
@@ -1272,4 +1272,6 @@
 #define CONFIG_SYS_MPC512x_USB_ADDR \
 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET)
 
+#define IIM_BASE_ADDR	(CONFIG_SYS_IMMR + offsetof(immap_t, iim))
+
 #endif /* __IMMAP_512x__ */
diff --git a/arch/powerpc/include/asm/immap_8220.h b/arch/powerpc/include/asm/immap_8220.h
deleted file mode 100644
index f9595f4..0000000
--- a/arch/powerpc/include/asm/immap_8220.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * MPC8220 Internal Memory Map
- * Copyright (c) 2004 TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * The Internal Memory Map of the 8220.
- *
- */
-#ifndef __IMMAP_MPC8220__
-#define __IMMAP_MPC8220__
-
-/*
- * System configuration registers.
- */
-typedef struct sys_conf {
-    u16     mbar;       /* 0x00 */
-    u16     res1;
-
-    u16     res2;       /* 0x04 */
-    u16     sdramds;
-
-    u32     res3[6];    /* 0x08 */
-
-    u32     cscfg[6];   /* 0x20 */
-
-    u32     res4[2];    /* 0x38 */
-
-    u8      res5[3];    /* 0x40 */
-    u8      rstctrl;
-
-    u8      res6[3];    /* 0x44 */
-    u8      rststat;
-
-    u32     res7[2];    /* 0x48 */
-
-    u32     jtagid;     /* 0x50 */
-} sysconf8220_t;
-
-
-/*
- * Memory controller registers.
- */
-typedef struct mem_ctlr {
-    ushort  mode;           /* 0x100 */
-    ushort  res1;
-    u32     ctrl;           /* 0x104 */
-    u32     cfg1;           /* 0x108 */
-    u32     cfg2;           /* 0x10c */
-} memctl8220_t;
-
-/*
- * XLB Arbitration registers
- */
-typedef struct xlb_arb
-{
-    uint    res1[16];       /* 0x200 */
-    uint    config;         /* 0x240 */
-    uint    version;        /* 0x244 */
-    uint    status;         /* 0x248 */
-    uint    intEnable;      /* 0x24c */
-    uint    addrCap;        /* 0x250 */
-    uint    busSigCap;      /* 0x254 */
-    uint    addrTenTimeOut; /* 0x258 */
-    uint    dataTenTimeOut; /* 0x25c */
-    uint    busActTimeOut;  /* 0x260 */
-    uint    mastPriEn;      /* 0x264 */
-    uint    mastPriority;   /* 0x268 */
-    uint    baseAddr;       /* 0x26c */
-} xlbarb8220_t;
-
-/*
- * Flexbus registers
- */
-typedef struct flexbus
-{
-    ushort  csar0;          /* 0x00 */
-    ushort  res1;
-    uint    csmr0;          /* 0x04 */
-    uint    cscr0;          /* 0x08 */
-
-    ushort  csar1;          /* 0x0c */
-    ushort  res2;
-    uint    csmr1;          /* 0x10 */
-    uint    cscr1;          /* 0x14 */
-
-    ushort  csar2;          /* 0x18 */
-    ushort  res3;
-    uint    csmr2;          /* 0x1c */
-    uint    cscr2;          /* 0x20 */
-
-    ushort  csar3;          /* 0x24 */
-    ushort  res4;
-    uint    csmr3;          /* 0x28 */
-    uint    cscr3;          /* 0x2c */
-
-    ushort  csar4;          /* 0x30 */
-    ushort  res5;
-    uint    csmr4;          /* 0x34 */
-    uint    cscr4;          /* 0x38 */
-
-    ushort  csar5;          /* 0x3c */
-    ushort  res6;
-    uint    csmr5;          /* 0x40 */
-    uint    cscr5;          /* 0x44 */
-} flexbus8220_t;
-
-/*
- * GPIO registers
- */
-typedef struct gpio
-{
-    u32     out;        /* 0x00 */
-    u32     obs;        /* 0x04 */
-    u32     obc;        /* 0x08 */
-    u32     obt;        /* 0x0c */
-    u32     en;         /* 0x10 */
-    u32     ebs;        /* 0x14 */
-    u32     ebc;        /* 0x18 */
-    u32     ebt;        /* 0x1c */
-    u32     mc;         /* 0x20 */
-    u32     st;         /* 0x24 */
-    u32     intr;       /* 0x28 */
-} gpio8220_t;
-
-/*
- * General Purpose Timer registers
- */
-typedef struct gptimer
-{
-    u8  OCPW;
-    u8  OctIct;
-    u8  Control;
-    u8  Mode;
-
-    u16 Prescl;  /* Prescale */
-    u16 Count;   /* Count */
-
-    u16 PwmWid;  /* PWM Width */
-    u8  PwmOp;   /* Output Polarity */
-    u8  PwmLd;   /* Immediate Update */
-
-    u16 Capture; /* Capture internal counter */
-    u8  OvfPin;  /* Ovf and Pin */
-    u8  Int;     /* Interrupts */
-} gptmr8220_t;
-
-/*
- * PSC registers
- */
-typedef struct psc
-{
-    u32 mr1_2;             /* 0x00 Mode reg 1 & 2 */
-    u32 sr_csr;            /* 0x04 Status/Clock Select reg */
-    u32 cr;                /* 0x08 Command reg */
-    u8  xmitbuf[4];        /* 0x0c Receive/Transmit Buffer */
-    u32 ipcr_acr;          /* 0x10 Input Port Change/Auxiliary Control reg */
-    u32 isr_imr;           /* 0x14 Interrupt Status/Mask reg */
-    u32 ctur;              /* 0x18 Counter Timer Upper reg */
-    u32 ctlr;              /* 0x1c Counter Timer Lower reg */
-    u32 rsvd1[4];          /* 0x20 ... 0x2c */
-    u32 ivr;               /* 0x30 Interrupt Vector reg */
-    u32 ipr;               /* 0x34 Input Port reg */
-    u32 opsetr;            /* 0x38 Output Port Set reg */
-    u32 opresetr;          /* 0x3c Output Port Reset reg */
-    u32 sicr;              /* 0x40 PSC/IrDA control reg */
-    u32 ircr1;             /* 0x44 IrDA control reg 1*/
-    u32 ircr2;             /* 0x48 IrDA control reg 2*/
-    u32 irsdr;             /* 0x4c IrDA SIR Divide reg */
-    u32 irmdr;             /* 0x50 IrDA MIR Divide reg */
-    u32 irfdr;             /* 0x54 PSC IrDA FIR Divide reg */
-    u32 rfnum;             /* 0x58 RX-FIFO counter */
-    u32 txnum;             /* 0x5c TX-FIFO counter */
-    u32 rfdata;            /* 0x60 RX-FIFO data */
-    u32 rfstat;            /* 0x64 RX-FIFO status */
-    u32 rfcntl;            /* 0x68 RX-FIFO control */
-    u32 rfalarm;           /* 0x6c RX-FIFO alarm */
-    u32 rfrptr;            /* 0x70 RX-FIFO read pointer */
-    u32 rfwptr;            /* 0x74 RX-FIFO write pointer */
-    u32 rflfrptr;          /* 0x78 RX-FIFO last read frame pointer */
-    u32 rflfwptr;          /* 0x7c RX-FIFO last write frame pointer */
-
-    u32 tfdata;            /* 0x80 TX-FIFO data */
-    u32 tfstat;            /* 0x84 TX-FIFO status */
-    u32 tfcntl;            /* 0x88 TX-FIFO control */
-    u32 tfalarm;           /* 0x8c TX-FIFO alarm */
-    u32 tfrptr;            /* 0x90 TX-FIFO read pointer */
-    u32 tfwptr;            /* 0x94 TX-FIFO write pointer */
-    u32 tflfrptr;          /* 0x98 TX-FIFO last read frame pointer */
-    u32 tflfwptr;          /* 0x9c TX-FIFO last write frame pointer */
-} psc8220_t;
-
-/*
- * Interrupt Controller registers
- */
-typedef struct interrupt_controller {
-} intctl8220_t;
-
-
-/* Fast controllers
-*/
-
-/*
- * I2C registers
- */
-typedef struct i2c
-{
-    u8   adr;            /* 0x00 */
-    u8   res1[3];
-    u8   fdr;            /* 0x04 */
-    u8   res2[3];
-    u8   cr;             /* 0x08 */
-    u8   res3[3];
-    u8   sr;             /* 0x0C */
-    u8   res4[3];
-    u8   dr;             /* 0x10 */
-    u8   res5[3];
-    u32  reserved0;      /* 0x14 */
-    u32  reserved1;      /* 0x18 */
-    u32  reserved2;      /* 0x1c */
-    u8   icr;            /* 0x20 */
-    u8   res6[3];
-} i2c8220_t;
-
-/*
- * Port Configuration Registers
- */
-typedef struct pcfg
-{
-    uint    pcfg0;          /* 0x00 */
-    uint    pcfg1;          /* 0x04 */
-    uint    pcfg2;          /* 0x08 */
-    uint    pcfg3;          /* 0x0c */
-} pcfg8220_t;
-
-/* ...and the whole thing wrapped up....
-*/
-typedef struct immap {
-    sysconf8220_t   im_sysconf; /* System Configuration */
-    memctl8220_t    im_memctl;  /* Memory Controller */
-    xlbarb8220_t    im_xlbarb;  /* XLB Arbitration */
-    psc8220_t       im_psc;     /* PSC controller */
-    flexbus8220_t   im_fb;      /* FlexBus Controller */
-    i2c8220_t       im_i2c;     /* I2C control/status */
-    pcfg8220_t      im_pcfg;    /* Port configuration */
-} immap_t;
-
-#endif /* __IMMAP_MPC8220__ */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index baaa9fe..4052037 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1676,18 +1676,17 @@
 /* Global Utilities Block */
 #ifdef CONFIG_FSL_CORENET
 typedef struct ccsr_gur {
-	u32	porsr1;		/* POR status */
-	u8	res1[28];
+	u32	porsr1;		/* POR status 1 */
+	u32	porsr2;		/* POR status 2 */
+	u8	res_008[0x20-0x8];
 	u32	gpporcr1;	/* General-purpose POR configuration */
-	u8	res2[12];
-	u32	gpiocr;		/* GPIO control */
-	u8	res3[12];
-	u32	gpoutdr;	/* General-purpose output data */
-	u8	res4[12];
-	u32	gpindr;		/* General-purpose input data */
-	u8	res5[12];
-	u32	alt_pmuxcr;	/* Alt function signal multiplex control */
-	u8	res6[12];
+	u32	gpporcr2;	/* General-purpose POR configuration 2 */
+	u32	dcfg_fusesr;	/* Fuse status register */
+#define FSL_CORENET_DCFG_FUSESR_VID_SHIFT	25
+#define FSL_CORENET_DCFG_FUSESR_VID_MASK	0x1F
+#define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT	20
+#define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK	0x1F
+	u8	res_02c[0x70-0x2c];
 	u32	devdisr;	/* Device disable control */
 	u32	devdisr2;	/* Device disable control 2 */
 	u32	devdisr3;	/* Device disable control 3 */
@@ -1831,7 +1830,7 @@
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	16
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x3f
-#if defined(CONFIG_PPC_T4240)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xfc000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	26
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00fe0000
@@ -1845,6 +1844,11 @@
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	25
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00ff0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	16
+#elif defined(CONFIG_PPC_T1040)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL	0xff000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00fe0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	17
 #endif
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1	0x00800000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2	0x00400000
@@ -1899,7 +1903,7 @@
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII          0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE         0x00180000
 #endif
-#if defined(CONFIG_PPC_T4240)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 #define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII	0x00000000
 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO		0x40000000
@@ -1992,6 +1996,7 @@
 
 #define TP_CLUSTER_EOC		0x80000000	/* end of clusters */
 #define TP_CLUSTER_INIT_MASK	0x0000003f	/* initiator mask */
+#define TP_INIT_PER_CLUSTER	4
 
 #define FSL_CORENET_DCSR_SZ_MASK	0x00000003
 #define FSL_CORENET_DCSR_SZ_4M		0x0
@@ -2004,22 +2009,13 @@
 #define rmuliodnr rio1maintliodnr
 
 typedef struct ccsr_clk {
-	u32	clkc0csr;	/* 0x000 Core 0 Clock control/status */
-	u8	res1[0x1c];
-	u32	clkc1csr;	/* 0x020 Core 1 Clock control/status */
-	u8	res2[0x1c];
-	u32	clkc2csr;	/* 0x040 Core 2 Clock control/status */
-	u8	res3[0x1c];
-	u32	clkc3csr;	/* 0x060 Core 3 Clock control/status */
-	u8	res4[0x1c];
-	u32	clkc4csr;	/* 0x080 Core 4 Clock control/status */
-	u8	res5[0x1c];
-	u32	clkc5csr;	/* 0x0a0 Core 5 Clock control/status */
-	u8	res6[0x1c];
-	u32	clkc6csr;	/* 0x0c0 Core 6 Clock control/status */
-	u8	res7[0x1c];
-	u32	clkc7csr;	/* 0x0e0 Core 7 Clock control/status */
-	u8	res8[0x71c];
+	struct {
+		u32 clkcncsr;	/* core cluster n clock control status */
+		u8  res_004[0x0c];
+		u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
+		u8  res_014[0x0c];
+	} clkcsr[8];
+	u8	res_100[0x700]; /* 0x100 */
 	u32	pllc1gsr;	/* 0x800 Cluster PLL 1 General Status */
 	u8	res10[0x1c];
 	u32	pllc2gsr;	/* 0x820 Cluster PLL 2 General Status */
@@ -2829,12 +2825,53 @@
 	u8	res4[0x400];
 } ccsr_pme_t;
 
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+struct ccsr_usb_port_ctrl {
+	u32	ctrl;
+	u32	drvvbuscfg;
+	u32	pwrfltcfg;
+	u32	sts;
+	u8	res_14[0xc];
+	u32	bistcfg;
+	u32	biststs;
+	u32	abistcfg;
+	u32	abiststs;
+	u8	res_30[0x10];
+	u32	xcvrprg;
+	u32	anaprg;
+	u32	anadrv;
+	u32	anasts;
+};
+
+typedef struct ccsr_usb_phy {
+	u32	id;
+	struct  ccsr_usb_port_ctrl port1;
+	u8	res_50[0xc];
+	u32	tvr;
+	u32	pllprg[4];
+	u8	res_70[0x4];
+	u32	anaccfg;
+	u32	dbg;
+	u8	res_7c[0x4];
+	struct  ccsr_usb_port_ctrl port2;
+	u8	res_dc[0x334];
+} ccsr_usb_phy_t;
+
+#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
+#else
 typedef struct ccsr_usb_phy {
 	u8	res0[0x18];
 	u32	usb_enable_override;
 	u8	res[0xe4];
 } ccsr_usb_phy_t;
 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+#endif
 
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
 struct ccsr_raide {
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 8c91f08..56b22d8 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -507,6 +507,15 @@
 #define   L2CSR0_L2IO		0x00100000	/* L2 Cache Instruction Only */
 #define   L2CSR0_L2DO		0x00010000	/* L2 Cache Data Only */
 #define   L2CSR0_L2REP		0x00003000	/* L2 Line Replacement Algo */
+
+/* e6500 */
+#define   L2CSR0_L2REP_SPLRUAGE	0x00000000	/* L2REP Streaming PLRU with Aging */
+#define   L2CSR0_L2REP_FIFO	0x00001000	/* L2REP FIFO */
+#define   L2CSR0_L2REP_SPLRU	0x00002000	/* L2REP Streaming PLRU */
+#define   L2CSR0_L2REP_PLRU	0x00003000	/* L2REP PLRU */
+
+#define   L2CSR0_L2REP_MODE	L2CSR0_L2REP_SPLRUAGE
+
 #define   L2CSR0_L2FL		0x00000800	/* L2 Cache Flush */
 #define   L2CSR0_L2LFC		0x00000400	/* L2 Cache Lock Flash Clear */
 #define   L2CSR0_L2LOA		0x00000080	/* L2 Cache Lock Overflow Allocate */
@@ -575,6 +584,16 @@
 #define SPRN_MSSSR0	0x3f7
 #endif
 
+#define SPRN_HDBCR0	0x3d0
+#define SPRN_HDBCR1	0x3d1
+#define SPRN_HDBCR2	0x3d2
+#define SPRN_HDBCR3	0x3d3
+#define SPRN_HDBCR4	0x3d4
+#define SPRN_HDBCR5	0x3d5
+#define SPRN_HDBCR6	0x3d6
+#define SPRN_HDBCR7	0x277
+#define SPRN_HDBCR8	0x278
+
 /* Short-hand versions for a number of the above SPRNs */
 
 #define CTR	SPRN_CTR	/* Counter Register */
@@ -1099,6 +1118,7 @@
 #define SVR_P5040	0x820400
 #define SVR_T4240	0x824000
 #define SVR_T4120	0x824001
+#define SVR_T4160	0x824100
 #define SVR_B4860	0X868000
 #define SVR_G4860	0x868001
 #define SVR_G4060	0x868003
@@ -1106,6 +1126,12 @@
 #define SVR_G4440	0x868101
 #define SVR_B4420	0x868102
 #define SVR_B4220	0x868103
+#define SVR_T1040	0x852000
+#define SVR_T1041	0x852001
+#define SVR_T1042	0x852002
+#define SVR_T1020	0x852100
+#define SVR_T1021	0x852101
+#define SVR_T1022	0x852102
 
 #define SVR_8610	0x80A000
 #define SVR_8641	0x809000
@@ -1174,6 +1200,8 @@
 struct cpu_type *identify_cpu(u32 ver);
 int fixup_cpu(void);
 
+int fsl_qoriq_core_to_cluster(unsigned int core);
+
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 #define CPU_TYPE_ENTRY(n, v, nc) \
 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index cf972d2..93496a0 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -59,14 +59,6 @@
 #if defined(CONFIG_MPC83xx)
 	unsigned long	bi_immrbar;
 #endif
-#if defined(CONFIG_MPC8220)
-	unsigned long	bi_mbar_base;	/* base of internal registers */
-	unsigned long   bi_inpfreq;     /* Input Freq, In MHz */
-	unsigned long   bi_pcifreq;     /* PCI Freq, in MHz */
-	unsigned long   bi_pevfreq;     /* PEV Freq, in MHz */
-	unsigned long   bi_flbfreq;     /* Flexbus Freq, in MHz */
-	unsigned long   bi_vcofreq;     /* VCO Freq, in MHz */
-#endif
 	unsigned long	bi_bootflags;	/* boot / reboot flag (Unused) */
 	unsigned long	bi_ip_addr;	/* IP Address */
 	unsigned char	bi_enetaddr[6];	/* OLD: see README.enetaddr */
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 41b2294..fc4c1d5 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -301,9 +301,6 @@
 #if defined(CONFIG_MPC5xxx)
 	prt_mpc5xxx_clks,
 #endif /* CONFIG_MPC5xxx */
-#if defined(CONFIG_MPC8220)
-	prt_mpc8220_clks,
-#endif
 	checkboard,
 	INIT_FUNC_WATCHDOG_INIT
 #if defined(CONFIG_MISC_INIT_F)
@@ -548,27 +545,6 @@
 #if defined(CONFIG_MPC83xx)
 	bd->bi_immrbar = CONFIG_SYS_IMMR;
 #endif
-#if defined(CONFIG_MPC8220)
-	bd->bi_mbar_base = CONFIG_SYS_MBAR;	/* base of internal registers */
-	bd->bi_inpfreq = gd->arch.inp_clk;
-	bd->bi_pcifreq = gd->pci_clk;
-	bd->bi_vcofreq = gd->arch.vco_clk;
-	bd->bi_pevfreq = gd->arch.pev_clk;
-	bd->bi_flbfreq = gd->arch.flb_clk;
-
-	/* store bootparam to sram (backward compatible), here? */
-	{
-		u32 *sram = (u32 *) CONFIG_SYS_SRAM_BASE;
-
-		*sram++ = gd->ram_size;
-		*sram++ = gd->bus_clk;
-		*sram++ = gd->arch.inp_clk;
-		*sram++ = gd->cpu_clk;
-		*sram++ = gd->arch.vco_clk;
-		*sram++ = gd->arch.flb_clk;
-		*sram++ = 0xb8c3ba11;	/* boot signature */
-	}
-#endif
 
 	WATCHDOG_RESET();
 	bd->bi_intfreq = gd->cpu_clk;	/* Internal Freq, in Hz */
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 0119a7b..dd6c98c 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -220,101 +220,19 @@
 	return ret;
 }
 
-/*
- * Verify the device tree.
- *
- * This function is called after all device tree fix-ups have been enacted,
- * so that the final device tree can be verified.  The definition of "verified"
- * is up to the specific implementation.  However, it generally means that the
- * addresses of some of the devices in the device tree are compared with the
- * actual addresses at which U-Boot has placed them.
- *
- * Returns 1 on success, 0 on failure.  If 0 is returned, U-boot will halt the
- * boot process.
- */
-static int __ft_verify_fdt(void *fdt)
-{
-	return 1;
-}
-__attribute__((weak, alias("__ft_verify_fdt"))) int ft_verify_fdt(void *fdt);
-
 static int boot_body_linux(bootm_headers_t *images)
 {
-	ulong rd_len;
-	struct lmb *lmb = &images->lmb;
-	ulong *initrd_start = &images->initrd_start;
-	ulong *initrd_end = &images->initrd_end;
-#if defined(CONFIG_OF_LIBFDT)
-	ulong of_size = images->ft_len;
-	char **of_flat_tree = &images->ft_addr;
-#endif
-
 	int ret;
 
-#if defined(CONFIG_OF_LIBFDT)
-	boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
-#endif
-
-	/* allocate space and init command line */
-	ret = boot_cmdline_linux(images);
-	if (ret)
-		return ret;
-
 	/* allocate space for kernel copy of board info */
 	ret = boot_bd_t_linux(images);
 	if (ret)
 		return ret;
 
-	rd_len = images->rd_end - images->rd_start;
-	ret = boot_ramdisk_high (lmb, images->rd_start, rd_len, initrd_start, initrd_end);
+	ret = image_setup_linux(images);
 	if (ret)
 		return ret;
 
-#if defined(CONFIG_OF_LIBFDT)
-	ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
-	if (ret)
-		return ret;
-
-	/*
-	 * Add the chosen node if it doesn't exist, add the env and bd_t
-	 * if the user wants it (the logic is in the subroutines).
-	 */
-	if (of_size) {
-		if (fdt_chosen(*of_flat_tree, 1) < 0) {
-			puts ("ERROR: ");
-			puts ("/chosen node create failed");
-			puts (" - must RESET the board to recover.\n");
-			return -1;
-		}
-#ifdef CONFIG_OF_BOARD_SETUP
-		/* Call the board-specific fixup routine */
-		ft_board_setup(*of_flat_tree, gd->bd);
-#endif
-
-		/* Delete the old LMB reservation */
-		lmb_free(lmb, (phys_addr_t)(u32)*of_flat_tree,
-				(phys_size_t)fdt_totalsize(*of_flat_tree));
-
-		ret = fdt_resize(*of_flat_tree);
-		if (ret < 0)
-			return ret;
-		of_size = ret;
-
-		if (*initrd_start && *initrd_end) {
-			of_size += FDT_RAMDISK_OVERHEAD;
-			fdt_set_totalsize(*of_flat_tree, of_size);
-		}
-		/* Create a new LMB reservation */
-		lmb_reserve(lmb, (ulong)*of_flat_tree, of_size);
-
-		/* fixup the initrd now that we know where it should be */
-		if (*initrd_start && *initrd_end)
-			fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
-
-		if (!ft_verify_fdt(*of_flat_tree))
-			return -1;
-	}
-#endif	/* CONFIG_OF_LIBFDT */
 	return 0;
 }
 
@@ -368,13 +286,6 @@
 		/* convert all clock information to MHz */
 		kbd->bi_intfreq /= 1000000L;
 		kbd->bi_busfreq /= 1000000L;
-#if defined(CONFIG_MPC8220)
-		kbd->bi_inpfreq /= 1000000L;
-		kbd->bi_pcifreq /= 1000000L;
-		kbd->bi_pevfreq /= 1000000L;
-		kbd->bi_flbfreq /= 1000000L;
-		kbd->bi_vcofreq /= 1000000L;
-#endif
 #if defined(CONFIG_CPM2)
 		kbd->bi_cpmfreq /= 1000000L;
 		kbd->bi_brgfreq /= 1000000L;
diff --git a/arch/sparc/lib/bootm.c b/arch/sparc/lib/bootm.c
index bcc6358..1a9343c 100644
--- a/arch/sparc/lib/bootm.c
+++ b/arch/sparc/lib/bootm.c
@@ -95,10 +95,8 @@
 int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t * images)
 {
 	char *bootargs;
-	ulong initrd_start, initrd_end;
 	ulong rd_len;
 	void (*kernel) (struct linux_romvec *, void *);
-	struct lmb *lmb = &images->lmb;
 	int ret;
 
 	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
@@ -131,24 +129,23 @@
 	 * extracted and is writeable.
 	 */
 
+	ret = image_setup_linux(images);
+	if (ret) {
+		puts("### Failed to relocate RAM disk\n");
+		goto error;
+	}
+
 	/* Calc length of RAM disk, if zero no ramdisk available */
 	rd_len = images->rd_end - images->rd_start;
 
 	if (rd_len) {
-		ret = boot_ramdisk_high(lmb, images->rd_start, rd_len,
-					&initrd_start, &initrd_end);
-		if (ret) {
-			puts("### Failed to relocate RAM disk\n");
-			goto error;
-		}
-
 		/* Update SPARC kernel header so that Linux knows
 		 * what is going on and where to find RAM disk.
 		 *
 		 * Set INITRD Image address relative to RAM Start
 		 */
 		linux_hdr->hdr_input.ver_0203.sparc_ramdisk_image =
-		    initrd_start - CONFIG_SYS_RAM_BASE;
+			images->initrd_start - CONFIG_SYS_RAM_BASE;
 		linux_hdr->hdr_input.ver_0203.sparc_ramdisk_size = rd_len;
 		/* Clear READ ONLY flag if set to non-zero */
 		linux_hdr->hdr_input.ver_0203.root_flags = 1;
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 7b520f8..cddf0dd 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -30,7 +30,7 @@
 
 START-y	= start.o
 START-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
-COBJS	= interrupts.o cpu.o timer.o
+COBJS	= interrupts.o cpu.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index f8e28f0..14cb699 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -26,6 +26,7 @@
 #include <asm/u-boot-x86.h>
 #include <flash.h>
 #include <netdev.h>
+#include <ns16550.h>
 #include <asm/msr.h>
 #include <asm/cache.h>
 #include <asm/io.h>
@@ -90,6 +91,9 @@
 
 int last_stage_init(void)
 {
+	if (gd->flags & GD_FLG_COLD_BOOT)
+		timestamp_add_to_bootstage();
+
 	return 0;
 }
 
@@ -135,3 +139,12 @@
 
 	return 0;
 }
+
+void panic_puts(const char *str)
+{
+	NS16550_t port = (NS16550_t)0x3f8;
+
+	NS16550_init(port, 1);
+	while (*str)
+		NS16550_putc(port, *str++);
+}
diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c
index 2ca7a57..bd3558a 100644
--- a/arch/x86/cpu/coreboot/timestamp.c
+++ b/arch/x86/cpu/coreboot/timestamp.c
@@ -39,7 +39,9 @@
 void timestamp_init(void)
 {
 	ts_table = lib_sysinfo.tstamp_table;
-	timer_set_tsc_base(ts_table->base_time);
+#ifdef CONFIG_SYS_X86_TSC_TIMER
+	timer_set_base(ts_table->base_time);
+#endif
 	timestamp_add_now(TS_U_BOOT_INITTED);
 }
 
@@ -59,3 +61,41 @@
 {
 	timestamp_add(id, rdtsc());
 }
+
+int timestamp_add_to_bootstage(void)
+{
+	uint i;
+
+	if (!ts_table)
+		return -1;
+
+	for (i = 0; i < ts_table->num_entries; i++) {
+		struct timestamp_entry *tse = &ts_table->entries[i];
+		const char *name = NULL;
+
+		switch (tse->entry_id) {
+		case TS_START_ROMSTAGE:
+			name = "start-romstage";
+			break;
+		case TS_BEFORE_INITRAM:
+			name = "before-initram";
+			break;
+		case TS_DEVICE_INITIALIZE:
+			name = "device-initialize";
+			break;
+		case TS_DEVICE_DONE:
+			name = "device-done";
+			break;
+		case TS_SELFBOOT_JUMP:
+			name = "selfboot-jump";
+			break;
+		}
+		if (name) {
+			bootstage_add_record(0, name, BOOTSTAGEF_ALLOC,
+					     tse->entry_stamp /
+							get_tbclk_mhz());
+		}
+	}
+
+	return 0;
+}
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 1a2f85c..7a914a5 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -120,6 +120,11 @@
 
 int __weak x86_cleanup_before_linux(void)
 {
+#ifdef CONFIG_BOOTSTAGE_STASH
+	bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH,
+			CONFIG_BOOTSTAGE_STASH_SIZE);
+#endif
+
 	return 0;
 }
 
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index 6dc74e3..e733bcb 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -37,6 +37,8 @@
 #include <asm/msr.h>
 #include <asm/u-boot-x86.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define DECLARE_INTERRUPT(x) \
 	".globl irq_"#x"\n" \
 	".hidden irq_"#x"\n" \
diff --git a/arch/x86/cpu/timer.c b/arch/x86/cpu/timer.c
deleted file mode 100644
index 149109d..0000000
--- a/arch/x86/cpu/timer.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#include <common.h>
-
-unsigned long timer_get_us(void)
-{
-	printf("timer_get_us used but not implemented.\n");
-	return 0;
-}
diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds
index 2d6911a..b4ecd4b 100644
--- a/arch/x86/cpu/u-boot.lds
+++ b/arch/x86/cpu/u-boot.lds
@@ -79,18 +79,6 @@
 	/DISCARD/ : { *(.interp*) }
 	/DISCARD/ : { *(.gnu*) }
 
-	/* 16bit realmode trampoline code */
-	.realmode REALMODE_BASE : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) }
-
-	__realmode_start = LOADADDR(.realmode);
-	__realmode_size = SIZEOF(.realmode);
-
-	/* 16bit BIOS emulation code (just enough to boot Linux) */
-	.bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { KEEP(*(.bios)) }
-
-	__bios_start = LOADADDR(.bios);
-	__bios_size = SIZEOF(.bios);
-
 #ifdef CONFIG_X86_RESET_VECTOR
 
 	/*
diff --git a/arch/x86/include/asm/arch-coreboot/timestamp.h b/arch/x86/include/asm/arch-coreboot/timestamp.h
index d104912..fcfc1d5 100644
--- a/arch/x86/include/asm/arch-coreboot/timestamp.h
+++ b/arch/x86/include/asm/arch-coreboot/timestamp.h
@@ -49,4 +49,11 @@
 void timestamp_add(enum timestamp_id id, uint64_t ts_time);
 void timestamp_add_now(enum timestamp_id id);
 
+/**
+ * timestamp_add_to_bootstage - Add important coreboot timestamps to bootstage
+ *
+ * @return 0 if ok, -1 if no timestamps were found
+ */
+int timestamp_add_to_bootstage(void);
+
 #endif
diff --git a/arch/x86/include/asm/init_helpers.h b/arch/x86/include/asm/init_helpers.h
index d018b29..0a6a675 100644
--- a/arch/x86/include/asm/init_helpers.h
+++ b/arch/x86/include/asm/init_helpers.h
@@ -24,19 +24,10 @@
 #ifndef _INIT_HELPERS_H_
 #define _INIT_HELPERS_H_
 
-int display_banner(void);
-int display_dram_config(void);
-int init_baudrate_f(void);
 int calculate_relocation_address(void);
 
 int init_cache_f_r(void);
-
-int set_reloc_flag_r(void);
-int mem_malloc_init_r(void);
 int init_bd_struct_r(void);
-int flash_init_r(void);
-int status_led_set_r(void);
-int set_load_addr_r(void);
 int init_func_spi(void);
 int find_fdt(void);
 int prepare_fdt(void);
diff --git a/arch/x86/include/asm/init_wrappers.h b/arch/x86/include/asm/init_wrappers.h
deleted file mode 100644
index 899ffb1..0000000
--- a/arch/x86/include/asm/init_wrappers.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * (C) Copyright 2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _INIT_WRAPPERS_H_
-#define _INIT_WRAPPERS_H_
-
-int serial_initialize_r(void);
-int env_relocate_r(void);
-int pci_init_r(void);
-int jumptable_init_r(void);
-int pcmcia_init_r(void);
-int kgdb_init_r(void);
-int enable_interrupts_r(void);
-int eth_initialize_r(void);
-int reset_phy_r(void);
-int ide_init_r(void);
-int scsi_init_r(void);
-int doc_init_r(void);
-int bb_miiphy_init_r(void);
-int post_run_r(void);
-
-#endif	/* !_INIT_WRAPPERS_H_ */
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index 6d68ab6..9cc2034 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -30,8 +30,4 @@
 	const struct pci_device_id _table[]
 
 void pci_setup_type1(struct pci_controller *hose);
-int pci_enable_legacy_video_ports(struct pci_controller* hose);
-int pci_shadow_rom(pci_dev_t dev, unsigned char *dest);
-void pci_remove_rom_window(struct pci_controller* hose, u32 addr);
-u32 pci_get_rom_window(struct pci_controller* hose, int size);
 #endif
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index ae0c388..22e0934 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -33,11 +33,15 @@
 void setup_gdt(gd_t *id, u64 *gdt_addr);
 int init_cache(void);
 int cleanup_before_linux(void);
+void panic_puts(const char *str);
 
 /* cpu/.../timer.c */
 void timer_isr(void *);
 typedef void (timer_fnc_t) (void);
 int register_timer_isr (timer_fnc_t *isr_func);
+unsigned long get_tbclk_mhz(void);
+void timer_set_base(uint64_t base);
+int pcat_timer_init(void);
 
 /* Architecture specific - can be in arch/x86/cpu/, arch/x86/lib/, or $(BOARD)/ */
 int dram_init_f(void);
diff --git a/arch/x86/include/asm/u-boot.h b/arch/x86/include/asm/u-boot.h
index df759fa..006232b 100644
--- a/arch/x86/include/asm/u-boot.h
+++ b/arch/x86/include/asm/u-boot.h
@@ -36,40 +36,8 @@
 #ifndef _U_BOOT_H_
 #define _U_BOOT_H_	1
 
-#include <config.h>
-#include <compiler.h>
-
-#ifdef CONFIG_SYS_GENERIC_BOARD
 /* Use the generic board which requires a unified bd_info */
 #include <asm-generic/u-boot.h>
-#else
-
-#ifndef __ASSEMBLY__
-
-typedef struct bd_info {
-	unsigned long	bi_memstart;	/* start of DRAM memory */
-	phys_size_t	bi_memsize;	/* size	 of DRAM memory in bytes */
-	unsigned long	bi_flashstart;	/* start of FLASH memory */
-	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
-	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
-	unsigned long	bi_sramstart;	/* start of SRAM memory */
-	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
-	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
-	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
-	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
-	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
-	unsigned int	bi_baudrate;	/* Console Baudrate */
-	unsigned long   bi_boot_params;	/* where this board expects params */
-	struct				/* RAM configuration */
-	{
-		ulong start;
-		ulong size;
-	}bi_dram[CONFIG_NR_DRAM_BANKS];
-} bd_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* !CONFIG_SYS_GENERIC_BOARD */
 
 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_I386
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index ee89354..f66ad30 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -25,24 +25,18 @@
 
 LIB	= $(obj)lib$(ARCH).o
 
-ifeq ($(CONFIG_SYS_GENERIC_BOARD),)
-COBJS-y	+= board.o
-endif
-
 COBJS-y	+= bootm.o
 COBJS-y	+= cmd_boot.o
 COBJS-y	+= gcc.o
 COBJS-y	+= init_helpers.o
-COBJS-y	+= init_wrappers.o
 COBJS-y	+= interrupts.o
 COBJS-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o
-COBJS-$(CONFIG_SYS_GENERIC_TIMER) += pcat_timer.o
-COBJS-$(CONFIG_PCI) += pci.o
+COBJS-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o
 COBJS-$(CONFIG_PCI) += pci_type1.o
 COBJS-y	+= relocate.o
 COBJS-y += physmem.o
 COBJS-y	+= string.o
-COBJS-$(CONFIG_SYS_X86_ISR_TIMER)	+= timer.o
+COBJS-$(CONFIG_SYS_X86_TSC_TIMER)	+= tsc_timer.o
 COBJS-$(CONFIG_VIDEO_VGA)	+= video.o
 COBJS-$(CONFIG_CMD_ZBOOT)	+= zimage.o
 
diff --git a/arch/x86/lib/bios.h b/arch/x86/lib/bios.h
deleted file mode 100644
index 96509b0..0000000
--- a/arch/x86/lib/bios.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _BIOS_H_
-#define _BIOS_H_
-
-#define OFFS_ES		0	/* 16bit */
-#define OFFS_GS		2	/* 16bit */
-#define OFFS_DS		4	/* 16bit */
-#define OFFS_EDI	6	/* 32bit */
-#define OFFS_DI		6	/* low 16 bits of EDI */
-#define OFFS_ESI	10	/* 32bit */
-#define OFFS_SI		10	/* low 16 bits of ESI */
-#define OFFS_EBP	14	/* 32bit */
-#define OFFS_BP		14	/* low 16 bits of EBP */
-#define OFFS_ESP	18	/* 32bit */
-#define OFFS_SP		18	/* low 16 bits of ESP */
-#define OFFS_EBX	22	/* 32bit */
-#define OFFS_BX		22	/* low 16 bits of EBX */
-#define OFFS_BL		22	/* low  8 bits of BX */
-#define OFFS_BH		23	/* high 8 bits of BX */
-#define OFFS_EDX	26	/* 32bit */
-#define OFFS_DX		26	/* low 16 bits of EBX */
-#define OFFS_DL		26	/* low  8 bits of BX */
-#define OFFS_DH		27	/* high 8 bits of BX */
-#define OFFS_ECX	30	/* 32bit */
-#define OFFS_CX		30	/* low 16 bits of EBX */
-#define OFFS_CL		30	/* low  8 bits of BX */
-#define OFFS_CH		31	/* high 8 bits of BX */
-#define OFFS_EAX	34	/* 32bit */
-#define OFFS_AX		34	/* low 16 bits of EBX */
-#define OFFS_AL		34	/* low  8 bits of BX */
-#define OFFS_AH		35	/* high 8 bits of BX */
-#define OFFS_VECTOR	38	/* 16bit */
-#define OFFS_IP		40	/* 16bit */
-#define OFFS_CS		42	/* 16bit */
-#define OFFS_FLAGS	44	/* 16bit */
-
-/* stack at 0x40:0x800 -> 0x800 */
-#define SEGMENT		0x40
-#define STACK		0x800
-
-/*
- * save general registers
- * save some segments
- * save callers stack segment
- * setup BIOS segments
- * setup BIOS stackpointer
- */
-#define MAKE_BIOS_STACK		\
-	pushal;			\
-	pushw	%ds;		\
-	pushw	%gs;		\
-	pushw	%es;		\
-	pushw	%ss;		\
-	popw	%gs;		\
-	movw	$SEGMENT, %ax;	\
-	movw	%ax, %ds;	\
-	movw	%ax, %es;	\
-	movw	%ax, %ss;	\
-	movw	%sp, %bp;	\
-	movw	$STACK, %sp
-
-/*
- * restore callers stack segment
- * restore some segments
- * restore general registers
- */
-#define RESTORE_CALLERS_STACK	\
-	pushw	%gs;		\
-	popw	%ss;		\
-	movw	%bp, %sp;	\
-	popw	%es;		\
-	popw	%gs;		\
-	popw	%ds;		\
-	popal
-
-#ifndef __ASSEMBLY__
-#define BIOS_DATA	((char *)0x400)
-#define BIOS_DATA_SIZE	256
-#define BIOS_BASE	((char *)0xf0000)
-#define BIOS_CS		0xf000
-
-extern ulong __bios_start;
-extern ulong __bios_size;
-
-/* these are defined in a 16bit segment and needs
- * to be accessed with the RELOC_16_xxxx() macros below
- */
-extern u16 ram_in_64kb_chunks;
-extern u16 bios_equipment;
-extern u8  pci_last_bus;
-
-extern void *rm_int00;
-extern void *rm_int01;
-extern void *rm_int02;
-extern void *rm_int03;
-extern void *rm_int04;
-extern void *rm_int05;
-extern void *rm_int06;
-extern void *rm_int07;
-extern void *rm_int08;
-extern void *rm_int09;
-extern void *rm_int0a;
-extern void *rm_int0b;
-extern void *rm_int0c;
-extern void *rm_int0d;
-extern void *rm_int0e;
-extern void *rm_int0f;
-extern void *rm_int10;
-extern void *rm_int11;
-extern void *rm_int12;
-extern void *rm_int13;
-extern void *rm_int14;
-extern void *rm_int15;
-extern void *rm_int16;
-extern void *rm_int17;
-extern void *rm_int18;
-extern void *rm_int19;
-extern void *rm_int1a;
-extern void *rm_int1b;
-extern void *rm_int1c;
-extern void *rm_int1d;
-extern void *rm_int1e;
-extern void *rm_int1f;
-extern void *rm_def_int;
-
-#define RELOC_16_LONG(seg, off) (*(u32 *)(seg << 4 | (u32)&off))
-#define RELOC_16_WORD(seg, off) (*(u16 *)(seg << 4 | (u32)&off))
-#define RELOC_16_BYTE(seg, off) (*(u8 *)(seg << 4 | (u32)&off))
-
-#ifdef PCI_BIOS_DEBUG
-extern u32 num_pci_bios_present;
-extern u32 num_pci_bios_find_device;
-extern u32 num_pci_bios_find_class;
-extern u32 num_pci_bios_generate_special_cycle;
-extern u32 num_pci_bios_read_cfg_byte;
-extern u32 num_pci_bios_read_cfg_word;
-extern u32 num_pci_bios_read_cfg_dword;
-extern u32 num_pci_bios_write_cfg_byte;
-extern u32 num_pci_bios_write_cfg_word;
-extern u32 num_pci_bios_write_cfg_dword;
-extern u32 num_pci_bios_get_irq_routing;
-extern u32 num_pci_bios_set_irq;
-extern u32 num_pci_bios_unknown_function;
-#endif
-
-#endif
-
-#endif
diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c
deleted file mode 100644
index 228c2c8..0000000
--- a/arch/x86/lib/board.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * (C) Copyright 2008-2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <fdtdec.h>
-#include <watchdog.h>
-#include <stdio_dev.h>
-#include <asm/u-boot-x86.h>
-#include <asm/relocate.h>
-#include <asm/processor.h>
-#include <asm/sections.h>
-
-#include <asm/init_helpers.h>
-#include <asm/init_wrappers.h>
-
-/*
- * Breath some life into the board...
- *
- * Getting the board up and running is a three-stage process:
- *  1) Execute from Flash, SDRAM Uninitialised
- *     At this point, there is a limited amount of non-SDRAM memory
- *     (typically the CPU cache, but can also be SRAM or even a buffer of
- *     of some peripheral). This limited memory is used to hold:
- *      - The initial copy of the Global Data Structure
- *      - A temporary stack
- *      - A temporary x86 Global Descriptor Table
- *      - The pre-console buffer (if enabled)
- *
- *     The following is performed during this phase of execution:
- *      - Core low-level CPU initialisation
- *      - Console initialisation
- *      - SDRAM initialisation
- *
- *  2) Execute from Flash, SDRAM Initialised
- *     At this point we copy Global Data from the initial non-SDRAM
- *     memory and set up the permanent stack in SDRAM. The CPU cache is no
- *     longer being used as temporary memory, so we can now fully enable
- *     it.
- *
- *     The following is performed during this phase of execution:
- *      - Create final stack in SDRAM
- *      - Copy Global Data from temporary memory to SDRAM
- *      - Enabling of CPU cache(s),
- *      - Copying of U-Boot code and data from Flash to RAM
- *      - Clearing of the BSS
- *      - ELF relocation adjustments
- *
- *  3) Execute from SDRAM
- *     The following is performed during this phase of execution:
- *      - All remaining initialisation
- */
-
-/*
- * The requirements for any new initalization function is simple: it is
- * a function with no parameters which returns an integer return code,
- * where 0 means "continue" and != 0 means "fatal error, hang the system"
- */
-typedef int (init_fnc_t) (void);
-
-/*
- * init_sequence_f is the list of init functions which are run when U-Boot
- * is executing from Flash with a limited 'C' environment. The following
- * limitations must be considered when implementing an '_f' function:
- *  - 'static' variables are read-only
- *  - Global Data (gd->xxx) is read/write
- *  - Stack space is limited
- *
- * The '_f' sequence must, as a minimum, initialise SDRAM. It _should_
- * also initialise the console (to provide early debug output)
- */
-init_fnc_t *init_sequence_f[] = {
-	cpu_init_f,
-	board_early_init_f,
-#ifdef CONFIG_OF_CONTROL
-	find_fdt,
-	fdtdec_check_fdt,
-#endif
-	env_init,
-	init_baudrate_f,
-	serial_init,
-	console_init_f,
-#ifdef CONFIG_OF_CONTROL
-	prepare_fdt,
-#endif
-	dram_init_f,
-	calculate_relocation_address,
-
-	NULL,
-};
-
-/*
- * init_sequence_f_r is the list of init functions which are run when
- * U-Boot is executing from Flash with a semi-limited 'C' environment.
- * The following limitations must be considered when implementing an
- * '_f_r' function:
- *  - 'static' variables are read-only
- *  - Global Data (gd->xxx) is read/write
- *
- * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
- * supported).  It _should_, if possible, copy global data to RAM and
- * initialise the CPU caches (to speed up the relocation process)
- */
-init_fnc_t *init_sequence_f_r[] = {
-	init_cache_f_r,
-	copy_uboot_to_ram,
-	copy_fdt_to_ram,
-	clear_bss,
-	do_elf_reloc_fixups,
-
-	NULL,
-};
-
-/*
- * init_sequence_r is the list of init functions which are run when U-Boot
- * is executing from RAM with a full 'C' environment. There are no longer
- * any limitations which must be considered when implementing an '_r'
- * function, (i.e.'static' variables are read/write)
- *
- * If not already done, the '_r' sequence must copy global data to RAM and
- * (should) initialise the CPU caches.
- */
-init_fnc_t *init_sequence_r[] = {
-	set_reloc_flag_r,
-	init_bd_struct_r,
-	mem_malloc_init_r,
-	cpu_init_r,
-	board_early_init_r,
-	dram_init,
-	interrupt_init,
-	timer_init,
-	display_banner,
-	display_dram_config,
-	serial_initialize_r,
-#ifndef CONFIG_SYS_NO_FLASH
-	flash_init_r,
-#endif
-#ifdef CONFIG_PCI
-	pci_init_r,
-#endif
-#ifdef CONFIG_SPI
-	init_func_spi,
-#endif
-	env_relocate_r,
-	stdio_init,
-	jumptable_init_r,
-	console_init_r,
-#ifdef CONFIG_MISC_INIT_R
-	misc_init_r,
-#endif
-#if defined(CONFIG_CMD_KGDB)
-	kgdb_init_r,
-#endif
-	enable_interrupts_r,
-#ifdef CONFIG_STATUS_LED
-	status_led_set_r,
-#endif
-	set_load_addr_r,
-#if defined(CONFIG_CMD_IDE)
-	ide_init_r,
-#endif
-#if defined(CONFIG_CMD_SCSI)
-	scsi_init_r,
-#endif
-#if defined(CONFIG_CMD_DOC)
-	doc_init_r,
-#endif
-#ifdef CONFIG_BITBANGMII
-	bb_miiphy_init_r,
-#endif
-#if defined(CONFIG_CMD_NET)
-	eth_initialize_r,
-#ifdef CONFIG_RESET_PHY_R
-	reset_phy_r,
-#endif
-#endif
-#ifdef CONFIG_LAST_STAGE_INIT
-	last_stage_init,
-#endif
-	NULL,
-};
-
-static void do_init_loop(init_fnc_t **init_fnc_ptr)
-{
-	for (; *init_fnc_ptr; ++init_fnc_ptr) {
-		WATCHDOG_RESET();
-		if ((*init_fnc_ptr)() != 0)
-			hang();
-	}
-}
-
-void board_init_f(ulong boot_flags)
-{
-	gd->fdt_blob = gd->new_fdt = NULL;
-	gd->flags = boot_flags;
-
-	do_init_loop(init_sequence_f);
-
-	/*
-	 * SDRAM and console are now initialised. The final stack can now
-	 * be setup in SDRAM. Code execution will continue in Flash, but
-	 * with the stack in SDRAM and Global Data in temporary memory
-	 * (CPU cache)
-	 */
-	board_init_f_r_trampoline(gd->start_addr_sp);
-
-	/* NOTREACHED - board_init_f_r_trampoline() does not return */
-	while (1)
-		;
-}
-
-void board_init_f_r(void)
-{
-	do_init_loop(init_sequence_f_r);
-
-	/*
-	 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
-	 * Transfer execution from Flash to RAM by calculating the address
-	 * of the in-RAM copy of board_init_r() and calling it
-	 */
-	(board_init_r + gd->reloc_off)(gd, gd->relocaddr);
-
-	/* NOTREACHED - board_init_r() does not return */
-	while (1)
-		;
-}
-
-void board_init_r(gd_t *id, ulong dest_addr)
-{
-	do_init_loop(init_sequence_r);
-
-	/* main_loop() can return to retry autoboot, if so just run it again. */
-	for (;;)
-		main_loop();
-
-	/* NOTREACHED - no way out of command loop except booting */
-}
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 83caf6b..2520228 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -93,14 +93,6 @@
 		goto error;
 	}
 
-#ifdef DEBUG
-	printf("## Transferring control to Linux (at address %08x) ...\n",
-		(u32)base_ptr);
-#endif
-
-	/* we assume that the kernel is in place */
-	printf("\nStarting kernel ...\n\n");
-
 	boot_zimage(base_ptr, load_address);
 	/* does not return */
 
diff --git a/arch/x86/lib/cmd_boot.c b/arch/x86/lib/cmd_boot.c
index a81a9a3..315be5a 100644
--- a/arch/x86/lib/cmd_boot.c
+++ b/arch/x86/lib/cmd_boot.c
@@ -36,6 +36,8 @@
 #include <malloc.h>
 #include <asm/u-boot-x86.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 unsigned long do_go_exec(ulong (*entry)(int, char * const []),
 			 int argc, char * const argv[])
 {
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index af9dbc1..a57a0eb 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -21,60 +21,12 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <command.h>
 #include <fdtdec.h>
-#include <stdio_dev.h>
-#include <version.h>
-#include <malloc.h>
-#include <net.h>
-#include <ide.h>
-#include <serial.h>
 #include <spi.h>
-#include <status_led.h>
-#include <asm/processor.h>
 #include <asm/sections.h>
-#include <asm/u-boot-x86.h>
-#include <linux/compiler.h>
-
-#include <asm/init_helpers.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/************************************************************************
- * Init Utilities							*
- ************************************************************************
- * Some of this code should be moved into the core functions,
- * or dropped completely,
- * but let's get it working (again) first...
- */
-
-int display_banner(void)
-{
-	printf("\n\n%s\n\n", version_string);
-
-	return 0;
-}
-
-int display_dram_config(void)
-{
-	int i;
-
-	puts("DRAM Configuration:\n");
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
-		print_size(gd->bd->bi_dram[i].size, "\n");
-	}
-
-	return 0;
-}
-
-int init_baudrate_f(void)
-{
-	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
-	return 0;
-}
-
 /* Get the top of usable RAM */
 __weak ulong board_get_usable_ram_top(ulong total_size)
 {
@@ -134,21 +86,6 @@
 	return init_cache();
 }
 
-int set_reloc_flag_r(void)
-{
-	gd->flags = GD_FLG_RELOC;
-
-	return 0;
-}
-
-int mem_malloc_init_r(void)
-{
-	mem_malloc_init(((gd->relocaddr - CONFIG_SYS_MALLOC_LEN)+3)&~3,
-			CONFIG_SYS_MALLOC_LEN);
-
-	return 0;
-}
-
 bd_t bd_data;
 
 int init_bd_struct_r(void)
@@ -159,39 +96,6 @@
 	return 0;
 }
 
-#ifndef CONFIG_SYS_NO_FLASH
-int flash_init_r(void)
-{
-	ulong size;
-
-	puts("Flash: ");
-
-	/* configure available FLASH banks */
-	size = flash_init();
-
-	print_size(size, "\n");
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_STATUS_LED
-int status_led_set_r(void)
-{
-	status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
-
-	return 0;
-}
-#endif
-
-int set_load_addr_r(void)
-{
-	/* Initialize from environment */
-	load_addr = getenv_ulong("loadaddr", 16, load_addr);
-
-	return 0;
-}
-
 int init_func_spi(void)
 {
 	puts("SPI:   ");
@@ -200,7 +104,6 @@
 	return 0;
 }
 
-#ifdef CONFIG_OF_CONTROL
 int find_fdt(void)
 {
 #ifdef CONFIG_OF_EMBED
@@ -227,4 +130,3 @@
 
 	return 0;
 }
-#endif
diff --git a/arch/x86/lib/init_wrappers.c b/arch/x86/lib/init_wrappers.c
deleted file mode 100644
index 19af875..0000000
--- a/arch/x86/lib/init_wrappers.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * (C) Copyright 2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <environment.h>
-#include <fdtdec.h>
-#include <serial.h>
-#include <kgdb.h>
-#include <scsi.h>
-#include <post.h>
-#include <miiphy.h>
-
-#include <asm/init_wrappers.h>
-
-int serial_initialize_r(void)
-{
-	serial_initialize();
-
-	return 0;
-}
-
-/*
- * Tell if it's OK to load the environment early in boot.
- *
- * If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see
- * if this is OK (defaulting to saying it's not OK).
- *
- * NOTE: Loading the environment early can be a bad idea if security is
- *       important, since no verification is done on the environment.
- *
- * @return 0 if environment should not be loaded, !=0 if it is ok to load
- */
-static int should_load_env(void)
-{
-#ifdef CONFIG_OF_CONTROL
-	return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 0);
-#elif defined CONFIG_DELAY_ENVIRONMENT
-	return 0;
-#else
-	return 1;
-#endif
-}
-
-int env_relocate_r(void)
-{
-	/* initialize environment */
-	if (should_load_env())
-		env_relocate();
-	else
-		set_default_env(NULL);
-
-	return 0;
-}
-
-
-int pci_init_r(void)
-{
-	/* Do pci configuration */
-	pci_init();
-
-	return 0;
-}
-
-int jumptable_init_r(void)
-{
-	jumptable_init();
-
-	return 0;
-}
-
-int pcmcia_init_r(void)
-{
-	puts("PCMCIA:");
-	pcmcia_init();
-
-	return 0;
-}
-
-int kgdb_init_r(void)
-{
-	puts("KGDB:  ");
-	kgdb_init();
-
-	return 0;
-}
-
-int enable_interrupts_r(void)
-{
-	/* enable exceptions */
-	enable_interrupts();
-
-	return 0;
-}
-
-int eth_initialize_r(void)
-{
-	puts("Net:   ");
-	eth_initialize(gd->bd);
-
-	return 0;
-}
-
-int reset_phy_r(void)
-{
-#ifdef DEBUG
-	puts("Reset Ethernet PHY\n");
-#endif
-	reset_phy();
-
-	return 0;
-}
-
-int ide_init_r(void)
-{
-	puts("IDE:   ");
-	ide_init();
-
-	return 0;
-}
-
-int scsi_init_r(void)
-{
-	puts("SCSI:  ");
-	scsi_init();
-
-	return 0;
-}
-
-#ifdef CONFIG_BITBANGMII
-int bb_miiphy_init_r(void)
-{
-	bb_miiphy_init();
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_POST
-int post_run_r(void)
-{
-	post_run(NULL, POST_RAM | post_bootmode_get(0));
-
-	return 0;
-}
-#endif
diff --git a/arch/x86/lib/pcat_timer.c b/arch/x86/lib/pcat_timer.c
index b0b6637..1ca3eb9 100644
--- a/arch/x86/lib/pcat_timer.c
+++ b/arch/x86/lib/pcat_timer.c
@@ -24,83 +24,20 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/i8254.h>
-#include <asm/ibmpc.h>
-#include <asm/interrupt.h>
 
-#define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */
 #define TIMER2_VALUE 0x0a8e /* 440Hz */
 
-static int timer_init_done;
-
-int timer_init(void)
+int pcat_timer_init(void)
 {
-	/* initialize timer 0 and 2
-	 *
-	 * Timer 0 is used to increment system_tick 1000 times/sec
-	 * Timer 1 was used for DRAM refresh in early PC's
-	 * Timer 2 is used to drive the speaker
+	/*
+	 * initialize 2, used to drive the speaker
 	 * (to start a beep: write 3 to port 0x61,
 	 * to stop it again: write 0)
 	 */
-	outb(PIT_CMD_CTR0 | PIT_CMD_BOTH | PIT_CMD_MODE2,
-			PIT_BASE + PIT_COMMAND);
-	outb(TIMER0_VALUE & 0xff, PIT_BASE + PIT_T0);
-	outb(TIMER0_VALUE >> 8, PIT_BASE + PIT_T0);
-
 	outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3,
 			PIT_BASE + PIT_COMMAND);
 	outb(TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2);
 	outb(TIMER2_VALUE >> 8, PIT_BASE + PIT_T2);
 
-	irq_install_handler(0, timer_isr, NULL);
-	unmask_irq(0);
-
-	timer_init_done = 1;
-
 	return 0;
 }
-
-static u16 read_pit(void)
-{
-	u8 low;
-
-	outb(PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND);
-	low = inb(PIT_BASE + PIT_T0);
-
-	return (inb(PIT_BASE + PIT_T0) << 8) | low;
-}
-
-/* this is not very exact */
-void __udelay(unsigned long usec)
-{
-	int counter;
-	int wraps;
-
-	if (timer_init_done) {
-		counter = read_pit();
-		wraps = usec / 1000;
-		usec = usec % 1000;
-
-		usec *= 1194;
-		usec /= 1000;
-		usec += counter;
-
-		while (usec > 1194) {
-			usec -= 1194;
-			wraps++;
-		}
-
-		while (1) {
-			int new_count = read_pit();
-
-			if (((new_count < usec) && !wraps) || wraps < 0)
-				break;
-
-			if (new_count > counter)
-				wraps--;
-
-			counter = new_count;
-		}
-	}
-
-}
diff --git a/arch/x86/lib/pci.c b/arch/x86/lib/pci.c
deleted file mode 100644
index 71878dd..0000000
--- a/arch/x86/lib/pci.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-
-#undef PCI_ROM_SCAN_VERBOSE
-
-int pci_shadow_rom(pci_dev_t dev, unsigned char *dest)
-{
-	struct pci_controller *hose;
-	int res = -1;
-	int i;
-
-	u32 rom_addr;
-	u32 addr_reg;
-	u32 size;
-
-	u16 vendor;
-	u16 device;
-	u32 class_code;
-
-	u32 pci_data;
-
-	hose = pci_bus_to_hose(PCI_BUS(dev));
-
-	debug("pci_shadow_rom() asked to shadow device %x to %x\n",
-	       dev, (u32)dest);
-
-	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
-	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
-	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_code);
-
-	class_code &= 0xffffff00;
-	class_code >>= 8;
-
-	debug("PCI Header Vendor %04x device %04x class %06x\n",
-	       vendor, device, class_code);
-
-	/* Enable the rom addess decoder */
-	pci_write_config_dword(dev, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK);
-	pci_read_config_dword(dev, PCI_ROM_ADDRESS, &addr_reg);
-
-	if (!addr_reg) {
-		/* register unimplemented */
-		printf("pci_chadow_rom: device do not seem to have a rom\n");
-		return -1;
-	}
-
-	size = (~(addr_reg&PCI_ROM_ADDRESS_MASK)) + 1;
-
-	debug("ROM is %d bytes\n", size);
-
-	rom_addr = pci_get_rom_window(hose, size);
-
-	debug("ROM mapped at %x\n", rom_addr);
-
-	pci_write_config_dword(dev, PCI_ROM_ADDRESS,
-			       pci_phys_to_mem(dev, rom_addr)
-			       |PCI_ROM_ADDRESS_ENABLE);
-
-
-	for (i = rom_addr; i < rom_addr + size; i += 512) {
-		if (readw(i) == 0xaa55) {
-#ifdef PCI_ROM_SCAN_VERBOSE
-			printf("ROM signature found\n");
-#endif
-			pci_data = readw(0x18 + i);
-			pci_data += i;
-
-			if (0 == memcmp((void *)pci_data, "PCIR", 4)) {
-#ifdef PCI_ROM_SCAN_VERBOSE
-				printf("Fount PCI rom image at offset %d\n",
-				       i - rom_addr);
-				printf("Vendor %04x device %04x class %06x\n",
-				       readw(pci_data + 4), readw(pci_data + 6),
-				       readl(pci_data + 0x0d) & 0xffffff);
-				printf("%s\n",
-				       (readw(pci_data + 0x15) & 0x80) ?
-				       "Last image" : "More images follow");
-				switch	(readb(pci_data + 0x14)) {
-				case 0:
-					printf("X86 code\n");
-					break;
-				case 1:
-					printf("Openfirmware code\n");
-					break;
-				case 2:
-					printf("PARISC code\n");
-					break;
-				}
-				printf("Image size %d\n",
-				       readw(pci_data + 0x10) * 512);
-#endif
-				/*
-				 * FixMe: I think we should compare the class
-				 * code bytes as well but I have no reference
-				 * on the exact order of these bytes in the PCI
-				 * ROM header
-				 */
-				if (readw(pci_data + 4) == vendor &&
-				    readw(pci_data + 6) == device &&
-				    readb(pci_data + 0x14) == 0) {
-#ifdef PCI_ROM_SCAN_VERBOSE
-					printf("Suitable ROM image found\n");
-#endif
-					memmove(dest, (void *)rom_addr,
-						readw(pci_data + 0x10) * 512);
-					res = 0;
-					break;
-
-				}
-
-				if (readw(pci_data + 0x15) & 0x80)
-					break;
-			}
-		}
-
-	}
-
-#ifdef PCI_ROM_SCAN_VERBOSE
-	if (res)
-		printf("No suitable image found\n");
-#endif
-	/* disable PAR register and PCI device ROM address devocer */
-	pci_remove_rom_window(hose, rom_addr);
-
-	pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0);
-
-	return res;
-}
-
-#ifdef PCI_BIOS_DEBUG
-
-void print_bios_bios_stat(void)
-{
-	printf("16 bit functions:\n");
-	printf("pci_bios_present:                %d\n",
-			RELOC_16_LONG(0xf000, num_pci_bios_present));
-	printf("pci_bios_find_device:            %d\n",
-			RELOC_16_LONG(0xf000, num_pci_bios_find_device));
-	printf("pci_bios_find_class:             %d\n",
-			RELOC_16_LONG(0xf000, num_pci_bios_find_class));
-	printf("pci_bios_generate_special_cycle: %d\n",
-			RELOC_16_LONG(0xf000,
-				      num_pci_bios_generate_special_cycle));
-	printf("pci_bios_read_cfg_byte:          %d\n",
-			RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_byte));
-	printf("pci_bios_read_cfg_word:          %d\n",
-			RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_word));
-	printf("pci_bios_read_cfg_dword:         %d\n",
-			RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_dword));
-	printf("pci_bios_write_cfg_byte:         %d\n",
-			RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_byte));
-	printf("pci_bios_write_cfg_word:         %d\n",
-			RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_word));
-	printf("pci_bios_write_cfg_dword:        %d\n",
-			RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_dword));
-	printf("pci_bios_get_irq_routing:        %d\n",
-			RELOC_16_LONG(0xf000, num_pci_bios_get_irq_routing));
-	printf("pci_bios_set_irq:                %d\n",
-			RELOC_16_LONG(0xf000, num_pci_bios_set_irq));
-	printf("pci_bios_unknown_function:       %d\n",
-			RELOC_16_LONG(0xf000, num_pci_bios_unknown_function));
-}
-#endif
diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c
index 18f0e62..59b3fe9 100644
--- a/arch/x86/lib/physmem.c
+++ b/arch/x86/lib/physmem.c
@@ -12,6 +12,8 @@
 #include <physmem.h>
 #include <linux/compiler.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Large pages are 2MB. */
 #define LARGE_PAGE_SIZE ((1 << 20) * 2)
 
diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c
index f178db9..21982db 100644
--- a/arch/x86/lib/relocate.c
+++ b/arch/x86/lib/relocate.c
@@ -39,6 +39,8 @@
 #include <asm/sections.h>
 #include <elf.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int copy_uboot_to_ram(void)
 {
 	size_t len = (size_t)&__data_end - (size_t)&__text_start;
diff --git a/arch/x86/lib/timer.c b/arch/x86/lib/timer.c
deleted file mode 100644
index 1f8ce60..0000000
--- a/arch/x86/lib/timer.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * (C) Copyright 2008,2009
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/i8254.h>
-#include <asm/ibmpc.h>
-
-struct timer_isr_function {
-	struct timer_isr_function *next;
-	timer_fnc_t *isr_func;
-};
-
-static struct timer_isr_function *first_timer_isr;
-static unsigned long system_ticks;
-
-/*
- * register_timer_isr() allows multiple architecture and board specific
- * functions to be called every millisecond. Keep the execution time of
- * each function as low as possible
- */
-int register_timer_isr(timer_fnc_t *isr_func)
-{
-	struct timer_isr_function *new_func;
-	struct timer_isr_function *temp;
-	int flag;
-
-	new_func = malloc(sizeof(struct timer_isr_function));
-
-	if (new_func == NULL)
-		return 1;
-
-	new_func->isr_func = isr_func;
-	new_func->next = NULL;
-
-	/*
-	 *  Don't allow timer interrupts while the
-	 *  linked list is being modified
-	 */
-	flag = disable_interrupts();
-
-	if (first_timer_isr == NULL) {
-		first_timer_isr = new_func;
-	} else {
-		temp = first_timer_isr;
-		while (temp->next != NULL)
-			temp = temp->next;
-		temp->next = new_func;
-	}
-
-	if (flag)
-		enable_interrupts();
-
-	return 0;
-}
-
-/*
- * timer_isr() MUST be the registered interrupt handler for
- */
-void timer_isr(void *unused)
-{
-	struct timer_isr_function *temp = first_timer_isr;
-
-	system_ticks++;
-
-	/* Execute each registered function */
-	while (temp != NULL) {
-		temp->isr_func();
-		temp = temp->next;
-	}
-}
-
-ulong get_timer(ulong base)
-{
-	return system_ticks - base;
-}
-
-void timer_set_tsc_base(uint64_t new_base)
-{
-	gd->arch.tsc_base = new_base;
-}
-
-uint64_t timer_get_tsc(void)
-{
-	uint64_t time_now;
-
-	time_now = rdtsc();
-	if (!gd->arch.tsc_base)
-		gd->arch.tsc_base = time_now;
-
-	return time_now - gd->arch.tsc_base;
-}
diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c
new file mode 100644
index 0000000..c509801
--- /dev/null
+++ b/arch/x86/lib/tsc_timer.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/i8254.h>
+#include <asm/ibmpc.h>
+#include <asm/msr.h>
+#include <asm/u-boot-x86.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void timer_set_base(u64 base)
+{
+	gd->arch.tsc_base = base;
+}
+
+/*
+ * Get the number of CPU time counter ticks since it was read first time after
+ * restart. This yields a free running counter guaranteed to take almost 6
+ * years to wrap around even at 100GHz clock rate.
+ */
+u64 get_ticks(void)
+{
+	u64 now_tick = rdtsc();
+
+	/* We assume that 0 means the base hasn't been set yet */
+	if (!gd->arch.tsc_base)
+		panic("No tick base available");
+	return now_tick - gd->arch.tsc_base;
+}
+
+#define PLATFORM_INFO_MSR 0xce
+
+/* Get the speed of the TSC timer in MHz */
+unsigned long get_tbclk_mhz(void)
+{
+	u32 ratio;
+	u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
+
+	/* 100MHz times Max Non Turbo ratio */
+	ratio = (platform_info >> 8) & 0xff;
+	return 100 * ratio;
+}
+
+unsigned long get_tbclk(void)
+{
+	return get_tbclk_mhz() * 1000 * 1000;
+}
+
+static ulong get_ms_timer(void)
+{
+	return (get_ticks() * 1000) / get_tbclk();
+}
+
+ulong get_timer(ulong base)
+{
+	return get_ms_timer() - base;
+}
+
+ulong timer_get_us(void)
+{
+	return get_ticks() / get_tbclk_mhz();
+}
+
+ulong timer_get_boot_us(void)
+{
+	return timer_get_us();
+}
+
+void __udelay(unsigned long usec)
+{
+	u64 now = get_ticks();
+	u64 stop;
+
+	stop = now + usec * get_tbclk_mhz();
+
+	while ((int64_t)(stop - get_ticks()) > 0)
+		;
+}
+
+int timer_init(void)
+{
+#ifdef CONFIG_SYS_PCAT_TIMER
+	/* Set up the PCAT timer if required */
+	pcat_timer_init();
+#endif
+
+	return 0;
+}
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 4e9e1f7..b54cf12 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -283,6 +283,13 @@
 
 void boot_zimage(void *setup_base, void *load_address)
 {
+	debug("## Transferring control to Linux (at address %08x) ...\n",
+	      (u32)setup_base);
+
+	bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
+#ifdef CONFIG_BOOTSTAGE_REPORT
+	bootstage_report();
+#endif
 	board_final_cleanup();
 
 	printf("\nStarting kernel ...\n\n");
@@ -363,10 +370,6 @@
 		return -1;
 	}
 
-	printf("## Transferring control to Linux "
-	       "(at address %08x) ...\n",
-	       (u32)base_ptr);
-
 	/* we assume that the kernel is in place */
 	boot_zimage(base_ptr, load_address);
 	/* does not return */
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
index f2b4284..af5338e 100644
--- a/board/CarMediaLab/flea3/flea3.c
+++ b/board/CarMediaLab/flea3/flea3.c
@@ -29,8 +29,7 @@
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
-#include <asm/arch/mx35_pins.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx35.h>
 #include <i2c.h>
 #include <linux/types.h>
 #include <asm/gpio.h>
@@ -165,62 +164,68 @@
 
 static void setup_iomux_uart3(void)
 {
-	mxc_request_iomux(MX35_PIN_RTS2, MUX_CONFIG_ALT7);
-	mxc_request_iomux(MX35_PIN_CTS2, MUX_CONFIG_ALT7);
+	static const iomux_v3_cfg_t uart3_pads[] = {
+		MX35_PAD_RTS2__UART3_RXD_MUX,
+		MX35_PAD_CTS2__UART3_TXD_MUX,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 }
 
+#define I2C_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
+
 static void setup_iomux_i2c(void)
 {
-	int pad;
+	static const iomux_v3_cfg_t i2c_pads[] = {
+		NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
 
-	mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
-	mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
+		NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
+	};
 
-	pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
-			| PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
-
-	mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
-	mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
-
-	mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
-	mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
-
-	mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
-	mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
+	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 }
 
 
 static void setup_iomux_spi(void)
 {
-	mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
-	mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
-	mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
-	mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
-	mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+	static const iomux_v3_cfg_t spi_pads[] = {
+		MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
+		MX35_PAD_CSPI1_MISO__CSPI1_MISO,
+		MX35_PAD_CSPI1_SS0__CSPI1_SS0,
+		MX35_PAD_CSPI1_SS1__CSPI1_SS1,
+		MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
 }
 
 static void setup_iomux_fec(void)
 {
-	/* setup pins for FEC */
-	mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+	static const iomux_v3_cfg_t fec_pads[] = {
+		MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+		MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+		MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+		MX35_PAD_FEC_COL__FEC_COL,
+		MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+		MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+		MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+		MX35_PAD_FEC_MDC__FEC_MDC,
+		MX35_PAD_FEC_MDIO__FEC_MDIO,
+		MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+		MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+		MX35_PAD_FEC_CRS__FEC_CRS,
+		MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+		MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+		MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+		MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+		MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+		MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+	};
 
+	/* setup pins for FEC */
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 int board_early_init_f(void)
@@ -229,7 +234,7 @@
 		(struct ccm_regs *)IMX_CCM_BASE;
 
 	/* setup GPIO3_1 to set HighVCore signal */
-	mxc_request_iomux(MX35_PIN_ATA_DA1, MUX_CONFIG_ALT5);
+	imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
 	gpio_direction_output(65, 1);
 
 	/* initialize PLL and clock configuration */
diff --git a/board/LaCie/net2big_v2/kwbimage.cfg b/board/LaCie/net2big_v2/kwbimage.cfg
index 8d9f153..d3904d3 100644
--- a/board/LaCie/net2big_v2/kwbimage.cfg
+++ b/board/LaCie/net2big_v2/kwbimage.cfg
@@ -19,7 +19,7 @@
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/LaCie/netspace_v2/kwbimage-is2.cfg b/board/LaCie/netspace_v2/kwbimage-is2.cfg
index 590720a..93b803c 100644
--- a/board/LaCie/netspace_v2/kwbimage-is2.cfg
+++ b/board/LaCie/netspace_v2/kwbimage-is2.cfg
@@ -19,7 +19,7 @@
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
index d008eb0..0a8a514 100644
--- a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
+++ b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
@@ -19,7 +19,7 @@
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/LaCie/netspace_v2/kwbimage.cfg b/board/LaCie/netspace_v2/kwbimage.cfg
index 7e53649..0cf4682 100644
--- a/board/LaCie/netspace_v2/kwbimage.cfg
+++ b/board/LaCie/netspace_v2/kwbimage.cfg
@@ -19,7 +19,7 @@
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg
index 0daf5b5..aeddc0c 100644
--- a/board/LaCie/wireless_space/kwbimage.cfg
+++ b/board/LaCie/wireless_space/kwbimage.cfg
@@ -22,7 +22,7 @@
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/Marvell/dreamplug/kwbimage.cfg b/board/Marvell/dreamplug/kwbimage.cfg
index ca9cd74..e662b2d 100644
--- a/board/Marvell/dreamplug/kwbimage.cfg
+++ b/board/Marvell/dreamplug/kwbimage.cfg
@@ -24,7 +24,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/Marvell/guruplug/kwbimage.cfg b/board/Marvell/guruplug/kwbimage.cfg
index 2afd927..9baf6bc 100644
--- a/board/Marvell/guruplug/kwbimage.cfg
+++ b/board/Marvell/guruplug/kwbimage.cfg
@@ -21,7 +21,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg b/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
index ec2513f..f74d443 100644
--- a/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
+++ b/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
@@ -21,7 +21,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/Marvell/openrd/kwbimage.cfg b/board/Marvell/openrd/kwbimage.cfg
index 757eb28..19d0bac 100644
--- a/board/Marvell/openrd/kwbimage.cfg
+++ b/board/Marvell/openrd/kwbimage.cfg
@@ -21,7 +21,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/Marvell/rd6281a/kwbimage.cfg b/board/Marvell/rd6281a/kwbimage.cfg
index 0d12dd9..c8b5d74 100644
--- a/board/Marvell/rd6281a/kwbimage.cfg
+++ b/board/Marvell/rd6281a/kwbimage.cfg
@@ -21,7 +21,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/Seagate/dockstar/kwbimage.cfg b/board/Seagate/dockstar/kwbimage.cfg
index 98b514d..4b0351d 100644
--- a/board/Seagate/dockstar/kwbimage.cfg
+++ b/board/Seagate/dockstar/kwbimage.cfg
@@ -24,7 +24,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/alaska/Makefile b/board/Seagate/goflexhome/Makefile
similarity index 64%
copy from board/alaska/Makefile
copy to board/Seagate/goflexhome/Makefile
index a21f851..9948fe2 100644
--- a/board/alaska/Makefile
+++ b/board/Seagate/goflexhome/Makefile
@@ -1,6 +1,13 @@
 #
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+#
+# Based on dockstar/Makefile originally written by
+# Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/Makefile originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -12,27 +19,27 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
 #
 
 include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= $(BOARD).o flash.o
+COBJS	:= goflexhome.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
 
 #########################################################################
 
diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c
new file mode 100644
index 0000000..17c1905
--- /dev/null
+++ b/board/Seagate/goflexhome/goflexhome.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+ *
+ * Based on dockstar.c originally written by
+ * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.c originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_UART0_RTS,
+		MPP9_UART0_CTS,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GPIO,
+		MPP21_GPIO,
+		MPP22_GPIO,
+		MPP23_GPIO,
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_TSMP9,
+		MPP30_GPIO,
+		MPP31_GPIO,
+		MPP32_GPIO,
+		MPP33_GPIO,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(GOFLEXHOME_OE_VAL_LOW,
+		       GOFLEXHOME_OE_VAL_HIGH,
+		       GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+		       __func__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#define GREEN_LED	(1 << 14)
+#define ORANGE_LED	(1 << 15)
+#define BOTH_LEDS	(GREEN_LED | ORANGE_LED)
+#define NEITHER_LED	0
+
+static void set_leds(u32 leds, u32 blinking)
+{
+	struct kwgpio_registers *r;
+	u32 oe;
+	u32 bl;
+
+	r = (struct kwgpio_registers *)KW_GPIO1_BASE;
+	oe = readl(&r->oe) | BOTH_LEDS;
+	writel(oe & ~leds, &r->oe);	/* active low */
+	bl = readl(&r->blink_en) & ~BOTH_LEDS;
+	writel(bl | blinking, &r->blink_en);
+}
+
+void show_boot_progress(int val)
+{
+	switch (val) {
+	case BOOTSTAGE_ID_RUN_OS:		/* booting Linux */
+		set_leds(BOTH_LEDS, NEITHER_LED);
+		break;
+	case BOOTSTAGE_ID_NET_ETH_START:	/* Ethernet initialization */
+		set_leds(GREEN_LED, GREEN_LED);
+		break;
+	default:
+		if (val < 0)	/* error */
+			set_leds(ORANGE_LED, ORANGE_LED);
+		break;
+	}
+}
diff --git a/board/Seagate/goflexhome/kwbimage.cfg b/board/Seagate/goflexhome/kwbimage.cfg
new file mode 100644
index 0000000..e984d72
--- /dev/null
+++ b/board/Seagate/goflexhome/kwbimage.cfg
@@ -0,0 +1,168 @@
+#
+# Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+#
+# Based on dockstar/kwbimage.cfg originally written by
+# Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/kwbimage.cfg originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000d	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs1width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c
index 644c445..80a7822 100644
--- a/board/ait/cam_enc_4xx/cam_enc_4xx.c
+++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c
@@ -120,7 +120,7 @@
 #ifdef CONFIG_NAND_DAVINCI
 static int
 davinci_std_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
-				   uint8_t *buf, int page)
+				   uint8_t *buf, int oob_required, int page)
 {
 	struct nand_chip *this = mtd->priv;
 	int i, eccsize = chip->ecc.size;
@@ -167,8 +167,9 @@
 	return 0;
 }
 
-static void davinci_std_write_page_syndrome(struct mtd_info *mtd,
-				    struct nand_chip *chip, const uint8_t *buf)
+static int davinci_std_write_page_syndrome(struct mtd_info *mtd,
+				    struct nand_chip *chip, const uint8_t *buf,
+				    int oob_required)
 {
 	unsigned char davinci_ecc_buf[NAND_MAX_OOBSIZE];
 	struct nand_chip *this = mtd->priv;
@@ -218,6 +219,7 @@
 	i = mtd->oobsize - (oob - chip->oob_poi);
 	if (i)
 		chip->write_buf(mtd, oob, i);
+	return 0;
 }
 
 static int davinci_std_write_oob_syndrome(struct mtd_info *mtd,
@@ -239,7 +241,7 @@
 }
 
 static int davinci_std_read_oob_syndrome(struct mtd_info *mtd,
-	struct nand_chip *chip, int page, int sndcmd)
+	struct nand_chip *chip, int page)
 {
 	struct nand_chip *this = mtd->priv;
 	uint8_t *buf = chip->oob_poi;
@@ -249,7 +251,7 @@
 
 	chip->read_buf(mtd, bufpoi, mtd->oobsize);
 
-	return 1;
+	return 0;
 }
 
 static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
diff --git a/board/alaska/README b/board/alaska/README
deleted file mode 100644
index 3345073..0000000
--- a/board/alaska/README
+++ /dev/null
@@ -1,482 +0,0 @@
-Freescale Alaska MPC8220 board
-==============================
-
-TsiChung Liew(Tsi-Chung.Liew@freescale.com)
-Created 9/21/04
-===========================================
-
-
-Changed files:
-==============
-
-- Makefile		    added MPC8220 and Alaska8220_config
-- MAKEALL		    added MPC8220 and Alaska8220
-- README		    added CONFIG_MPC8220, Alaska8220_config
-
-- common/cmd_bdinfo.c	    added board information members for MPC8220
-- common/cmd_bootm.c	    added clocks for MPC8220 in do_bootm_linux()
-
-- include/common.h	    added CONFIG_MPC8220
-
-- include/asm-ppc/u-boot.h  added board information members for MPC8220
-- include/asm-ppc/global_data.h added global variables - inp_clk, pci_clk,
-			    vco_clk, pev_clk, flb_clk, and bExtUart
-
-- arch/powerpc/lib/board.c	    added CONFIG_MPC8220 support
-
-- net/eth.c		    added FEC support for MPC8220
-
-Added files:
-============
-- board/alaska		    directory for Alaska MPC8220
-- board/alaska/alaska.c	    Alaska dram and BATs setup
-- board/alaska/extserial.c  external serial (debug card serial) support
-- board/alaska/flash.c	    Socket (AMD) and Onboard (INTEL) flash support
-- board/alaska/serial.c	    to determine which int/ext serial to use
-- board/alaska/Makefile	    Makefile
-- board/alaska/config.mk    config make
-- board/alaska/u-boot.lds   Linker description
-
-- arch/powerpc/cpu/mpc8220/dma.h	    multi-channel dma header file
-- arch/powerpc/cpu/mpc8220/dramSetup.h   dram setup header file
-- arch/powerpc/cpu/mpc8220/fec.h	    MPC8220 FEC header file
-- arch/powerpc/cpu/mpc8220/cpu.c	    cpu specific code
-- arch/powerpc/cpu/mpc8220/cpu_init.c    Flexbus ChipSelect and Mux pins setup
-- arch/powerpc/cpu/mpc8220/dramSetup.c   MPC8220 DDR SDRAM setup
-- arch/powerpc/cpu/mpc8220/fec.c	    MPC8220 FEC driver
-- arch/powerpc/cpu/mpc8220/i2c.c	    MPC8220 I2C driver
-- arch/powerpc/cpu/mpc8220/interrupts.c  interrupt support (not enable)
-- arch/powerpc/cpu/mpc8220/loadtask.c    load dma
-- arch/powerpc/cpu/mpc8220/speed.c	    system, pci, flexbus, pev, and cpu clock
-- arch/powerpc/cpu/mpc8220/traps.c	    exception
-- arch/powerpc/cpu/mpc8220/uart.c	    MPC8220 UART driver
-- arch/powerpc/cpu/mpc8220/Makefile	    Makefile
-- arch/powerpc/cpu/mpc8220/config.mk	    config make
-- arch/powerpc/cpu/mpc8220/fec_dma_task.S MPC8220 FEC multi-channel dma program
-- arch/powerpc/cpu/mpc8220/io.S	    io functions
-- arch/powerpc/cpu/mpc8220/start.S	    start up
-
-- include/mpc8220.h
-
-- include/asm-ppc/immap_8220.h
-
-- include/configs/Alaska8220.h
-
-
-1. SWITCH SETTINGS
-==================
-1.1 SW1: 0 - Boot from Socket Flash (AMD) or 1 - Onboard Flash (INTEL)
-    SW2: 0 - Select MPC8220 UART or 1 - Debug Card UART
-    SW3: unsed
-    SW4: 0 - 1284 or 1 - FEC1
-    SW5: 0 - PEV or 1 - FEC2
-
-
-2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
-===========================================
-2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and
-     linux kernel, you can customize it based on your system requirements:
-      DDR:	    0x00000000-0x1fffffff (max 512MB)
-      MBAR:	    0xf0000000-0xf0027fff (128KB)
-      CPLD:	    0xf1000000-0xf103ffff (256KB)
-      FPGA:	    0xf2000000-0xf203ffff (256KB)
-      Flash:	    0xfe000000-0xffffffff (max 32MB)
-
-3. DEFINITIONS AND COMPILATION
-==============================
-3.1 Explanation on NEW definitions in include/configs/alaska8220.h
-    CONFIG_MPC8220	    MPC8220 specific
-    CONFIG_ALASKA8220	    Alaska board specific
-    CONFIG_SYS_MPC8220_CLKIN	    Define Alaska Input Clock
-    CONFIG_PSC_CONSOLE	    Enable MPC8220 UART
-    CONFIG_EXTUART_CONSOLE  Enable External 16552 UART
-    CONFIG_SYS_AMD_BOOT	    To determine the u-boot is booted from AMD or Intel
-    CONFIG_SYS_MBAR		    MBAR base address
-    CONFIG_SYS_DEFAULT_MBAR	    Reset MBAR base address
-
-3.2 Compilation
-   export CROSS_COMPILE=cross-compile-prefix
-   cd u-boot-1-1-x
-   make distclean
-   make Alaska8220_config
-   make
-
-
-4. SCREEN DUMP
-==============
-4.1 Alaska MPC8220 board
-    Boot from AMD (NOTE: May not show exactly the same)
-
-U-Boot 1.1.1 (Sep 22 2004 - 22:14:41)
-
-CPU:   MPC8220 (JTAG ID 1640301d) at 300 MHz
-       Bus 120 MHz, CPU 300 MHz, PCI 30 MHz, VCO 480 MHz
-Board: Alaska MPC8220 Evaluation Board
-I2C:   93 kHz, ready
-DRAM:  256 MB
-Reserving 167k for U-Boot at: 0ffd6000
-FLASH: 16.5 MB
-*** Warning - bad CRC, using default environment
-
-In:    serial
-Out:   serial
-Err:   serial
-Net:   FEC ETHERNET
-=> flinfo
-
-Bank # 1: INTEL 28F128J3A
-  Size: 8 MB in 64 Sectors
-  Sector Start Addresses:
-    FE000000	  FE020000	FE040000      FE060000	    FE080000
-    FE0A0000	  FE0C0000	FE0E0000      FE100000	    FE120000
-    FE140000	  FE160000	FE180000      FE1A0000	    FE1C0000
-    FE1E0000	  FE200000	FE220000      FE240000	    FE260000
-    FE280000	  FE2A0000	FE2C0000      FE2E0000	    FE300000
-    FE320000	  FE340000	FE360000      FE380000	    FE3A0000
-    FE3C0000	  FE3E0000	FE400000      FE420000	    FE440000
-    FE460000	  FE480000	FE4A0000      FE4C0000	    FE4E0000
-    FE500000	  FE520000	FE540000      FE560000	    FE580000
-    FE5A0000	  FE5C0000	FE5E0000      FE600000	    FE620000
-    FE640000	  FE660000	FE680000      FE6A0000	    FE6C0000
-    FE6E0000	  FE700000	FE720000      FE740000	    FE760000
-    FE780000	  FE7A0000	FE7C0000      FE7E0000
-
-Bank # 2: INTEL 28F128J3A
-  Size: 8 MB in 64 Sectors
-  Sector Start Addresses:
-    FE800000	  FE820000	FE840000      FE860000	    FE880000
-    FE8A0000	  FE8C0000	FE8E0000      FE900000	    FE920000
-    FE940000	  FE960000	FE980000      FE9A0000	    FE9C0000
-    FE9E0000	  FEA00000	FEA20000      FEA40000	    FEA60000
-    FEA80000	  FEAA0000	FEAC0000      FEAE0000	    FEB00000
-    FEB20000	  FEB40000	FEB60000      FEB80000	    FEBA0000
-    FEBC0000	  FEBE0000	FEC00000      FEC20000	    FEC40000
-    FEC60000	  FEC80000	FECA0000      FECC0000	    FECE0000
-    FED00000	  FED20000	FED40000      FED60000	    FED80000
-    FEDA0000	  FEDC0000	FEDE0000      FEE00000	    FEE20000
-    FEE40000	  FEE60000	FEE80000      FEEA0000	    FEEC0000
-    FEEE0000	  FEF00000 (RO) FEF20000 (RO) FEF40000	    FEF60000
-    FEF80000	  FEFA0000	FEFC0000      FEFE0000 (RO)
-
-Bank # 3: AMD AMD29F040B
-  Size: 0 MB in 7 Sectors
-  Sector Start Addresses:
-    FFF00000 (RO) FFF10000 (RO) FFF20000 (RO) FFF30000	    FFF40000
-    FFF50000	  FFF60000
-
-Bank # 4: AMD AMD29F040B
-  Size: 0 MB in 1 Sectors
-  Sector Start Addresses:
-    FFF70000 (RO)
-=> bdinfo
-
-memstart    = 0xF0009800
-memsize	    = 0x10000000
-flashstart  = 0xFFF00000
-flashsize   = 0x01080000
-flashoffset = 0x00025000
-sramstart   = 0xF0020000
-sramsize    = 0x00008000
-bootflags   = 0x00000001
-intfreq	    =	 300 MHz
-busfreq	    =	 120 MHz
-inpfreq	    =	  30 MHz
-flbfreq	    =	  30 MHz
-pcifreq	    =	  30 MHz
-vcofreq	    =	 480 MHz
-pevfreq	    =	  81 MHz
-ethaddr	    = 00:E0:0C:BC:E0:60
-eth1addr    = 00:E0:0C:BC:E0:61
-IP addr	    = 192.162.1.2
-baudrate    = 115200 bps
-=> printenv
-bootargs=root=/dev/ram rw
-bootdelay=5
-baudrate=115200
-ethaddr=00:e0:0c:bc:e0:60
-eth1addr=00:e0:0c:bc:e0:61
-ipaddr=192.162.1.2
-serverip=192.162.1.1
-gatewayip=192.162.1.1
-netmask=255.255.255.0
-hostname=Alaska
-stdin=serial
-stdout=serial
-stderr=serial
-ethact=FEC ETHERNET
-
-Environment size: 268/65532 bytes
-=> setenv ipaddr 192.160.1.2
-=> setenv serverip 192.160.1.1
-=> setenv gatewayip 192.160.1.1
-=> saveenv
-Saving Environment to Flash...
-
-.
-Un-Protected 1 sectors
-Erasing Flash...
-Erasing sector	0 ...  done
-Erased 1 sectors
-Writing to Flash... done
-
-.
-Protected 1 sectors
-=> tftp 0x10000 linux.elf
-Using FEC ETHERNET device
-TFTP from server 192.160.1.1; our IP address is 192.160.1.2; sending through gateway 192.160.1.1
-Filename 'linux.elf'.
-Load address: 0x10000
-Loading: invalid RARP header
-#################################################################
-	 #################################################################
-	 #################################################################
-	 #################################################################
-	 #################################################################
-	 #################################################################
-	 #################################################################
-	 #################################################################
-	 ##################################################
-done
-Bytes transferred = 2917494 (2c8476 hex)
-=> bootelf
-Loading .text @ 0x00a00000 (23820 bytes)
-Loading .data @ 0x00a06000 (2752512 bytes)
-Clearing .bss @ 0x00ca6000 (12764 bytes)
-## Starting application at 0x00a00000 ...
-
-Collect some entropy from RAM........done
-loaded at:     00A00000 00CA91DC
-zimage at:     00A06A93 00AD7756
-initrd at:     00AD8000 00CA5565
-avail ram:     00CAA000 014AA000
-
-Linux/PPC load: ip=off console=ttyS0,115200
-Uncompressing Linux...done.
-Now booting the kernel
-Total memory in system: 256 MB
-Memory BAT mapping: BAT2=256Mb, BAT3=0Mb, residual: 0Mb
-Linux version 2.4.21-rc1 (r61688@bluesocks.sps.mot.com) (gcc version 3.3.1) #17 Wed Sep 8 11:49:16 CDT 2004
-Motorola Alaska port (C) 2003 Motorola, Inc.
-CPLD rev 3
-CPLD switches 0x1b
-Set Pin Mux for FEC1
-Set Pin Mux for FEC2
-Alaska Pin Multiplexing:
-Port Configuration Register 0 = 0
-Port Configuration Register 1 = 0
-Port Configuration Register 2 = 0
-Port Configuration Register 3 = 50000000
-Port Configuration Register 3 - PCI = 51400180
-Setup Alaska FPGA PIC:
-Interrupt Enable Register *(u32) = 0
-Interrupt Status Register = 2f0000
-Interrupt Enable Register in_be32 = 0
-Interrupt Status Register = 2f0000
-Interrupt Enable Register in_le32 = 0
-Interrupt Status Register = 2f00
-Interrupt Enable Register readl = 0
-Interrupt Status Register = 2f00
-Interrupt Enable Register = 0
-Interrupt Status Register = 2f0000
-Setup Alaska PCI Controller:
-On node 0 totalpages: 65536
-zone(0): 65536 pages.
-zone(1): 0 pages.
-zone(2): 0 pages.
-Kernel command line: ip=off console=ttyS0,115200
-Using XLB clock (120.00 MHz) to set up decrementer
-Calibrating delay loop... 199.88 BogoMIPS
-Memory: 254792k available (1476k kernel code, 708k data, 228k init, 0k highmem)
-Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
-Inode cache hash table entries: 16384 (order: 5, 131072 bytes)
-Mount cache hash table entries: 512 (order: 0, 4096 bytes)
-Buffer-cache hash table entries: 16384 (order: 4, 65536 bytes)
-Page-cache hash table entries: 65536 (order: 6, 262144 bytes)
-POSIX conformance testing by UNIFIX
-PCI: Probing PCI hardware
-PCI: (pcibios_init) Global-Hose = 0xc029d000
-Scanning bus 00
-Fixups for bus 00
-Bus scan for 00 returning with max=00
-PCI: (pcibios_init) finished pci_scan_bus(hose->first_busno = 0, hose->ops = c01a1a74, hose = c029d000)
-PCI: (pcibios_init) PCI Bus Count = 0 =?= Next Bus# = 1
-PCI: (pcibios_init@pci_fixup_irqs) finished machine dependent PCI interrupt routing!
-PCI: bridge rsrc 81000000..81ffffff (100), parent c01a7f88
-PCI: bridge rsrc 84000000..87ffffff (200), parent c01a7fa4
-PCI: (pcibios_init) finished allocating and assigning resources!
-initDma!
-Using 90 DMA buffer descriptors
-descUsed f0023600, descriptors f002360c freeSram f0024140
-unmask SDMA tasks: 0xf0008018 = 0x6f000000
-Linux NET4.0 for Linux 2.4
-Based upon Swansea University Computer Society NET3.039
-Initializing RT netlink socket
-Starting kswapd
-Journalled Block Device driver loaded
-JFFS version 1.0, (C) 1999, 2000  Axis Communications AB
-JFFS2 version 2.1. (C) 2001 Red Hat, Inc., designed by Axis Communications AB.
-pty: 256 Unix98 ptys configured
-tracek: Copyright (C) Motorola, 2003.
-Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
-ttyS00 at 0xf1001008 (irq = 73) is a ST16650
-ttyS01 at 0xf1001010 (irq = 74) is a ST16650
-elp-fpanel: Copyright (C) Motorola, 2003.
-fpanel: fpanelWait timeout
-elp-engine: Copyright (C) Motorola, 2003.
-Video disabled due to configuration switch 4
-Alpine 1284 driver: Copyright (C) Motorola, 2003.
-1284 disabled due to configuration switch 5
-Alpine USB driver: Copyright (C) Motorola, 2003.
-OK
-USB: Descriptor download completed OK
-enable_irq(41) unbalanced
-enable_irq(75) unbalanced
-elp-dmaram: Copyright (C) Motorola, 2003.
-Total memory in system: 256 MB
-elp_dmaram: offset is 0x10000000, size is 0
-Xicor NVRAM driver: Copyright (C) Motorola, 2003.
-elp-video: Copyright (C) Motorola, 2003.
-Video disabled due to configuration switch 4
-elp-pfm: Copyright (C) Motorola, 2003.
-paddle: Copyright (C) Motorola, 2001, present.
-RAMDISK driver initialized: 16 RAM disks of 12288K size 1024 blocksize
-loop: loaded (max 8 devices)
-PPP generic driver version 2.4.2
-PPP Deflate Compression module registered
-Uniform Multi-Platform E-IDE driver Revision: 7.00beta-2.4
-ide: Assuming 50MHz system bus speed for PIO modes; override with idebus=xx
-init_alaska_mtd: chip probing count 0
-cfi_cmdset_0001: Erase suspend on write enabled
-Using buffer write method
-init_alaska_mtd: bank1, name:ALASKA0, size:16777216bytes
-ALASKA flash0: Using Static image partition definition
-Creating 3 MTD partitions on "ALASKA0":
-0x00000000-0x00280000 : "kernel"
-0x00280000-0x00fe0000 : "user"
-0x00fe0000-0x01000000 : "signature"
-mgt_fec_module_init
-mgt_fec_init()
-mgt_fec_init
-mgt_init_fec_dev(0xc05f6000,0)
-dev c05f6000 fec_priv c05f6160 fec f0009000
-mgt_init_fec_dev(0xc05f6800,1)
-dev c05f6800 fec_priv c05f6960 fec f0009800
-NET4: Linux TCP/IP 1.0 for NET4.0
-IP Protocols: ICMP, UDP, TCP, IGMP
-IP: routing cache hash table of 2048 buckets, 16Kbytes
-TCP: Hash tables configured (established 16384 bind 32768)
-NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
-RAMDISK: Compressed image found at block 0
-Freeing initrd memory: 1845k freed
-JFFS: Trying to mount a non-mtd device.
-VFS: Mounted root (romfs filesystem) readonly.
-Freeing unused kernel memory: 228k init
-INIT: version 2.78 booting
-INIT: Entering runlevel: 1
-"Space, a great big place of unknown stuff."  -Dexter, for our MotD.
-[01/Jan/1970:00:00:01 +0000] boa: server version Boa/0.94.8.3
-[01/Jan/1970:00:00:01 +0000] boa: server built Sep  7 2004 at 17:40:55.
-[01/Jan/1970:00:00:01 +0000] boa: starting server pid=28, port 80
-Mounting flash filesystem, will take a minute...
-/etc/rc: line 30: /dev/lp0: No such devish-2.05b#
-sh-2.05b# ifup eth0
-client (v0.9.9-pre) started
-adapter index 2
-adapter hardware address 00:e0:0c:bc:e0:60
-execle'ing /usr/share/udhcpc/default.script
-/sbin/ifconfig eth0
-eth0	  Link encap:Ethernet  HWaddr 00:E0:0C:BC:E0:60
-	  BROADCAST MULTICAST  MTU:1500	 Metric:1
-	 mgt_fec_open
- Rfec request irq
-X fec_open: rcv_ring_size 8, xmt_ring_size 8
-packmgt_fec_open(): call netif_start_queue()
-ets:0 errors:0 dropped:0 overruns:0 frame:0
-	  TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
-	  collisions:0 txqueuelen:100
-	  RX bytes:0 (0.0 b)  TX bytes:0 (0.0 b)
-	  Base address:0x9000
-
-/sbin/ifconfig eth0 up
-entering raw listen mode
-Opening raw socket on ifindex 2
-adding option 0x35
-adding option 0x3d
-adding option 0x3c
-Sending discover...
-Waiting on select...
-unrelated/bogus packet
-Waiting on select...
-oooooh!!! got some!
-adding option 0x35
-adding option 0x3d
-adding option 0x3c
-adding option 0x32
-adding option 0x36
-Sending select for 163.12.48.146...
-Waiting on select...
-oooooh!!! got some!
-Waiting on select...
-oooooh!!! got some!
-Lease of 163.12.48.146 obtained, lease time 345600
-execle'ing /usr/share/udhcpc/default.script
-/sbin/ifconfig eth0 163.12.48.146 netmask 255.255.254.0
-/sbin/ifconfig eth0 up
-deleting routers
-/sbin/route del default
-/sbin/route add default gw 163.12.49.254 dev eth0
-adding dns 163.12.252.230
-adding dns 192.55.22.4
-adding dns 192.5.249.4
-entering none listen mode
-sh-2.05b#
-
-5. REPROGRAM U-BOOT
-===================
-5.1 Reprogram u-boot (boot from AMD)
-    1. Unprotect the boot sector
-    => protect off bank 3
-    2. Download new u-boot binary file
-    => tftp 0x10000 u-boot.bin
-    3. Erase bootsector (max 7 sectors)
-    => erase 0xfff00000 0xfff6ffff
-    4. Program the u-boot to flash
-    => cp.b 0x10000 0xfff00000
-    5. Reset for the new u-boot to take place
-    => reset
-
-5.2 Reprogram u-boot (boot from AMD program at INTEL)
-    1. Unprotect the boot sector
-    => protect off bank 2
-    2. Download new u-boot binary file
-    => tftp 0x10000 u-boot.bin
-    3. Erase bootsector (max 7 sectors)
-    => erase 0xfef00000 0xfefdffff
-    4. Program the u-boot to flash
-    => cp.b 0x10000 0xfef00000
-    5. Reset for the new u-boot to take place
-    => reset
-
-5.3 Reprogram u-boot (boot from INTEL)
-    1. Unprotect the boot sector
-    => protect off bank 4
-    2. Download new u-boot binary file
-    => tftp 0x10000 u-boot.bin
-    3. Erase bootsector (max 7 sectors)
-    => erase 0xfff00000 0xfffdffff
-    4. Program the u-boot to flash
-    => cp.b 0x10000 0xfff00000
-    5. Reset for the new u-boot to take place
-    => reset
-
-5.4 Reprogram u-boot (boot from INTEL program at AMD)
-    1. Unprotect the boot sector
-    => protect off bank 1
-    2. Download new u-boot binary file
-    => tftp 0x10000 u-boot.bin
-    3. Erase bootsector (max 7 sectors)
-    => erase 0xfe080000 0xfe0effff
-    4. Program the u-boot to flash
-    => cp.b 0x10000 0xfe080000
-    5. Reset for the new u-boot to take place
-    => reset
diff --git a/board/alaska/alaska.c b/board/alaska/alaska.c
deleted file mode 100644
index 89c1abd..0000000
--- a/board/alaska/alaska.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale Inc.
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8220.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-
-void setupBat (ulong size)
-{
-	ulong batu, batl;
-	int blocksize = 0;
-
-	/* Flash 0 */
-#if defined (CONFIG_SYS_AMD_BOOT)
-	batu = CONFIG_SYS_FLASH0_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
-#else
-	batu = CONFIG_SYS_FLASH0_BASE | BATU_BL_16M | BPP_RW | BPP_RX;
-#endif
-	batl = CONFIG_SYS_FLASH0_BASE | 0x22;
-	write_bat (IBAT0, batu, batl);
-	write_bat (DBAT0, batu, batl);
-
-	/* Flash 1 */
-#if defined (CONFIG_SYS_AMD_BOOT)
-	batu = CONFIG_SYS_FLASH1_BASE | BATU_BL_16M | BPP_RW | BPP_RX;
-#else
-	batu = CONFIG_SYS_FLASH1_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
-#endif
-	batl = CONFIG_SYS_FLASH1_BASE | 0x22;
-	write_bat (IBAT1, batu, batl);
-	write_bat (DBAT1, batu, batl);
-
-	/* CPLD */
-	batu = CONFIG_SYS_CPLD_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
-	batl = CONFIG_SYS_CPLD_BASE | 0x22;
-	write_bat (IBAT2, 0, 0);
-	write_bat (DBAT2, batu, batl);
-
-	/* FPGA */
-	batu = CONFIG_SYS_FPGA_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
-	batl = CONFIG_SYS_FPGA_BASE | 0x22;
-	write_bat (IBAT3, 0, 0);
-	write_bat (DBAT3, batu, batl);
-
-	/* MBAR - Data only */
-	batu = CONFIG_SYS_MBAR | BPP_RW | BPP_RX;
-	batl = CONFIG_SYS_MBAR | 0x22;
-	mtspr (IBAT4L, 0);
-	mtspr (IBAT4U, 0);
-	mtspr (DBAT4L, batl);
-	mtspr (DBAT4U, batu);
-
-	/* MBAR - SRAM */
-	batu = CONFIG_SYS_SRAM_BASE | BPP_RW | BPP_RX;
-	batl = CONFIG_SYS_SRAM_BASE | 0x42;
-	mtspr (IBAT5L, batl);
-	mtspr (IBAT5U, batu);
-	mtspr (DBAT5L, batl);
-	mtspr (DBAT5U, batu);
-
-	if (size <= 0x800000)	/* 8MB */
-		blocksize = BATU_BL_8M;
-	else if (size <= 0x1000000)	/* 16MB */
-		blocksize = BATU_BL_16M;
-	else if (size <= 0x2000000)	/* 32MB */
-		blocksize = BATU_BL_32M;
-	else if (size <= 0x4000000)	/* 64MB */
-		blocksize = BATU_BL_64M;
-	else if (size <= 0x8000000)	/* 128MB */
-		blocksize = BATU_BL_128M;
-	else if (size <= 0x10000000)	/* 256MB */
-		blocksize = BATU_BL_256M;
-
-	/* Memory */
-	batu = CONFIG_SYS_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
-	batl = CONFIG_SYS_SDRAM_BASE | 0x42;
-	mtspr (IBAT6L, batl);
-	mtspr (IBAT6U, batu);
-	mtspr (DBAT6L, batl);
-	mtspr (DBAT6U, batu);
-
-	/* memory size is less than 256MB */
-	if (size <= 0x10000000) {
-		/* Nothing */
-		batu = 0;
-		batl = 0;
-	} else {
-		size -= 0x10000000;
-		if (size <= 0x800000)	/* 8MB */
-			blocksize = BATU_BL_8M;
-		else if (size <= 0x1000000)	/* 16MB */
-			blocksize = BATU_BL_16M;
-		else if (size <= 0x2000000)	/* 32MB */
-			blocksize = BATU_BL_32M;
-		else if (size <= 0x4000000)	/* 64MB */
-			blocksize = BATU_BL_64M;
-		else if (size <= 0x8000000)	/* 128MB */
-			blocksize = BATU_BL_128M;
-		else if (size <= 0x10000000)	/* 256MB */
-			blocksize = BATU_BL_256M;
-
-		batu = (CONFIG_SYS_SDRAM_BASE +
-			0x10000000) | blocksize | BPP_RW | BPP_RX;
-		batl = (CONFIG_SYS_SDRAM_BASE + 0x10000000) | 0x42;
-	}
-
-	mtspr (IBAT7L, batl);
-	mtspr (IBAT7U, batu);
-	mtspr (DBAT7L, batl);
-	mtspr (DBAT7U, batu);
-}
-
-phys_size_t initdram (int board_type)
-{
-	ulong size;
-
-	size = dramSetup ();
-
-/* if iCache ad dCache is defined */
-#if defined(CONFIG_CMD_CACHE)
-/*    setupBat(size);*/
-#endif
-
-	return size;
-}
-
-int checkboard (void)
-{
-	puts ("Board: Alaska MPC8220 Evaluation Board\n");
-
-	return 0;
-}
diff --git a/board/alaska/flash.c b/board/alaska/flash.c
deleted file mode 100644
index 977822a..0000000
--- a/board/alaska/flash.c
+++ /dev/null
@@ -1,945 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
-
-/* Board support for 1 or 2 flash devices */
-#define FLASH_PORT_WIDTH8
-
-typedef unsigned char FLASH_PORT_WIDTH;
-typedef volatile unsigned char FLASH_PORT_WIDTHV;
-
-#define SWAP(x)         (x)
-
-/* Intel-compatible flash ID */
-#define INTEL_COMPAT    0x89
-#define INTEL_ALT       0xB0
-
-/* Intel-compatible flash commands */
-#define INTEL_PROGRAM   0x10
-#define INTEL_ERASE     0x20
-#define INTEL_CLEAR     0x50
-#define INTEL_LOCKBIT   0x60
-#define INTEL_PROTECT   0x01
-#define INTEL_STATUS    0x70
-#define INTEL_READID    0x90
-#define INTEL_CONFIRM   0xD0
-#define INTEL_RESET     0xFF
-
-/* Intel-compatible flash status bits */
-#define INTEL_FINISHED  0x80
-#define INTEL_OK        0x80
-
-#define FPW             FLASH_PORT_WIDTH
-#define FPWV            FLASH_PORT_WIDTHV
-
-#define FLASH_CYCLE1    0x0555
-#define FLASH_CYCLE2    0x02aa
-
-#define WR_BLOCK        0x20
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static int write_data_block (flash_info_t * info, ulong src, ulong dest);
-static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-static void flash_sync_real_protect (flash_info_t * info);
-static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
-static unsigned char same_chip_banks (int bank1, int bank2);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	int i;
-	ulong size = 0;
-	ulong fsize = 0;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		memset (&flash_info[i], 0, sizeof (flash_info_t));
-
-		switch (i) {
-		case 0:
-			flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
-					&flash_info[i]);
-			flash_get_offsets (CONFIG_SYS_FLASH1_BASE, &flash_info[i]);
-			break;
-		case 1:
-			flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
-					&flash_info[i]);
-			fsize = CONFIG_SYS_FLASH1_BASE + flash_info[i - 1].size;
-			flash_get_offsets (fsize, &flash_info[i]);
-			break;
-		case 2:
-			flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
-					&flash_info[i]);
-			flash_get_offsets (CONFIG_SYS_FLASH0_BASE, &flash_info[i]);
-			break;
-		case 3:
-			flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
-					&flash_info[i]);
-			fsize = CONFIG_SYS_FLASH0_BASE + flash_info[i - 1].size;
-			flash_get_offsets (fsize, &flash_info[i]);
-			break;
-		default:
-			panic ("configured to many flash banks!\n");
-			break;
-		}
-		size += flash_info[i].size;
-
-		/* get the h/w and s/w protection status in sync */
-		flash_sync_real_protect(&flash_info[i]);
-	}
-
-	/* Protect monitor and environment sectors
-	 */
-#if defined (CONFIG_SYS_AMD_BOOT)
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_MONITOR_BASE,
-		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
-		       &flash_info[2]);
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_INTEL_BASE,
-		       CONFIG_SYS_INTEL_BASE + monitor_flash_len - 1,
-		       &flash_info[1]);
-#else
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_MONITOR_BASE,
-		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
-		       &flash_info[3]);
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_AMD_BASE,
-		       CONFIG_SYS_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
-#endif
-
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV1_ADDR,
-		       CONFIG_ENV1_ADDR + CONFIG_ENV1_SIZE - 1, &flash_info[1]);
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR,
-		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[3]);
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN)
-		return;
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * PHYS_AMD_SECT_SIZE);
-			info->protect[i] = 0;
-		}
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE);
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_INTEL:
-		printf ("INTEL ");
-		break;
-	case FLASH_MAN_AMD:
-		printf ("AMD ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F128J3A:
-		printf ("28F128J3A\n");
-		break;
-
-	case FLASH_AM040:
-		printf ("AMD29F040B\n");
-		break;
-
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i], info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-	return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
-	FPWV value;
-	static int amd = 0;
-
-	/* Write auto select command: read Manufacturer ID */
-	/* Write auto select command sequence and test FLASH answer */
-	addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
-	__asm__ ("sync");
-	addr[FLASH_CYCLE2] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
-	__asm__ ("sync");
-	addr[FLASH_CYCLE1] = (FPW) 0x00900090;	/* selects Intel or AMD */
-	__asm__ ("sync");
-
-	udelay (100);
-
-	switch (addr[0] & 0xff) {
-
-	case (uchar) AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		value = addr[1];
-		break;
-
-	case (uchar) INTEL_MANUFACT:
-		info->flash_id = FLASH_MAN_INTEL;
-		value = addr[2];
-		break;
-
-	default:
-		printf ("unknown\n");
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-		return (0);	/* no or unknown flash  */
-	}
-
-	switch (value) {
-
-	case (FPW) INTEL_ID_28F128J3A:
-		info->flash_id += FLASH_28F128J3A;
-		info->sector_count = 64;
-		info->size = 0x00800000;	/* => 16 MB     */
-		break;
-
-	case (FPW) AMD_ID_LV040B:
-		info->flash_id += FLASH_AM040;
-		if (amd == 0) {
-			info->sector_count = 7;
-			info->size = 0x00070000;	/* => 448 KB     */
-			amd = 1;
-		} else {
-			/* for Environment settings */
-			info->sector_count = 1;
-			info->size = PHYS_AMD_SECT_SIZE;	/* => 64 KB     */
-			amd = 0;
-		}
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		break;
-	}
-
-	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	}
-
-	if (value == (FPW) INTEL_ID_28F128J3A)
-		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-	else
-		addr[0] = (FPW) 0x00F000F0;	/* restore read mode */
-
-	return (info->size);
-}
-
-
-/*
- * This function gets the u-boot flash sector protection status
- * (flash_info_t.protect[]) in sync with the sector protection
- * status stored in hardware.
- */
-static void flash_sync_real_protect (flash_info_t * info)
-{
-	int i;
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F128J3A:
-		for (i = 0; i < info->sector_count; ++i) {
-			info->protect[i] = intel_sector_protected(info, i);
-		}
-		break;
-	case FLASH_AM040:
-	default:
-		/* no h/w protect support */
-		break;
-	}
-}
-
-
-/*
- * checks if "sector" in bank "info" is protected. Should work on intel
- * strata flash chips 28FxxxJ3x in 8-bit mode.
- * Returns 1 if sector is protected (or timed-out while trying to read
- * protection status), 0 if it is not.
- */
-static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
-{
-	FPWV *addr;
-	FPWV *lock_conf_addr;
-	ulong start;
-	unsigned char ret;
-
-	/*
-	 * first, wait for the WSM to be finished. The rationale for
-	 * waiting for the WSM to become idle for at most
-	 * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
-	 * because of: (1) erase, (2) program or (3) lock bit
-	 * configuration. So we just wait for the longest timeout of
-	 * the (1)-(3), i.e. the erase timeout.
-	 */
-
-	/* wait at least 35ns (W12) before issuing Read Status Register */
-	udelay(1);
-	addr = (FPWV *) info->start[sector];
-	*addr = (FPW) INTEL_STATUS;
-
-	start = get_timer (0);
-	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			*addr = (FPW) INTEL_RESET; /* restore read mode */
-			printf("WSM busy too long, can't get prot status\n");
-			return 1;
-		}
-	}
-
-	/* issue the Read Identifier Codes command */
-	*addr = (FPW) INTEL_READID;
-
-	/* wait at least 35ns (W12) before reading */
-	udelay(1);
-
-	/* Intel example code uses offset of 4 for 8-bit flash */
-	lock_conf_addr = (FPWV *) info->start[sector] + 4;
-	ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
-
-	/* put flash back in read mode */
-	*addr = (FPW) INTEL_RESET;
-
-	return ret;
-}
-
-
-/*
- * Checks if "bank1" and "bank2" are on the same chip.  Returns 1 if they
- * are and 0 otherwise.
- */
-static unsigned char same_chip_banks (int bank1, int bank2)
-{
-	unsigned char same_chip[CONFIG_SYS_MAX_FLASH_BANKS][CONFIG_SYS_MAX_FLASH_BANKS] = {
-		{1, 1, 0, 0},
-		{1, 1, 0, 0},
-		{0, 0, 1, 1},
-		{0, 0, 1, 1}
-	};
-	return same_chip[bank1][bank2];
-}
-
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, prot, sect;
-	ulong type, start;
-	int rcode = 0, intel = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN)
-			printf ("- missing\n");
-		else
-			printf ("- no sectors to erase\n");
-		return 1;
-	}
-
-	type = (info->flash_id & FLASH_VENDMASK);
-	if ((type != FLASH_MAN_INTEL)) {
-		type = (info->flash_id & FLASH_VENDMASK);
-		if ((type != FLASH_MAN_AMD)) {
-			printf ("Can't erase unknown flash type %08lx - aborted\n",
-				info->flash_id);
-			return 1;
-		}
-	}
-
-	if (type == FLASH_MAN_INTEL)
-		intel = 1;
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
-	} else {
-		printf ("\n");
-	}
-
-	start = get_timer (0);
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			FPWV *addr = (FPWV *) (info->start[sect]);
-			FPW status;
-
-			printf ("Erasing sector %2d ... ", sect);
-
-			/* arm simple, non interrupt dependent timer */
-			start = get_timer (0);
-
-			if (intel) {
-				*addr = (FPW) 0x00500050;	/* clear status register */
-				*addr = (FPW) 0x00200020;	/* erase setup */
-				*addr = (FPW) 0x00D000D0;	/* erase confirm */
-			} else {
-				FPWV *base;	/* first address in bank */
-
-				base = (FPWV *) (CONFIG_SYS_AMD_BASE);
-				base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
-				base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
-				base[FLASH_CYCLE1] = (FPW) 0x00800080;	/* erase mode */
-				base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
-				base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
-				*addr = (FPW) 0x00300030;	/* erase sector */
-			}
-
-			while (((status =
-				 *addr) & (FPW) 0x00800080) !=
-			       (FPW) 0x00800080) {
-				if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf ("Timeout\n");
-					if (intel) {
-						*addr = (FPW) 0x00B000B0;	/* suspend erase     */
-						*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
-					} else
-						*addr = (FPW) 0x00F000F0;	/* reset to read mode */
-
-					rcode = 1;
-					break;
-				}
-			}
-
-			if (intel) {
-				*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
-				*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
-			} else
-				*addr = (FPW) 0x00F000F0;	/* reset to read mode */
-
-			printf (" done\n");
-		}
-	}
-	if (flag)
-		enable_interrupts();
-
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return 4;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:
-	    {
-		FPW data = 0;	/* 16 or 32 bit word, matches flash bus width */
-		int bytes;	/* number of bytes to program in current word */
-		int left;	/* number of bytes left to program */
-		int i, res;
-
-		for (left = cnt, res = 0;
-		     left > 0 && res == 0;
-		     addr += sizeof (data), left -=
-		     sizeof (data) - bytes) {
-
-			bytes = addr & (sizeof (data) - 1);
-			addr &= ~(sizeof (data) - 1);
-
-			/* combine source and destination data so can program
-			 * an entire word of 16 or 32 bits
-			 */
-			for (i = 0; i < sizeof (data); i++) {
-				data <<= 8;
-				if (i < bytes || i - bytes >= left)
-					data += *((uchar *) addr + i);
-				else
-					data += *src++;
-			}
-
-			res = write_word_amd (info, (FPWV *) addr,
-					      data);
-		}
-		return res;
-	    }		/* case FLASH_MAN_AMD */
-
-	case FLASH_MAN_INTEL:
-	    {
-		ulong cp, wp;
-		FPW data;
-		int count, i, l, rc, port_width;
-
-		/* get lower word aligned address */
-		wp = addr;
-		port_width = 1;
-
-		/*
-		 * handle unaligned start bytes
-		 */
-		if ((l = addr - wp) != 0) {
-			data = 0;
-			for (i = 0, cp = wp; i < l; ++i, ++cp) {
-				data = (data << 8) | (*(uchar *) cp);
-			}
-
-			for (; i < port_width && cnt > 0; ++i) {
-				data = (data << 8) | *src++;
-				--cnt;
-				++cp;
-			}
-
-			for (; cnt == 0 && i < port_width; ++i, ++cp)
-				data = (data << 8) | (*(uchar *) cp);
-
-			if ((rc =
-			     write_data (info, wp, SWAP (data))) != 0)
-				return (rc);
-			wp += port_width;
-		}
-
-		if (cnt > WR_BLOCK) {
-			/*
-			 * handle word aligned part
-			 */
-			count = 0;
-			while (cnt >= WR_BLOCK) {
-
-				if ((rc =
-				     write_data_block (info,
-						       (ulong) src,
-						       wp)) != 0)
-					return (rc);
-
-				wp += WR_BLOCK;
-				src += WR_BLOCK;
-				cnt -= WR_BLOCK;
-
-				if (count++ > 0x800) {
-					spin_wheel ();
-					count = 0;
-				}
-			}
-		}
-
-		if (cnt < WR_BLOCK) {
-			/*
-			 * handle word aligned part
-			 */
-			count = 0;
-			while (cnt >= port_width) {
-				data = 0;
-				for (i = 0; i < port_width; ++i)
-					data = (data << 8) | *src++;
-
-				if ((rc =
-				     write_data (info, wp,
-						 SWAP (data))) != 0)
-					return (rc);
-
-				wp += port_width;
-				cnt -= port_width;
-				if (count++ > 0x800) {
-					spin_wheel ();
-					count = 0;
-				}
-			}
-		}
-
-		if (cnt == 0)
-			return (0);
-
-		/*
-		 * handle unaligned tail bytes
-		 */
-		data = 0;
-		for (i = 0, cp = wp; i < port_width && cnt > 0;
-		     ++i, ++cp) {
-			data = (data << 8) | *src++;
-			--cnt;
-		}
-
-		for (; i < port_width; ++i, ++cp)
-			data = (data << 8) | (*(uchar *) cp);
-
-		return (write_data (info, wp, SWAP (data)));
-	    }		/* case FLASH_MAN_INTEL */
-
-	}			/* switch */
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
-	FPWV *addr = (FPWV *) dest;
-	ulong start;
-	int flag, rc = 0;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		printf ("not erased at %08lx (%lx)\n", (ulong)addr, (ulong)*addr);
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	*addr = (FPW) 0x00400040;	/* write setup */
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer (0);
-
-	/* wait while polling the status register */
-	while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			rc = 1;
-			goto OUT;
-		}
-	}
-
-OUT:
-	*addr = (FPW)0x00FF00FF;	/* restore read mode */
-
-	if (flag)
-		enable_interrupts();
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data_block (flash_info_t * info, ulong src, ulong dest)
-{
-	FPWV *srcaddr = (FPWV *) src;
-	FPWV *dstaddr = (FPWV *) dest;
-	ulong start;
-	int flag, i, rc = 0;
-
-	/* Check if Flash is (sufficiently) erased */
-	for (i = 0; i < WR_BLOCK; i++)
-		if ((*dstaddr++ & 0xff) != 0xff) {
-			printf ("not erased at %08lx (%lx)\n",
-				(ulong)dstaddr, (ulong)*dstaddr);
-			return (2);
-		}
-
-	dstaddr = (FPWV *) dest;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	*dstaddr = (FPW) 0x00e800e8;	/* write block setup */
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer (0);
-
-	/* wait while polling the status register */
-	while ((*dstaddr & (FPW)0x00800080) != (FPW)0x00800080) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			rc = 1;
-			goto OUT;
-		}
-	}
-
-	*dstaddr = (FPW) 0x001f001f;	/* write 32 to buffer */
-	for (i = 0; i < WR_BLOCK; i++)
-		*dstaddr++ = *srcaddr++;
-
-	dstaddr -= 1;
-	*dstaddr = (FPW) 0x00d000d0;	/* write 32 to buffer */
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer (0);
-
-	/* wait while polling the status register */
-	while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			*dstaddr = (FPW) 0x00FF00FF;	/* restore read mode */
-			return (1);
-		}
-	}
-
-OUT:
-	*dstaddr = (FPW)0x00FF00FF;	/* restore read mode */
-	if (flag)
-		enable_interrupts();
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
-{
-	ulong start;
-	int flag;
-	int res = 0;		/* result, assume success */
-	FPWV *base;		/* first address in flash bank */
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*dest & data) != data) {
-		return (2);
-	}
-
-	base = (FPWV *) (CONFIG_SYS_AMD_BASE);
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
-	base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
-	base[FLASH_CYCLE1] = (FPW) 0x00A000A0;	/* selects program mode */
-
-	*dest = data;		/* start programming the data */
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	start = get_timer (0);
-
-	/* data polling for D7 */
-	while (res == 0
-	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			*dest = (FPW) 0x00F000F0;	/* reset bank */
-			res = 1;
-		}
-	}
-
-	return (res);
-}
-
-void inline spin_wheel (void)
-{
-	static int p = 0;
-	static char w[] = "\\/-";
-
-	printf ("\010%c", w[p]);
-	(++p == 3) ? (p = 0) : 0;
-}
-
-/*-----------------------------------------------------------------------
- * Set/Clear sector's lock bit, returns:
- * 0 - OK
- * 1 - Error (timeout, voltage problems, etc.)
- */
-int flash_real_protect (flash_info_t * info, long sector, int prot)
-{
-	ulong start;
-	int i, j;
-	int curr_bank;
-	int bank;
-	int rc = 0;
-	FPWV *addr = (FPWV *) (info->start[sector]);
-	int flag = disable_interrupts ();
-
-	/*
-	 * 29F040B AMD flash does not support software protection/unprotection,
-	 * the only way to protect the AMD flash is marked it as prot bit.
-	 * This flash only support hardware protection, by supply or not supply
-	 * 12vpp to the flash
-	 */
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
-		info->protect[sector] = prot;
-
-		return 0;
-	}
-
-	*addr = INTEL_CLEAR;	/* Clear status register    */
-	if (prot) {		/* Set sector lock bit      */
-		*addr = INTEL_LOCKBIT;	/* Sector lock bit          */
-		*addr = INTEL_PROTECT;	/* set                      */
-	} else {		/* Clear sector lock bit    */
-		*addr = INTEL_LOCKBIT;	/* All sectors lock bits    */
-		*addr = INTEL_CONFIRM;	/* clear                    */
-	}
-
-	start = get_timer (0);
-
-	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
-			printf ("Flash lock bit operation timed out\n");
-			rc = 1;
-			break;
-		}
-	}
-
-	if (*addr != INTEL_OK) {
-		printf ("Flash lock bit operation failed at %08X, CSR=%08X\n",
-			(uint) addr, (uint) * addr);
-		rc = 1;
-	}
-
-	if (!rc)
-		info->protect[sector] = prot;
-
-	/*
-	 * Clear lock bit command clears all sectors lock bits, so
-	 * we have to restore lock bits of protected sectors.
-	 */
-	if (!prot) {
-		/*
-		 * re-locking must be done for all banks that belong on one
-		 * FLASH chip, as all the sectors on the chip were unlocked
-		 * by INTEL_LOCKBIT/INTEL_CONFIRM commands. (let's hope
-		 * that banks never span chips, in particular chips which
-		 * support h/w protection differently).
-		 */
-
-		/* find the current bank number */
-		curr_bank = CONFIG_SYS_MAX_FLASH_BANKS + 1;
-		for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; ++j) {
-			if (&flash_info[j] == info) {
-				curr_bank = j;
-			}
-		}
-		if (curr_bank == CONFIG_SYS_MAX_FLASH_BANKS + 1) {
-			printf("Error: can't determine bank number!\n");
-		}
-
-		for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
-			if (!same_chip_banks(curr_bank, bank)) {
-				continue;
-			}
-			info = &flash_info[bank];
-			for (i = 0; i < info->sector_count; i++) {
-				if (info->protect[i]) {
-					start = get_timer (0);
-					addr = (FPWV *) (info->start[i]);
-					*addr = INTEL_LOCKBIT;	/* Sector lock bit  */
-					*addr = INTEL_PROTECT;	/* set              */
-					while ((*addr & INTEL_FINISHED) !=
-					       INTEL_FINISHED) {
-						if (get_timer (start) >
-						    CONFIG_SYS_FLASH_UNLOCK_TOUT) {
-							printf ("Flash lock bit operation timed out\n");
-							rc = 1;
-							break;
-						}
-					}
-				}
-			}
-		}
-
-		/*
-		 * get the s/w sector protection status in sync with the h/w,
-		 * in case something went wrong during the re-locking.
-		 */
-		flash_sync_real_protect(info); /* resets flash to read  mode */
-	}
-
-	if (flag)
-		enable_interrupts ();
-
-	*addr = INTEL_RESET;	/* Reset to read array mode */
-
-	return rc;
-}
diff --git a/board/armltd/vexpress/Makefile b/board/armltd/vexpress/Makefile
index 8749590..6719f3d 100644
--- a/board/armltd/vexpress/Makefile
+++ b/board/armltd/vexpress/Makefile
@@ -25,7 +25,7 @@
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= ca9x4_ct_vxp.o
+COBJS	:= vexpress_common.o
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c b/board/armltd/vexpress/vexpress_common.c
similarity index 89%
rename from board/armltd/vexpress/ca9x4_ct_vxp.c
rename to board/armltd/vexpress/vexpress_common.c
index d5e109e..2c54869 100644
--- a/board/armltd/vexpress/ca9x4_ct_vxp.c
+++ b/board/armltd/vexpress/vexpress_common.c
@@ -45,8 +45,7 @@
 static ulong timestamp;
 static ulong lastdec;
 
-static struct wdt *wdt_base = (struct wdt *)WDT_BASE;
-static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
+static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
 static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
 
 static void flash__init(void);
@@ -166,20 +165,38 @@
 	 */
 	writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
 	writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
-	writel(SYSTIMER_EN | SYSTIMER_32BIT | \
-	       readl(&systimer_base->timer0control), \
+	writel(SYSTIMER_EN | SYSTIMER_32BIT |
+	       readl(&systimer_base->timer0control),
 	       &systimer_base->timer0control);
 
 	reset_timer_masked();
 }
 
+int v2m_cfg_write(u32 devfn, u32 data)
+{
+	/* Configuration interface broken? */
+	u32 val;
+
+	devfn |= SYS_CFG_START | SYS_CFG_WRITE;
+
+	val = readl(V2M_SYS_CFGSTAT);
+	writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
+
+	writel(data, V2M_SYS_CFGDATA);
+	writel(devfn, V2M_SYS_CFGCTRL);
+
+	do {
+		val = readl(V2M_SYS_CFGSTAT);
+	} while (val == 0);
+
+	return !!(val & SYS_CFG_ERR);
+}
+
 /* Use the ARM Watchdog System to cause reset */
 void reset_cpu(ulong addr)
 {
-	writeb(WDT_EN, &wdt_base->wdogcontrol);
-	writel(WDT_RESET_LOAD, &wdt_base->wdogload);
-	while (1)
-		;
+	if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
+		printf("Unable to reboot\n");
 }
 
 /*
@@ -251,7 +268,7 @@
 	return get_timer(0);
 }
 
-ulong get_tbclk (void)
+ulong get_tbclk(void)
 {
 	return (ulong)CONFIG_SYS_HZ;
 }
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index 3aa394a..8d3fc75 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -30,6 +30,7 @@
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
+#include <atmel_mci.h>
 
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 # include <net.h>
@@ -143,6 +144,15 @@
 }
 #endif
 
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI);
+}
+#endif
+
 int board_early_init_f(void)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
@@ -157,18 +167,6 @@
 
 int board_init(void)
 {
-#ifdef CONFIG_AT91SAM9G20EK_2MMC
-	/* arch number of AT91SAM9G20EK_2MMC-Board */
-	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK_2MMC;
-#else
-#ifdef CONFIG_AT91SAM9G20EK
-	/* arch number of AT91SAM9G20EK-Board */
-	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK;
-#else
-	/* arch number of AT91SAM9260EK-Board */
-	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
-#endif
-#endif
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
diff --git a/board/alaska/Makefile b/board/atmel/at91sam9n12ek/Makefile
similarity index 69%
copy from board/alaska/Makefile
copy to board/atmel/at91sam9n12ek/Makefile
index a21f851..3aa67d5 100644
--- a/board/alaska/Makefile
+++ b/board/atmel/at91sam9n12ek/Makefile
@@ -1,7 +1,15 @@
 #
-# (C) Copyright 2003-2006
+# (C) Copyright 2003-2008
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2013
+# Josh Wu <josh.wu@atmel.com>
+# Atmel corporation <www.atmel.com>
+#
 # See file CREDITS for list of people who contributed to this
 # project.
 #
@@ -12,7 +20,7 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
@@ -25,14 +33,14 @@
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= $(BOARD).o flash.o
+COBJS-y	+= at91sam9n12ek.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
 
 #########################################################################
 
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
new file mode 100644
index 0000000..8752794
--- /dev/null
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -0,0 +1,228 @@
+/*
+ * (C) Copyright 2013 Atmel Corporation
+ * Josh Wu <josh.wu@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9x5_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+#ifdef CONFIG_NAND_ATMEL
+static void at91sam9n12ek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Assign CS3 to NAND/SmartMedia Interface */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+	/* Configure databus */
+	csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
+	/* Configure IO drive */
+	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		AT91_SMC_MODE_DBW_8 |
+#endif
+		AT91_SMC_MODE_TDF_CYCLE(1),
+		&smc->cs[3].mode);
+
+	/* Configure RDY/BSY pin */
+	at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
+
+	/* Configure ENABLE pin for NandFlash */
+	at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
+
+	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);    /* NAND OE */
+	at91_set_a_periph(AT91_PIO_PORTD, 1, 1);    /* NAND WE */
+	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);    /* ALE */
+	at91_set_a_periph(AT91_PIO_PORTD, 3, 1);    /* CLE */
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col = 480,
+	.vl_row = 272,
+	.vl_clk = 9000000,
+	.vl_bpix = LCD_BPP,
+	.vl_sync = 0,
+	.vl_tft = 1,
+	.vl_hsync_len = 5,
+	.vl_left_margin = 8,
+	.vl_right_margin = 43,
+	.vl_vsync_len = 10,
+	.vl_upper_margin = 4,
+	.vl_lower_margin = 12,
+	.mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 25, 0);	/* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 25, 1);	/* power down */
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf("%s\n", U_BOOT_VERSION);
+	lcd_printf("ATMEL Corp\n");
+	lcd_printf("at91@atmel.com\n");
+	lcd_printf("%s CPU at %s MHz\n",
+		ATMEL_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+	lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 0:
+		at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
+		break;
+	case 1:
+		at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
+		break;
+	}
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 0:
+		at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
+		break;
+	case 1:
+		at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
+		break;
+	}
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	/* Enable clocks for all PIOs */
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer);
+
+	at91_seriald_hw_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+	at91sam9n12ek_nand_hw_init();
+#endif
+
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 0);
+#endif
+
+#ifdef CONFIG_LCD
+	at91_lcd_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+					CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
diff --git a/board/alaska/Makefile b/board/atmel/sama5d3xek/Makefile
similarity index 71%
copy from board/alaska/Makefile
copy to board/atmel/sama5d3xek/Makefile
index a21f851..45d24d2 100644
--- a/board/alaska/Makefile
+++ b/board/atmel/sama5d3xek/Makefile
@@ -1,7 +1,14 @@
 #
-# (C) Copyright 2003-2006
+# (C) Copyright 2003-2008
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2013
+# Bo Shen <voice.shen@atmel.com>
+#
 # See file CREDITS for list of people who contributed to this
 # project.
 #
@@ -12,7 +19,7 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
@@ -25,14 +32,14 @@
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= $(BOARD).o flash.o
+COBJS-y += sama5d3xek.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
 
 #########################################################################
 
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
new file mode 100644
index 0000000..541296d
--- /dev/null
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -0,0 +1,275 @@
+/*
+ * Copyright (C) 2012 - 2013 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#include <atmel_mci.h>
+#include <net.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_NAND_ATMEL
+void sama5d3xek_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
+	       AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
+	       AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+	       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+	       AT91_SMC_MODE_DBW_8 |
+#endif
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d3xek_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
+	at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
+	at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+static void sama5d3xek_mci_hw_init(void)
+{
+	at91_mci_hw_init();
+
+	at91_set_pio_output(AT91_PIO_PORTB, 10, 0);	/* MCI0 Power */
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col = 800,
+	.vl_row = 480,
+	.vl_clk = 24000000,
+	.vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL,
+	.vl_bpix = LCD_BPP,
+	.vl_tft = 1,
+	.vl_hsync_len = 128,
+	.vl_left_margin = 64,
+	.vl_right_margin = 64,
+	.vl_vsync_len = 2,
+	.vl_upper_margin = 22,
+	.vl_lower_margin = 21,
+	.mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+}
+
+void lcd_disable(void)
+{
+}
+
+static void sama5d3xek_lcd_hw_init(void)
+{
+	gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
+
+	/* The higher 8 bit of LCD is board related */
+	at91_set_c_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD16 */
+	at91_set_c_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD17 */
+	at91_set_c_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD18 */
+	at91_set_c_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD19 */
+	at91_set_c_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD20 */
+	at91_set_c_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD21 */
+	at91_set_c_periph(AT91_PIO_PORTE, 27, 0);	/* LCDD22 */
+	at91_set_c_periph(AT91_PIO_PORTE, 28, 0);	/* LCDD23 */
+
+	/* Configure lower 16 bit of LCD and enable clock */
+	at91_lcd_hw_init();
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	lcd_printf("%s\n", U_BOOT_VERSION);
+	lcd_printf("(C) 2013 ATMEL Corp\n");
+	lcd_printf("at91@atmel.com\n");
+	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
+		   strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+
+	nand_size = 0;
+#ifdef CONFIG_NAND_ATMEL
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+#endif
+	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
+		   dram_size >> 20, nand_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+int board_early_init_f(void)
+{
+	at91_seriald_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+	sama5d3xek_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	sama5d3xek_usb_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	sama5d3xek_mci_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	if (has_emac())
+		at91_macb_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	if (has_lcdc())
+		sama5d3xek_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	if (has_emac())
+		rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+
+	return rc;
+}
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bis)
+{
+	int rc = 0;
+
+	rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
+
+	return rc;
+}
+#endif
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs < 4;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 0:
+		at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
+	case 1:
+		at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
+	case 2:
+		at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
+	case 3:
+		at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
+	default:
+		break;
+	}
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 0:
+		at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
+	case 1:
+		at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
+	case 2:
+		at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
+	case 3:
+		at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
+	default:
+		break;
+	}
+}
+#endif /* CONFIG_ATMEL_SPI */
diff --git a/board/bf609-ezkit/soft_switch.c b/board/bf609-ezkit/soft_switch.c
new file mode 100644
index 0000000..e0c8d93
--- /dev/null
+++ b/board/bf609-ezkit/soft_switch.c
@@ -0,0 +1,171 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "soft_switch.h"
+
+struct switch_config {
+	uchar dir0; /* IODIRA */
+	uchar dir1; /* IODIRB */
+	uchar value0; /* OLATA */
+	uchar value1; /* OLATB */
+};
+
+static struct switch_config switch_config_array[NUM_SWITCH] = {
+	{
+/*
+	U45 Port A                     U45 Port B
+
+	7---------------  RMII_CLK_EN  |  7--------------- ~TEMP_THERM_EN
+	| 6------------- ~CNT0ZM_EN    |  | 6------------- ~TEMP_IRQ_EN
+	| | 5----------- ~CNT0DG_EN    |  | | 5----------- ~UART0CTS_146_EN
+	| | | 4--------- ~CNT0UD_EN    |  | | | 4--------- ~UART0CTS_RST_EN
+	| | | | 3------- ~CAN0RX_EN    |  | | | | 3------- ~UART0CTS_RTS_LPBK
+	| | | | | 2----- ~CAN0_ERR_EN  |  | | | | | 2----- ~UART0CTS_EN
+	| | | | | | 1--- ~CAN_STB      |  | | | | | | 1--- ~UART0RX_EN
+	| | | | | | | 0-  CAN_EN       |  | | | | | | | 0- ~UART0RTS_EN
+	| | | | | | | |                |  | | | | | | | |
+	O O O O O O O O                |  O O O O O O O O   (I/O direction)
+	1 0 0 0 0 0 1 1                |  1 1 1 1 1 0 0 0   (value being set)
+*/
+		.dir0 = 0x0, /* all output */
+		.dir1 = 0x0, /* all output */
+		.value0 = RMII_CLK_EN | CAN_STB | CAN_EN,
+		.value1 = TEMP_THERM_EN | TEMP_IRQ_EN | UART0CTS_146_EN
+				| UART0CTS_RST_EN | UART0CTS_RTS_LPBK,
+	},
+	{
+/*
+	U46 Port A                       U46 Port B
+
+	7--------------- ~LED4_GPIO_EN   |  7---------------  EMPTY
+	| 6------------- ~LED3_GPIO_EN   |  | 6------------- ~SPI0D3_EN
+	| | 5----------- ~LED2_GPIO_EN   |  | | 5----------- ~SPI0D2_EN
+	| | | 4--------- ~LED1_GPIO_EN   |  | | | 4--------- ~SPIFLASH_CS_EN
+	| | | | 3-------  SMC0_LP0_EN    |  | | | | 3------- ~SD_WP_EN
+	| | | | | 2-----  EMPTY          |  | | | | | 2----- ~SD_CD_EN
+	| | | | | | 1---  SMC0_EPPI2     |  | | | | | | 1--- ~PUSHBUTTON2_EN
+			  _LP1_SWITCH
+	| | | | | | | 0-  OVERRIDE_SMC0  |  | | | | | | | 0- ~PUSHBUTTON1_EN
+			  _LP0_BOOT
+	| | | | | | | |                  |  | | | | | | | |
+	O O O O O O O O                  |  O O O O O O O O   (I/O direction)
+	0 0 0 0 0 X 0 1                  |  X 0 0 0 0 0 0 0   (value being set)
+*/
+		.dir0 = 0x0, /* all output */
+		.dir1 = 0x0, /* all output */
+#ifdef CONFIG_BFIN_LINKPORT
+		.value0 = OVERRIDE_SMC0_LP0_BOOT,
+#else
+		.value0 = SMC0_EPPI2_LP1_SWITCH,
+#endif
+		.value1 = 0x0,
+	},
+	{
+/*
+	U47 Port A                         U47 Port B
+
+	7--------------- ~PD2_SPI0MISO |  7---------------  EMPTY
+			  _EI3_EN
+	| 6------------- ~PD1_SPI0D3   |  | 6-------------  EMPTY
+			  _EPPI1D17
+			  _SPI0SEL2
+			  _EI3_EN
+	| | 5----------- ~PD0_SPI0D2   |  | | 5-----------  EMPTY
+			  _EPPI1D16
+			  _SPI0SEL3
+			  _EI3_EN
+	| | | 4--------- ~WAKE_PUSH    |  | | | 4---------  EMPTY
+			  BUTTON_EN
+	| | | | 3------- ~ETHERNET_EN  |  | | | | 3-------  EMPTY
+	| | | | | 2-----  PHYAD0       |  | | | | | 2-----  EMPTY
+	| | | | | | 1---  PHY_PWR      |  | | | | | | 1--- ~PD4_SPI0CK_EI3_EN
+			  _DWN_INT
+	| | | | | | | 0- ~PHYINT_EN    |  | | | | | | | 0- ~PD3_SPI0MOSI_EI3_EN
+	| | | | | | | |                |  | | | | | | | |
+	O O O O O I I O                |  O O O O O O O O   (I/O direction)
+	1 1 1 0 0 0 0 0                |  X X X X X X 1 1   (value being set)
+*/
+		.dir0 = 0x6, /* bits 1 and 2 input, all others output */
+		.dir1 = 0x0, /* all output */
+		.value0 = PD1_SPI0D3_EN | PD0_SPI0D2_EN,
+		.value1 = 0,
+	},
+};
+
+static int setup_soft_switch(int addr, struct switch_config *config)
+{
+	int ret = 0;
+
+	ret = i2c_write(addr, OLATA, 1, &config->value0, 1);
+	if (ret)
+		return ret;
+	ret = i2c_write(addr, OLATB, 1, &config->value1, 1);
+	if (ret)
+		return ret;
+
+	ret = i2c_write(addr, IODIRA, 1, &config->dir0, 1);
+	if (ret)
+		return ret;
+	return i2c_write(addr, IODIRB, 1, &config->dir1, 1);
+}
+
+int config_switch_bit(int addr, int port, int bit, int dir, uchar value)
+{
+	int ret, data_reg, dir_reg;
+	uchar tmp;
+
+	if (port == IO_PORT_A) {
+		data_reg = OLATA;
+		dir_reg = IODIRA;
+	} else {
+		data_reg = OLATB;
+		dir_reg = IODIRB;
+	}
+
+	if (dir == IO_PORT_INPUT) {
+		ret = i2c_read(addr, dir_reg, 1, &tmp, 1);
+		if (ret)
+			return ret;
+		tmp |= bit;
+		return i2c_write(addr, dir_reg, 1, &tmp, 1);
+	} else {
+		ret = i2c_read(addr, data_reg, 1, &tmp, 1);
+		if (ret)
+			return ret;
+		if (value)
+			tmp |= bit;
+		else
+			tmp &= ~bit;
+		ret = i2c_write(addr, data_reg, 1, &tmp, 1);
+		if (ret)
+			return ret;
+		ret = i2c_read(addr, dir_reg, 1, &tmp, 1);
+		if (ret)
+			return ret;
+		tmp &= ~bit;
+		return i2c_write(addr, dir_reg, 1, &tmp, 1);
+	}
+}
+
+int setup_board_switches(void)
+{
+	int ret;
+	int i;
+
+	for (i = 0; i < NUM_SWITCH; i++) {
+		ret = setup_soft_switch(SWITCH_ADDR + i,
+				&switch_config_array[i]);
+		if (ret)
+			return ret;
+	}
+	return 0;
+}
diff --git a/board/bf609-ezkit/soft_switch.h b/board/bf609-ezkit/soft_switch.h
new file mode 100644
index 0000000..d147fe1
--- /dev/null
+++ b/board/bf609-ezkit/soft_switch.h
@@ -0,0 +1,80 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BOARD_SOFT_SWITCH_H__
+#define __BOARD_SOFT_SWITCH_H__
+
+#include <asm/soft_switch.h>
+
+/* switch 0 port A */
+#define CAN_EN                 0x1
+#define CAN_STB                0x2
+#define CAN0_ERR_EN            0x4
+#define CAN0RX_EN              0x8
+#define CNT0UD_EN              0x10
+#define CNT0DG_EN              0x20
+#define CNT0ZM_EN              0x40
+#define RMII_CLK_EN            0x80
+
+/* switch 0 port B */
+#define UART0RTS_EN            0x1
+#define UART0RX_EN             0x2
+#define UART0CTS_EN            0x4
+#define UART0CTS_RTS_LPBK      0x8
+#define UART0CTS_RST_EN        0x10
+#define UART0CTS_146_EN        0x20
+#define TEMP_IRQ_EN            0x40
+#define TEMP_THERM_EN          0x80
+
+/* switch 1 port A */
+#define OVERRIDE_SMC0_LP0_BOOT 0x1
+#define SMC0_EPPI2_LP1_SWITCH  0x2
+#define SMC0_LP0_EN            0x8
+#define LED1_GPIO_EN           0x10
+#define LED2_GPIO_EN           0x20
+#define LED3_GPIO_EN           0x40
+#define LED4_GPIO_EN           0x80
+
+/* switch 1 port B */
+#define PUSHBUTTON1_EN         0x1
+#define PUSHBUTTON2_EN         0x2
+#define SD_CD_EN               0x4
+#define SD_WP_EN               0x8
+#define SPIFLASH_CS_EN         0x10
+#define SPI0D2_EN              0x20
+#define SPI0D3_EN              0x40
+
+/* switch 2 port A */
+#define PHYINT_EN              0x1
+#define PHY_PWR_DWN_INT        0x2
+#define PHYAD0                 0x4
+#define ETHERNET_EN            0x8
+#define WAKE_PUSHBUTTON_EN     0x10
+#define PD0_SPI0D2_EN          0x20
+#define PD1_SPI0D3_EN          0x40
+#define PD2_SPI0MISO_EN        0x80
+
+/* switch 2 port B */
+#define PD3_SPI0MOSI_EN        0x1
+#define PD4_SPI0CK_EN          0x2
+
+#ifdef CONFIG_BFIN_BOARD_VERSION_1_0
+#define SWITCH_ADDR     0x21
+#else
+#define SWITCH_ADDR     0x20
+#endif
+
+#define NUM_SWITCH      3
+#define IODIRA          0x0
+#define IODIRB          0x1
+#define OLATA           0x14
+#define OLATB           0x15
+
+int setup_board_switches(void);
+
+#endif /* __BOARD_SOFT_SWITCH_H__ */
diff --git a/board/boundary/nitrogen6x/clocks.cfg b/board/boundary/nitrogen6x/clocks.cfg
index e7d1f86..0a3b47b 100644
--- a/board/boundary/nitrogen6x/clocks.cfg
+++ b/board/boundary/nitrogen6x/clocks.cfg
@@ -44,3 +44,14 @@
 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
 DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg
index d6da96c..6625790 100644
--- a/board/boundary/nitrogen6x/nitrogen6dl.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg
@@ -19,7 +19,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
index 0b1c35c..dccd497 100644
--- a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
@@ -19,7 +19,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg
index 680a853..e317374 100644
--- a/board/boundary/nitrogen6x/nitrogen6q.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6q.cfg
@@ -19,7 +19,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
index f57ab0e..5a06220 100644
--- a/board/boundary/nitrogen6x/nitrogen6q2g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
@@ -19,7 +19,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg
index b5af5cc..d7d5f29 100644
--- a/board/boundary/nitrogen6x/nitrogen6s.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6s.cfg
@@ -19,7 +19,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
index 5aeefc8..cf2690a 100644
--- a/board/boundary/nitrogen6x/nitrogen6s1g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
@@ -19,7 +19,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index cc071d6..e155556 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -47,40 +47,34 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |	       \
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	       \
-	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |	       \
-	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	       \
-	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
-#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
-	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
 	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
 
-#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
-#define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
-#define WEAK_PULLUP	(PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+#define WEAK_PULLUP	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_SRE_SLOW)
 
-#define WEAK_PULLDOWN	(PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
-	PAD_CTL_SRE_SLOW)
+#define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 
 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
 
diff --git a/board/buffalo/lsxl/kwbimage-lschl.cfg b/board/buffalo/lsxl/kwbimage-lschl.cfg
index 2b9b3cd..4ac381e 100644
--- a/board/buffalo/lsxl/kwbimage-lschl.cfg
+++ b/board/buffalo/lsxl/kwbimage-lschl.cfg
@@ -20,7 +20,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/buffalo/lsxl/kwbimage-lsxhl.cfg b/board/buffalo/lsxl/kwbimage-lsxhl.cfg
index 8a94b6c..c62f22c 100644
--- a/board/buffalo/lsxl/kwbimage-lsxhl.cfg
+++ b/board/buffalo/lsxl/kwbimage-lsxhl.cfg
@@ -20,7 +20,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/cloudengines/pogo_e02/kwbimage.cfg b/board/cloudengines/pogo_e02/kwbimage.cfg
index a02e88d..32c0cd5 100644
--- a/board/cloudengines/pogo_e02/kwbimage.cfg
+++ b/board/cloudengines/pogo_e02/kwbimage.cfg
@@ -23,7 +23,7 @@
 # You should have received a copy of the GNU General Public License
 # along with this program; If not, see <http://www.gnu.org/licenses/>.
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/cm_t35/Makefile b/board/compulab/cm_t35/Makefile
similarity index 81%
rename from board/cm_t35/Makefile
rename to board/compulab/cm_t35/Makefile
index bde56e6..31d9bbb 100644
--- a/board/cm_t35/Makefile
+++ b/board/compulab/cm_t35/Makefile
@@ -1,6 +1,8 @@
 #
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Nikita Kiryanov <nikita@compulab.co.il>
+#	   Igor Grinberg <grinberg@compulab.co.il>
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -17,9 +19,7 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
+# Foundation, Inc.
 
 include $(TOPDIR)/config.mk
 
@@ -42,3 +42,5 @@
 include $(SRCTREE)/rules.mk
 
 sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
similarity index 96%
rename from board/cm_t35/cm_t35.c
rename to board/compulab/cm_t35/cm_t35.c
index 84c36ba..b0b80e5 100644
--- a/board/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
+ * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
  *
  * Authors: Mike Rapoport <mike@compulab.co.il>
  *	    Igor Grinberg <grinberg@compulab.co.il>
@@ -448,7 +448,7 @@
 {
 	u8 val;
 
-	if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, TWL4030_BASEADD_GPIO))
+	if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val))
 		return -1;
 
 	return !(val & 1);
@@ -493,17 +493,17 @@
 static void reset_net_chip(void)
 {
 	/* Set GPIO1 of TPS65930 as output */
-	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
-				TWL4030_BASEADD_GPIO + 0x03);
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,
+			     0x02);
 	/* Send a pulse on the GPIO pin */
-	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
-				TWL4030_BASEADD_GPIO + 0x0C);
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
+			     0x02);
 	udelay(1);
-	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
-				TWL4030_BASEADD_GPIO + 0x09);
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09,
+			     0x02);
 	mdelay(40);
-	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
-				TWL4030_BASEADD_GPIO + 0x0C);
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
+			     0x02);
 	mdelay(1);
 }
 #else
@@ -597,13 +597,13 @@
 	udelay(1000);
 
 	offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
-	twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, offset);
+	twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);
 	/* Set GPIO6 and GPIO7 of TPS65930 as output */
 	val |= 0xC0;
-	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, val, offset);
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val);
 	offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1;
 	/* Take both PHYs out of reset */
-	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0xC0, offset);
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0);
 	udelay(1);
 
 	return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
diff --git a/board/cm_t35/display.c b/board/compulab/cm_t35/display.c
similarity index 99%
rename from board/cm_t35/display.c
rename to board/compulab/cm_t35/display.c
index a004ea1..adc4853 100644
--- a/board/cm_t35/display.c
+++ b/board/compulab/cm_t35/display.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2012 CompuLab, Ltd. <www.compulab.co.il>
+ * (C) Copyright 2012 - 2013 CompuLab, Ltd. <www.compulab.co.il>
  *
  * Authors: Nikita Kiryanov <nikita@compulab.co.il>
  *
diff --git a/board/cm_t35/eeprom.c b/board/compulab/cm_t35/eeprom.c
similarity index 100%
rename from board/cm_t35/eeprom.c
rename to board/compulab/cm_t35/eeprom.c
diff --git a/board/cm_t35/eeprom.h b/board/compulab/cm_t35/eeprom.h
similarity index 100%
rename from board/cm_t35/eeprom.h
rename to board/compulab/cm_t35/eeprom.h
diff --git a/board/cm_t35/leds.c b/board/compulab/cm_t35/leds.c
similarity index 94%
rename from board/cm_t35/leds.c
rename to board/compulab/cm_t35/leds.c
index 48ad598..dcae135 100644
--- a/board/cm_t35/leds.c
+++ b/board/compulab/cm_t35/leds.c
@@ -1,6 +1,5 @@
 /*
- * (C) Copyright 2011
- * CompuLab, Ltd. <www.compulab.co.il>
+ * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
  *
  * Author: Igor Grinberg <grinberg@compulab.co.il>
  *
diff --git a/board/d-link/dns325/kwbimage.cfg b/board/d-link/dns325/kwbimage.cfg
index 97cb090..6df7939 100644
--- a/board/d-link/dns325/kwbimage.cfg
+++ b/board/d-link/dns325/kwbimage.cfg
@@ -25,7 +25,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/alaska/Makefile b/board/denx/m53evk/Makefile
similarity index 79%
rename from board/alaska/Makefile
rename to board/denx/m53evk/Makefile
index a21f851..bfb040a 100644
--- a/board/alaska/Makefile
+++ b/board/denx/m53evk/Makefile
@@ -1,9 +1,6 @@
 #
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
+# DENX M53EVK
+# Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
@@ -25,13 +22,12 @@
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= $(BOARD).o flash.o
+COBJS	:= m53evk.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(OBJS)
+$(LIB):	$(obj).depend $(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
 #########################################################################
diff --git a/board/denx/m53evk/imximage.cfg b/board/denx/m53evk/imximage.cfg
new file mode 100644
index 0000000..27c593a
--- /dev/null
+++ b/board/denx/m53evk/imximage.cfg
@@ -0,0 +1,108 @@
+/*
+ * DENX M53 DRAM init values
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION	2
+
+
+/* Boot Offset 0x400, valid for both SD and NAND boot. */
+BOOT_OFFSET	FLASH_OFFSET_STANDARD
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x53fa86f4 0x00000000	 /* GRP_DDRMODE_CTL */
+DATA 4 0x53fa8714 0x00000000	 /* GRP_DDRMODE */
+DATA 4 0x53fa86fc 0x00000000	 /* GRP_DDRPKE */
+DATA 4 0x53fa8724 0x04000000	 /* GRP_DDR_TYPE */
+
+DATA 4 0x53fa872c 0x00300000	 /* GRP_B3DS */
+DATA 4 0x53fa8554 0x00300000	 /* DRAM_DQM3 */
+DATA 4 0x53fa8558 0x00300040	 /* DRAM_SDQS3 */
+
+DATA 4 0x53fa8728 0x00300000	 /* GRP_B2DS */
+DATA 4 0x53fa8560 0x00300000	 /* DRAM_DQM2 */
+DATA 4 0x53fa8568 0x00300040	 /* DRAM_SDQS2 */
+
+DATA 4 0x53fa871c 0x00300000	 /* GRP_B1DS */
+DATA 4 0x53fa8594 0x00300000	 /* DRAM_DQM1 */
+DATA 4 0x53fa8590 0x00300040	 /* DRAM_SDQS1 */
+
+DATA 4 0x53fa8718 0x00300000	 /* GRP_B0DS */
+DATA 4 0x53fa8584 0x00300000	 /* DRAM_DQM0 */
+DATA 4 0x53fa857c 0x00300040	 /* DRAM_SDQS0 */
+
+DATA 4 0x53fa8578 0x00300000	 /* DRAM_SDCLK_0 */
+DATA 4 0x53fa8570 0x00300000	 /* DRAM_SDCLK_1 */
+
+DATA 4 0x53fa8574 0x00300000	 /* DRAM_CAS */
+DATA 4 0x53fa8588 0x00300000	 /* DRAM_RAS */
+DATA 4 0x53fa86f0 0x00300000	 /* GRP_ADDDS */
+DATA 4 0x53fa8720 0x00300000	 /* GRP_CTLDS */
+
+DATA 4 0x53fa8564 0x00300040	 /* DRAM_SDODT1 */
+DATA 4 0x53fa8580 0x00300040	 /* DRAM_SDODT0 */
+
+/* ESDCTL */
+DATA 4 0x63fd9088 0x32383535
+DATA 4 0x63fd9090 0x40383538
+DATA 4 0x63fd907c 0x0136014d
+DATA 4 0x63fd9080 0x01510141
+
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd900c 0x555952e3
+DATA 4 0x63fd9010 0xb68e8b63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x092080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x09208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00001800
+DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901c 0x00000000
diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c
new file mode 100644
index 0000000..12917fd
--- /dev/null
+++ b/board/denx/m53evk/m53evk.c
@@ -0,0 +1,328 @@
+/*
+ * DENX M53 module
+ *
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/spl.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <spl.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+#include <usb/ehci-fsl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	u32 size1, size2;
+
+	size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+	gd->ram_size = size1 + size2;
+
+	return 0;
+}
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+static void setup_iomux_uart(void)
+{
+	static const iomux_v3_cfg_t uart_pads[] = {
+		MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
+		MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+	if (port == 0) {
+		/* USB OTG PWRON */
+		imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
+					PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
+		gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
+
+		/* USB OTG Over Current */
+		imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
+	} else if (port == 1) {
+		/* USB Host PWRON */
+		imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
+					PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
+		gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
+
+		/* USB Host Over Current */
+		imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
+	}
+
+	return 0;
+}
+#endif
+
+static void setup_iomux_fec(void)
+{
+	static const iomux_v3_cfg_t fec_pads[] = {
+		/* MDIO pads */
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+
+		/* FEC 0 pads */
+		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+
+		/* FEC 1 pads */
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg = {
+	MMC_SDHC1_BASE_ADDR,
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+	gpio_direction_input(IMX_GPIO_NR(1, 1));
+
+	return !gpio_get_value(IMX_GPIO_NR(1, 1));
+}
+
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+		MX53_PAD_EIM_DA13__GPIO3_13,
+
+		MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */
+	};
+
+	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+
+	/* GPIO 2_31 is SD power */
+	gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+#endif
+
+#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+	static const iomux_v3_cfg_t i2c_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
+}
+
+static void setup_iomux_nand(void)
+{
+	static const iomux_v3_cfg_t nand_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
+				PAD_CTL_PUS_100K_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
+				PAD_CTL_PUS_100K_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+}
+
+static void m53_set_clock(void)
+{
+	int ret;
+	const uint32_t ref_clk = MXC_HCLK;
+	const uint32_t dramclk = 400;
+	uint32_t cpuclk;
+
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
+					    PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
+	gpio_direction_input(IMX_GPIO_NR(4, 0));
+
+	/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
+	cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
+
+	ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
+
+	ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
+	if (ret) {
+		printf("CPU:   Switch peripheral clock to %dMHz failed\n",
+			dramclk);
+	}
+
+	ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
+}
+
+static void m53_set_nand(void)
+{
+	u32 i;
+
+	/* NAND flash is muxed on ATA pins */
+	setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
+
+	/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
+	for (i = 0x4; i < 0x94; i += 0x18) {
+		clrbits_le32(WEIM_BASE_ADDR + i,
+			     WEIM_GCR2_MUX16_BYP_GRANT_MASK);
+	}
+
+	mxc_set_clock(0, 33, MXC_NFC_CLK);
+	enable_nfc_clk(1);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_iomux_fec();
+	setup_iomux_i2c();
+	setup_iomux_nand();
+
+	m53_set_clock();
+
+	mxc_set_sata_internal_clock();
+
+	/* NAND clock @ 33MHz */
+	m53_set_nand();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: DENX M53EVK\n");
+
+	return 0;
+}
+
+/*
+ * NAND SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+	setup_iomux_nand();
+	m53_set_clock();
+	m53_set_nand();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NAND;
+}
+#endif
diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c
index 41d6bb6..051fa6e 100644
--- a/board/esg/ima3-mx53/ima3-mx53.c
+++ b/board/esg/ima3-mx53/ima3-mx53.c
@@ -23,11 +23,10 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
 #include <asm/errno.h>
 #include <netdev.h>
 #include <mmc.h>
@@ -66,109 +65,53 @@
 	return 0;
 }
 
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
 static void setup_iomux_uart(void)
 {
-	/* UART4 RXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D13,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-		PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
-		PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
+	static const iomux_v3_cfg_t uart_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__UART4_RXD_MUX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__UART4_TXD_MUX, UART_PAD_CTRL),
+	};
 
-	/* UART4 TXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D12,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-		PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
-		PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
 static void setup_iomux_fec(void)
 {
-	/*FEC_MDIO*/
-	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-		PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU |
-		PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+	};
 
-	/*FEC_MDC*/
-	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
-
-	/* FEC RXD3 */
-	mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6);
-	mxc_iomux_set_pad(MX53_PIN_KEY_COL0, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC RXD2 */
-	mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6);
-	mxc_iomux_set_pad(MX53_PIN_KEY_COL2, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC RXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC RXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC TXD3 */
-	mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6);
-	mxc_iomux_set_pad(MX53_PIN_GPIO_19, PAD_CTL_DRV_HIGH);
-
-	/* FEC TXD2 */
-	mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6);
-	mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH);
-
-	/* FEC TXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
-
-	/* FEC TXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_EN */
-	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_CLK */
-	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC RX_ER */
-	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC RX_DV */
-	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC CRS */
-	mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6);
-	mxc_iomux_set_pad(MX53_PIN_KEY_COL3, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC COL */
-	mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6);
-	mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-	mxc_iomux_set_input(MX53_FEC_FEC_COL_SELECT_INPUT, 0x0);
-
-	/* FEC RX_CLK */
-	mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6);
-	mxc_iomux_set_pad(MX53_PIN_KEY_COL1, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-	mxc_iomux_set_input(MX53_FEC_FEC_RX_CLK_SELECT_INPUT, 0x0);
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 #ifdef CONFIG_FSL_ESDHC
@@ -178,76 +121,51 @@
 {
 	int ret;
 
-	ret = !gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
+	ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
 
 	return ret;
 }
 
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+#define SD_CD_PAD_CTRL		(PAD_CTL_DSE_HIGH | PAD_CTL_HYS | PAD_CTL_PKE)
+
 int board_mmc_init(bd_t *bis)
 {
-	mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX53_PIN_GPIO_1,
-		PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
-		PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE);
-	gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, SD_CD_PAD_CTRL),
+	};
 
-	mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
-	mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
-		PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
-		PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH);
-	mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-	mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-	mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-	mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+	gpio_direction_input(IMX_GPIO_NR(1, 1));
 
 	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg);
 }
 #endif
 
+#define SPI_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
+
 static void setup_iomux_spi(void)
 {
-	/* SCLK */
-	mxc_request_iomux(MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-	mxc_iomux_set_input(MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x1);
-	/* MOSI */
-	mxc_request_iomux(MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-	mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, 0x1);
-	/* MISO */
-	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-	mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, 0x1);
-	/* SSEL 0 */
-	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_GPIO);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11), 1);
+	static const iomux_v3_cfg_t spi_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL),
+		/* SSEL 0 */
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__GPIO5_29, SPI_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
+	gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
 }
 
 int board_early_init_f(void)
diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg
index fce7492..ab22385 100644
--- a/board/esg/ima3-mx53/imximage.cfg
+++ b/board/esg/ima3-mx53/imximage.cfg
@@ -20,7 +20,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index 41887c2..a39c17a 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -166,11 +166,13 @@
 		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
 		if (!ret) {
 			ret = vsc3316_config(VSC3316_TX_ADDRESS,
-					vsc16_tx_sgmii_lane_ab, num_vsc16_con);
+					vsc16_tx_4sfp_sgmii_12_56,
+					num_vsc16_con);
 			if (ret)
 				return ret;
 			ret = vsc3316_config(VSC3316_RX_ADDRESS,
-					vsc16_rx_sgmii_lane_ab, num_vsc16_con);
+					vsc16_rx_4sfp_sgmii_12_56,
+					num_vsc16_con);
 			if (ret)
 				return ret;
 		} else {
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
index 994dec5..c2b6c44 100644
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -26,42 +26,53 @@
 static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
 				{5, 11}, {4, 5}, {2, 6}, {12, 9} };
 
-static const int8_t vsc16_tx_sfp[8][2] = { {15, 8}, {0, 0}, {7, 7}, {9, 1},
-				{5, 15}, {4, 14}, {2, 12}, {12, 13} };
+static const int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
+				{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
-static const int8_t vsc16_tx_sgmii_lane_ab[8][2] = { {2, 14}, {12, 15},
-		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+static const int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
+				{7, 8}, {9, 0}, {2, 14}, {12, 15},
+				{-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
+				{7, 8}, {9, 0}, {5, 14}, {4, 15},
+				{-1, -1}, {-1, -1} };
 
 #ifdef CONFIG_PPC_B4420
 static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
 		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 #endif
+
 static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
 			{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
 static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
 				{11, 11}, {5, 10}, {6, 3}, {9, 12} };
 
-static const int8_t vsc16_rx_sfp[8][2] = { {0, 15}, {8, 1}, {1, 8}, {7, 9},
+static const int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
 				{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
-static const int8_t vsc16_rx_sgmii_lane_ab[8][2] = { {14, 3}, {15, 12},
-		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+static const int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
+				{7, 8}, {1, 9}, {14, 3}, {15, 12},
+				{-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
+				{7, 8}, {1, 9}, {14, 11}, {15, 10},
+				{-1, -1}, {-1, -1} };
 
 #ifdef CONFIG_PPC_B4420
 static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
 		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 #endif
 
-static const int8_t vsc16_rx_aurora[8][2] = { {12, 3}, {13, 12}, {-1, -1},
+static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1},
 			{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
 static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
 
-static const int8_t vsc08_tx_sfp[4][2] = { {2, 6}, {3, 7}, {7, 1}, {1, 0} };
+static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} };
 
 static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
 
-static const int8_t vsc08_rx_sfp[4][2] = { {6, 3}, {7, 4}, {1, 7}, {0, 1} };
+static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} };
 
 #endif
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index dd4c0f6..b82b3d4 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -13,6 +13,7 @@
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
+#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -188,3 +189,74 @@
 	puts("    DDR: ");
 	return dram_size;
 }
+
+unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
+			  unsigned int dbw_cap_adj[])
+{
+	int i, j;
+	unsigned long long total_mem, current_mem_base, total_ctlr_mem;
+	unsigned long long rank_density, ctlr_density = 0;
+
+	current_mem_base = 0ull;
+	total_mem = 0;
+	/*
+	 * This board has soldered DDR chips. DDRC1 has two rank.
+	 * DDRC2 has only one rank.
+	 * Assigning DDRC2 to lower address and DDRC1 to higher address.
+	 */
+	if (pinfo->memctl_opts[0].memctl_interleaving) {
+		rank_density = pinfo->dimm_params[0][0].rank_density >>
+					dbw_cap_adj[0];
+		ctlr_density = rank_density;
+
+		debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
+		      rank_density, ctlr_density);
+		for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+			switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
+			case FSL_DDR_CACHE_LINE_INTERLEAVING:
+			case FSL_DDR_PAGE_INTERLEAVING:
+			case FSL_DDR_BANK_INTERLEAVING:
+			case FSL_DDR_SUPERBANK_INTERLEAVING:
+				total_ctlr_mem = 2 * ctlr_density;
+				break;
+			default:
+				panic("Unknown interleaving mode");
+			}
+			pinfo->common_timing_params[i].base_address =
+						current_mem_base;
+			pinfo->common_timing_params[i].total_mem =
+						total_ctlr_mem;
+			total_mem = current_mem_base + total_ctlr_mem;
+			debug("ctrl %d base 0x%llx\n", i, current_mem_base);
+			debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
+		}
+	} else {
+		/*
+		 * Simple linear assignment if memory
+		 * controllers are not interleaved.
+		 */
+		for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+			total_ctlr_mem = 0;
+			pinfo->common_timing_params[i].base_address =
+						current_mem_base;
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				/* Compute DIMM base addresses. */
+				unsigned long long cap =
+					pinfo->dimm_params[i][j].capacity;
+				pinfo->dimm_params[i][j].base_address =
+					current_mem_base;
+				debug("ctrl %d dimm %d base 0x%llx\n",
+				      i, j, current_mem_base);
+				current_mem_base += cap;
+				total_ctlr_mem += cap;
+			}
+			debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
+			pinfo->common_timing_params[i].total_mem =
+							total_ctlr_mem;
+			total_mem += total_ctlr_mem;
+		}
+	}
+	debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
+
+	return total_mem;
+}
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 68e2725..3bcda6d 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -275,6 +275,24 @@
 		fm_info_set_phy_address(FM1_DTSEC4,
 				CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
 		break;
+	case 0x98:
+		/* XAUI in Slot1 and Slot2 */
+		debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n",
+		      CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_10GEC1,
+					CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+		debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
+		      CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_10GEC2,
+					CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+		break;
+	case 0x9E:
+		/* XAUI in Slot2 */
+		debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
+		      CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_10GEC2,
+					CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+		break;
 	default:
 		printf("Fman:  Unsupported SerDes2 Protocol 0x%02x\n",
 				serdes2_prtcl);
@@ -300,6 +318,23 @@
 		}
 	}
 
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+		int idx = i - FM1_10GEC1;
+
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			fm_info_set_mdio(i,
+					 miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
+			break;
+		default:
+			printf("Fman1: 10GSEC%u set to unknown interface %i\n",
+			       idx + 1, fm_info_get_enet_if(i));
+			fm_info_set_phy_address(i, 0);
+			break;
+		}
+	}
+
+
 	cpu_eth_init(bis);
 #endif
 
diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c
index 4142e01..b26725b 100644
--- a/board/freescale/b4860qds/law.c
+++ b/board/freescale/b4860qds/law.c
@@ -33,8 +33,12 @@
 	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
 #endif
 	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_MAPLE_MEM_PHYS
+	SET_LAW(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_MAPLE),
+#endif
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
 #ifdef CONFIG_SYS_NAND_BASE_PHYS
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
index 6d634bf..29cc41b 100644
--- a/board/freescale/b4860qds/tlb.c
+++ b/board/freescale/b4860qds/tlb.c
@@ -106,7 +106,7 @@
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_4M, 1),
+		      0, 10, BOOKE_PAGESZ_32M, 1),
 #endif
 #ifdef CONFIG_SYS_NAND_BASE
 	/*
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index 8d914d5..2cf8738 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -78,7 +78,11 @@
 	u8 trig_stat;
 	u8 res12[3];
 	u8 trig_ctr[4];
-	u8 res13[48];
+	u8 res13[16];
+	u8 clk_freq[6];	/* Clock Measurement Registers */
+	u8 res_c6[8];
+	u8 clk_base[2];	/* Clock Frequency Base Reg */
+	u8 res_d0[16];
 	u8 aux2[4];	/* Auxiliary Registers,0xE0 */
 	u8 res14[10];
 	u8 aux_ad;
diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c
index ef9de25..ae07073 100644
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -605,8 +605,8 @@
 	lane = serdes_get_first_lane(XAUI_FM1);
 	if (lane >= 0) {
 		debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
-		mdio_mux[FM1_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK;
-		mdio_mux[FM1_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT2;
+		mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
+		mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2;
 		super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO",
 					mdio_mux[i].mask, mdio_mux[i].val);
 	}
@@ -704,8 +704,8 @@
 	lane = serdes_get_first_lane(XAUI_FM2);
 	if (lane >= 0) {
 		debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
-		mdio_mux[FM2_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK;
-		mdio_mux[FM2_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT1;
+		mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
+		mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1;
 		super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO",
 					mdio_mux[i].mask, mdio_mux[i].val);
 	}
diff --git a/board/freescale/corenet_ds/pbi.cfg b/board/freescale/corenet_ds/pbi.cfg
index 50806ca..af1ebd6 100644
--- a/board/freescale/corenet_ds/pbi.cfg
+++ b/board/freescale/corenet_ds/pbi.cfg
@@ -19,7 +19,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.pblimage for more details about how-to configure
+# Refer doc/README.pblimage for more details about how-to configure
 # and create PBL boot image
 #
 
diff --git a/board/freescale/corenet_ds/rcw_p5040ds.cfg b/board/freescale/corenet_ds/rcw_p5040ds.cfg
new file mode 100644
index 0000000..82fa741
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p5040ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P5040DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+0c580000 00000000 22121200 00000000
+089c4400 00283000 58000000 61000000
+00000000 00000000 00000000 10070000
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index f4cae5e..bae5c23 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -20,7 +20,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
@@ -172,3 +172,14 @@
 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4 0x020c4060 0x000000fb
diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c
index b6f4e7e..6be8c8d 100644
--- a/board/freescale/mx23evk/spl_boot.c
+++ b/board/freescale/mx23evk/spl_boot.c
@@ -25,8 +25,8 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
 
-#define	MUX_CONFIG_SSP1	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
-#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_16MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP1	(MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
 
 const iomux_cfg_t iomux_setup[] = {
 	/* DUART */
diff --git a/board/freescale/mx25pdk/imximage.cfg b/board/freescale/mx25pdk/imximage.cfg
index c42a283..8cc8bde 100644
--- a/board/freescale/mx25pdk/imximage.cfg
+++ b/board/freescale/mx25pdk/imximage.cfg
@@ -15,7 +15,7 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c
index d73e27e..5e6047f 100644
--- a/board/freescale/mx25pdk/mx25pdk.c
+++ b/board/freescale/mx25pdk/mx25pdk.c
@@ -21,8 +21,7 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/imx25-pinmux.h>
-#include <asm/arch/sys_proto.h>
+#include <asm/arch/iomux-mx25.h>
 #include <asm/arch/clock.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
@@ -31,8 +30,8 @@
 #include <fsl_pmic.h>
 #include <mc34704.h>
 
-#define FEC_RESET_B		IMX_GPIO_NR(2, 3)
-#define FEC_ENABLE_B		IMX_GPIO_NR(4, 8)
+#define FEC_RESET_B		IMX_GPIO_NR(4, 8)
+#define FEC_ENABLE_B		IMX_GPIO_NR(2, 3)
 #define CARD_DETECT		IMX_GPIO_NR(2, 1)
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -43,29 +42,42 @@
 };
 #endif
 
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ *	0 for no pull
+ * or:
+ *	PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define FEC_OUT_PAD_CTRL	0
+
+#define I2C_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
+				 PAD_CTL_ODE)
+
 static void mx25pdk_fec_init(void)
 {
-	struct iomuxc_mux_ctl *muxctl;
-	struct iomuxc_pad_ctl *padctl;
-	u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
-	u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
+	static const iomux_v3_cfg_t fec_pads[] = {
+		MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+		MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+		MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
+		MX25_PAD_FEC_MDIO__FEC_MDIO,
+		MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
 
-	/* FEC pin init is generic */
-	mx25_fec_init_pins();
+		NEW_PAD_CTRL(MX25_PAD_D12__GPIO_4_8, 0), /* FEC_RESET_B */
+		NEW_PAD_CTRL(MX25_PAD_A17__GPIO_2_3, 0), /* FEC_ENABLE_B */
+	};
 
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-	/*
-	 * Set up FEC_RESET_B and FEC_ENABLE_B
-	 *
-	 * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12
-	 * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17
-	 */
-	writel(gpio_mux_mode, &muxctl->pad_d12);
-	writel(gpio_mux_mode, &muxctl->pad_a17);
+	static const iomux_v3_cfg_t i2c_pads[] = {
+		NEW_PAD_CTRL(MX25_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL),
+	};
 
-	writel(0x0, &padctl->pad_d12);
-	writel(0x0, &padctl->pad_a17);
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 
 	/* Assert RESET and ENABLE low */
 	gpio_direction_output(FEC_RESET_B, 0);
@@ -78,10 +90,7 @@
 	gpio_set_value(FEC_ENABLE_B, 1);
 
 	/* Setup I2C pins so that PMIC can turn on PHY supply */
-	writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk);
-	writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat);
-	writel(0x1E8, &padctl->pad_i2c1_clk);
-	writel(0x1E8, &padctl->pad_i2c1_dat);
+	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 }
 
 int dram_init(void)
@@ -92,9 +101,35 @@
 	return 0;
 }
 
+/*
+ * Set up input pins with hysteresis and 100-k pull-ups
+ */
+#define UART1_IN_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ *	0 for no pull
+ * or:
+ *	PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define UART1_OUT_PAD_CTRL	0
+
+static void mx25pdk_uart1_init(void)
+{
+	static const iomux_v3_cfg_t uart1_pads[] = {
+		NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
 int board_early_init_f(void)
 {
-	mx25_uart1_init_pins();
+	mx25pdk_uart1_init();
 
 	return 0;
 }
@@ -131,21 +166,8 @@
 #ifdef CONFIG_FSL_ESDHC
 int board_mmc_getcd(struct mmc *mmc)
 {
-	struct iomuxc_mux_ctl *muxctl;
-	struct iomuxc_pad_ctl *padctl;
-	u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
-
-	/*
-	 * Set up the Card Detect pin.
-	 *
-	 * SD1_GPIO_CD: gpio2_1 is ALT 5 mode of pin A15
-	 *
-	 */
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-
-	writel(gpio_mux_mode, &muxctl->pad_a15);
-	writel(0x0, &padctl->pad_a15);
+	/* Set up the Card Detect pin. */
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_A15__GPIO_2_1, 0));
 
 	gpio_direction_input(CARD_DETECT);
 	return !gpio_get_value(CARD_DETECT);
@@ -153,16 +175,16 @@
 
 int board_mmc_init(bd_t *bis)
 {
-	struct iomuxc_mux_ctl *muxctl;
-	u32 sdhc1_mux_mode = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
+	static const iomux_v3_cfg_t sdhc1_pads[] = {
+		NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
+	};
 
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	writel(sdhc1_mux_mode, &muxctl->pad_sd1_cmd);
-	writel(sdhc1_mux_mode, &muxctl->pad_sd1_clk);
-	writel(sdhc1_mux_mode, &muxctl->pad_sd1_data0);
-	writel(sdhc1_mux_mode, &muxctl->pad_sd1_data1);
-	writel(sdhc1_mux_mode, &muxctl->pad_sd1_data2);
-	writel(sdhc1_mux_mode, &muxctl->pad_sd1_data3);
+	imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
 
 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c
index 49158bd..4f6cfee 100644
--- a/board/freescale/mx31pdk/mx31pdk.c
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -39,7 +39,21 @@
 #ifdef CONFIG_SPL_BUILD
 void board_init_f(ulong bootflag)
 {
-	relocate_code(CONFIG_SPL_TEXT_BASE);
+	/*
+	 * copy ourselves from where we are running to where we were
+	 * linked at. Use ulong pointers as all addresses involved
+	 * are 4-byte-aligned.
+	 */
+	ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
+	asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
+	asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
+	asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
+	asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
+	for (dst = start_ptr; dst < end_ptr; dst++)
+		*dst = *(dst+(run_ptr-link_ptr));
+	/*
+	 * branch to nand_boot's link-time address.
+	 */
 	asm volatile("ldr pc, =nand_boot");
 }
 #endif
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c
index b7f474e..9f667d2 100644
--- a/board/freescale/mx35pdk/mx35pdk.c
+++ b/board/freescale/mx35pdk/mx35pdk.c
@@ -28,8 +28,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/mx35_pins.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx35.h>
 #include <i2c.h>
 #include <power/pmic.h>
 #include <fsl_pmic.h>
@@ -73,114 +72,88 @@
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 }
 
+#define I2C_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
+
 static void setup_iomux_i2c(void)
 {
-	int pad;
+	static const iomux_v3_cfg_t i2c1_pads[] = {
+		NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
+	};
 
 	/* setup pins for I2C1 */
-	mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
-	mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
-
-	pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
-			| PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
-
-	mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
-	mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+	imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
 }
 
 
 static void setup_iomux_spi(void)
 {
-	mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
-	mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
-	mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
-	mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
-	mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+	static const iomux_v3_cfg_t spi_pads[] = {
+		MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
+		MX35_PAD_CSPI1_MISO__CSPI1_MISO,
+		MX35_PAD_CSPI1_SS0__CSPI1_SS0,
+		MX35_PAD_CSPI1_SS1__CSPI1_SS1,
+		MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
 }
 
+#define USBOTG_IN_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
+				 PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
+#define USBOTG_OUT_PAD_CTRL	(PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
+
 static void setup_iomux_usbotg(void)
 {
-	int in_pad, out_pad;
+	static const iomux_v3_cfg_t usbotg_pads[] = {
+		NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
+				USBOTG_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
+				USBOTG_IN_PAD_CTRL),
+	};
 
 	/* Set up pins for USBOTG. */
-	mxc_request_iomux(MX35_PIN_USBOTG_PWR,
-			  MUX_CONFIG_SION | MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_USBOTG_OC,
-			  MUX_CONFIG_SION | MUX_CONFIG_FUNC);
-
-	in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
-		PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
-		PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
-	out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
-		PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
-
-	mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
-	mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
+	imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
 }
 
+#define FEC_PAD_CTRL	(PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
+
 static void setup_iomux_fec(void)
 {
-	int pad;
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
+					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+		NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
+					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+		NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
+					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+		NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
+					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+		NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
+					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+		NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
+		NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
+		NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
+		NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
+					PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
+		NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
+		NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
+					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+		NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
+					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+		NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
+					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+		NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
+		NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
+					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+		NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
+		NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
+					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+		NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
+	};
 
 	/* setup pins for FEC */
-	mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
-
-	pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \
-			PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW);
-
-	mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
-			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
-			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \
-			 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \
-			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \
-			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \
-			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \
-			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \
-			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \
-			  PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU);
-	mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \
-			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \
-			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \
-			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \
-			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \
-			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \
-			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \
-			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \
-			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
-	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \
-			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 int board_early_init_f(void)
@@ -262,8 +235,7 @@
 
 	if (pmic_detect()) {
 		p = pmic_get("FSL_PMIC");
-		mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
-					MUX_CONFIG_ALT1);
+		imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
 
 		pmic_reg_read(p, REG_SETTING_0, &pmic_val);
 		pmic_reg_write(p, REG_SETTING_0,
@@ -271,10 +243,9 @@
 		pmic_reg_read(p, REG_MODE_0, &pmic_val);
 		pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
 
-		mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
-		mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
+		imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
 
-		gpio_direction_output(IMX_GPIO_NR(2, 5), 1);
+		gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
 	}
 
 	val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
@@ -312,13 +283,17 @@
 
 int board_mmc_init(bd_t *bis)
 {
+	static const iomux_v3_cfg_t sdhc1_pads[] = {
+		MX35_PAD_SD1_CMD__ESDHC1_CMD,
+		MX35_PAD_SD1_CLK__ESDHC1_CLK,
+		MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+		MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+		MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+		MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+	};
+
 	/* configure pins for SDHC1 only */
-	mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
+	imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
 
 	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg);
diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg
index 3e141ee..aaa490a 100644
--- a/board/freescale/mx51evk/imximage.cfg
+++ b/board/freescale/mx51evk/imximage.cfg
@@ -20,7 +20,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 54c16b1..369da6d 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -24,8 +24,7 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx51.h>
 #include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
@@ -64,160 +63,103 @@
 	return rev;
 }
 
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
+
 static void setup_iomux_uart(void)
 {
-	unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-			PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
+	static const iomux_v3_cfg_t uart_pads[] = {
+		MX51_PAD_UART1_RXD__UART1_RXD,
+		MX51_PAD_UART1_TXD__UART1_TXD,
+		NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
+	};
 
-	mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
-	mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
-	mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
-	mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
 static void setup_iomux_fec(void)
 {
-	/*FEC_MDIO*/
-	mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
+				PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+		MX51_PAD_NANDF_CS3__FEC_MDC,
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
+		MX51_PAD_NANDF_D9__FEC_RDATA0,
+		MX51_PAD_NANDF_CS6__FEC_TDATA3,
+		MX51_PAD_NANDF_CS5__FEC_TDATA2,
+		MX51_PAD_NANDF_CS4__FEC_TDATA1,
+		MX51_PAD_NANDF_D8__FEC_TDATA0,
+		MX51_PAD_NANDF_CS7__FEC_TX_EN,
+		MX51_PAD_NANDF_CS2__FEC_TX_ER,
+		MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
+		MX51_PAD_EIM_CS5__FEC_CRS,
+		MX51_PAD_EIM_CS4__FEC_RX_ER,
+		NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
+	};
 
-	/*FEC_MDC*/
-	mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
-
-	/* FEC RDATA[3] */
-	mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
-
-	/* FEC RDATA[2] */
-	mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
-
-	/* FEC RDATA[1] */
-	mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
-
-	/* FEC RDATA[0] */
-	mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
-
-	/* FEC TDATA[3] */
-	mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
-
-	/* FEC TDATA[2] */
-	mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
-
-	/* FEC TDATA[1] */
-	mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
-
-	/* FEC TDATA[0] */
-	mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
-
-	/* FEC TX_EN */
-	mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
-
-	/* FEC TX_ER */
-	mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
-
-	/* FEC TX_CLK */
-	mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
-
-	/* FEC TX_COL */
-	mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
-
-	/* FEC RX_CLK */
-	mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
-
-	/* FEC RX_CRS */
-	mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
-
-	/* FEC RX_ER */
-	mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
-
-	/* FEC RX_DV */
-	mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 #ifdef CONFIG_MXC_SPI
 static void setup_iomux_spi(void)
 {
-	/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
-	mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
+	static const iomux_v3_cfg_t spi_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
+				MX51_GPIO_PAD_CTRL),
+		MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+	};
 
-	/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
-
-	/* de-select SS1 of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
-
-	/* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
-	mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
-
-	/* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
-
-	/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
+	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
 }
 #endif
 
 #ifdef CONFIG_USB_EHCI_MX5
-#define MX51EVK_USBH1_HUB_RST	IOMUX_TO_GPIO(MX51_PIN_GPIO1_7) /* GPIO1_7 */
-#define MX51EVK_USBH1_STP	IOMUX_TO_GPIO(MX51_PIN_USBH1_STP) /* GPIO1_27 */
-#define MX51EVK_USB_CLK_EN_B	IOMUX_TO_GPIO(MX51_PIN_EIM_D18) /* GPIO2_1 */
-#define MX51EVK_USB_PHY_RESET	IOMUX_TO_GPIO(MX51_PIN_EIM_D21) /* GPIO2_5 */
-
-#define USBH1_PAD	(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |		\
-			 PAD_CTL_100K_PU | PAD_CTL_PUE_PULL |		\
-			 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE)
-#define GPIO_PAD	(PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE |	\
-			 PAD_CTL_SRE_FAST)
-#define NO_PAD		(1 << 16)
+#define MX51EVK_USBH1_HUB_RST	IMX_GPIO_NR(1, 7)
+#define MX51EVK_USBH1_STP	IMX_GPIO_NR(1, 27)
+#define MX51EVK_USB_CLK_EN_B	IMX_GPIO_NR(2, 2)
+#define MX51EVK_USB_PHY_RESET	IMX_GPIO_NR(2, 5)
 
 static void setup_usb_h1(void)
 {
-	setup_iomux_usb_h1();
+	static const iomux_v3_cfg_t usb_h1_pads[] = {
+		MX51_PAD_USBH1_CLK__USBH1_CLK,
+		MX51_PAD_USBH1_DIR__USBH1_DIR,
+		MX51_PAD_USBH1_STP__USBH1_STP,
+		MX51_PAD_USBH1_NXT__USBH1_NXT,
+		MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+		MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+		MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+		MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+		MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+		MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+		MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+		MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 
-	/* GPIO_1_7 for USBH1 hub reset */
-	mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_GPIO1_7, NO_PAD);
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
+		MX51_PAD_EIM_D17__GPIO2_1,
+		MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
+	};
 
-	/* GPIO_2_1 */
-	mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D17, GPIO_PAD);
-
-	/* GPIO_2_5 for USB PHY reset */
-	mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D21, GPIO_PAD);
+	imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
 }
 
 int board_ehci_hcd_init(int port)
 {
 	/* Set USBH1_STP to GPIO and toggle it */
-	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
+						MX51_USBH_PAD_CTRL));
 
 	gpio_direction_output(MX51EVK_USBH1_STP, 0);
 	gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
@@ -225,8 +167,7 @@
 	gpio_set_value(MX51EVK_USBH1_STP, 1);
 
 	/* Set back USBH1_STP to be function */
-	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
+	imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
 
 	/* De-assert USB PHY RESETB */
 	gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
@@ -328,7 +269,8 @@
 		VVIDEOEN | VAUDIOEN  | VSDEN;
 	pmic_reg_write(p, REG_MODE_1, val);
 
-	mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
+						NO_PAD_CTRL));
 	gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
 
 	udelay(500);
@@ -342,9 +284,11 @@
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret;
 
-	mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
+						NO_PAD_CTRL));
 	gpio_direction_input(IMX_GPIO_NR(1, 0));
-	mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
+						NO_PAD_CTRL));
 	gpio_direction_input(IMX_GPIO_NR(1, 6));
 
 	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
@@ -357,6 +301,40 @@
 
 int board_mmc_init(bd_t *bis)
 {
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
+			PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
+	};
+
+	static const iomux_v3_cfg_t sd2_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
+	};
+
 	u32 index;
 	s32 status = 0;
 
@@ -367,98 +345,12 @@
 			index++) {
 		switch (index) {
 		case 0:
-			mxc_request_iomux(MX51_PIN_SD1_CMD,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_SD1_CLK,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_SD1_DATA0,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_SD1_DATA1,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_SD1_DATA2,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_SD1_DATA3,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
-				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_PUE_PULL |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
-				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-				PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
-				PAD_CTL_PUE_PULL |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
-				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_PUE_PULL |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
-				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_PUE_PULL |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
-				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_PUE_PULL |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
-				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
-				PAD_CTL_PUE_PULL |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-			mxc_request_iomux(MX51_PIN_GPIO1_0,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
-				PAD_CTL_HYS_ENABLE);
-			mxc_request_iomux(MX51_PIN_GPIO1_1,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
-				PAD_CTL_HYS_ENABLE);
+			imx_iomux_v3_setup_multiple_pads(sd1_pads,
+							 ARRAY_SIZE(sd1_pads));
 			break;
 		case 1:
-			mxc_request_iomux(MX51_PIN_SD2_CMD,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_SD2_CLK,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_SD2_DATA0,
-				IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX51_PIN_SD2_DATA1,
-				IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX51_PIN_SD2_DATA2,
-				IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX51_PIN_SD2_DATA3,
-				IOMUX_CONFIG_ALT0);
-			mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
-				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
-				PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
-				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
-				PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
-				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
-				PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
-				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
-				PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
-				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
-				PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
-				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
-				PAD_CTL_SRE_FAST);
-			mxc_request_iomux(MX51_PIN_SD2_CMD,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_GPIO1_6,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
-				PAD_CTL_HYS_ENABLE);
-			mxc_request_iomux(MX51_PIN_GPIO1_5,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
-				PAD_CTL_HYS_ENABLE);
+			imx_iomux_v3_setup_multiple_pads(sd2_pads,
+							 ARRAY_SIZE(sd2_pads));
 			break;
 		default:
 			printf("Warning: you configured more ESDHC controller"
diff --git a/board/freescale/mx51evk/mx51evk_video.c b/board/freescale/mx51evk/mx51evk_video.c
index 7be5c9b..556cb38 100644
--- a/board/freescale/mx51evk/mx51evk_video.c
+++ b/board/freescale/mx51evk/mx51evk_video.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <linux/list.h>
 #include <asm/gpio.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx51.h>
 #include <linux/fb.h>
 #include <ipu_pixfmt.h>
 
@@ -67,25 +67,25 @@
 void setup_iomux_lcd(void)
 {
 	/* DI2_PIN15 */
-	mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4);
+	imx_iomux_v3_setup_pad(MX51_PAD_DI_GP4__DI2_PIN15);
 
-	/* Pad settings for MX51_PIN_DI2_DISP_CLK */
-	mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE |
-			  PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-			  PAD_CTL_DRV_MAX | PAD_CTL_SRE_SLOW);
+	/* Pad settings for DI2_DISP_CLK */
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK,
+			    PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW));
 
 	/* Turn on 3.3V voltage for LCD */
-	mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D12__GPIO4_9,
+						NO_PAD_CTRL));
 	gpio_direction_output(MX51EVK_LCD_3V3, 1);
 
 	/* Turn on 5V voltage for LCD */
-	mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D13__GPIO4_10,
+						NO_PAD_CTRL));
 	gpio_direction_output(MX51EVK_LCD_5V, 1);
 
 	/* Turn on GPIO backlight */
-	mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
-	mxc_iomux_set_input(MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
-							INPUT_CTL_PATH1);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4,
+						NO_PAD_CTRL));
 	gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
 }
 
diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg
index 4633e4d..a103d95 100644
--- a/board/freescale/mx53ard/imximage_dd3.cfg
+++ b/board/freescale/mx53ard/imximage_dd3.cfg
@@ -20,7 +20,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c
index 8d433a3..e2dbf63 100644
--- a/board/freescale/mx53ard/mx53ard.c
+++ b/board/freescale/mx53ard/mx53ard.c
@@ -23,11 +23,10 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
 #include <asm/errno.h>
 #include <netdev.h>
 #include <mmc.h>
@@ -61,9 +60,42 @@
 #ifdef CONFIG_NAND_MXC
 static void setup_iomux_nand(void)
 {
+	static const iomux_v3_cfg_t nand_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
+				PAD_CTL_PUS_100K_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
+				PAD_CTL_PUS_100K_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+	};
+
 	u32 i, reg;
-	#define M4IF_GENP_WEIM_MM_MASK		0x00000001
-	#define WEIM_GCR2_MUX16_BYP_GRANT_MASK	0x00001000
 
 	reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
 	reg &= ~M4IF_GENP_WEIM_MM_MASK;
@@ -74,48 +106,7 @@
 		__raw_writel(reg, WEIM_BASE_ADDR + i);
 	}
 
-	mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
-	mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
-	mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA0, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA1, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA2, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA3, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA4, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA5, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA6, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
 }
 #else
 static void setup_iomux_nand(void)
@@ -123,24 +114,17 @@
 }
 #endif
 
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
 static void setup_iomux_uart(void)
 {
-	/* UART1 RXD */
-	mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX53_PIN_ATA_DMACK,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
+	static const iomux_v3_cfg_t uart_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL),
+	};
 
-	/* UART1 TXD */
-	mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX53_PIN_ATA_DIOW,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
 #ifdef CONFIG_FSL_ESDHC
@@ -154,9 +138,9 @@
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret;
 
-	mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
 	gpio_direction_input(IMX_GPIO_NR(1, 1));
-	mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);
 	gpio_direction_input(IMX_GPIO_NR(1, 4));
 
 	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
@@ -167,8 +151,36 @@
 	return ret;
 }
 
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_CLK_PAD_CTRL		(PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
 int board_mmc_init(bd_t *bis)
 {
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+	};
+
+	static const iomux_v3_cfg_t sd2_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL),
+	};
+
 	u32 index;
 	s32 status = 0;
 
@@ -178,56 +190,12 @@
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:
-			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA0,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA1,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA2,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA3,
-						IOMUX_CONFIG_ALT0);
-
-			mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
-			mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
+			imx_iomux_v3_setup_multiple_pads(sd1_pads,
+							 ARRAY_SIZE(sd1_pads));
 			break;
 		case 1:
-			mxc_request_iomux(MX53_PIN_SD2_CMD,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX53_PIN_SD2_CLK,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX53_PIN_SD2_DATA0,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD2_DATA1,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD2_DATA2,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD2_DATA3,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_ATA_DATA12,
-						IOMUX_CONFIG_ALT2);
-			mxc_request_iomux(MX53_PIN_ATA_DATA13,
-						IOMUX_CONFIG_ALT2);
-			mxc_request_iomux(MX53_PIN_ATA_DATA14,
-						IOMUX_CONFIG_ALT2);
-			mxc_request_iomux(MX53_PIN_ATA_DATA15,
-						IOMUX_CONFIG_ALT2);
-
-			mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4);
-			mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4);
-			mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4);
+			imx_iomux_v3_setup_multiple_pads(sd2_pads,
+							 ARRAY_SIZE(sd2_pads));
 			break;
 		default:
 			printf("Warning: you configured more ESDHC controller"
@@ -244,85 +212,70 @@
 
 static void weim_smc911x_iomux(void)
 {
+	static const iomux_v3_cfg_t weim_smc911x_pads[] = {
+		/* Data bus */
+		NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+
+		/* Address lines */
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+
+		/* other EIM signals for ethernet */
+		MX53_PAD_EIM_OE__EMI_WEIM_OE,
+		MX53_PAD_EIM_RW__EMI_WEIM_RW,
+		MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
+	};
+
 	/* ETHERNET_INT as GPIO2_31 */
-	mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31);
 	gpio_direction_input(ETHERNET_INT);
 
-	/* Data bus */
-	mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4);
-
-	/* Address lines */
-	mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4);
-
-	/* other EIM signals for ethernet */
-	mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0);
+	/* WEIM bus */
+	imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads,
+						ARRAY_SIZE(weim_smc911x_pads));
 }
 
 static void weim_cs1_settings(void)
diff --git a/board/freescale/mx53evk/imximage.cfg b/board/freescale/mx53evk/imximage.cfg
index 1cd61d5..c1cfdda 100644
--- a/board/freescale/mx53evk/imximage.cfg
+++ b/board/freescale/mx53evk/imximage.cfg
@@ -20,7 +20,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
index 1273501..727ad65 100644
--- a/board/freescale/mx53evk/mx53evk.c
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -23,11 +23,10 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
 #include <asm/errno.h>
 #include <asm/imx-common/boot_mode.h>
 #include <netdev.h>
@@ -49,69 +48,42 @@
 	return 0;
 }
 
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
 static void setup_iomux_uart(void)
 {
-	/* UART1 RXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
+	static const iomux_v3_cfg_t uart_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
+	};
 
-	/* UART1 TXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
+#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_HYS | PAD_CTL_ODE)
+
 static void setup_i2c(unsigned int port_number)
 {
+	static const iomux_v3_cfg_t i2c1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
+	};
+
+	static const iomux_v3_cfg_t i2c2_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL),
+	};
+
 	switch (port_number) {
 	case 0:
-		/* i2c1 SDA */
-		mxc_request_iomux(MX53_PIN_CSI0_D8,
-				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
-		mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
-				INPUT_CTL_PATH0);
-		mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
-				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
-				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
-		/* i2c1 SCL */
-		mxc_request_iomux(MX53_PIN_CSI0_D9,
-				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
-		mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
-				INPUT_CTL_PATH0);
-		mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
-				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
-				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+		imx_iomux_v3_setup_multiple_pads(i2c1_pads,
+							ARRAY_SIZE(i2c1_pads));
 		break;
 	case 1:
-		/* i2c2 SDA */
-		mxc_request_iomux(MX53_PIN_KEY_ROW3,
-				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
-		mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
-				INPUT_CTL_PATH0);
-		mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
-				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
-				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
-
-		/* i2c2 SCL */
-		mxc_request_iomux(MX53_PIN_KEY_COL3,
-				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
-		mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
-				INPUT_CTL_PATH0);
-		mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
-				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
-				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+		imx_iomux_v3_setup_multiple_pads(i2c2_pads,
+							ARRAY_SIZE(i2c2_pads));
 		break;
 	default:
 		printf("Warning: Wrong I2C port number\n");
@@ -160,54 +132,26 @@
 
 static void setup_iomux_fec(void)
 {
-	/*FEC_MDIO*/
-	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+	};
 
-	/*FEC_MDC*/
-	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
-
-	/* FEC RXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC RXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	 /* FEC TXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
-
-	/* FEC TXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_EN */
-	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_CLK */
-	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC RX_ER */
-	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC CRS */
-	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 #ifdef CONFIG_FSL_ESDHC
@@ -221,9 +165,9 @@
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret;
 
-	mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
 	gpio_direction_input(IMX_GPIO_NR(3, 11));
-	mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
 	gpio_direction_input(IMX_GPIO_NR(3, 13));
 
 	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
@@ -234,8 +178,38 @@
 	return ret;
 }
 
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
 int board_mmc_init(bd_t *bis)
 {
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+		MX53_PAD_EIM_DA13__GPIO3_13,
+	};
+
+	static const iomux_v3_cfg_t sd2_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+				SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
+		MX53_PAD_EIM_DA11__GPIO3_11,
+	};
+
 	u32 index;
 	s32 status = 0;
 
@@ -245,109 +219,12 @@
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:
-			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA0,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA1,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA2,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA3,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_EIM_DA13,
-						IOMUX_CONFIG_ALT1);
-
-			mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_DRV_HIGH);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			imx_iomux_v3_setup_multiple_pads(sd1_pads,
+							 ARRAY_SIZE(sd1_pads));
 			break;
 		case 1:
-			mxc_request_iomux(MX53_PIN_ATA_RESET_B,
-						IOMUX_CONFIG_ALT2);
-			mxc_request_iomux(MX53_PIN_ATA_IORDY,
-						IOMUX_CONFIG_ALT2);
-			mxc_request_iomux(MX53_PIN_ATA_DATA8,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA9,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA10,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA11,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA0,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA1,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA2,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA3,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_EIM_DA11,
-						IOMUX_CONFIG_ALT1);
-
-			mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_DRV_HIGH);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-
+			imx_iomux_v3_setup_multiple_pads(sd2_pads,
+							 ARRAY_SIZE(sd2_pads));
 			break;
 		default:
 			printf("Warning: you configured more ESDHC controller"
diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg
index e6b90c1..2f75ad0 100644
--- a/board/freescale/mx53loco/imximage.cfg
+++ b/board/freescale/mx53loco/imximage.cfg
@@ -20,7 +20,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index 8f39c38..10e9d36 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -24,11 +24,10 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
 #include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/imx-common/mx5_video.h>
@@ -82,86 +81,51 @@
 	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
 }
 
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
 static void setup_iomux_uart(void)
 {
-	/* UART1 RXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
+	static const iomux_v3_cfg_t uart_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
+	};
 
-	/* UART1 TXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
 #ifdef CONFIG_USB_EHCI_MX5
 int board_ehci_hcd_init(int port)
 {
 	/* request VBUS power enable pin, GPIO7_8 */
-	mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
+	imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
+	gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
 	return 0;
 }
 #endif
 
 static void setup_iomux_fec(void)
 {
-	/*FEC_MDIO*/
-	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+	};
 
-	/*FEC_MDC*/
-	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
-
-	/* FEC RXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC RXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	 /* FEC TXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
-
-	/* FEC TXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_EN */
-	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_CLK */
-	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC RX_ER */
-	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC CRS */
-	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 #ifdef CONFIG_FSL_ESDHC
@@ -175,9 +139,9 @@
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret;
 
-	mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
 	gpio_direction_input(IMX_GPIO_NR(3, 11));
-	mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
 	gpio_direction_input(IMX_GPIO_NR(3, 13));
 
 	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
@@ -188,8 +152,38 @@
 	return ret;
 }
 
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
 int board_mmc_init(bd_t *bis)
 {
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+		MX53_PAD_EIM_DA13__GPIO3_13,
+	};
+
+	static const iomux_v3_cfg_t sd2_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+				SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
+		MX53_PAD_EIM_DA11__GPIO3_11,
+	};
+
 	u32 index;
 	s32 status = 0;
 
@@ -199,109 +193,12 @@
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:
-			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA0,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA1,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA2,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA3,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_EIM_DA13,
-						IOMUX_CONFIG_ALT1);
-
-			mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_DRV_HIGH);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			imx_iomux_v3_setup_multiple_pads(sd1_pads,
+							 ARRAY_SIZE(sd1_pads));
 			break;
 		case 1:
-			mxc_request_iomux(MX53_PIN_ATA_RESET_B,
-						IOMUX_CONFIG_ALT2);
-			mxc_request_iomux(MX53_PIN_ATA_IORDY,
-						IOMUX_CONFIG_ALT2);
-			mxc_request_iomux(MX53_PIN_ATA_DATA8,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA9,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA10,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA11,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA0,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA1,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA2,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA3,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_EIM_DA11,
-						IOMUX_CONFIG_ALT1);
-
-			mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_DRV_HIGH);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-
+			imx_iomux_v3_setup_multiple_pads(sd2_pads,
+							 ARRAY_SIZE(sd2_pads));
 			break;
 		default:
 			printf("Warning: you configured more ESDHC controller"
@@ -316,28 +213,17 @@
 }
 #endif
 
+#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
 static void setup_iomux_i2c(void)
 {
-	/* I2C1 SDA */
-	mxc_request_iomux(MX53_PIN_CSI0_D8,
-		IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
-	mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
-		PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
-		PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	/* I2C1 SCL */
-	mxc_request_iomux(MX53_PIN_CSI0_D9,
-		IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
-	mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
-		PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
-		PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	static const iomux_v3_cfg_t i2c1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
 }
 
 static int power_init(void)
diff --git a/board/freescale/mx53loco/mx53loco_video.c b/board/freescale/mx53loco/mx53loco_video.c
index a4d5a6a..c4654c9 100644
--- a/board/freescale/mx53loco/mx53loco_video.c
+++ b/board/freescale/mx53loco/mx53loco_video.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <linux/list.h>
 #include <asm/gpio.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
 #include <linux/fb.h>
 #include <ipu_pixfmt.h>
 
@@ -63,42 +63,46 @@
 
 void setup_iomux_lcd(void)
 {
-	mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0);
+	static const iomux_v3_cfg_t lcd_pads[] = {
+		MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
+		MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
+		MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
+		MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
+		MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
+		MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
+		MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
+		MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
+		MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
+		MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
+		MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
+		MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
+		MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
+		MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
+		MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
+		MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
+		MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
+		MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
+		MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
+		MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
+		MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
+		MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
+		MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
+		MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
+		MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
+		MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
+		MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
+		MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 
 	/* Turn on GPIO backlight */
-	mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_D24__GPIO3_24);
 	gpio_direction_output(MX53LOCO_LCD_POWER, 1);
 
 	/* Turn on display contrast */
-	mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1);
+	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+	gpio_direction_output(IMX_GPIO_NR(1, 1), 1);
 }
 
 int board_video_skip(void)
diff --git a/board/freescale/mx53smd/imximage.cfg b/board/freescale/mx53smd/imximage.cfg
index 4633e4d..a103d95 100644
--- a/board/freescale/mx53smd/imximage.cfg
+++ b/board/freescale/mx53smd/imximage.cfg
@@ -20,7 +20,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c
index 761f727..d04f44f 100644
--- a/board/freescale/mx53smd/mx53smd.c
+++ b/board/freescale/mx53smd/mx53smd.c
@@ -23,11 +23,10 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
 #include <asm/errno.h>
 #include <netdev.h>
 #include <mmc.h>
@@ -56,76 +55,41 @@
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 }
 
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
 static void setup_iomux_uart(void)
 {
-	/* UART1 RXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
+	static const iomux_v3_cfg_t uart_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
+	};
 
-	/* UART1 TXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
 static void setup_iomux_fec(void)
 {
-	/*FEC_MDIO*/
-	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+	};
 
-	/*FEC_MDC*/
-	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
-
-	/* FEC RXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC RXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	 /* FEC TXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
-
-	/* FEC TXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_EN */
-	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_CLK */
-	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC RX_ER */
-	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC CRS */
-	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 #ifdef CONFIG_FSL_ESDHC
@@ -135,13 +99,28 @@
 
 int board_mmc_getcd(struct mmc *mmc)
 {
-	mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
 	gpio_direction_input(IMX_GPIO_NR(3, 13));
 	return !gpio_get_value(IMX_GPIO_NR(3, 13));
 }
 
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
 int board_mmc_init(bd_t *bis)
 {
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+		MX53_PAD_EIM_DA13__GPIO3_13,
+	};
+
 	u32 index;
 	s32 status = 0;
 
@@ -150,43 +129,8 @@
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:
-			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA0,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA1,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA2,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA3,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_EIM_DA13,
-						IOMUX_CONFIG_ALT1);
-
-			mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_DRV_HIGH);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			imx_iomux_v3_setup_multiple_pads(sd1_pads,
+							 ARRAY_SIZE(sd1_pads));
 			break;
 
 		default:
diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg
index 4ed211e..6f18b37 100644
--- a/board/freescale/mx6qarm2/imximage.cfg
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -20,7 +20,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
index ff7f5e8..e336746 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -35,17 +35,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
-	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
 int dram_init(void)
 {
diff --git a/board/freescale/mx6qsabreauto/imximage.cfg b/board/freescale/mx6qsabreauto/imximage.cfg
index bbff813..e720c6b 100644
--- a/board/freescale/mx6qsabreauto/imximage.cfg
+++ b/board/freescale/mx6qsabreauto/imximage.cfg
@@ -19,7 +19,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index aec3286..bfe4868 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -35,17 +35,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
-	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
-	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
 int dram_init(void)
 {
@@ -179,7 +178,10 @@
 	 * i.MX6Q ARD RevB: 0x02
 	 */
 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-	int reg = readl(&ocotp->gp1);
+	struct fuse_bank *bank = &ocotp->bank[4];
+	struct fuse_bank4_regs *fuse =
+			(struct fuse_bank4_regs *)bank->fuse_regs;
+	int reg = readl(&fuse->gp1);
 	int ret;
 
 	switch (reg >> 8 & 0x0F) {
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 9f9cac8..8ce054e 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -45,29 +45,25 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |	       \
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	       \
-	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |	       \
-	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	       \
-	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
-#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
-	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
 	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
 
-#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
-#define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
 int dram_init(void)
diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c
index 0d7cb9e..2529826 100644
--- a/board/freescale/mx6qsabresd/mx6qsabresd.c
+++ b/board/freescale/mx6qsabresd/mx6qsabresd.c
@@ -34,17 +34,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
-	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
-	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
 int dram_init(void)
 {
@@ -166,6 +165,7 @@
 
 int board_mmc_init(bd_t *bis)
 {
+	s32 status = 0;
 	int i;
 
 	/*
@@ -196,15 +196,15 @@
 			break;
 		default:
 			printf("Warning: you configured more USDHC controllers"
-				"(%d) than supported by the board\n", i + 1);
-			return 0;
-	       }
+			       "(%d) then supported by the board (%d)\n",
+			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return status;
+		}
 
-	       if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
-			printf("Warning: failed to initialize mmc dev %d\n", i);
+		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 	}
 
-	return 0;
+	return status;
 }
 #endif
 
diff --git a/board/freescale/mx6slevk/Makefile b/board/freescale/mx6slevk/Makefile
new file mode 100644
index 0000000..43af351
--- /dev/null
+++ b/board/freescale/mx6slevk/Makefile
@@ -0,0 +1,28 @@
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := mx6slevk.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg
new file mode 100644
index 0000000..df39a16
--- /dev/null
+++ b/board/freescale/mx6slevk/imximage.cfg
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x020c4018 0x00260324
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020e0344 0x00003030
+DATA 4 0x020e0348 0x00003030
+DATA 4 0x020e034c 0x00003030
+DATA 4 0x020e0350 0x00003030
+DATA 4 0x020e030c 0x00000030
+DATA 4 0x020e0310 0x00000030
+DATA 4 0x020e0314 0x00000030
+DATA 4 0x020e0318 0x00000030
+DATA 4 0x020e0300 0x00000030
+DATA 4 0x020e031c 0x00000030
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e0320 0x00000030
+DATA 4 0x020e032c 0x00000000
+DATA 4 0x020e033c 0x00000008
+DATA 4 0x020e0340 0x00000008
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x020e05cc 0x00000030
+DATA 4 0x020e05d4 0x00000030
+DATA 4 0x020e05d8 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05c8 0x00000030
+DATA 4 0x020e05b0 0x00020000
+DATA 4 0x020e05b4 0x00000000
+DATA 4 0x020e05c0 0x00020000
+DATA 4 0x020e05d0 0x00080000
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b085c 0x1b4700c7
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b0890 0x00300000
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b082c 0xf3333333
+DATA 4 0x021b0830 0xf3333333
+DATA 4 0x021b0834 0xf3333333
+DATA 4 0x021b0838 0xf3333333
+DATA 4 0x021b0848 0x4241444a
+DATA 4 0x021b0850 0x3030312b
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x00000000
+DATA 4 0x021b08c0 0x24911492
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b000c 0x33374133
+DATA 4 0x021b0004 0x00020024
+DATA 4 0x021b0010 0x00100A82
+DATA 4 0x021b0014 0x00000093
+DATA 4 0x021b0018 0x00001688
+DATA 4 0x021b002c 0x0f9f26d2
+DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0038 0x00190778
+DATA 4 0x021b0008 0x00000000
+DATA 4 0x021b0040 0x0000004f
+DATA 4 0x021b0000 0xc3110000
+DATA 4 0x021b001c 0x003f8030
+DATA 4 0x021b001c 0xff0a8030
+DATA 4 0x021b001c 0x82018030
+DATA 4 0x021b001c 0x04028030
+DATA 4 0x021b001c 0x02038030
+DATA 4 0x021b001c 0xff0a8038
+DATA 4 0x021b001c 0x82018038
+DATA 4 0x021b001c 0x04028038
+DATA 4 0x021b001c 0x02038038
+DATA 4 0x021b0800 0xa1310003
+DATA 4 0x021b0020 0x00001800
+DATA 4 0x021b0818 0x00000000
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b0004 0x00025564
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
new file mode 100644
index 0000000..69fe8fc
--- /dev/null
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <asm/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;	/* Assume boot SD always present */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6SLEVK\n");
+
+	return 0;
+}
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index a706a6d..44d3e0c 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -227,6 +227,17 @@
 				"'00' is unsupported\n");
 		else
 			actual[i] = freq[i][clock];
+
+		/*
+		 * PC board uses a different CPLD with PB board, this CPLD
+		 * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
+		 * board has cpld_ver_sub = 0, and pcba_ver = 4.
+		 */
+		if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
+		    (CPLD_READ(pcba_ver) == 5)) {
+			/* PC board bank2 frequency */
+			actual[i] = freq[i-1][clock];
+		}
 	}
 
 	for (i = 0; i < NUM_SRDS_BANKS; i++) {
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 692616a..058d625 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -19,6 +19,7 @@
 struct board_specific_parameters {
 	u32 n_ranks;
 	u32 datarate_mhz_high;
+	u32 rank_gb;
 	u32 clk_adjust;
 	u32 wrlvl_start;
 	u32 wrlvl_ctl_2;
@@ -36,16 +37,19 @@
 static const struct board_specific_parameters udimm0[] = {
 	/*
 	 * memory controller 0
-	 *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
-	{2,  1350,    5,     7, 0x0809090b, 0x0c0c0d09,   0xff,    2,  0},
-	{2,  1666,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{2,  2140,    5,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-	{1,  1350,    5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{1,  1700,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{1,  1900,    4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-	{1,  2140,    4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
+	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
+	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
+	{2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+	{2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
+	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
 	{}
 };
 
@@ -61,19 +65,19 @@
 static const struct board_specific_parameters rdimm0[] = {
 	/*
 	 * memory controller 0
-	 *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
-	{4,  1350,    5,     9, 0x08070605, 0x07080805,   0xff,    2,  0},
-	{4,  1666,    5,     8, 0x08070605, 0x07080805,   0xff,    2,  0},
-	{4,  2140,    5,     8, 0x08070605, 0x07081805,   0xff,    2,  0},
-	{2,  1350,    5,     7, 0x0809090b, 0x0c0c0d09,   0xff,    2,  0},
-	{2,  1666,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{2,  2140,    5,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-	{1,  1350,    5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{1,  1700,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{1,  1900,    4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-	{1,  2140,    4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{4,  1350, 0, 5,     9, 0x08070605, 0x07080805,   0xff,    2,  0},
+	{4,  1666, 0, 5,     8, 0x08070605, 0x07080805,   0xff,    2,  0},
+	{4,  2140, 0, 5,     8, 0x08070605, 0x07081805,   0xff,    2,  0},
+	{2,  1350, 0, 5,     7, 0x0809090b, 0x0c0c0d09,   0xff,    2,  0},
+	{2,  1666, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{2,  2140, 0, 5,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
+	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
 	{}
 };
 
@@ -113,7 +117,8 @@
 	 */
 	ddr_freq = get_ddr_freq(0) / 1000000;
 	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks) {
+		if (pbsp->n_ranks == pdimm->n_ranks &&
+		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
 			if (ddr_freq <= pbsp->datarate_mhz_high) {
 				popts->cpo_override = pbsp->cpo;
 				popts->write_data_delay =
@@ -146,6 +151,13 @@
 		panic("DIMM is not supported by this board");
 	}
 found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+		"wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
 	/*
 	 * Factors to consider for half-strength driver enable:
 	 *	- number of DIMMs installed
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index a49c7d4..7103a0d 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -52,7 +52,7 @@
 #define EMI1_SLOT4	4
 #define EMI1_SLOT5	5
 #define EMI1_SLOT7	7
-#define EMI2		8 /* tmp, FIXME */
+#define EMI2		8
 /* Slot6 and Slot8 do not have EMI connections */
 
 static int mdio_mux[NUM_FM_PORTS];
@@ -71,6 +71,14 @@
 
 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
+static u8 slot_qsgmii_phyaddr[5][4] = {
+	{0, 0, 0, 0},/* not used, to make index match slot No. */
+	{0, 1, 2, 3},
+	{4, 5, 6, 7},
+	{8, 9, 0xa, 0xb},
+	{0xc, 0xd, 0xe, 0xf},
+};
+static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
 
 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
 {
@@ -180,21 +188,228 @@
 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 				enum fm_port port, int offset)
 {
-	if (mdio_mux[port] == EMI1_RGMII)
-		fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
-
-	/* TODO: will do with dts */
+	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+		switch (port) {
+		case FM1_DTSEC1:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						   "sgmii_phy21");
+			break;
+		case FM1_DTSEC2:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						   "sgmii_phy22");
+			break;
+		case FM1_DTSEC3:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						   "sgmii_phy23");
+			break;
+		case FM1_DTSEC4:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						   "sgmii_phy24");
+			break;
+		case FM1_DTSEC6:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						   "sgmii_phy12");
+			break;
+		case FM1_DTSEC9:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						   "sgmii_phy14");
+			else
+				fdt_set_phy_handle(blob, prop, pa,
+						   "phy_sgmii4");
+			break;
+		case FM1_DTSEC10:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						   "sgmii_phy13");
+			else
+				fdt_set_phy_handle(blob, prop, pa,
+						   "phy_sgmii3");
+			break;
+		case FM2_DTSEC1:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						   "sgmii_phy41");
+			break;
+		case FM2_DTSEC2:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						   "sgmii_phy42");
+			break;
+		case FM2_DTSEC3:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						   "sgmii_phy43");
+			break;
+		case FM2_DTSEC4:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						   "sgmii_phy44");
+			break;
+		case FM2_DTSEC6:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						   "sgmii_phy32");
+			break;
+		case FM2_DTSEC9:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						   "sgmii_phy34");
+			else
+				fdt_set_phy_handle(blob, prop, pa,
+						   "phy_sgmii12");
+			break;
+		case FM2_DTSEC10:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						   "sgmii_phy33");
+			else
+				fdt_set_phy_handle(blob, prop, pa,
+						   "phy_sgmii11");
+			break;
+		default:
+			break;
+		}
+	}
 }
 
 void fdt_fixup_board_enet(void *fdt)
 {
-	/* TODO: will do with dts */
+	int i;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+	prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+	for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			switch (mdio_mux[i]) {
+			case EMI1_SLOT1:
+				fdt_status_okay_by_alias(fdt, "emi1_slot1");
+				break;
+			case EMI1_SLOT2:
+				fdt_status_okay_by_alias(fdt, "emi1_slot2");
+				break;
+			case EMI1_SLOT3:
+				fdt_status_okay_by_alias(fdt, "emi1_slot3");
+				break;
+			case EMI1_SLOT4:
+				fdt_status_okay_by_alias(fdt, "emi1_slot4");
+				break;
+			default:
+				break;
+			}
+			break;
+		case PHY_INTERFACE_MODE_XGMII:
+			/* check if it's XFI interface for 10g */
+			if ((prtcl2 == 56) || (prtcl2 == 57)) {
+				fdt_status_okay_by_alias(fdt, "emi2_xfislot3");
+				break;
+			}
+			switch (i) {
+			case FM1_10GEC1:
+				fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
+				break;
+			case FM1_10GEC2:
+				fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
+				break;
+			case FM2_10GEC1:
+				fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
+				break;
+			case FM2_10GEC2:
+				fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
+				break;
+			default:
+				break;
+			}
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+static void initialize_qsgmiiphy_fix(void)
+{
+	int i;
+	unsigned short reg;
+
+	for (i = 1; i <= 4; i++) {
+		/*
+		 * Try to read if a SGMII card is used, we do it slot by slot.
+		 * if a SGMII PHY address is valid on a slot, then we mark
+		 * all ports on the slot, then fix the PHY address for the
+		 * marked port when doing dtb fixup.
+		 */
+		if (miiphy_read(mdio_names[i],
+				SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {
+			debug("Slot%d PHY ID register 2 read failed\n", i);
+			continue;
+		}
+
+		debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
+
+		if (reg == 0xFFFF) {
+			/* No physical device present at this address */
+			continue;
+		}
+
+		switch (i) {
+		case 1:
+			qsgmiiphy_fix[FM1_DTSEC5] = 1;
+			qsgmiiphy_fix[FM1_DTSEC6] = 1;
+			qsgmiiphy_fix[FM1_DTSEC9] = 1;
+			qsgmiiphy_fix[FM1_DTSEC10] = 1;
+			slot_qsgmii_phyaddr[1][0] =  SGMII_CARD_PORT1_PHY_ADDR;
+			slot_qsgmii_phyaddr[1][1] =  SGMII_CARD_PORT2_PHY_ADDR;
+			slot_qsgmii_phyaddr[1][2] =  SGMII_CARD_PORT3_PHY_ADDR;
+			slot_qsgmii_phyaddr[1][3] =  SGMII_CARD_PORT4_PHY_ADDR;
+			break;
+		case 2:
+			qsgmiiphy_fix[FM1_DTSEC1] = 1;
+			qsgmiiphy_fix[FM1_DTSEC2] = 1;
+			qsgmiiphy_fix[FM1_DTSEC3] = 1;
+			qsgmiiphy_fix[FM1_DTSEC4] = 1;
+			slot_qsgmii_phyaddr[2][0] =  SGMII_CARD_PORT1_PHY_ADDR;
+			slot_qsgmii_phyaddr[2][1] =  SGMII_CARD_PORT2_PHY_ADDR;
+			slot_qsgmii_phyaddr[2][2] =  SGMII_CARD_PORT3_PHY_ADDR;
+			slot_qsgmii_phyaddr[2][3] =  SGMII_CARD_PORT4_PHY_ADDR;
+			break;
+		case 3:
+			qsgmiiphy_fix[FM2_DTSEC5] = 1;
+			qsgmiiphy_fix[FM2_DTSEC6] = 1;
+			qsgmiiphy_fix[FM2_DTSEC9] = 1;
+			qsgmiiphy_fix[FM2_DTSEC10] = 1;
+			slot_qsgmii_phyaddr[3][0] =  SGMII_CARD_PORT1_PHY_ADDR;
+			slot_qsgmii_phyaddr[3][1] =  SGMII_CARD_PORT2_PHY_ADDR;
+			slot_qsgmii_phyaddr[3][2] =  SGMII_CARD_PORT3_PHY_ADDR;
+			slot_qsgmii_phyaddr[3][3] =  SGMII_CARD_PORT4_PHY_ADDR;
+			break;
+		case 4:
+			qsgmiiphy_fix[FM2_DTSEC1] = 1;
+			qsgmiiphy_fix[FM2_DTSEC2] = 1;
+			qsgmiiphy_fix[FM2_DTSEC3] = 1;
+			qsgmiiphy_fix[FM2_DTSEC4] = 1;
+			slot_qsgmii_phyaddr[4][0] =  SGMII_CARD_PORT1_PHY_ADDR;
+			slot_qsgmii_phyaddr[4][1] =  SGMII_CARD_PORT2_PHY_ADDR;
+			slot_qsgmii_phyaddr[4][2] =  SGMII_CARD_PORT3_PHY_ADDR;
+			slot_qsgmii_phyaddr[4][3] =  SGMII_CARD_PORT4_PHY_ADDR;
+			break;
+		default:
+			break;
+		}
+	}
 }
 
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FMAN_ENET)
-	int i;
+	int i, idx, lane, slot;
 	struct memac_mdio_info dtsec_mdio_info;
 	struct memac_mdio_info tgec_mdio_info;
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -236,6 +451,7 @@
 	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
 	t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 
+	initialize_qsgmiiphy_fix();
 
 	switch (srds_prtcl_s1) {
 	case 1:
@@ -248,44 +464,48 @@
 	case 28:
 	case 36:
 		/* SGMII in Slot1 and Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+		fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+		fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+		fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
+		fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 		if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 			fm_info_set_phy_address(FM1_DTSEC9,
-						SGMII_CARD_PORT4_PHY_ADDR);
+						slot_qsgmii_phyaddr[1][3]);
 			fm_info_set_phy_address(FM1_DTSEC10,
-						SGMII_CARD_PORT3_PHY_ADDR);
+						slot_qsgmii_phyaddr[1][2]);
 		}
 		break;
 	case 38:
-		fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+		fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+		fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+		fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
+		fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 		if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 			fm_info_set_phy_address(FM1_DTSEC9,
-						QSGMII_CARD_PHY_ADDR);
+						slot_qsgmii_phyaddr[1][3]);
 			fm_info_set_phy_address(FM1_DTSEC10,
-						QSGMII_CARD_PHY_ADDR);
+						slot_qsgmii_phyaddr[1][2]);
 		}
 		break;
 	case 40:
 	case 46:
 	case 48:
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 		if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 			fm_info_set_phy_address(FM1_DTSEC10,
-						SGMII_CARD_PORT3_PHY_ADDR);
+						slot_qsgmii_phyaddr[1][3]);
 			fm_info_set_phy_address(FM1_DTSEC9,
-						SGMII_CARD_PORT4_PHY_ADDR);
+						slot_qsgmii_phyaddr[1][2]);
 		}
-		fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+		fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+		fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+		fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 		break;
 	default:
 		puts("Invalid SerDes1 protocol for T4240QDS\n");
@@ -293,7 +513,7 @@
 	}
 
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		int idx = i - FM1_DTSEC1, lane, slot;
+		idx = i - FM1_DTSEC1;
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_SGMII:
 			lane = serdes_get_first_lane(FSL_SRDS_1,
@@ -334,8 +554,16 @@
 	}
 
 	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+		idx = i - FM1_10GEC1;
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_XGMII:
+			lane = serdes_get_first_lane(FSL_SRDS_1,
+						XAUI_FM1_MAC9 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot_fsm1[lane];
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
 			mdio_mux[i] = EMI2;
 			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 			break;
@@ -344,7 +572,6 @@
 		}
 	}
 
-
 #if (CONFIG_SYS_NUM_FMAN == 2)
 	switch (srds_prtcl_s2) {
 	case 1:
@@ -364,68 +591,64 @@
 	case 26:
 		/* XAUI/HiGig in Slot3, SGMII in Slot4 */
 		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
 	case 28:
 	case 36:
 		/* SGMII in Slot3 and Slot4 */
-		fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
+		fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+		fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
+		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 		break;
 	case 38:
 		/* QSGMII in Slot3 and Slot4 */
-		fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
+		fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+		fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
+		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 		break;
 	case 40:
 	case 46:
 	case 48:
 		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+		fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
+		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 		/* QSGMII in Slot4 */
-		fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
 	case 50:
 	case 52:
 	case 54:
 		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
 	case 56:
 	case 57:
 		/* XFI in Slot3, SGMII in Slot4 */
-		fm_info_set_phy_address(FM1_10GEC1, XFI_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_10GEC2, XFI_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_10GEC2, XFI_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM2_10GEC1, XFI_CARD_PORT4_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
 	default:
 		puts("Invalid SerDes2 protocol for T4240QDS\n");
@@ -433,7 +656,7 @@
 	}
 
 	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
-		int idx = i - FM2_DTSEC1, lane, slot;
+		idx = i - FM2_DTSEC1;
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_SGMII:
 			lane = serdes_get_first_lane(FSL_SRDS_2,
@@ -477,8 +700,16 @@
 	}
 
 	for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
+		idx = i - FM2_10GEC1;
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_XGMII:
+			lane = serdes_get_first_lane(FSL_SRDS_2,
+						XAUI_FM2_MAC9 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot_fsm2[lane];
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
 			mdio_mux[i] = EMI2;
 			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 			break;
diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c
index 6f2c5c8..f3848f3 100644
--- a/board/freescale/t4qds/law.c
+++ b/board/freescale/t4qds/law.c
@@ -37,7 +37,8 @@
 #endif
 	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
 #ifdef CONFIG_SYS_NAND_BASE_PHYS
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
diff --git a/board/freescale/t4qds/t4240qds_qixis.h b/board/freescale/t4qds/t4240qds_qixis.h
index efb718d..485353d 100644
--- a/board/freescale/t4qds/t4240qds_qixis.h
+++ b/board/freescale/t4qds/t4240qds_qixis.h
@@ -42,7 +42,7 @@
 #define QIXIS_DDRCLK_125		0x2
 #define QIXIS_DDRCLK_133		0x3
 
-#define BRDCFG5_RESET			0x00
+#define BRDCFG5_IRE			0x20	/* i2c Remote i2c1 enable */
 
 #define BRDCFG12_SD3EN_MASK		0x20
 #define BRDCFG12_SD3MX_MASK		0x08
diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg
new file mode 100644
index 0000000..c598fb5
--- /dev/null
+++ b/board/freescale/t4qds/t4_pbi.cfg
@@ -0,0 +1,36 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#workaround for IFC bus speed
+091241c0 f03f3f3f
+091241c4 ff003f3f
+09124010 00000101
+09124130 0000000c
+#workaround for SERDES A-006031
+090ea000 064740e6
+090ea020 064740e6
+090eb000 064740e6
+090eb020 064740e6
+090ec000 064740e6
+090ec020 064740e6
+090ed000 064740e6
+090ed020 064740e6
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
new file mode 100644
index 0000000..6ac95ff
--- /dev/null
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#serdes protocol  1_28_6_12
+14180019 0c101916 00000000 00000000
+04383060 30548c00 6c020000 19000000
+00000000 ee0000ee 00000000 000187fc
+00000000 00000000 00000000 00000018
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index 3c95f3f..f0f280b 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -110,7 +110,7 @@
 	for (i = 0; i < MAX_SERDES; i++) {
 		static const char *freq[] = {
 			"100", "125", "156.25", "161.1328125"};
-		unsigned int clock = (sw >> (2 * i)) & 3;
+		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
 
 		printf("SERDES%u=%sMHz ", i+1, freq[clock]);
 	}
@@ -132,6 +132,243 @@
 	return 0;
 }
 
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for 532us befor another reading
+ */
+#define NUM_READINGS	4	/* prefer to be power of 2 for efficiency */
+#define WAIT_FOR_ADC	532	/* wait for 532 microseconds for ADC */
+
+static inline int read_voltage(void)
+{
+	int i, ret, voltage_read = 0;
+	u16 vol_mon;
+
+	for (i = 0; i < NUM_READINGS; i++) {
+		ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+			I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
+		if (ret) {
+			printf("VID: failed to read core voltage\n");
+			return ret;
+		}
+		if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
+			printf("VID: Core voltage sensor error\n");
+			return -1;
+		}
+		debug("VID: bus voltage reads 0x%04x\n", vol_mon);
+		/* LSB = 4mv */
+		voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
+		udelay(WAIT_FOR_ADC);
+	}
+	/* calculate the average */
+	voltage_read /= NUM_READINGS;
+
+	return voltage_read;
+}
+
+/*
+ * We need to calculate how long before the voltage starts to drop or increase
+ * It returns with the loop count. Each loop takes several readings (532us)
+ */
+static inline int wait_for_voltage_change(int vdd_last)
+{
+	int timeout, vdd_current;
+
+	vdd_current = read_voltage();
+	/* wait until voltage starts to drop */
+	for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
+		timeout < 100; timeout++) {
+		vdd_current = read_voltage();
+	}
+	if (timeout >= 100) {
+		printf("VID: Voltage adjustment timeout\n");
+		return -1;
+	}
+	return timeout;
+}
+
+/*
+ * argument 'wait' is the time we know the voltage difference can be measured
+ * this function keeps reading the voltage until it is stable
+ */
+static inline int wait_for_voltage_stable(int wait)
+{
+	int timeout, vdd_current, vdd_last;
+
+	vdd_last = read_voltage();
+	udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
+	/* wait until voltage is stable */
+	vdd_current = read_voltage();
+	for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
+		timeout < 100; timeout++) {
+		vdd_last = vdd_current;
+		udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
+		vdd_current = read_voltage();
+	}
+	if (timeout >= 100) {
+		printf("VID: Voltage adjustment timeout\n");
+		return -1;
+	}
+
+	return vdd_current;
+}
+
+static inline int set_voltage(u8 vid)
+{
+	int wait, vdd_last;
+
+	vdd_last = read_voltage();
+	QIXIS_WRITE(brdcfg[6], vid);
+	wait = wait_for_voltage_change(vdd_last);
+	if (wait < 0)
+		return -1;
+	debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
+	wait = wait ? wait : 1;
+
+	vdd_last = wait_for_voltage_stable(wait);
+	if (vdd_last < 0)
+		return -1;
+	debug("VID: Current voltage is %d mV\n", vdd_last);
+
+	return vdd_last;
+}
+
+
+static int adjust_vdd(ulong vdd_override)
+{
+	int re_enable = disable_interrupts();
+	ccsr_gur_t __iomem *gur =
+		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 fusesr;
+	u8 vid, vid_current;
+	int vdd_target, vdd_current, vdd_last;
+	int ret;
+	unsigned long vdd_string_override;
+	char *vdd_string;
+	static const uint16_t vdd[32] = {
+		0,	/* unused */
+		9875,	/* 0.9875V */
+		9750,
+		9625,
+		9500,
+		9375,
+		9250,
+		9125,
+		9000,
+		8875,
+		8750,
+		8625,
+		8500,
+		8375,
+		8250,
+		8125,
+		10000,	/* 1.0000V */
+		10125,
+		10250,
+		10375,
+		10500,
+		10625,
+		10750,
+		10875,
+		11000,
+		0,	/* reserved */
+	};
+	struct vdd_drive {
+		u8 vid;
+		unsigned voltage;
+	};
+
+	ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
+	if (ret) {
+		debug("VID: I2c failed to switch channel\n");
+		ret = -1;
+		goto exit;
+	}
+
+	/* get the voltage ID from fuse status register */
+	fusesr = in_be32(&gur->dcfg_fusesr);
+	vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+		FSL_CORENET_DCFG_FUSESR_VID_MASK;
+	if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
+		vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+			FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+	}
+	vdd_target = vdd[vid];
+
+	/* check override variable for overriding VDD */
+	vdd_string = getenv("t4240qds_vdd_mv");
+	if (vdd_override == 0 && vdd_string &&
+	    !strict_strtoul(vdd_string, 10, &vdd_string_override))
+		vdd_override = vdd_string_override;
+	if (vdd_override >= 819 && vdd_override <= 1212) {
+		vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+		debug("VDD override is %lu\n", vdd_override);
+	} else if (vdd_override != 0) {
+		printf("Invalid value.\n");
+	}
+
+	if (vdd_target == 0) {
+		debug("VID: VID not used\n");
+		ret = 0;
+		goto exit;
+	} else {
+		/* round up and divice by 10 to get a value in mV */
+		vdd_target = DIV_ROUND_UP(vdd_target, 10);
+		debug("VID: vid = %d mV\n", vdd_target);
+	}
+
+	/*
+	 * Check current board VID setting
+	 * Voltage regulator support output to 6.250mv step
+	 * The highes voltage allowed for this board is (vid=0x40) 1.21250V
+	 * the lowest is (vid=0x7f) 0.81875V
+	 */
+	vid_current =  QIXIS_READ(brdcfg[6]);
+	vdd_current = 121250 - (vid_current - 0x40) * 625;
+	debug("VID: Current vid setting is (0x%x) %d mV\n",
+	      vid_current, vdd_current/100);
+
+	/*
+	 * Read voltage monitor to check real voltage.
+	 * Voltage monitor LSB is 4mv.
+	 */
+	vdd_last = read_voltage();
+	if (vdd_last < 0) {
+		printf("VID: Could not read voltage sensor abort VID adjustment\n");
+		ret = -1;
+		goto exit;
+	}
+	debug("VID: Core voltage is at %d mV\n", vdd_last);
+	/*
+	 * Adjust voltage to at or 8mV above target.
+	 * Each step of adjustment is 6.25mV.
+	 * Stepping down too fast may cause over current.
+	 */
+	while (vdd_last > 0 && vid_current < 0x80 &&
+		vdd_last > (vdd_target + 8)) {
+		vid_current++;
+		vdd_last = set_voltage(vid_current);
+	}
+	/*
+	 * Check if we need to step up
+	 * This happens when board voltage switch was set too low
+	 */
+	while (vdd_last > 0 && vid_current >= 0x40 &&
+		vdd_last < vdd_target + 2) {
+		vid_current--;
+		vdd_last = set_voltage(vid_current);
+	}
+	if (vdd_last > 0)
+		printf("VID: Core voltage %d mV\n", vdd_last);
+	else
+		ret = -1;
+
+exit:
+	if (re_enable)
+		enable_interrupts();
+	return ret;
+}
+
 /* Configure Crossbar switches for Front-Side SerDes Ports */
 int config_frontside_crossbar_vsc3316(void)
 {
@@ -282,8 +519,15 @@
 	setup_portals();
 #endif
 
-	/* Disable remote I2C connectoin */
-	QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET);
+	/* Disable remote I2C connection to qixis fpga */
+	QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
+
+	/*
+	 * Adjust core voltage according to voltage ID
+	 * This function changes I2C mux to channel 2.
+	 */
+	if (adjust_vdd(0))
+		printf("Warning: Adjusting core voltage failed.\n");
 
 	/* Configure board SERDES ports crossbar */
 	config_frontside_crossbar_vsc3316();
@@ -296,6 +540,20 @@
 unsigned long get_board_sys_clk(void)
 {
 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+	/* use accurate clock measurement */
+	int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
+	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+	u32 val;
+
+	val =  freq * base;
+	if (val) {
+		debug("SYS Clock measurement is: %d\n", val);
+		return val;
+	} else {
+		printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
+	}
+#endif
 
 	switch (sysclk_conf & 0x0F) {
 	case QIXIS_SYSCLK_83:
@@ -319,6 +577,20 @@
 unsigned long get_board_ddr_clk(void)
 {
 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+	/* use accurate clock measurement */
+	int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
+	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+	u32 val;
+
+	val =  freq * base;
+	if (val) {
+		debug("DDR Clock measurement is: %d\n", val);
+		return val;
+	} else {
+		printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
+	}
+#endif
 
 	switch ((ddrclk_conf & 0x30) >> 4) {
 	case QIXIS_DDRCLK_100:
@@ -357,7 +629,7 @@
 
 	sw = QIXIS_READ(brdcfg[2]);
 	for (i = 0; i < MAX_SERDES; i++) {
-		unsigned int clock = (sw >> (2 * i)) & 3;
+		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
 		switch (clock) {
 		case 0:
 			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
@@ -414,6 +686,106 @@
 }
 
 /*
+ * This function is called by bdinfo to print detail board information.
+ * As an exmaple for future board, we organize the messages into
+ * several sections. If applicable, the message is in the format of
+ * <name>      = <value>
+ * It should aligned with normal output of bdinfo command.
+ *
+ * Voltage: Core, DDR and another configurable voltages
+ * Clock  : Critical clocks which are not printed already
+ * RCW    : RCW source if not printed already
+ * Misc   : Other important information not in above catagories
+ */
+void board_detail(void)
+{
+	int i;
+	u8 brdcfg[16], dutcfg[16], rst_ctl;
+	int vdd, rcwsrc;
+	static const char * const clk[] = {"66.67", "100", "125", "133.33"};
+
+	for (i = 0; i < 16; i++) {
+		brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
+		dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
+	}
+
+	/* Voltage secion */
+	if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
+		vdd = read_voltage();
+		if (vdd > 0)
+			printf("Core voltage= %d mV\n", vdd);
+		select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	}
+
+	printf("XVDD        = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
+
+	/* clock section */
+	printf("SYSCLK      = %s MHz\nDDRCLK      = %s MHz\n",
+	       clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
+
+	/* RCW section */
+	rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
+	puts("RCW source  = ");
+	switch (rcwsrc) {
+	case 0x017:
+	case 0x01f:
+		puts("8-bit NOR\n");
+		break;
+	case 0x027:
+	case 0x02F:
+		puts("16-bit NOR\n");
+		break;
+	case 0x040:
+		puts("SDHC/eMMC\n");
+		break;
+	case 0x044:
+		puts("SPI 16-bit addressing\n");
+		break;
+	case 0x045:
+		puts("SPI 24-bit addressing\n");
+		break;
+	case 0x048:
+		puts("I2C normal addressing\n");
+		break;
+	case 0x049:
+		puts("I2C extended addressing\n");
+		break;
+	case 0x108:
+	case 0x109:
+	case 0x10a:
+	case 0x10b:
+		puts("8-bit NAND, 2KB\n");
+		break;
+	default:
+		if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
+			puts("Hard-coded RCW\n");
+		else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
+			puts("8-bit NAND, 4KB\n");
+		else
+			puts("unknown\n");
+		break;
+	}
+
+	/* Misc section */
+	rst_ctl = QIXIS_READ(rst_ctl);
+	puts("HRESET_REQ  = ");
+	switch (rst_ctl & 0x30) {
+	case 0x00:
+		puts("Ignored\n");
+		break;
+	case 0x10:
+		puts("Assert HRESET\n");
+		break;
+	case 0x30:
+		puts("Reset system\n");
+		break;
+	default:
+		puts("N/A\n");
+		break;
+	}
+}
+
+/*
  * Reverse engineering switch settings.
  * Some bits cannot be figured out. They will be displayed as
  * underscore in binary format. mask[] has those bits.
@@ -429,7 +801,7 @@
 	 * Any bit with 1 means that bit cannot be reverse engineered.
 	 * It will be displayed as _ in binary format.
 	 */
-	static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xdf, 0x3f, 0x1f};
+	static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
 	char buf[10];
 	u8 brdcfg[16], dutcfg[16];
 
@@ -460,7 +832,8 @@
 	sw[5] = ((brdcfg[0] & 0x0f) << 4)	| \
 		((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \
 		((brdcfg[0] & 0x40) >> 5);
-	sw[6] = (brdcfg[11] & 0x20);
+	sw[6] = (brdcfg[11] & 0x20)		|
+		((brdcfg[5] & 0x02) << 3);
 	sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \
 		((brdcfg[5] & 0x10) << 2);
 	sw[8] = ((brdcfg[12] & 0x08) << 4)	| \
@@ -472,3 +845,23 @@
 			i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
 	}
 }
+
+static int do_vdd_adjust(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong override;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	if (!strict_strtoul(argv[1], 10, &override))
+		adjust_vdd(override);	/* the value is checked by callee */
+	else
+		return CMD_RET_USAGE;
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	vdd_override, 2, 0, do_vdd_adjust,
+	"Override VDD",
+	"- override with the voltage specified in mV, eg. 1050"
+);
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
index 80eb511..92c01cf 100644
--- a/board/freescale/t4qds/tlb.c
+++ b/board/freescale/t4qds/tlb.c
@@ -115,7 +115,7 @@
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 13, BOOKE_PAGESZ_4M, 1),
+		      0, 13, BOOKE_PAGESZ_32M, 1),
 #endif
 #ifdef CONFIG_SYS_NAND_BASE
 	/*
diff --git a/board/freescale/titanium/Makefile b/board/freescale/titanium/Makefile
new file mode 100644
index 0000000..46827f8
--- /dev/null
+++ b/board/freescale/titanium/Makefile
@@ -0,0 +1,36 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := titanium.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/titanium/imximage.cfg b/board/freescale/titanium/imximage.cfg
new file mode 100644
index 0000000..1934343
--- /dev/null
+++ b/board/freescale/titanium/imximage.cfg
@@ -0,0 +1,178 @@
+/*
+ * Projectiondesign AS
+ * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * sd, nand
+ */
+BOOT_FROM      nand
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+
+/* (differential input) */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* disable ddr pullups */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+/* (differential input) */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
+
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
diff --git a/board/freescale/titanium/titanium.c b/board/freescale/titanium/titanium.c
new file mode 100644
index 0000000..5250522
--- /dev/null
+++ b/board/freescale/titanium/titanium.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright (C) 2013 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6q_pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
+			PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	\
+			PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |	\
+			PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
+			 PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
+			 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart4_pads[] = {
+	MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+struct i2c_pads_info i2c_pad_info0 = {
+	.scl = {
+		.i2c_mode  = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC,
+		.gp = IMX_GPIO_NR(5, 27)
+	},
+	.sda = {
+		 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
+		 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC,
+		 .gp = IMX_GPIO_NR(5, 26)
+	 }
+};
+
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
+		 .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
+		 .gp = IMX_GPIO_NR(7, 11)
+	 }
+};
+
+iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const enet_pads1[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/* pin 35 - 1 (PHY_AD2) on reset */
+	MX6_PAD_RGMII_RXC__GPIO_6_30		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 32 - 1 - (MODE0) all */
+	MX6_PAD_RGMII_RD0__GPIO_6_25		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 31 - 1 - (MODE1) all */
+	MX6_PAD_RGMII_RD1__GPIO_6_27		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 28 - 1 - (MODE2) all */
+	MX6_PAD_RGMII_RD2__GPIO_6_28		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 27 - 1 - (MODE3) all */
+	MX6_PAD_RGMII_RD3__GPIO_6_29		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+	MX6_PAD_RGMII_RX_CTL__GPIO_6_24		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 42 PHY nRST */
+	MX6_PAD_EIM_D23__GPIO_3_23		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads2[] = {
+	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+iomux_v3_cfg_t nfc_pads[] = {
+	MX6_PAD_NANDF_CLE__RAWNAND_CLE		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_ALE__RAWNAND_ALE		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_WP_B__RAWNAND_RESETN	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_RB0__RAWNAND_READY0	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS0__RAWNAND_CE0N		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS1__RAWNAND_CE1N		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS2__RAWNAND_CE2N		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS3__RAWNAND_CE3N		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_CMD__RAWNAND_RDN		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_CLK__RAWNAND_WRN		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D0__RAWNAND_D0		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D1__RAWNAND_D1		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D2__RAWNAND_D2		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D3__RAWNAND_D3		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D4__RAWNAND_D4		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D5__RAWNAND_D5		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D6__RAWNAND_D6		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D7__RAWNAND_D7		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__RAWNAND_DQS		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	imx_iomux_v3_setup_multiple_pads(nfc_pads,
+					 ARRAY_SIZE(nfc_pads));
+
+	/* config gpmi and bch clock to 100 MHz */
+	clrsetbits_le32(&mxc_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+	/* enable gpmi and bch clock gating */
+	setbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+
+static void setup_iomux_enet(void)
+{
+	gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+	gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+
+	/* Need delay 10ms according to KSZ9021 spec */
+	udelay(1000 * 10);
+	gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+
+	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+}
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{ USDHC3_BASE_ADDR },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
+		gpio_direction_input(IMX_GPIO_NR(7, 0));
+		return !gpio_get_value(IMX_GPIO_NR(7, 0));
+	}
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	/*
+	 * Only one USDHC controller on titianium
+	 */
+	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* min rx data delay */
+	ksz9021_phy_extended_write(phydev,
+				   MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
+	/* min tx data delay */
+	ksz9021_phy_extended_write(phydev,
+				   MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
+	/* max rx/tx clock delay, min rx/tx control */
+	ksz9021_phy_extended_write(phydev,
+				   MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+
+	setup_iomux_enet();
+
+	ret = cpu_eth_init(bis);
+	if (ret)
+		printf("FEC MXC: %s:failed\n", __func__);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+	setup_gpmi_nand();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Titanium\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* NAND */
+	{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
+	/* 4 bit bus width */
+	{ "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
+	{ "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
+	{ NULL, 0 },
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	return 0;
+}
diff --git a/board/genesi/mx51_efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c
index cf020c3..cabad70 100644
--- a/board/genesi/mx51_efikamx/efikamx-usb.c
+++ b/board/genesi/mx51_efikamx/efikamx-usb.c
@@ -26,8 +26,7 @@
 #include <usb.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx51.h>
 #include <asm/gpio.h>
 #include <usb/ehci-fsl.h>
 #include <usb/ulpi.h>
@@ -35,40 +34,57 @@
 
 #include "../../../drivers/usb/host/ehci.h"
 
-/* USB pin configuration */
-#define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
-			PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
-
 /*
  * Configure the USB H1 and USB H2 IOMUX
  */
 void setup_iomux_usb(void)
 {
-	setup_iomux_usb_h1();
+	static const iomux_v3_cfg_t usb_h1_pads[] = {
+		MX51_PAD_USBH1_CLK__USBH1_CLK,
+		MX51_PAD_USBH1_DIR__USBH1_DIR,
+		MX51_PAD_USBH1_STP__USBH1_STP,
+		MX51_PAD_USBH1_NXT__USBH1_NXT,
+		MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+		MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+		MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+		MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+		MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+		MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+		MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+		MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+	};
 
-	if (machine_is_efikasb())
-		setup_iomux_usb_h2();
+	static const iomux_v3_cfg_t usb_pads[] = {
+		MX51_PAD_EIM_D27__GPIO2_9, /* USB PHY reset */
+		MX51_PAD_GPIO1_5__GPIO1_5, /* USB HUB reset */
+		NEW_PAD_CTRL(MX51_PAD_EIM_A22__GPIO2_16, 0), /* WIFI /EN */
+		NEW_PAD_CTRL(MX51_PAD_EIM_A16__GPIO2_10, 0), /* WIFI RESET */
+		NEW_PAD_CTRL(MX51_PAD_EIM_A17__GPIO2_11, 0), /* BT /EN */
+	};
 
-	/* USB PHY reset */
-	mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
-			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+	imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
 
-	/* USB HUB reset */
-	mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
-			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+	if (machine_is_efikasb()) {
+		static const iomux_v3_cfg_t usb_h2_pads[] = {
+			MX51_PAD_EIM_A24__USBH2_CLK,
+			MX51_PAD_EIM_A25__USBH2_DIR,
+			MX51_PAD_EIM_A26__USBH2_STP,
+			MX51_PAD_EIM_A27__USBH2_NXT,
+			MX51_PAD_EIM_D16__USBH2_DATA0,
+			MX51_PAD_EIM_D17__USBH2_DATA1,
+			MX51_PAD_EIM_D18__USBH2_DATA2,
+			MX51_PAD_EIM_D19__USBH2_DATA3,
+			MX51_PAD_EIM_D20__USBH2_DATA4,
+			MX51_PAD_EIM_D21__USBH2_DATA5,
+			MX51_PAD_EIM_D22__USBH2_DATA6,
+			MX51_PAD_EIM_D23__USBH2_DATA7,
+		};
 
-	/* WIFI EN (act low) */
-	mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
-	/* WIFI RESET */
-	mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
-	/* BT EN (act low) */
-	mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
+		imx_iomux_v3_setup_multiple_pads(usb_h2_pads,
+						 ARRAY_SIZE(usb_h2_pads));
+	}
+
+	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 }
 
 /*
@@ -77,18 +93,18 @@
 static void efika_usb_enable_devices(void)
 {
 	/* Enable Bluetooth */
-	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
+	gpio_direction_output(IMX_GPIO_NR(2, 11), 0);
 	udelay(10000);
-	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
+	gpio_set_value(IMX_GPIO_NR(2, 11), 1);
 
 	/* Enable WiFi */
-	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
+	gpio_direction_output(IMX_GPIO_NR(2, 16), 1);
 	udelay(10000);
 
 	/* Reset the WiFi chip */
-	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
+	gpio_direction_output(IMX_GPIO_NR(2, 10), 0);
 	udelay(10000);
-	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
+	gpio_set_value(IMX_GPIO_NR(2, 10), 1);
 }
 
 /*
@@ -97,11 +113,11 @@
 static void efika_usb_hub_reset(void)
 {
 	/* HUB reset */
-	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+	gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
 	udelay(1000);
-	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
+	gpio_set_value(IMX_GPIO_NR(1, 5), 0);
 	udelay(1000);
-	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+	gpio_set_value(IMX_GPIO_NR(1, 5), 1);
 }
 
 /*
@@ -110,28 +126,26 @@
 static void efika_usb_phy_reset(void)
 {
 	/* SMSC 3317 PHY reset */
-	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
+	gpio_direction_output(IMX_GPIO_NR(2, 9), 0);
 	udelay(1000);
-	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
+	gpio_set_value(IMX_GPIO_NR(2, 9), 1);
 }
 
 static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio,
-				uint32_t alt0, uint32_t alt1)
+				iomux_v3_cfg_t stp_pad_gpio,
+				iomux_v3_cfg_t stp_pad_usb)
 {
 	int ret;
 	struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
 	struct ulpi_viewport ulpi_vp;
 
-	mxc_request_iomux(stp_gpio, alt0);
-	mxc_iomux_set_pad(stp_gpio, PAD_CTL_DRV_HIGH |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-	gpio_direction_output(IOMUX_TO_GPIO(stp_gpio), 0);
+	imx_iomux_v3_setup_pad(stp_pad_gpio);
+	gpio_direction_output(stp_gpio, 0);
 	udelay(1000);
-	gpio_set_value(IOMUX_TO_GPIO(stp_gpio), 1);
+	gpio_set_value(stp_gpio, 1);
 	udelay(1000);
 
-	mxc_request_iomux(stp_gpio, alt1);
-	mxc_iomux_set_pad(stp_gpio, USB_PAD_CONFIG);
+	imx_iomux_v3_setup_pad(stp_pad_usb);
 	udelay(10000);
 
 	ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
@@ -204,11 +218,13 @@
 		tmp = (tmp & ~0x3) | 0x01;
 		writel(tmp, OTG_BASE_ADDR + 0x80c);
 	} else if (port == 1) {
-		efika_ehci_init(ehci, MX51_PIN_USBH1_STP,
-				IOMUX_CONFIG_ALT2, IOMUX_CONFIG_ALT0);
+		efika_ehci_init(ehci, IMX_GPIO_NR(1, 27),
+				MX51_PAD_USBH1_STP__GPIO1_27,
+				MX51_PAD_USBH1_STP__USBH1_STP);
 	} else if ((port == 2) && machine_is_efikasb()) {
-		efika_ehci_init(ehci, MX51_PIN_EIM_A26,
-				IOMUX_CONFIG_ALT1, IOMUX_CONFIG_ALT2);
+		efika_ehci_init(ehci, IMX_GPIO_NR(2, 20),
+				MX51_PAD_EIM_A26__GPIO2_20,
+				MX51_PAD_EIM_A26__USBH2_STP);
 	}
 
 	if (port)
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c
index 69d41db..13582a2 100644
--- a/board/genesi/mx51_efikamx/efikamx.c
+++ b/board/genesi/mx51_efikamx/efikamx.c
@@ -293,7 +293,7 @@
 
 static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
 	MX51_PAD_GPIO1_0__SD1_CD,
-	MX51_PAD_EIM_CS2__SD1_CD,
+	NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, MX51_ESDHC_PAD_CTRL),
 };
 
 #define EFIKAMX_SDHC1_CD	IMX_GPIO_NR(1, 0)
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg
index 21ff6d6..0173535 100644
--- a/board/genesi/mx51_efikamx/imximage_mx.cfg
+++ b/board/genesi/mx51_efikamx/imximage_mx.cfg
@@ -26,7 +26,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/genesi/mx51_efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg
index 7ddd0b1..5c46769 100644
--- a/board/genesi/mx51_efikamx/imximage_sb.cfg
+++ b/board/genesi/mx51_efikamx/imximage_sb.cfg
@@ -26,7 +26,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/h2200/h2200.c b/board/h2200/h2200.c
index 720b06e..738e480 100644
--- a/board/h2200/h2200.c
+++ b/board/h2200/h2200.c
@@ -32,6 +32,15 @@
 	return 0;
 }
 
+void reset_cpu(ulong ignore)
+{
+	/* Enable VLIO interface on Hamcop */
+	writeb(0x1, 0x4000);
+
+	/* Reset board (cold reset) */
+	writeb(0xff, 0x4002);
+}
+
 int board_init(void)
 {
 	/* We have RAM, disable cache */
diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg
index 4b64dab..1b66207 100644
--- a/board/iomega/iconnect/kwbimage.cfg
+++ b/board/iomega/iconnect/kwbimage.cfg
@@ -19,7 +19,7 @@
 # You should have received a copy of the GNU General Public License
 # along with this program. If not, see <http://www.gnu.org/licenses/>.
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/isee/igep0033/Makefile b/board/isee/igep0033/Makefile
new file mode 100644
index 0000000..54a4b75
--- /dev/null
+++ b/board/isee/igep0033/Makefile
@@ -0,0 +1,46 @@
+#
+# Makefile
+#
+# Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS	:= mux.o
+endif
+
+COBJS	+= board.o
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
new file mode 100644
index 0000000..826cead
--- /dev/null
+++ b/board/isee/igep0033/board.c
@@ -0,0 +1,241 @@
+/*
+ * Board functions for IGEP COM AQUILA/CYGNUS based boards
+ *
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+#ifdef CONFIG_SPL_BUILD
+static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+#endif
+
+/* MII mode defines */
+#define RMII_MODE_ENABLE	0x4D
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* UART Defines */
+#ifdef CONFIG_SPL_BUILD
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+
+static void rtc32k_enable(void)
+{
+	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+
+	/*
+	 * Unlock the RTC's registers.  For more details please see the
+	 * RTC_SS section of the TRM.  In order to unlock we need to
+	 * write these specific values (keys) in this order.
+	 */
+	writel(0x83e70b13, &rtc->kick0r);
+	writel(0x95a4f1e0, &rtc->kick1r);
+
+	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
+	writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
+	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
+	.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
+	.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
+	.datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = K4B2G1646EBIH9_RATIO,
+	.cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
+	.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+
+	.cmd1csratio = K4B2G1646EBIH9_RATIO,
+	.cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
+	.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+
+	.cmd2csratio = K4B2G1646EBIH9_RATIO,
+	.cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
+	.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
+	.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
+	.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
+	.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
+	.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
+	.zq_config = K4B2G1646EBIH9_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
+};
+#endif
+
+/*
+ * Early system init of muxing and clocks.
+ */
+void s_init(void)
+{
+	/*
+	 * Save the boot parameters passed from romcode.
+	 * We cannot delay the saving further than this,
+	 * to prevent overwrites.
+	 */
+#ifdef CONFIG_SPL_BUILD
+	save_omap_boot_params();
+#endif
+
+	/* WDT1 is already running when the bootloader gets control
+	 * Disable it to avoid "random" resets
+	 */
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+
+#ifdef CONFIG_SPL_BUILD
+	/* Setup the PLLs and the clocks for the peripherals */
+	pll_init();
+
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+
+	/* UART softreset */
+	u32 regval;
+
+	enable_uart0_pin_mux();
+
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_RESET;
+	writel(regval, &uart_base->uartsyscfg);
+	while ((readl(&uart_base->uartsyssts) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_SMART_IDLE_EN;
+	writel(regval, &uart_base->uartsyscfg);
+
+	gd = &gdata;
+
+	preloader_console_init();
+
+	/* Configure board pin mux */
+	enable_board_pin_mux();
+
+	config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
+		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+#endif
+}
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+	gpmc_init();
+
+	return 0;
+}
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_id		= 0,
+		.phy_if		= PHY_INTERFACE_MODE_RMII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, ret = 0;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+	writel(RMII_MODE_ENABLE, &cdev->miisel);
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		ret += rv;
+
+	return ret;
+}
+#endif
+
diff --git a/board/isee/igep0033/board.h b/board/isee/igep0033/board.h
new file mode 100644
index 0000000..37988e0
--- /dev/null
+++ b/board/isee/igep0033/board.h
@@ -0,0 +1,27 @@
+/*
+ * IGEP COM AQUILA/CYGNUS boards information header
+ *
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We must be able to enable uart0, for initial output. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/board/isee/igep0033/mux.c b/board/isee/igep0033/mux.c
new file mode 100644
index 0000000..16f4add
--- /dev/null
+++ b/board/isee/igep0033/mux.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(mcasp0_aclkx), (MODE(4) | RXACTIVE)},		/* MMC0_CD */
+	{-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},		/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS_DV */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TXD0 */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TXD1 */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_REF_CLK */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},	/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+/*
+ * Do board-specific muxes.
+ */
+void enable_board_pin_mux(void)
+{
+	/* NAND Flash */
+	configure_module_pin_mux(nand_pin_mux);
+	/* SD Card */
+	configure_module_pin_mux(mmc0_pin_mux);
+	/* Ethernet pinmux. */
+	configure_module_pin_mux(rmii1_pin_mux);
+}
+
diff --git a/board/karo/tk71/kwbimage.cfg b/board/karo/tk71/kwbimage.cfg
index 0166826..9a9cf9d 100644
--- a/board/karo/tk71/kwbimage.cfg
+++ b/board/karo/tk71/kwbimage.cfg
@@ -24,7 +24,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c
index 85719a0..461e21f 100644
--- a/board/karo/tx25/tx25.c
+++ b/board/karo/tx25/tx25.c
@@ -27,51 +27,72 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/imx25-pinmux.h>
+#include <asm/arch/iomux-mx25.h>
 #include <asm/gpio.h>
-#include <asm/arch/sys_proto.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_SPL_BUILD
 void board_init_f(ulong bootflag)
 {
-	relocate_code(CONFIG_SPL_TEXT_BASE);
+	/*
+	 * copy ourselves from where we are running to where we were
+	 * linked at. Use ulong pointers as all addresses involved
+	 * are 4-byte-aligned.
+	 */
+	ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
+	asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
+	asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
+	asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
+	asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
+	for (dst = start_ptr; dst < end_ptr; dst++)
+		*dst = *(dst+(run_ptr-link_ptr));
+	/*
+	 * branch to nand_boot's link-time address.
+	 */
 	asm volatile("ldr pc, =nand_boot");
 }
 #endif
 
 #ifdef CONFIG_FEC_MXC
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ *	0 for no pull
+ * or:
+ *	PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define FEC_OUT_PAD_CTRL	0
+
 #define GPIO_FEC_RESET_B	IMX_GPIO_NR(4, 7)
 #define GPIO_FEC_ENABLE_B	IMX_GPIO_NR(4, 9)
 
 void tx25_fec_init(void)
 {
-	struct iomuxc_mux_ctl *muxctl;
-	struct iomuxc_pad_ctl *padctl;
-	u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
-	u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode;
+	static const iomux_v3_cfg_t fec_pads[] = {
+		MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+		MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+		MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
+		MX25_PAD_FEC_MDIO__FEC_MDIO,
+		MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
+
+		NEW_PAD_CTRL(MX25_PAD_D13__GPIO_4_7, 0), /* FEC_RESET_B */
+		NEW_PAD_CTRL(MX25_PAD_D11__GPIO_4_9, 0), /* FEC_ENABLE_B */
+	};
+
+	static const iomux_v3_cfg_t fec_cfg_pads[] = {
+		MX25_PAD_FEC_RDATA0__GPIO_3_10,
+		MX25_PAD_FEC_RDATA1__GPIO_3_11,
+		MX25_PAD_FEC_RX_DV__GPIO_3_12,
+	};
 
 	debug("tx25_fec_init\n");
-	/*
-	 * fec pin init is generic
-	 */
-	mx25_fec_init_pins();
-
-	/*
-	 * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
-	 *
-	 * FEC_RESET_B: gpio4[7] is ALT 5 mode of pin D13
-	 * FEC_ENABLE_B: gpio4[9] is ALT 5 mode of pin D11
-	 */
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-
-	writel(gpio_mux_mode, &muxctl->pad_d13);
-	writel(gpio_mux_mode, &muxctl->pad_d11);
-
-	writel(0x0, &padctl->pad_d13);
-	writel(0x0, &padctl->pad_d11);
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 
 	/* drop PHY power and assert reset (low) */
 	gpio_direction_output(GPIO_FEC_RESET_B, 0);
@@ -99,15 +120,10 @@
 	 *  RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode
 	 */
 	/*
-	 * save three current mux modes and set each to gpio mode
+	 * set each mux mode to gpio mode
 	 */
-	saved_rdata0_mode = readl(&muxctl->pad_fec_rdata0);
-	saved_rdata1_mode = readl(&muxctl->pad_fec_rdata1);
-	saved_rx_dv_mode = readl(&muxctl->pad_fec_rx_dv);
-
-	writel(gpio_mux_mode, &muxctl->pad_fec_rdata0);
-	writel(gpio_mux_mode, &muxctl->pad_fec_rdata1);
-	writel(gpio_mux_mode, &muxctl->pad_fec_rx_dv);
+	imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
+						ARRAY_SIZE(fec_cfg_pads));
 
 	/*
 	 * set each to 1 and make each an output
@@ -128,19 +144,46 @@
 	/*
 	 * set FEC pins back
 	 */
-	writel(saved_rdata0_mode, &muxctl->pad_fec_rdata0);
-	writel(saved_rdata1_mode, &muxctl->pad_fec_rdata1);
-	writel(saved_rx_dv_mode, &muxctl->pad_fec_rx_dv);
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 #else
 #define tx25_fec_init()
 #endif
 
+#ifdef CONFIG_MXC_UART
+/*
+ * Set up input pins with hysteresis and 100-k pull-ups
+ */
+#define UART1_IN_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ *	0 for no pull
+ * or:
+ *	PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define UART1_OUT_PAD_CTRL	0
+
+static void tx25_uart1_init(void)
+{
+	static const iomux_v3_cfg_t uart1_pads[] = {
+		NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+#else
+#define tx25_uart1_init()
+#endif
+
 int board_init()
 {
-#ifdef CONFIG_MXC_UART
-	mx25_uart1_init_pins();
-#endif
+	tx25_uart1_init();
+
 	/* board id for linux */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 	return 0;
diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg
index 5aa0de2..63822a5 100644
--- a/board/keymile/km_arm/kwbimage-memphis.cfg
+++ b/board/keymile/km_arm/kwbimage-memphis.cfg
@@ -23,7 +23,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg
index e5e9942..d941d7e 100644
--- a/board/keymile/km_arm/kwbimage.cfg
+++ b/board/keymile/km_arm/kwbimage.cfg
@@ -20,7 +20,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg
index 5de8df7..4c31a0d 100644
--- a/board/keymile/km_arm/kwbimage_128M16_1.cfg
+++ b/board/keymile/km_arm/kwbimage_128M16_1.cfg
@@ -25,7 +25,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg b/board/keymile/km_arm/kwbimage_256M8_1.cfg
index d0a09f6..31b9203 100644
--- a/board/keymile/km_arm/kwbimage_256M8_1.cfg
+++ b/board/keymile/km_arm/kwbimage_256M8_1.cfg
@@ -22,7 +22,7 @@
 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 # MA 02110-1301 USA
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 # This configuration applies to COGE5 design (ARM-part)
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index 48eb65f..42bf8b6 100644
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@@ -332,10 +332,10 @@
 static void twl4030_regulator_set_mode(u8 id, u8 mode)
 {
 	u16 msg = MSG_SINGULAR(DEV_GRP_P1, id, mode);
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg >> 8,
-			TWL4030_PM_MASTER_PB_WORD_MSB);
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg & 0xff,
-			TWL4030_PM_MASTER_PB_WORD_LSB);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PB_WORD_MSB, msg >> 8);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PB_WORD_LSB, msg & 0xff);
 }
 
 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
@@ -406,12 +406,12 @@
 				TWL4030_PM_RECEIVER_DEV_GRP_P1);
 
 	/* store I2C access state */
-	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &state,
-			TWL4030_PM_MASTER_PB_CFG);
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+			    &state);
 
 	/* enable I2C access to powerbus (needed for twl4030 regulator) */
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x02,
-			TWL4030_PM_MASTER_PB_CFG);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+			     0x02);
 
 	/* set VAUX3, VSIM and VMMC1 state to active - enable eMMC memory */
 	twl4030_regulator_set_mode(RES_VAUX3, RES_STATE_ACTIVE);
@@ -419,8 +419,8 @@
 	twl4030_regulator_set_mode(RES_VMMC1, RES_STATE_ACTIVE);
 
 	/* restore I2C access state */
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, state,
-			TWL4030_PM_MASTER_PB_CFG);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+			     state);
 
 	/* set env variable attkernaddr for relocated kernel */
 	sprintf(buf, "%#x", KERNEL_ADDRESS);
@@ -475,14 +475,14 @@
 		return;
 
 	/* read actual watchdog timeout */
-	twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &timeout,
-			TWL4030_PM_RECEIVER_WATCHDOG_CFG);
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER,
+			    TWL4030_PM_RECEIVER_WATCHDOG_CFG, &timeout);
 
 	/* timeout 0 means watchdog is disabled */
 	/* reset watchdog timeout to 31s (maximum) */
 	if (timeout != 0)
-		twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 31,
-				TWL4030_PM_RECEIVER_WATCHDOG_CFG);
+		twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+				     TWL4030_PM_RECEIVER_WATCHDOG_CFG, 31);
 
 	/* store last watchdog reset time */
 	twl_wd_time = get_timer(0);
@@ -531,8 +531,8 @@
 {
 	int ret = 0;
 	u8 ctrl;
-	ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl,
-		TWL4030_KEYPAD_KEYP_CTRL_REG);
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
+				  TWL4030_KEYPAD_KEYP_CTRL_REG, &ctrl);
 
 	if (ret)
 		return ret;
@@ -541,18 +541,18 @@
 	ctrl |= TWL4030_KEYPAD_CTRL_KBD_ON;
 	ctrl |= TWL4030_KEYPAD_CTRL_SOFT_NRST;
 	ctrl |= TWL4030_KEYPAD_CTRL_SOFTMODEN;
-	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl,
-				TWL4030_KEYPAD_KEYP_CTRL_REG);
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_CTRL_REG, ctrl);
 	/* enable key event status */
-	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0xfe,
-				TWL4030_KEYPAD_KEYP_IMR1);
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_IMR1, 0xfe);
 	/* enable interrupt generation on rising and falling */
 	/* this is a workaround for qemu twl4030 emulation */
-	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x57,
-				TWL4030_KEYPAD_KEYP_EDR);
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_EDR, 0x57);
 	/* enable ISR clear on read */
-	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x05,
-				TWL4030_KEYPAD_KEYP_SIH_CTRL);
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_SIH_CTRL, 0x05);
 	return 0;
 }
 
@@ -615,8 +615,8 @@
 	for (i = 0; i < 2; i++) {
 
 		/* check interrupt register for events */
-		twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &intr,
-				TWL4030_KEYPAD_KEYP_ISR1+(2*i));
+		twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_ISR1 + (2 * i), &intr);
 
 		/* no event */
 		if (!(intr&1))
diff --git a/board/nvidia/beaver/Makefile b/board/nvidia/beaver/Makefile
new file mode 100644
index 0000000..9510f60
--- /dev/null
+++ b/board/nvidia/beaver/Makefile
@@ -0,0 +1,38 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+$(shell mkdir -p $(obj)../cardhu)
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= ../cardhu/cardhu.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c
index a96c293..6ba8c86 100644
--- a/board/olimex/mx23_olinuxino/spl_boot.c
+++ b/board/olimex/mx23_olinuxino/spl_boot.c
@@ -29,8 +29,8 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
 
-#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_16MA | MXS_PAD_PULLUP)
-#define	MUX_CONFIG_SSP	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP	(MXS_PAD_8MA | MXS_PAD_PULLUP)
 
 const iomux_cfg_t iomux_setup[] = {
 	/* DUART */
diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c
index 9ff5dd7..5f0c58d 100644
--- a/board/pandora/pandora.c
+++ b/board/pandora/pandora.c
@@ -114,8 +114,9 @@
 
 	/* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
 	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+		TWL4030_PM_RECEIVER_BB_CFG,
 		TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
-		TWL4030_BB_CFG_BBISEL_500UA, TWL4030_PM_RECEIVER_BB_CFG);
+		TWL4030_BB_CFG_BBISEL_500UA);
 
 	dieid_num_r();
 
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 43d7b6e..93c611d 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -115,6 +115,15 @@
 void s_init(void)
 {
 	/*
+	 * Save the boot parameters passed from romcode.
+	 * We cannot delay the saving further than this,
+	 * to prevent overwrites.
+	 */
+#ifdef CONFIG_SPL_BUILD
+	save_omap_boot_params();
+#endif
+
+	/*
 	 * WDT1 is already running when the bootloader gets control
 	 * Disable it to avoid "random" resets
 	 */
diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg
index bade627..27a5e31 100644
--- a/board/raidsonic/ib62x0/kwbimage.cfg
+++ b/board/raidsonic/ib62x0/kwbimage.cfg
@@ -20,7 +20,7 @@
 # You should have received a copy of the GNU General Public License
 # along with this program. If not, see <http://www.gnu.org/licenses/>.
 #
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
diff --git a/board/sorcery/Makefile b/board/sorcery/Makefile
deleted file mode 100644
index e1752e3..0000000
--- a/board/sorcery/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# (C) Copyright 2005-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/sorcery/sorcery.c b/board/sorcery/sorcery.c
deleted file mode 100644
index 90d4298..0000000
--- a/board/sorcery/sorcery.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale Inc.
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8220.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <pci.h>
-#include <netdev.h>
-
-phys_size_t initdram (int board_type)
-{
-	ulong size;
-
-	size = dramSetup ();
-
-	return get_ram_size(CONFIG_SYS_SDRAM_BASE, size);
-}
-
-int checkboard (void)
-{
-	puts ("Board: Sorcery-C MPC8220\n");
-
-	return 0;
-}
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI devices, report devices found.
- */
-static struct pci_controller hose;
-
-#endif /* CONFIG_PCI */
-
-void pci_init_board (void)
-{
-#ifdef CONFIG_PCI
-	extern void pci_mpc8220_init (struct pci_controller *hose);
-	pci_mpc8220_init (&hose);
-#endif /* CONFIG_PCI */
-}
-
-int board_eth_init(bd_t *bis)
-{
-	/* Initialize built-in FEC first */
-	cpu_eth_init(bis);
-	return pci_eth_init(bis);
-}
diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c
index 4f37c59..087d856 100644
--- a/board/syteco/zmx25/zmx25.c
+++ b/board/syteco/zmx25/zmx25.c
@@ -32,91 +32,85 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/imx25-pinmux.h>
-#include <asm/arch/sys_proto.h>
+#include <asm/arch/iomux-mx25.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_init()
 {
-	struct iomuxc_mux_ctl *muxctl;
-	struct iomuxc_pad_ctl *padctl;
-	struct iomuxc_pad_input_select *inputselect;
-	u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
-	u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1);
-	u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
-	u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6);
-	u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1);
-	u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2);
+	static const iomux_v3_cfg_t sdhc1_pads[] = {
+		NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
+	};
+
+	static const iomux_v3_cfg_t dig_out_pads[] = {
+		MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */
+		MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */
+		NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */
+		NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */
+	};
+
+	static const iomux_v3_cfg_t led_pads[] = {
+		MX25_PAD_CSI_D9__GPIO_4_21,
+		MX25_PAD_CSI_D4__GPIO_1_29,
+	};
+
+	static const iomux_v3_cfg_t can_pads[] = {
+		NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL),
+	};
+
+	static const iomux_v3_cfg_t i2c3_pads[] = {
+		MX25_PAD_CSPI1_SS1__I2C3_DAT,
+		MX25_PAD_GPIO_E__I2C3_CLK,
+	};
 
 	icache_enable();
 
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-	inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE;
-
-	/* Setup of core volatage selection pin to run at 1.4V */
-	writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */
+	/* Setup of core voltage selection pin to run at 1.4V */
+	imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */
 	gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
 
-	/* Setup of input daisy chains for SD card pins*/
-	writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd);
-	writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk);
-	writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0);
-	writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1);
-	writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2);
-	writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3);
+	/* Setup of SD card pins*/
+	imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
 
 	/* Setup of digital output for USB power and OC */
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */
+	imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */
 	gpio_direction_output(IMX_GPIO_NR(1, 28), 1);
 
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */
+	imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */
 	gpio_direction_input(IMX_GPIO_NR(1, 18));
 
 	/* Setup of digital output control pins */
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/
-
-	writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */
-	writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */
+	imx_iomux_v3_setup_multiple_pads(dig_out_pads,
+						ARRAY_SIZE(dig_out_pads));
 
 	/* Switch both output drivers off */
 	gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
 	gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
 
-	/* Setup of key input pin GPIO2[29]*/
-	writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0);
-	writel(0, &padctl->pad_kpp_row0); /* Key pull up off */
+	/* Setup of key input pin */
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0));
 	gpio_direction_input(IMX_GPIO_NR(2, 29));
 
 	/* Setup of status LED outputs */
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d9);	/* GPIO4[21] */
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d4);	/* GPIO1[29] */
+	imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
 
 	/* Switch both LEDs off */
 	gpio_direction_output(IMX_GPIO_NR(4, 21), 0);
 	gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
 
 	/* Setup of CAN1 and CAN2 signals */
-	writel(gpio_mux_mode6, &muxctl->pad_gpio_a);	/* CAN1 TX */
-	writel(gpio_mux_mode6, &muxctl->pad_gpio_b);	/* CAN1 RX */
-	writel(gpio_mux_mode6, &muxctl->pad_gpio_c);	/* CAN2 TX */
-	writel(gpio_mux_mode6, &muxctl->pad_gpio_d);	/* CAN2 RX */
-
-	/* Setup of input daisy chains for CAN signals*/
-	writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */
-	writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */
+	imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads));
 
 	/* Setup of I2C3 signals */
-	writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1);	/* I2C3 SDA */
-	writel(gpio_mux_mode1, &muxctl->pad_gpio_e);	/* I2C3 SCL */
-
-	/* Setup of input daisy chains for I2C3 signals*/
-	writel(input_select1, &inputselect->i2c3_ipp_sda_in);	/* I2C3 SDA */
-	writel(input_select2, &inputselect->i2c3_ipp_scl_in);	/* I2C3 SCL */
+	imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
 
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
@@ -128,25 +122,32 @@
 	const char *e;
 
 #ifdef CONFIG_FEC_MXC
-	struct iomuxc_mux_ctl *muxctl;
-	u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2);
-	u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ *	0 for no pull
+ * or:
+ *	PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define FEC_OUT_PAD_CTRL	0
 
-	/*
-	 * fec pin init is generic
-	 */
-	mx25_fec_init_pins();
+	static const iomux_v3_cfg_t fec_pads[] = {
+		MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+		MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+		MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
+		MX25_PAD_FEC_MDIO__FEC_MDIO,
+		MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
 
-	/*
-	 * Set up LAN-RESET and FEC_RX_ERR
-	 *
-	 * LAN-RESET:  GPIO3[16] is ALT 5 mode of pin U20
-	 * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2
-	 */
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+		MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */
+		MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */
+	};
 
-	writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
-	writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 
 	/* assert PHY reset (low) */
 	gpio_direction_output(IMX_GPIO_NR(3, 16), 0);
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index b371376..ebddf0c 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -304,6 +304,15 @@
  */
 void s_init(void)
 {
+	/*
+	 * Save the boot parameters passed from romcode.
+	 * We cannot delay the saving further than this,
+	 * to prevent overwrites.
+	 */
+#ifdef CONFIG_SPL_BUILD
+	save_omap_boot_params();
+#endif
+
 	/* WDT1 is already running when the bootloader gets control
 	 * Disable it to avoid "random" resets
 	 */
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 3d9b6dd..c686f40 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -108,13 +108,14 @@
 /*
  * Routine: get_board_revision
  * Description: Detect if we are running on a Beagle revision Ax/Bx,
- *		C1/2/3, C4 or xM. This can be done by reading
+ *		C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading
  *		the level of GPIO173, GPIO172 and GPIO171. This should
  *		result in
  *		GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
  *		GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
  *		GPIO173, GPIO172, GPIO171: 1 0 1 => C4
- *		GPIO173, GPIO172, GPIO171: 0 0 0 => xM
+ *		GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx
+ *		GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx
  */
 static int get_board_revision(void)
 {
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 7bbb549..bf7e091 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -27,7 +27,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <twl6035.h>
+#include <palmas.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 55337c0..46db1bf 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -23,7 +23,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <twl6035.h>
+#include <palmas.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
@@ -63,8 +63,8 @@
  */
 int misc_init_r(void)
 {
-#ifdef CONFIG_TWL6035_POWER
-	twl6035_init_settings();
+#ifdef CONFIG_PALMAS_POWER
+	palmas_init_settings();
 #endif
 	return 0;
 }
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index cab0598..2bbe392 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -82,6 +82,12 @@
 	if (omap_revision() == OMAP4430_ES1_0)
 		return 0;
 
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	if (omap_revision() >= OMAP4460_ES1_0 ||
+		omap_revision() <= OMAP4460_ES1_1)
+		setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
+#endif
+
 	gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
 	phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
 
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 446e36b..4759b16 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -17,6 +17,7 @@
  */
 
 #include <common.h>
+#include <cpsw.h>
 #include <errno.h>
 #include <spl.h>
 #include <asm/arch/cpu.h>
@@ -39,6 +40,8 @@
 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 #endif
 
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
 /* UART Defines */
 #ifdef CONFIG_SPL_BUILD
 #define UART_RESET		(0x1 << 1)
@@ -146,11 +149,23 @@
 void s_init(void)
 {
 #ifdef CONFIG_SPL_BUILD
+	/*
+	 * Save the boot parameters passed from romcode.
+	 * We cannot delay the saving further than this,
+	 * to prevent overwrites.
+	 */
+#ifdef CONFIG_SPL_BUILD
+	save_omap_boot_params();
+#endif
+
 	/* WDT1 is already running when the bootloader gets control
 	 * Disable it to avoid "random" resets
 	 */
 	wdt_disable();
 
+	/* Enable timer */
+	timer_init();
+
 	/* Setup the PLLs and the clocks for the peripherals */
 	pll_init();
 
@@ -163,6 +178,9 @@
 	/* Set MMC pins */
 	enable_mmc1_pin_mux();
 
+	/* Set Ethernet pins */
+	enable_enet_pin_mux();
+
 	/* Enable UART */
 	uart_enable();
 
@@ -196,3 +214,69 @@
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x50,
+		.sliver_reg_ofs	= 0x700,
+		.phy_id		= 1,
+	},
+	{
+		.slave_reg_ofs	= 0x90,
+		.sliver_reg_ofs	= 0x740,
+		.phy_id		= 0,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x100,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0x600,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x28,
+	.hw_stats_reg_ofs	= 0x400,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_1,
+};
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		printf("<ethaddr> not set. Reading from E-fuse\n");
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+		else
+			printf("Unable to read MAC address. Set <ethaddr>\n");
+	}
+
+	return cpsw_register(&cpsw_data);
+}
diff --git a/board/ti/ti814x/evm.h b/board/ti/ti814x/evm.h
index 40f8710..6aebec6 100644
--- a/board/ti/ti814x/evm.h
+++ b/board/ti/ti814x/evm.h
@@ -3,5 +3,6 @@
 
 void enable_uart0_pin_mux(void);
 void enable_mmc1_pin_mux(void);
+void enable_enet_pin_mux(void);
 
 #endif /* _EVM_H */
diff --git a/board/ti/ti814x/mux.c b/board/ti/ti814x/mux.c
index 137acb4..fd9f364 100644
--- a/board/ti/ti814x/mux.c
+++ b/board/ti/ti814x/mux.c
@@ -40,6 +40,36 @@
 	{-1},
 };
 
+static struct module_pin_mux enet_pin_mux[] = {
+	{OFFSET(pincntl232), MODE(0x01)},		/* EMAC_RMREFCLK */
+	{OFFSET(pincntl233), PULLUP_EN | MODE(0x01)},	/* MDCLK */
+	{OFFSET(pincntl234), PULLUP_EN | MODE(0x01)},	/* MDIO */
+	{OFFSET(pincntl235), MODE(0x01)},		/* EMAC[0]_MTCLK */
+	{OFFSET(pincntl236), MODE(0x01)},		/* EMAC[0]_MCOL */
+	{OFFSET(pincntl237), MODE(0x01)},		/* EMAC[0]_MCRS */
+	{OFFSET(pincntl238), MODE(0x01)},		/* EMAC[0]_MRXER */
+	{OFFSET(pincntl239), MODE(0x01)},		/* EMAC[0]_MRCLK */
+	{OFFSET(pincntl240), MODE(0x01)},		/* EMAC[0]_MRXD[0] */
+	{OFFSET(pincntl241), MODE(0x01)},		/* EMAC[0]_MRXD[1] */
+	{OFFSET(pincntl242), MODE(0x01)},		/* EMAC[0]_MRXD[2] */
+	{OFFSET(pincntl243), MODE(0x01)},		/* EMAC[0]_MRXD[3] */
+	{OFFSET(pincntl244), MODE(0x01)},		/* EMAC[0]_MRXD[4] */
+	{OFFSET(pincntl245), MODE(0x01)},		/* EMAC[0]_MRXD[5] */
+	{OFFSET(pincntl246), MODE(0x01)},		/* EMAC[0]_MRXD[6] */
+	{OFFSET(pincntl247), MODE(0x01)},		/* EMAC[0]_MRXD[7] */
+	{OFFSET(pincntl248), MODE(0x01)},		/* EMAC[0]_MRXDV */
+	{OFFSET(pincntl249), MODE(0x01)},		/* EMAC[0]_GMTCLK */
+	{OFFSET(pincntl250), MODE(0x01)},		/* EMAC[0]_MTXD[0] */
+	{OFFSET(pincntl251), MODE(0x01)},		/* EMAC[0]_MTXD[1] */
+	{OFFSET(pincntl252), MODE(0x01)},		/* EMAC[0]_MTXD[2] */
+	{OFFSET(pincntl253), MODE(0x01)},		/* EMAC[0]_MTXD[3] */
+	{OFFSET(pincntl254), MODE(0x01)},		/* EMAC[0]_MTXD[4] */
+	{OFFSET(pincntl255), MODE(0x01)},		/* EMAC[0]_MTXD[5] */
+	{OFFSET(pincntl256), MODE(0x01)},		/* EMAC[0]_MTXD[6] */
+	{OFFSET(pincntl257), MODE(0x01)},		/* EMAC[0]_MTXD[7] */
+	{OFFSET(pincntl258), MODE(0x01)},		/* EMAC[0]_MTXEN */
+};
+
 void enable_uart0_pin_mux(void)
 {
 	configure_module_pin_mux(uart0_pin_mux);
@@ -49,3 +79,8 @@
 {
 	configure_module_pin_mux(mmc1_pin_mux);
 }
+
+void enable_enet_pin_mux(void)
+{
+	configure_module_pin_mux(enet_pin_mux);
+}
diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg
index c1de94f..64bddbb 100644
--- a/board/ttcontrol/vision2/imximage_hynix.cfg
+++ b/board/ttcontrol/vision2/imximage_hynix.cfg
@@ -23,7 +23,7 @@
  * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
  * MA 02110-1301 USA
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
index a471fec..9cc758a 100644
--- a/board/ttcontrol/vision2/vision2.c
+++ b/board/ttcontrol/vision2/vision2.c
@@ -26,10 +26,9 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx51.h>
 #include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>
 #include <i2c.h>
@@ -68,85 +67,67 @@
 	int val;
 
 	/* toggle watchdog trigger pin */
-	val = gpio_get_value(66);
+	val = gpio_get_value(IMX_GPIO_NR(3, 2));
 	val = val ? 0 : 1;
-	gpio_set_value(66, val);
+	gpio_set_value(IMX_GPIO_NR(3, 2), val);
 }
 #endif
 
 static void init_drive_strength(void)
 {
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
+	static const iomux_v3_cfg_t ddr_pads[] = {
+		NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0),
+		NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0),
+		NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP),
+		NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0),
+		NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0),
+		NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0),
+		NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0),
+		NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP),
+		NEW_PAD_CTRL(MX51_GRP_INMODE1, 0),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED),
 
-	/* Setting pad options */
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0,
+				MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1,
+				MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK,
+				MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0,
+				MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1,
+				MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2,
+				MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3,
+				MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
 }
 
 int dram_init(void)
@@ -170,134 +151,102 @@
 
 static void setup_uart(void)
 {
-	unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-			 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
-	/* console RX on Pin EIM_D25 */
-	mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
-	/* console TX on Pin EIM_D26 */
-	mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
+	static const iomux_v3_cfg_t uart_pads[] = {
+		MX51_PAD_EIM_D25__UART3_RXD, /* console RX */
+		MX51_PAD_EIM_D26__UART3_TXD, /* console TX */
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
 #ifdef CONFIG_MXC_SPI
 void spi_io_init(void)
 {
-	/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
-	mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+	static const iomux_v3_cfg_t spi_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS |
+			PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS |
+			PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS |
+			PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+	};
 
-	/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
-	/* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-		PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
-	/*
-	 * SS1 will be used as GPIO because of uninterrupted
-	 * long SPI transmissions (GPIO4_25)
-	 */
-	mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-		PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
-	/* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
-	mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-		PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
-	/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
 }
 
 static void reset_peripherals(int reset)
 {
+#ifdef CONFIG_VISION2_HW_1_0
+	static const iomux_v3_cfg_t fec_cfg_pads[] = {
+		/* RXD1 */
+		NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL),
+		/* RXD2 */
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL),
+		/* RXD3 */
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL),
+		/* RXER */
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL),
+		/* COL */
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL),
+		/* RCLK */
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL),
+		/* RXD0 */
+		NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL),
+	};
+
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
+		MX51_PAD_NANDF_D9__FEC_RDATA0,
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
+		MX51_PAD_EIM_CS4__FEC_RX_ER,
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
+	};
+#endif
+
 	if (reset) {
 
 		/* reset_n is on NANDF_D15 */
-		gpio_direction_output(89, 0);
+		gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
 
 #ifdef CONFIG_VISION2_HW_1_0
 		/*
 		 * set FEC Configuration lines
 		 * set levels of FEC config lines
 		 */
-		gpio_direction_output(75, 0);
-		gpio_direction_output(74, 1);
-		gpio_direction_output(95, 1);
+		gpio_direction_output(IMX_GPIO_NR(3, 11), 0);
+		gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
+		gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
 
 		/* set direction of FEC config lines */
-		gpio_direction_output(59, 0);
-		gpio_direction_output(60, 0);
-		gpio_direction_output(61, 0);
-		gpio_direction_output(55, 1);
+		gpio_direction_output(IMX_GPIO_NR(2, 27), 0);
+		gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
+		gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
+		gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
 
-		/* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
-		mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
-		/* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
-		mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
-		/* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
-		mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
-		/* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
-		mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
-		/* FEC_COL  - sel GPIO (3-10) for configuration -> 1 */
-		mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
-		/* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
-		mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
-		/* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
-		mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
+		imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
+						 ARRAY_SIZE(fec_cfg_pads));
 #endif
 
-		/*
-		 * activate reset_n pin
-		 * Select mux mode: ALT3 mux port: NAND D15
-		 */
-		mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
-		mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
-			PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
+		/* activate reset_n pin */
+		imx_iomux_v3_setup_pad(
+				NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25,
+						PAD_CTL_DSE_MAX));
 	} else {
 		/* set FEC Control lines */
-		gpio_direction_input(89);
+		gpio_direction_input(IMX_GPIO_NR(3, 25));
 		udelay(500);
 
 #ifdef CONFIG_VISION2_HW_1_0
-		/* FEC RDATA[3] */
-		mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
-		mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
-
-		/* FEC RDATA[2] */
-		mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
-		mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
-
-		/* FEC RDATA[1] */
-		mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
-		mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
-
-		/* FEC RDATA[0] */
-		mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
-		mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
-
-		/* FEC RX_CLK */
-		mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
-		mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
-
-		/* FEC RX_ER */
-		mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
-		mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
-
-		/* FEC COL */
-		mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
-		mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
+		imx_iomux_v3_setup_multiple_pads(fec_pads,
+							ARRAY_SIZE(fec_pads));
 #endif
 	}
 }
@@ -376,155 +325,94 @@
 
 static void setup_gpios(void)
 {
+	static const iomux_v3_cfg_t gpio_pads_1[] = {
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* CAM_SUP_DISn */
+		NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* DAB Display EN */
+		NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* WDOG_TRIGGER */
+	};
+
+	static const iomux_v3_cfg_t gpio_pads_2[] = {
+		NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* Display2 TxEN */
+		NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* DAB Light EN */
+		NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* AUDIO_MUTE */
+		NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* SPARE_OUT */
+		NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* BEEPER_EN */
+		NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* POWER_OFF */
+		NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* FRAM_WE */
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* EXPANSION_EN */
+		MX51_PAD_GPIO1_2__PWM1_PWMO,
+	};
+
 	unsigned int i;
 
-	/* CAM_SUP_DISn, GPIO1_7 */
-	mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
-
-	/* DAB Display EN, GPIO3_1 */
-	mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
-	mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
-
-	/* WDOG_TRIGGER, GPIO3_2 */
-	mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
-	mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
+	imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1));
 
 	/* Now we need to trigger the watchdog */
 	WATCHDOG_RESET();
 
-	/* Display2 TxEN, GPIO3_3 */
-	mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
-	mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
-
-	/* DAB Light EN, GPIO3_4 */
-	mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
-	mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
-
-	/* AUDIO_MUTE, GPIO3_5 */
-	mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
-	mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
-
-	/* SPARE_OUT, GPIO3_6 */
-	mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
-	mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
-
-	/* BEEPER_EN, GPIO3_26 */
-	mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
-
-	/* POWER_OFF, GPIO3_27 */
-	mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
-
-	/* FRAM_WE, GPIO3_30 */
-	mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
-
-	/* EXPANSION_EN, GPIO4_26 */
-	mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
-
-	/* PWM Output GPIO1_2 */
-	mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2));
 
 	/*
 	 * Set GPIO1_4 to high and output; it is used to reset
 	 * the system on reboot
 	 */
-	gpio_direction_output(4, 1);
+	gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
 
-	gpio_direction_output(7, 0);
-	for (i = 65; i < 71; i++)
+	gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
+	for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++)
 		gpio_direction_output(i, 0);
 
-	gpio_direction_output(94, 0);
+	gpio_direction_output(IMX_GPIO_NR(3, 30), 0);
 
 	/* Set POWER_OFF high */
-	gpio_direction_output(91, 1);
+	gpio_direction_output(IMX_GPIO_NR(3, 27), 1);
 
-	gpio_direction_output(90, 0);
+	gpio_direction_output(IMX_GPIO_NR(3, 26), 0);
 
-	gpio_direction_output(122, 0);
+	gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
 
-	gpio_direction_output(121, 1);
+	gpio_direction_output(IMX_GPIO_NR(4, 25), 1);
 
 	WATCHDOG_RESET();
 }
 
 static void setup_fec(void)
 {
-	/*FEC_MDIO*/
-	mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
+				PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+		MX51_PAD_NANDF_CS3__FEC_MDC,
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
+		MX51_PAD_NANDF_D9__FEC_RDATA0,
+		MX51_PAD_NANDF_CS6__FEC_TDATA3,
+		MX51_PAD_NANDF_CS5__FEC_TDATA2,
+		MX51_PAD_NANDF_CS4__FEC_TDATA1,
+		MX51_PAD_NANDF_D8__FEC_TDATA0,
+		MX51_PAD_NANDF_CS7__FEC_TX_EN,
+		MX51_PAD_NANDF_CS2__FEC_TX_ER,
+		MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
+		MX51_PAD_EIM_CS5__FEC_CRS,
+		MX51_PAD_EIM_CS4__FEC_RX_ER,
+		NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
+	};
 
-	/*FEC_MDC*/
-	mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
-
-	/* FEC RDATA[3] */
-	mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
-
-	/* FEC RDATA[2] */
-	mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
-
-	/* FEC RDATA[1] */
-	mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
-
-	/* FEC RDATA[0] */
-	mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
-
-	/* FEC TDATA[3] */
-	mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
-
-	/* FEC TDATA[2] */
-	mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
-
-	/* FEC TDATA[1] */
-	mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
-
-	/* FEC TDATA[0] */
-	mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
-
-	/* FEC TX_EN */
-	mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
-
-	/* FEC TX_ER */
-	mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
-
-	/* FEC TX_CLK */
-	mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
-
-	/* FEC TX_COL */
-	mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
-
-	/* FEC RX_CLK */
-	mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
-
-	/* FEC RX_CRS */
-	mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
-
-	/* FEC RX_ER */
-	mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
-
-	/* FEC RX_DV */
-	mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
@@ -536,7 +424,7 @@
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 
 	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
-		*cd = gpio_get_value(0);
+		*cd = gpio_get_value(IMX_GPIO_NR(1, 0));
 	else
 		*cd = 0;
 
@@ -546,56 +434,24 @@
 #ifdef CONFIG_FSL_ESDHC
 int board_mmc_init(bd_t *bis)
 {
-	mxc_request_iomux(MX51_PIN_SD1_CMD,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_request_iomux(MX51_PIN_SD1_CLK,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_request_iomux(MX51_PIN_SD1_DATA0,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_request_iomux(MX51_PIN_SD1_DATA1,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_request_iomux(MX51_PIN_SD1_DATA2,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_request_iomux(MX51_PIN_SD1_DATA3,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
-		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
-		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-		PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
-		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
-		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
-		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
-		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-		PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-	mxc_request_iomux(MX51_PIN_GPIO1_0,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
-		PAD_CTL_HYS_ENABLE);
-	mxc_request_iomux(MX51_PIN_GPIO1_1,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
-		PAD_CTL_HYS_ENABLE);
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
+			PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 
 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
@@ -604,13 +460,18 @@
 
 void lcd_enable(void)
 {
+	static const iomux_v3_cfg_t lcd_pads[] = {
+		MX51_PAD_DI1_PIN2__DI1_PIN2,
+		MX51_PAD_DI1_PIN3__DI1_PIN3,
+	};
+
 	int ret;
 
-	mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 
-	gpio_set_value(2, 1);
-	mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
+	gpio_set_value(IMX_GPIO_NR(1, 2), 1);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2,
+						NO_PAD_CTRL));
 
 	ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
 	if (ret)
@@ -624,9 +485,9 @@
 	init_drive_strength();
 
 	/* Setup debug led */
-	gpio_direction_output(6, 0);
-	mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
+					PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST));
 
 	/* wait a little while to give the pll time to settle */
 	sdelay(100000);
@@ -644,12 +505,12 @@
 static void backlight(int on)
 {
 	if (on) {
-		gpio_set_value(65, 1);
+		gpio_set_value(IMX_GPIO_NR(3, 1), 1);
 		udelay(10000);
-		gpio_set_value(68, 1);
+		gpio_set_value(IMX_GPIO_NR(3, 4), 1);
 	} else {
-		gpio_set_value(65, 0);
-		gpio_set_value(68, 0);
+		gpio_set_value(IMX_GPIO_NR(3, 1), 0);
+		gpio_set_value(IMX_GPIO_NR(3, 4), 0);
 	}
 }
 
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index ac7b89a..bb98352 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -16,6 +16,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
 #include <common.h>
@@ -26,18 +27,19 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
-	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
+#define USDHC1_CD_GPIO		IMX_GPIO_NR(1, 2)
+#define USDHC3_CD_GPIO		IMX_GPIO_NR(3, 9)
 #define ETH_PHY_RESET		IMX_GPIO_NR(3, 29)
 
 int dram_init(void)
@@ -52,6 +54,17 @@
 	MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
+iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* Carrier MicroSD Card Detect */
+	MX6_PAD_GPIO_2__GPIO_1_2      | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
 static iomux_v3_cfg_t const usdhc3_pads[] = {
 	MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -59,6 +72,8 @@
 	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* SOM MicroSD Card Detect */
+	MX6_PAD_EIM_DA9__GPIO_3_9     | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 static iomux_v3_cfg_t const enet_pads[] = {
@@ -96,18 +111,66 @@
 	gpio_set_value(ETH_PHY_RESET, 1);
 }
 
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 	{USDHC3_BASE_ADDR},
+	{USDHC1_BASE_ADDR},
 };
 
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
 int board_mmc_init(bd_t *bis)
 {
-	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+	s32 status = 0;
+	u32 index = 0;
 
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	usdhc_cfg[0].max_bus_width = 4;
+	/*
+	 * Following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    SOM MicroSD
+	 * mmc1                    Carrier board MicroSD
+	 */
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		switch (index) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			usdhc_cfg[0].max_bus_width = 4;
+			gpio_direction_input(USDHC3_CD_GPIO);
+			break;
+		case 1:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			usdhc_cfg[1].max_bus_width = 4;
+			gpio_direction_input(USDHC1_CD_GPIO);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+			       "(%d) then supported by the board (%d)\n",
+			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return status;
+		}
 
-	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+	}
+
+	return status;
 }
 
 static int mx6_rgmii_rework(struct phy_device *phydev)
@@ -162,6 +225,24 @@
 	return 0;
 }
 
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0",	  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{"mmc1",	  MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	return 0;
+}
+
 int board_init(void)
 {
 	/* address of boot parameters */
diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c
index 7c36af0..3f2e6b5 100644
--- a/board/woodburn/woodburn.c
+++ b/board/woodburn/woodburn.c
@@ -28,8 +28,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/mx35_pins.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx35.h>
 #include <i2c.h>
 #include <power/pmic.h>
 #include <fsl_pmic.h>
@@ -74,25 +73,29 @@
 
 static void setup_iomux_fec(void)
 {
+	static const iomux_v3_cfg_t fec_pads[] = {
+		MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+		MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+		MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+		MX35_PAD_FEC_COL__FEC_COL,
+		MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+		MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+		MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+		MX35_PAD_FEC_MDC__FEC_MDC,
+		MX35_PAD_FEC_MDIO__FEC_MDIO,
+		MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+		MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+		MX35_PAD_FEC_CRS__FEC_CRS,
+		MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+		MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+		MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+		MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+		MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+		MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+	};
+
 	/* setup pins for FEC */
-	mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 int woodburn_init(void)
@@ -130,9 +133,9 @@
 	setup_iomux_fec();
 
 	/* setup GPIO1_4 FEC_ENABLE signal */
-	mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5);
+	imx_iomux_v3_setup_pad(MX35_PAD_SCKR__GPIO1_4);
 	gpio_direction_output(4, 1);
-	mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5);
+	imx_iomux_v3_setup_pad(MX35_PAD_HCKT__GPIO1_9);
 	gpio_direction_output(9, 1);
 
 	return 0;
@@ -228,22 +231,24 @@
 
 int board_mmc_init(bd_t *bis)
 {
+	static const iomux_v3_cfg_t sdhc1_pads[] = {
+		MX35_PAD_SD1_CMD__ESDHC1_CMD,
+		MX35_PAD_SD1_CLK__ESDHC1_CLK,
+		MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+		MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+		MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+		MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+	};
+
 	/* configure pins for SDHC1 only */
-	mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
-	mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
+	imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
 
 	/* MMC Card Detect on GPIO1_7 */
-	mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_ALT5);
-	mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1);
+	imx_iomux_v3_setup_pad(MX35_PAD_SCKT__GPIO1_7);
 	gpio_direction_input(GPIO_MMC_CD);
 
 	/* MMC Write Protection on GPIO1_8 */
-	mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5);
-	mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1);
+	imx_iomux_v3_setup_pad(MX35_PAD_FST__GPIO1_8);
 	gpio_direction_input(GPIO_MMC_WP);
 
 	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index befbb3a..2f5f20e 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -31,12 +31,17 @@
 #include <asm/processor.h>
 #include <asm/microblaze_intc.h>
 #include <asm/asm.h>
+#include <asm/gpio.h>
+
+#ifdef CONFIG_XILINX_GPIO
+static int reset_pin = -1;
+#endif
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-#ifdef CONFIG_SYS_GPIO_0
-	*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) =
-	    ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)));
+#ifdef CONFIG_XILINX_GPIO
+	if (reset_pin != -1)
+		gpio_direction_output(reset_pin, 1);
 #endif
 
 #ifdef CONFIG_XILINX_TB_WATCHDOG
@@ -52,8 +57,10 @@
 
 int gpio_init (void)
 {
-#ifdef CONFIG_SYS_GPIO_0
-	*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0xFFFFFFFF;
+#ifdef CONFIG_XILINX_GPIO
+	reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1);
+	if (reset_pin != -1)
+		gpio_request(reset_pin, "reset_pin");
 #endif
 	return 0;
 }
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 8ed75c3..b02c364 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -22,13 +22,52 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <zynqpl.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_FPGA
+Xilinx_desc fpga;
+
+/* It can be done differently */
+Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+#endif
+
 int board_init(void)
 {
+#ifdef CONFIG_FPGA
+	u32 idcode;
+
+	idcode = zynq_slcr_get_idcode();
+
+	switch (idcode) {
+	case XILINX_ZYNQ_7010:
+		fpga = fpga010;
+		break;
+	case XILINX_ZYNQ_7020:
+		fpga = fpga020;
+		break;
+	case XILINX_ZYNQ_7030:
+		fpga = fpga030;
+		break;
+	case XILINX_ZYNQ_7045:
+		fpga = fpga045;
+		break;
+	}
+#endif
+
 	icache_enable();
 
+#ifdef CONFIG_FPGA
+	fpga_init();
+	fpga_add(fpga_xilinx, &fpga);
+#endif
+
 	return 0;
 }
 
@@ -38,10 +77,33 @@
 {
 	u32 ret = 0;
 
-#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
-	ret = zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
+#if defined(CONFIG_ZYNQ_GEM)
+# if defined(CONFIG_ZYNQ_GEM0)
+	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
+						CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
+# endif
+# if defined(CONFIG_ZYNQ_GEM1)
+	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
+						CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
+# endif
+#endif
+	return ret;
+}
 #endif
 
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bd)
+{
+	int ret = 0;
+
+#if defined(CONFIG_ZYNQ_SDHCI)
+# if defined(CONFIG_ZYNQ_SDHCI0)
+	ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
+# endif
+# if defined(CONFIG_ZYNQ_SDHCI1)
+	ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
+# endif
+#endif
 	return ret;
 }
 #endif
diff --git a/boards.cfg b/boards.cfg
index 5d78064..e2a8d42 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -94,6 +94,7 @@
 at91sam9g10ek_nandflash      arm         arm926ejs   at91sam9261ek       atmel          at91        at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH
 at91sam9g20ek_dataflash_cs0  arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0
 at91sam9g20ek_dataflash_cs1  arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1
+at91sam9g20ek_mmc            arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9G20,SYS_USE_MMC
 at91sam9g20ek_nandflash      arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH
 at91sam9g20ek_2mmc_nandflash arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH
 at91sam9m10g45ek_nandflash   arm         arm926ejs   at91sam9m10g45ek    atmel          at91        at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH
@@ -106,6 +107,9 @@
 at91sam9xeek_dataflash_cs0   arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0
 at91sam9xeek_dataflash_cs1   arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1
 at91sam9xeek_nandflash       arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH
+at91sam9n12ek_nandflash      arm         arm926ejs   at91sam9n12ek       atmel          at91        at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH
+at91sam9n12ek_spiflash       arm         arm926ejs   at91sam9n12ek       atmel          at91        at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH
+at91sam9n12ek_mmc            arm         arm926ejs   at91sam9n12ek       atmel          at91        at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC
 snapper9260                  arm         arm926ejs   -                   bluewater      at91        snapper9260:AT91SAM9260
 snapper9g20                  arm         arm926ejs   snapper9260         bluewater      at91        snapper9260:AT91SAM9G20
 vl_ma2sc                     arm         arm926ejs   vl_ma2sc            BuS            at91
@@ -185,6 +189,7 @@
 sheevaplug                   arm         arm926ejs   -                   Marvell        kirkwood
 ib62x0                       arm         arm926ejs   ib62x0              raidsonic      kirkwood
 dockstar                     arm         arm926ejs   -                   Seagate        kirkwood
+goflexhome                   arm         arm926ejs   -                   Seagate        kirkwood
 tk71                         arm         arm926ejs   tk71                karo           kirkwood
 devkit3250                   arm         arm926ejs   devkit3250          timll          lpc32xx
 jadecpu                      arm         arm926ejs   jadecpu             syteco         mb86r0x
@@ -234,7 +239,9 @@
 versatileqemu                arm         arm926ejs   versatile           armltd         versatile   versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB
 integratorap_cm946es         arm         arm946es    integrator          armltd         -               integratorap:CM946ES
 integratorcp_cm946es         arm         arm946es    integrator          armltd         -               integratorcp:CM946ES
-ca9x4_ct_vxp                 arm         armv7       vexpress            armltd
+vexpress_ca15_tc2            arm         armv7       vexpress            armltd
+vexpress_ca5x2               arm         armv7       vexpress            armltd
+vexpress_ca9x4               arm         armv7       vexpress            armltd
 am335x_evm                   arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1
 am335x_evm_spiboot           arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT
 am335x_evm_uart1             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL2,CONS_INDEX=2
@@ -245,7 +252,11 @@
 am335x_evm_usbspl            arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT
 ti814x_evm                   arm         armv7       ti814x              ti             am33xx
 pcm051                       arm         armv7       pcm051              phytec         am33xx      pcm051
+sama5d3xek_mmc               arm         armv7       sama5d3xek          atmel          at91        sama5d3xek:SAMA5D3,SYS_USE_MMC
+sama5d3xek_nandflash         arm         armv7       sama5d3xek          atmel          at91        sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH
+sama5d3xek_spiflash          arm         armv7       sama5d3xek          atmel          at91        sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH
 highbank                     arm         armv7       highbank            -              highbank
+m53evk                       arm         armv7       m53evk              denx		mx5		m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg
 mx51_efikamx                 arm         armv7       mx51_efikamx        genesi         mx5		mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
 mx51_efikasb                 arm         armv7       mx51_efikamx        genesi         mx5		mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
 mx51evk                      arm         armv7       mx51evk             freescale      mx5		mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
@@ -259,6 +270,8 @@
 mx6qsabreauto                arm         armv7       mx6qsabreauto       freescale      mx6		mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
 mx6qsabrelite                arm         armv7       mx6qsabrelite       freescale      mx6		mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
 mx6qsabresd                  arm         armv7       mx6qsabresd         freescale      mx6		mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+mx6slevk                     arm         armv7       mx6slevk            freescale      mx6		mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL
+titanium                     arm         armv7       titanium            freescale      mx6		titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg
 eco5pk                       arm         armv7       eco5pk              8dtech         omap3
 nitrogen6dl                  arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
 nitrogen6dl2g                arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048
@@ -268,15 +281,16 @@
 nitrogen6s1g                 arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024
 wandboard_dl		     arm	 armv7	     wandboard		 -		mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
 wandboard_solo		     arm	 armv7	     wandboard		 -		mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512
-cm_t35                       arm         armv7       cm_t35              -              omap3
 omap3_overo                  arm         armv7       overo               -              omap3
 omap3_pandora                arm         armv7       pandora             -              omap3
 dig297                       arm         armv7       dig297              comelit        omap3
+cm_t35                       arm         armv7       cm_t35              compulab       omap3
 igep0020                     arm         armv7       igep00x0            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND
 igep0020_nand                arm         armv7       igep00x0            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND
 igep0030                     arm         armv7       igep00x0            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND
 igep0030_nand                arm         armv7       igep00x0            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND
 igep0032                     arm         armv7       igep00x0            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND
+igep0033                     arm         armv7       igep0033            isee           am33xx
 am3517_evm                   arm         armv7       am3517evm           logicpd        omap3
 mt_ventoux                   arm         armv7       mt_ventoux          teejet         omap3
 omap3_zoom1                  arm         armv7       zoom1               logicpd        omap3
@@ -311,7 +325,7 @@
 ventana                      arm         armv7:arm720t ventana           nvidia         tegra20
 whistler                     arm         armv7:arm720t whistler          nvidia         tegra20
 cardhu                       arm         armv7:arm720t cardhu            nvidia         tegra30
-beaver                       arm         armv7:arm720t cardhu            nvidia         tegra30
+beaver                       arm         armv7:arm720t beaver            nvidia         tegra30
 dalmore                      arm         armv7:arm720t dalmore           nvidia         tegra114
 colibri_t20_iris             arm         armv7:arm720t colibri_t20_iris  toradex        tegra20
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
@@ -588,9 +602,6 @@
 TQM5200S                     powerpc     mpc5xxx     tqm5200             tqc            -           TQM5200:TQM5200_B,TQM5200S
 TQM5200S_HIGHBOOT            powerpc     mpc5xxx     tqm5200             tqc            -           TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000
 TQM5200_STK100               powerpc     mpc5xxx     tqm5200             tqc            -           TQM5200:STK52XX_REV100
-Alaska8220                   powerpc     mpc8220     alaska
-sorcery                      powerpc     mpc8220
-Yukon8220                    powerpc     mpc8220     alaska
 A3000                        powerpc     mpc824x     a3000
 CPC45                        powerpc     mpc824x     cpc45               -              -           CPC45
 CPC45_ROMBOOT                powerpc     mpc824x     cpc45               -              -           CPC45:BOOT_ROM
@@ -883,6 +894,9 @@
 P5020DS_SPIFLASH	     powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
 P5020DS_SRIO_PCIE_BOOT          powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
 P5040DS                      powerpc     mpc85xx     corenet_ds          freescale
+P5040DS_NAND		     powerpc     mpc85xx     corenet_ds          freescale      -           P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
+P5040DS_SDCARD		     powerpc     mpc85xx     corenet_ds          freescale      -           P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
+P5040DS_SPIFLASH	     powerpc     mpc85xx     corenet_ds          freescale      -           P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
 BSC9131RDB_SPIFLASH          powerpc     mpc85xx     bsc9131rdb          freescale      -           BSC9131RDB:BSC9131RDB,SPIFLASH
 BSC9132QDS_NOR_DDRCLK100     powerpc     mpc85xx     bsc9132qds          freescale      -           BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100
 BSC9132QDS_NOR_DDRCLK133     powerpc     mpc85xx     bsc9132qds          freescale      -           BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133
@@ -893,9 +907,12 @@
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
 stxssa_4M                    powerpc     mpc85xx     stxssa              stx            -           stxssa:STXSSA_4M
-T4240QDS                     powerpc     mpc85xx     t4qds               freescale
-T4240QDS_SDCARD              powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
-T4240QDS_SPIFLASH            powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+T4240QDS                     powerpc     mpc85xx     t4qds               freescale      -           T4240QDS:PPC_T4240
+T4240QDS_SDCARD              powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
+T4240QDS_SPIFLASH            powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+T4160QDS                     powerpc     mpc85xx     t4qds               freescale      -           T4240QDS:PPC_T4160
+T4160QDS_SDCARD              powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
+T4160QDS_SPIFLASH            powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
 B4860QDS                     powerpc     mpc85xx     b4860qds            freescale      -           B4860QDS:PPC_B4860
 B4860QDS_NAND		     powerpc     mpc85xx     b4860qds            freescale      -           B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
 B4860QDS_SPIFLASH            powerpc     mpc85xx     b4860qds            freescale	-           B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
diff --git a/common/Makefile b/common/Makefile
index 0e0fff1..3ba4316 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -111,6 +111,7 @@
 COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o
 endif
 COBJS-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o
+COBJS-$(CONFIG_CMD_FUSE) += cmd_fuse.o
 COBJS-$(CONFIG_CMD_GETTIME) += cmd_gettime.o
 COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
 COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o
@@ -164,6 +165,7 @@
 COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o
 COBJS-$(CONFIG_CMD_SHA1SUM) += cmd_sha1sum.o
 COBJS-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o
+COBJS-$(CONFIG_CMD_SOFTSWITCH) += cmd_softswitch.o
 COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o
 COBJS-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o
 COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o
@@ -230,6 +232,8 @@
 COBJS-y += console.o
 COBJS-y += dlmalloc.o
 COBJS-y += image.o
+COBJS-$(CONFIG_OF_LIBFDT) += image-fdt.o
+COBJS-$(CONFIG_FIT) += image-fit.o
 COBJS-y += memsize.o
 COBJS-y += stdio.o
 
diff --git a/common/board_f.c b/common/board_f.c
index 32e59fa..9fa7363 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -667,27 +667,6 @@
 #if defined(CONFIG_MPC83xx)
 	bd->bi_immrbar = CONFIG_SYS_IMMR;
 #endif
-#if defined(CONFIG_MPC8220)
-	bd->bi_mbar_base = CONFIG_SYS_MBAR;	/* base of internal registers */
-	bd->bi_inpfreq = gd->arch.inp_clk;
-	bd->bi_pcifreq = gd->pci_clk;
-	bd->bi_vcofreq = gd->arch.vco_clk;
-	bd->bi_pevfreq = gd->arch.pev_clk;
-	bd->bi_flbfreq = gd->arch.flb_clk;
-
-	/* store bootparam to sram (backward compatible), here? */
-	{
-		u32 *sram = (u32 *) CONFIG_SYS_SRAM_BASE;
-
-		*sram++ = gd->ram_size;
-		*sram++ = gd->bus_clk;
-		*sram++ = gd->arch.inp_clk;
-		*sram++ = gd->cpu_clk;
-		*sram++ = gd->arch.vco_clk;
-		*sram++ = gd->arch.flb_clk;
-		*sram++ = 0xb8c3ba11;	/* boot signature */
-	}
-#endif
 
 	return 0;
 }
@@ -872,12 +851,6 @@
 #ifdef CONFIG_ARM
 	timer_init,		/* initialize timer */
 #endif
-#ifdef CONFIG_BOARD_POSTCLK_INIT
-	board_postclk_init,
-#endif
-#ifdef CONFIG_FSL_ESDHC
-	get_clocks,
-#endif
 #ifdef CONFIG_SYS_ALLOC_DPRAM
 #if !defined(CONFIG_CPM2)
 	dpram_init,
@@ -886,6 +859,9 @@
 #if defined(CONFIG_BOARD_POSTCLK_INIT)
 	board_postclk_init,
 #endif
+#ifdef CONFIG_FSL_ESDHC
+	get_clocks,
+#endif
 	env_init,		/* initialize environment */
 #if defined(CONFIG_8xx_CPUCLK_DEFAULT)
 	/* get CPU and bus clocks according to the environment variable */
@@ -921,9 +897,6 @@
 #if defined(CONFIG_MPC5xxx)
 	prt_mpc5xxx_clks,
 #endif /* CONFIG_MPC5xxx */
-#if defined(CONFIG_MPC8220)
-	prt_mpc8220_clks,
-#endif
 #if defined(CONFIG_DISPLAY_BOARDINFO)
 	checkboard,		/* display board info */
 #endif
diff --git a/common/board_r.c b/common/board_r.c
index f801e41..fd1fd31 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -765,6 +765,7 @@
 #endif
 	initr_barrier,
 	initr_malloc,
+	bootstage_relocate,
 #ifdef CONFIG_ARCH_EARLY_INIT_R
 	arch_early_init_r,
 #endif
diff --git a/common/bootstage.c b/common/bootstage.c
index a1e0939..c5c6996 100644
--- a/common/bootstage.c
+++ b/common/bootstage.c
@@ -30,6 +30,8 @@
 
 #include <common.h>
 #include <libfdt.h>
+#include <malloc.h>
+#include <linux/compiler.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -56,6 +58,21 @@
 	uint32_t magic;		/* Unused */
 };
 
+int bootstage_relocate(void)
+{
+	int i;
+
+	/*
+	 * Duplicate all strings.  They may point to an old location in the
+	 * program .text section that can eventually get trashed.
+	 */
+	for (i = 0; i < BOOTSTAGE_ID_COUNT; i++)
+		if (record[i].name)
+			record[i].name = strdup(record[i].name);
+
+	return 0;
+}
+
 ulong bootstage_add_record(enum bootstage_id id, const char *name,
 			   int flags, ulong mark)
 {
@@ -102,6 +119,33 @@
 	return bootstage_add_record(id, name, flags, timer_get_boot_us());
 }
 
+ulong bootstage_mark_code(const char *file, const char *func, int linenum)
+{
+	char *str, *p;
+	__maybe_unused char *end;
+	int len = 0;
+
+	/* First work out the length we need to allocate */
+	if (linenum != -1)
+		len = 11;
+	if (func)
+		len += strlen(func);
+	if (file)
+		len += strlen(file);
+
+	str = malloc(len + 1);
+	p = str;
+	end = p + len;
+	if (file)
+		p += snprintf(p, end - p, "%s,", file);
+	if (linenum != -1)
+		p += snprintf(p, end - p, "%d", linenum);
+	if (func)
+		p += snprintf(p, end - p, ": %s", func);
+
+	return bootstage_mark_name(BOOTSTAGE_ID_ALLOC, str);
+}
+
 uint32_t bootstage_start(enum bootstage_id id, const char *name)
 {
 	struct bootstage_record *rec = &record[id];
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 85279d5..17dc961 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -84,6 +84,10 @@
 }
 
 #if defined(CONFIG_PPC)
+void __weak board_detail(void)
+{
+	/* Please define boot_detail() for your platform */
+}
 
 int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -130,13 +134,6 @@
 #endif
 	print_mhz("busfreq",		bd->bi_busfreq);
 #endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
-#if defined(CONFIG_MPC8220)
-	print_mhz("inpfreq",		bd->bi_inpfreq);
-	print_mhz("flbfreq",		bd->bi_flbfreq);
-	print_mhz("pcifreq",		bd->bi_pcifreq);
-	print_mhz("vcofreq",		bd->bi_vcofreq);
-	print_mhz("pevfreq",		bd->bi_pevfreq);
-#endif
 
 #ifdef CONFIG_ENABLE_36BIT_PHYS
 #ifdef CONFIG_PHYS_64BIT
@@ -169,6 +166,7 @@
 	printf("IP addr     = %s\n", getenv("ipaddr"));
 	printf("baudrate    = %6u bps\n", bd->bi_baudrate);
 	print_num("relocaddr", gd->relocaddr);
+	board_detail();
 	return 0;
 }
 
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 7438469..05130b6 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -36,6 +36,7 @@
 #include <lmb.h>
 #include <linux/ctype.h>
 #include <asm/byteorder.h>
+#include <asm/io.h>
 #include <linux/compiler.h>
 
 #if defined(CONFIG_CMD_USB)
@@ -92,12 +93,7 @@
 static void fixup_silent_linux(void);
 #endif
 
-static image_header_t *image_get_kernel(ulong img_addr, int verify);
-#if defined(CONFIG_FIT)
-static int fit_check_kernel(const void *fit, int os_noffset, int verify);
-#endif
-
-static void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc,
+static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc,
 				char * const argv[], bootm_headers_t *images,
 				ulong *os_data, ulong *os_len);
 
@@ -203,8 +199,8 @@
 
 static int bootm_start(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	void		*os_hdr;
-	int		ret;
+	const void *os_hdr;
+	int ret;
 
 	memset((void *)&images, 0, sizeof(images));
 	images.verify = getenv_yesno("verify");
@@ -275,7 +271,7 @@
 #if defined(CONFIG_FIT)
 	} else if (images.fit_uname_os) {
 		ret = fit_image_get_entry(images.fit_hdr_os,
-				images.fit_noffset_os, &images.ep);
+					  images.fit_noffset_os, &images.ep);
 		if (ret) {
 			puts("Can't get entry point property!\n");
 			return 1;
@@ -305,7 +301,7 @@
 
 #if defined(CONFIG_OF_LIBFDT)
 		/* find flattened device tree */
-		ret = boot_get_fdt(flag, argc, argv, &images,
+		ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images,
 				   &images.ft_addr, &images.ft_len);
 		if (ret) {
 			puts("Could not find a valid device tree\n");
@@ -335,12 +331,15 @@
 	ulong image_len = os.image_len;
 	__maybe_unused uint unc_len = CONFIG_SYS_BOOTM_LEN;
 	int no_overlap = 0;
+	void *load_buf, *image_buf;
 #if defined(CONFIG_LZMA) || defined(CONFIG_LZO)
 	int ret;
 #endif /* defined(CONFIG_LZMA) || defined(CONFIG_LZO) */
 
 	const char *type_name = genimg_get_type_name(os.type);
 
+	load_buf = map_sysmem(load, image_len);
+	image_buf = map_sysmem(image_start, image_len);
 	switch (comp) {
 	case IH_COMP_NONE:
 		if (load == blob_start || load == image_start) {
@@ -348,8 +347,7 @@
 			no_overlap = 1;
 		} else {
 			printf("   Loading %s ... ", type_name);
-			memmove_wd((void *)load, (void *)image_start,
-					image_len, CHUNKSZ);
+			memmove_wd(load_buf, image_buf, image_len, CHUNKSZ);
 		}
 		*load_end = load + image_len;
 		puts("OK\n");
@@ -357,8 +355,7 @@
 #ifdef CONFIG_GZIP
 	case IH_COMP_GZIP:
 		printf("   Uncompressing %s ... ", type_name);
-		if (gunzip((void *)load, unc_len,
-				(uchar *)image_start, &image_len) != 0) {
+		if (gunzip(load_buf, unc_len, image_buf, &image_len) != 0) {
 			puts("GUNZIP: uncompress, out-of-mem or overwrite "
 				"error - must RESET board to recover\n");
 			if (boot_progress)
@@ -377,9 +374,9 @@
 		 * use slower decompression algorithm which requires
 		 * at most 2300 KB of memory.
 		 */
-		int i = BZ2_bzBuffToBuffDecompress((char *)load,
-					&unc_len, (char *)image_start, image_len,
-					CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0);
+		int i = BZ2_bzBuffToBuffDecompress(load_buf, &unc_len,
+			image_buf, image_len,
+			CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0);
 		if (i != BZ_OK) {
 			printf("BUNZIP2: uncompress or overwrite error %d "
 				"- must RESET board to recover\n", i);
@@ -396,9 +393,8 @@
 		SizeT lzma_len = unc_len;
 		printf("   Uncompressing %s ... ", type_name);
 
-		ret = lzmaBuffToBuffDecompress(
-			(unsigned char *)load, &lzma_len,
-			(unsigned char *)image_start, image_len);
+		ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len,
+					       image_buf, image_len);
 		unc_len = lzma_len;
 		if (ret != SZ_OK) {
 			printf("LZMA: uncompress or overwrite error %d "
@@ -414,9 +410,8 @@
 	case IH_COMP_LZO:
 		printf("   Uncompressing %s ... ", type_name);
 
-		ret = lzop_decompress((const unsigned char *)image_start,
-					  image_len, (unsigned char *)load,
-					  &unc_len);
+		ret = lzop_decompress(image_buf, image_len, load_buf,
+				      &unc_len);
 		if (ret != LZO_E_OK) {
 			printf("LZO: uncompress or overwrite error %d "
 			      "- must RESET board to recover\n", ret);
@@ -796,54 +791,6 @@
 }
 
 /**
- * fit_check_kernel - verify FIT format kernel subimage
- * @fit_hdr: pointer to the FIT image header
- * os_noffset: kernel subimage node offset within FIT image
- * @verify: data CRC verification flag
- *
- * fit_check_kernel() verifies integrity of the kernel subimage and from
- * specified FIT image.
- *
- * returns:
- *     1, on success
- *     0, on failure
- */
-#if defined(CONFIG_FIT)
-static int fit_check_kernel(const void *fit, int os_noffset, int verify)
-{
-	fit_image_print(fit, os_noffset, "   ");
-
-	if (verify) {
-		puts("   Verifying Hash Integrity ... ");
-		if (!fit_image_check_hashes(fit, os_noffset)) {
-			puts("Bad Data Hash\n");
-			bootstage_error(BOOTSTAGE_ID_FIT_CHECK_HASH);
-			return 0;
-		}
-		puts("OK\n");
-	}
-	bootstage_mark(BOOTSTAGE_ID_FIT_CHECK_ARCH);
-
-	if (!fit_image_check_target_arch(fit, os_noffset)) {
-		puts("Unsupported Architecture\n");
-		bootstage_error(BOOTSTAGE_ID_FIT_CHECK_ARCH);
-		return 0;
-	}
-
-	bootstage_mark(BOOTSTAGE_ID_FIT_CHECK_KERNEL);
-	if (!fit_image_check_type(fit, os_noffset, IH_TYPE_KERNEL) &&
-	    !fit_image_check_type(fit, os_noffset, IH_TYPE_KERNEL_NOLOAD)) {
-		puts("Not a kernel image\n");
-		bootstage_error(BOOTSTAGE_ID_FIT_CHECK_KERNEL);
-		return 0;
-	}
-
-	bootstage_mark(BOOTSTAGE_ID_FIT_CHECKED);
-	return 1;
-}
-#endif /* CONFIG_FIT */
-
-/**
  * boot_get_kernel - find kernel image
  * @os_data: pointer to a ulong variable, will hold os data start address
  * @os_len: pointer to a ulong variable, will hold os data length
@@ -855,19 +802,16 @@
  *     pointer to image header if valid image was found, plus kernel start
  *     address and length, otherwise NULL
  */
-static void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc,
+static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc,
 		char * const argv[], bootm_headers_t *images, ulong *os_data,
 		ulong *os_len)
 {
 	image_header_t	*hdr;
 	ulong		img_addr;
+	const void *buf;
 #if defined(CONFIG_FIT)
-	void		*fit_hdr;
 	const char	*fit_uname_config = NULL;
 	const char	*fit_uname_kernel = NULL;
-	const void	*data;
-	size_t		len;
-	int		cfg_noffset;
 	int		os_noffset;
 #endif
 
@@ -898,7 +842,8 @@
 
 	/* check image type, for FIT images get FIT kernel node */
 	*os_data = *os_len = 0;
-	switch (genimg_get_format((void *)img_addr)) {
+	buf = map_sysmem(img_addr, 0);
+	switch (genimg_get_format(buf)) {
 	case IMAGE_FORMAT_LEGACY:
 		printf("## Booting kernel from Legacy Image at %08lx ...\n",
 				img_addr);
@@ -943,84 +888,16 @@
 		break;
 #if defined(CONFIG_FIT)
 	case IMAGE_FORMAT_FIT:
-		fit_hdr = (void *)img_addr;
-		printf("## Booting kernel from FIT Image at %08lx ...\n",
-				img_addr);
-
-		if (!fit_check_format(fit_hdr)) {
-			puts("Bad FIT kernel image format!\n");
-			bootstage_error(BOOTSTAGE_ID_FIT_FORMAT);
-			return NULL;
-		}
-		bootstage_mark(BOOTSTAGE_ID_FIT_FORMAT);
-
-		if (!fit_uname_kernel) {
-			/*
-			 * no kernel image node unit name, try to get config
-			 * node first. If config unit node name is NULL
-			 * fit_conf_get_node() will try to find default config
-			 * node
-			 */
-			bootstage_mark(BOOTSTAGE_ID_FIT_NO_UNIT_NAME);
-#ifdef CONFIG_FIT_BEST_MATCH
-			if (fit_uname_config)
-				cfg_noffset =
-					fit_conf_get_node(fit_hdr,
-							  fit_uname_config);
-			else
-				cfg_noffset =
-					fit_conf_find_compat(fit_hdr,
-							     gd->fdt_blob);
-#else
-			cfg_noffset = fit_conf_get_node(fit_hdr,
-							fit_uname_config);
-#endif
-			if (cfg_noffset < 0) {
-				bootstage_error(BOOTSTAGE_ID_FIT_NO_UNIT_NAME);
-				return NULL;
-			}
-			/* save configuration uname provided in the first
-			 * bootm argument
-			 */
-			images->fit_uname_cfg = fdt_get_name(fit_hdr,
-								cfg_noffset,
-								NULL);
-			printf("   Using '%s' configuration\n",
-				images->fit_uname_cfg);
-			bootstage_mark(BOOTSTAGE_ID_FIT_CONFIG);
-
-			os_noffset = fit_conf_get_kernel_node(fit_hdr,
-								cfg_noffset);
-			fit_uname_kernel = fit_get_name(fit_hdr, os_noffset,
-							NULL);
-		} else {
-			/* get kernel component image node offset */
-			bootstage_mark(BOOTSTAGE_ID_FIT_UNIT_NAME);
-			os_noffset = fit_image_get_node(fit_hdr,
-							fit_uname_kernel);
-		}
-		if (os_noffset < 0) {
-			bootstage_error(BOOTSTAGE_ID_FIT_CONFIG);
-			return NULL;
-		}
-
-		printf("   Trying '%s' kernel subimage\n", fit_uname_kernel);
-
-		bootstage_mark(BOOTSTAGE_ID_FIT_CHECK_SUBIMAGE);
-		if (!fit_check_kernel(fit_hdr, os_noffset, images->verify))
+		os_noffset = fit_image_load(images, FIT_KERNEL_PROP,
+				img_addr,
+				&fit_uname_kernel, fit_uname_config,
+				IH_ARCH_DEFAULT, IH_TYPE_KERNEL,
+				BOOTSTAGE_ID_FIT_KERNEL_START,
+				FIT_LOAD_IGNORED, os_data, os_len);
+		if (os_noffset < 0)
 			return NULL;
 
-		/* get kernel image data address and length */
-		if (fit_image_get_data(fit_hdr, os_noffset, &data, &len)) {
-			puts("Could not find kernel subimage data!\n");
-			bootstage_error(BOOTSTAGE_ID_FIT_KERNEL_INFO_ERR);
-			return NULL;
-		}
-		bootstage_mark(BOOTSTAGE_ID_FIT_KERNEL_INFO);
-
-		*os_len = len;
-		*os_data = (ulong)data;
-		images->fit_hdr_os = fit_hdr;
+		images->fit_hdr_os = map_sysmem(img_addr, 0);
 		images->fit_uname_os = fit_uname_kernel;
 		images->fit_noffset_os = os_noffset;
 		break;
@@ -1034,7 +911,7 @@
 	debug("   kernel data at 0x%08lx, len = 0x%08lx (%ld)\n",
 			*os_data, *os_len, *os_len);
 
-	return (void *)img_addr;
+	return buf;
 }
 
 #ifdef CONFIG_SYS_LONGHELP
@@ -1169,7 +1046,7 @@
 
 		fit_print_contents(hdr);
 
-		if (!fit_all_image_check_hashes(hdr)) {
+		if (!fit_all_image_verify(hdr)) {
 			puts("Bad hash in FIT image!\n");
 			return 1;
 		}
@@ -1420,9 +1297,14 @@
 /* helper routines */
 /*******************************************************************/
 #if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY)
+
+#define CONSOLE_ARG     "console="
+#define CONSOLE_ARG_LEN (sizeof(CONSOLE_ARG) - 1)
+
 static void fixup_silent_linux(void)
 {
-	char buf[256], *start, *end;
+	char *buf;
+	const char *env_val;
 	char *cmdline = getenv("bootargs");
 
 	/* Only fix cmdline when requested */
@@ -1430,25 +1312,37 @@
 		return;
 
 	debug("before silent fix-up: %s\n", cmdline);
-	if (cmdline) {
-		start = strstr(cmdline, "console=");
-		if (start) {
-			end = strchr(start, ' ');
-			strncpy(buf, cmdline, (start - cmdline + 8));
-			if (end)
-				strcpy(buf + (start - cmdline + 8), end);
-			else
-				buf[start - cmdline + 8] = '\0';
-		} else {
-			strcpy(buf, cmdline);
-			strcat(buf, " console=");
+	if (cmdline && (cmdline[0] != '\0')) {
+		char *start = strstr(cmdline, CONSOLE_ARG);
+
+		/* Allocate space for maximum possible new command line */
+		buf = malloc(strlen(cmdline) + 1 + CONSOLE_ARG_LEN + 1);
+		if (!buf) {
+			debug("%s: out of memory\n", __func__);
+			return;
 		}
+
+		if (start) {
+			char *end = strchr(start, ' ');
+			int num_start_bytes = start - cmdline + CONSOLE_ARG_LEN;
+
+			strncpy(buf, cmdline, num_start_bytes);
+			if (end)
+				strcpy(buf + num_start_bytes, end);
+			else
+				buf[num_start_bytes] = '\0';
+		} else {
+			sprintf(buf, "%s %s", cmdline, CONSOLE_ARG);
+		}
+		env_val = buf;
 	} else {
-		strcpy(buf, "console=");
+		buf = NULL;
+		env_val = CONSOLE_ARG;
 	}
 
-	setenv("bootargs", buf);
-	debug("after silent fix-up: %s\n", buf);
+	setenv("bootargs", env_val);
+	debug("after silent fix-up: %s\n", env_val);
+	free(buf);
 }
 #endif /* CONFIG_SILENT_CONSOLE */
 
@@ -1800,7 +1694,7 @@
 
 #if defined(CONFIG_OF_LIBFDT)
 	/* find flattened device tree */
-	ret = boot_get_fdt(flag, argc, argv, images,
+	ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, images,
 			   &images->ft_addr, &images->ft_len);
 	if (ret) {
 		puts("Could not find a valid device tree\n");
diff --git a/common/cmd_fitupd.c b/common/cmd_fitupd.c
index 7a3789e..618ff7c 100644
--- a/common/cmd_fitupd.c
+++ b/common/cmd_fitupd.c
@@ -8,13 +8,12 @@
 
 #include <common.h>
 #include <command.h>
+#include <net.h>
 
 #if !defined(CONFIG_UPDATE_TFTP)
 #error "CONFIG_UPDATE_TFTP required"
 #endif
 
-extern int update_tftp(ulong addr);
-
 static int do_fitupd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	ulong addr = 0UL;
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index 1834246..3cd1b13 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -27,14 +27,11 @@
  */
 #include <common.h>
 #include <command.h>
-#if defined(CONFIG_CMD_NET)
-#include <net.h>
-#endif
 #include <fpga.h>
 #include <malloc.h>
 
 /* Local functions */
-static int fpga_get_op (char *opstr);
+static int fpga_get_op(char *opstr);
 
 /* Local defines */
 #define FPGA_NONE   -1
@@ -44,102 +41,6 @@
 #define FPGA_DUMP   3
 #define FPGA_LOADMK 4
 
-/* Convert bitstream data and load into the fpga */
-int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
-{
-#if defined(CONFIG_FPGA_XILINX)
-	unsigned int length;
-	unsigned int swapsize;
-	char buffer[80];
-	unsigned char *dataptr;
-	unsigned int i;
-	int rc;
-
-	dataptr = (unsigned char *)fpgadata;
-
-	/* skip the first bytes of the bitsteam, their meaning is unknown */
-	length = (*dataptr << 8) + *(dataptr+1);
-	dataptr+=2;
-	dataptr+=length;
-
-	/* get design name (identifier, length, string) */
-	length = (*dataptr << 8) + *(dataptr+1);
-	dataptr+=2;
-	if (*dataptr++ != 0x61) {
-		debug("%s: Design name identifier not recognized "
-			"in bitstream\n",
-			__func__);
-		return FPGA_FAIL;
-	}
-
-	length = (*dataptr << 8) + *(dataptr+1);
-	dataptr+=2;
-	for(i=0;i<length;i++)
-		buffer[i] = *dataptr++;
-
-	printf("  design filename = \"%s\"\n", buffer);
-
-	/* get part number (identifier, length, string) */
-	if (*dataptr++ != 0x62) {
-		printf("%s: Part number identifier not recognized "
-			"in bitstream\n",
-			__func__);
-		return FPGA_FAIL;
-	}
-
-	length = (*dataptr << 8) + *(dataptr+1);
-	dataptr+=2;
-	for(i=0;i<length;i++)
-		buffer[i] = *dataptr++;
-	printf("  part number = \"%s\"\n", buffer);
-
-	/* get date (identifier, length, string) */
-	if (*dataptr++ != 0x63) {
-		printf("%s: Date identifier not recognized in bitstream\n",
-		       __func__);
-		return FPGA_FAIL;
-	}
-
-	length = (*dataptr << 8) + *(dataptr+1);
-	dataptr+=2;
-	for(i=0;i<length;i++)
-		buffer[i] = *dataptr++;
-	printf("  date = \"%s\"\n", buffer);
-
-	/* get time (identifier, length, string) */
-	if (*dataptr++ != 0x64) {
-		printf("%s: Time identifier not recognized in bitstream\n",
-			__func__);
-		return FPGA_FAIL;
-	}
-
-	length = (*dataptr << 8) + *(dataptr+1);
-	dataptr+=2;
-	for(i=0;i<length;i++)
-		buffer[i] = *dataptr++;
-	printf("  time = \"%s\"\n", buffer);
-
-	/* get fpga data length (identifier, length) */
-	if (*dataptr++ != 0x65) {
-		printf("%s: Data length identifier not recognized in bitstream\n",
-			__func__);
-		return FPGA_FAIL;
-	}
-	swapsize = ((unsigned int) *dataptr     <<24) +
-	           ((unsigned int) *(dataptr+1) <<16) +
-	           ((unsigned int) *(dataptr+2) <<8 ) +
-	           ((unsigned int) *(dataptr+3)     ) ;
-	dataptr+=4;
-	printf("  bytes in bitstream = %d\n", swapsize);
-
-	rc = fpga_load(dev, dataptr, swapsize);
-	return rc;
-#else
-	printf("Bitstream support only for Xilinx devices\n");
-	return FPGA_FAIL;
-#endif
-}
-
 /* ------------------------------------------------------------------------- */
 /* command form:
  *   fpga <op> <device number> <data addr> <datasize>
@@ -148,81 +49,81 @@
  * If there is no data addr field, the fpgadata environment variable is used.
  * The info command requires no data address field.
  */
-int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
 	int op, dev = FPGA_INVALID_DEVICE;
 	size_t data_size = 0;
 	void *fpga_data = NULL;
-	char *devstr = getenv ("fpga");
-	char *datastr = getenv ("fpgadata");
+	char *devstr = getenv("fpga");
+	char *datastr = getenv("fpgadata");
 	int rc = FPGA_FAIL;
 	int wrong_parms = 0;
-#if defined (CONFIG_FIT)
+#if defined(CONFIG_FIT)
 	const char *fit_uname = NULL;
 	ulong fit_addr;
 #endif
 
 	if (devstr)
-		dev = (int) simple_strtoul (devstr, NULL, 16);
+		dev = (int) simple_strtoul(devstr, NULL, 16);
 	if (datastr)
-		fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
+		fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
 
 	switch (argc) {
 	case 5:		/* fpga <op> <dev> <data> <datasize> */
-		data_size = simple_strtoul (argv[4], NULL, 16);
+		data_size = simple_strtoul(argv[4], NULL, 16);
 
 	case 4:		/* fpga <op> <dev> <data> */
 #if defined(CONFIG_FIT)
-		if (fit_parse_subimage (argv[3], (ulong)fpga_data,
-					&fit_addr, &fit_uname)) {
+		if (fit_parse_subimage(argv[3], (ulong)fpga_data,
+				       &fit_addr, &fit_uname)) {
 			fpga_data = (void *)fit_addr;
-			debug("*  fpga: subimage '%s' from FIT image "
-				"at 0x%08lx\n",
-				fit_uname, fit_addr);
+			debug("*  fpga: subimage '%s' from FIT image ",
+			      fit_uname);
+			debug("at 0x%08lx\n", fit_addr);
 		} else
 #endif
 		{
-			fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
+			fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
 			debug("*  fpga: cmdline image address = 0x%08lx\n",
-				(ulong)fpga_data);
+			      (ulong)fpga_data);
 		}
-		debug("%s: fpga_data = 0x%x\n", __func__, (uint) fpga_data);
+		debug("%s: fpga_data = 0x%x\n", __func__, (uint)fpga_data);
 
 	case 3:		/* fpga <op> <dev | data addr> */
-		dev = (int) simple_strtoul (argv[2], NULL, 16);
+		dev = (int)simple_strtoul(argv[2], NULL, 16);
 		debug("%s: device = %d\n", __func__, dev);
 		/* FIXME - this is a really weak test */
-		if ((argc == 3) && (dev > fpga_count ())) {	/* must be buffer ptr */
+		if ((argc == 3) && (dev > fpga_count())) {
+			/* must be buffer ptr */
 			debug("%s: Assuming buffer pointer in arg 3\n",
-				__func__);
+			      __func__);
 
 #if defined(CONFIG_FIT)
-			if (fit_parse_subimage (argv[2], (ulong)fpga_data,
-						&fit_addr, &fit_uname)) {
+			if (fit_parse_subimage(argv[2], (ulong)fpga_data,
+					       &fit_addr, &fit_uname)) {
 				fpga_data = (void *)fit_addr;
-				debug("*  fpga: subimage '%s' from FIT image "
-					"at 0x%08lx\n",
-					fit_uname, fit_addr);
+				debug("*  fpga: subimage '%s' from FIT image ",
+				      fit_uname);
+				debug("at 0x%08lx\n", fit_addr);
 			} else
 #endif
 			{
-				fpga_data = (void *) dev;
-				debug("*  fpga: cmdline image address = "
-					"0x%08lx\n", (ulong)fpga_data);
+				fpga_data = (void *)dev;
+				debug("*  fpga: cmdline image addr = 0x%08lx\n",
+				      (ulong)fpga_data);
 			}
 
 			debug("%s: fpga_data = 0x%x\n",
-				__func__, (uint) fpga_data);
+			      __func__, (uint)fpga_data);
 			dev = FPGA_INVALID_DEVICE;	/* reset device num */
 		}
 
 	case 2:		/* fpga <op> */
-		op = (int) fpga_get_op (argv[1]);
+		op = (int)fpga_get_op(argv[1]);
 		break;
 
 	default:
-		debug("%s: Too many or too few args (%d)\n",
-			__func__, argc);
+		debug("%s: Too many or too few args (%d)\n", __func__, argc);
 		op = FPGA_NONE;	/* force usage display */
 		break;
 	}
@@ -258,11 +159,11 @@
 		return CMD_RET_USAGE;
 
 	case FPGA_INFO:
-		rc = fpga_info (dev);
+		rc = fpga_info(dev);
 		break;
 
 	case FPGA_LOAD:
-		rc = fpga_load (dev, fpga_data, data_size);
+		rc = fpga_load(dev, fpga_data, data_size);
 		break;
 
 	case FPGA_LOADB:
@@ -270,15 +171,16 @@
 		break;
 
 	case FPGA_LOADMK:
-		switch (genimg_get_format (fpga_data)) {
+		switch (genimg_get_format(fpga_data)) {
 		case IMAGE_FORMAT_LEGACY:
 			{
-				image_header_t *hdr = (image_header_t *)fpga_data;
-				ulong	data;
+				image_header_t *hdr =
+						(image_header_t *)fpga_data;
+				ulong data;
 
-				data = (ulong)image_get_data (hdr);
-				data_size = image_get_data_size (hdr);
-				rc = fpga_load (dev, (void *)data, data_size);
+				data = (ulong)image_get_data(hdr);
+				data_size = image_get_data_size(hdr);
+				rc = fpga_load(dev, (void *)data, data_size);
 			}
 			break;
 #if defined(CONFIG_FIT)
@@ -289,95 +191,97 @@
 				const void *fit_data;
 
 				if (fit_uname == NULL) {
-					puts ("No FIT subimage unit name\n");
+					puts("No FIT subimage unit name\n");
 					return 1;
 				}
 
-				if (!fit_check_format (fit_hdr)) {
-					puts ("Bad FIT image format\n");
+				if (!fit_check_format(fit_hdr)) {
+					puts("Bad FIT image format\n");
 					return 1;
 				}
 
 				/* get fpga component image node offset */
-				noffset = fit_image_get_node (fit_hdr, fit_uname);
+				noffset = fit_image_get_node(fit_hdr,
+							     fit_uname);
 				if (noffset < 0) {
-					printf ("Can't find '%s' FIT subimage\n", fit_uname);
+					printf("Can't find '%s' FIT subimage\n",
+					       fit_uname);
 					return 1;
 				}
 
 				/* verify integrity */
-				if (!fit_image_check_hashes (fit_hdr, noffset)) {
+				if (!fit_image_verify(fit_hdr, noffset)) {
 					puts ("Bad Data Hash\n");
 					return 1;
 				}
 
 				/* get fpga subimage data address and length */
-				if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
-					puts ("Could not find fpga subimage data\n");
+				if (fit_image_get_data(fit_hdr, noffset,
+						       &fit_data, &data_size)) {
+					puts("Fpga subimage data not found\n");
 					return 1;
 				}
 
-				rc = fpga_load (dev, fit_data, data_size);
+				rc = fpga_load(dev, fit_data, data_size);
 			}
 			break;
 #endif
 		default:
-			puts ("** Unknown image type\n");
+			puts("** Unknown image type\n");
 			rc = FPGA_FAIL;
 			break;
 		}
 		break;
 
 	case FPGA_DUMP:
-		rc = fpga_dump (dev, fpga_data, data_size);
+		rc = fpga_dump(dev, fpga_data, data_size);
 		break;
 
 	default:
-		printf ("Unknown operation\n");
+		printf("Unknown operation\n");
 		return CMD_RET_USAGE;
 	}
-	return (rc);
+	return rc;
 }
 
 /*
  * Map op to supported operations.  We don't use a table since we
  * would just have to relocate it from flash anyway.
  */
-static int fpga_get_op (char *opstr)
+static int fpga_get_op(char *opstr)
 {
 	int op = FPGA_NONE;
 
-	if (!strcmp ("info", opstr)) {
+	if (!strcmp("info", opstr))
 		op = FPGA_INFO;
-	} else if (!strcmp ("loadb", opstr)) {
+	else if (!strcmp("loadb", opstr))
 		op = FPGA_LOADB;
-	} else if (!strcmp ("load", opstr)) {
+	else if (!strcmp("load", opstr))
 		op = FPGA_LOAD;
-	} else if (!strcmp ("loadmk", opstr)) {
+	else if (!strcmp("loadmk", opstr))
 		op = FPGA_LOADMK;
-	} else if (!strcmp ("dump", opstr)) {
+	else if (!strcmp("dump", opstr))
 		op = FPGA_DUMP;
-	}
 
-	if (op == FPGA_NONE) {
-		printf ("Unknown fpga operation \"%s\"\n", opstr);
-	}
+	if (op == FPGA_NONE)
+		printf("Unknown fpga operation \"%s\"\n", opstr);
+
 	return op;
 }
 
-U_BOOT_CMD (fpga, 6, 1, do_fpga,
-	"loadable FPGA image support",
-	"[operation type] [device number] [image address] [image size]\n"
-	"fpga operations:\n"
-	"  dump\t[dev]\t\t\tLoad device to memory buffer\n"
-	"  info\t[dev]\t\t\tlist known device information\n"
-	"  load\t[dev] [address] [size]\tLoad device from memory buffer\n"
-	"  loadb\t[dev] [address] [size]\t"
-	"Load device from bitstream buffer (Xilinx only)\n"
-	"  loadmk [dev] [address]\tLoad device generated with mkimage"
+U_BOOT_CMD(fpga, 6, 1, do_fpga,
+	   "loadable FPGA image support",
+	   "[operation type] [device number] [image address] [image size]\n"
+	   "fpga operations:\n"
+	   "  dump\t[dev]\t\t\tLoad device to memory buffer\n"
+	   "  info\t[dev]\t\t\tlist known device information\n"
+	   "  load\t[dev] [address] [size]\tLoad device from memory buffer\n"
+	   "  loadb\t[dev] [address] [size]\t"
+	   "Load device from bitstream buffer (Xilinx only)\n"
+	   "  loadmk [dev] [address]\tLoad device generated with mkimage"
 #if defined(CONFIG_FIT)
-	"\n"
-	"\tFor loadmk operating on FIT format uImage address must include\n"
-	"\tsubimage unit name in the form of addr:<subimg_uname>"
+	   "\n"
+	   "\tFor loadmk operating on FIT format uImage address must include\n"
+	   "\tsubimage unit name in the form of addr:<subimg_uname>"
 #endif
 );
diff --git a/common/cmd_fuse.c b/common/cmd_fuse.c
new file mode 100644
index 0000000..f24c01c
--- /dev/null
+++ b/common/cmd_fuse.c
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2009-2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on the mpc512x iim code:
+ * Copyright 2008 Silicon Turnkey Express, Inc.
+ * Martha Marx <mmarx@silicontkx.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fuse.h>
+#include <asm/errno.h>
+
+static int strtou32(const char *str, unsigned int base, u32 *result)
+{
+	char *ep;
+
+	*result = simple_strtoul(str, &ep, base);
+	if (ep == str || *ep != '\0')
+		return -EINVAL;
+
+	return 0;
+}
+
+static int confirm_prog(void)
+{
+	puts("Warning: Programming fuses is an irreversible operation!\n"
+			"         This may brick your system.\n"
+			"         Use this command only if you are sure of "
+					"what you are doing!\n"
+			"\nReally perform this fuse programming? <y/N>\n");
+
+	if (getc() == 'y') {
+		int c;
+
+		putc('y');
+		c = getc();
+		putc('\n');
+		if (c == '\r')
+			return 1;
+	}
+
+	puts("Fuse programming aborted\n");
+	return 0;
+}
+
+static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	const char *op = argc >= 2 ? argv[1] : NULL;
+	int confirmed = argc >= 3 && !strcmp(argv[2], "-y");
+	u32 bank, word, cnt, val;
+	int ret, i;
+
+	argc -= 2 + confirmed;
+	argv += 2 + confirmed;
+
+	if (argc < 2 || strtou32(argv[0], 0, &bank) ||
+			strtou32(argv[1], 0, &word))
+		return CMD_RET_USAGE;
+
+	if (!strcmp(op, "read")) {
+		if (argc == 2)
+			cnt = 1;
+		else if (argc != 3 || strtou32(argv[2], 0, &cnt))
+			return CMD_RET_USAGE;
+
+		printf("Reading bank %u:\n", bank);
+		for (i = 0; i < cnt; i++, word++) {
+			if (!(i % 4))
+				printf("\nWord 0x%.8x:", word);
+
+			ret = fuse_read(bank, word, &val);
+			if (ret)
+				goto err;
+
+			printf(" %.8x", val);
+		}
+		putc('\n');
+	} else if (!strcmp(op, "sense")) {
+		if (argc == 2)
+			cnt = 1;
+		else if (argc != 3 || strtou32(argv[2], 0, &cnt))
+			return CMD_RET_USAGE;
+
+		printf("Sensing bank %u:\n", bank);
+		for (i = 0; i < cnt; i++, word++) {
+			if (!(i % 4))
+				printf("\nWord 0x%.8x:", word);
+
+			ret = fuse_sense(bank, word, &val);
+			if (ret)
+				goto err;
+
+			printf(" %.8x", val);
+		}
+		putc('\n');
+	} else if (!strcmp(op, "prog")) {
+		if (argc < 3)
+			return CMD_RET_USAGE;
+
+		for (i = 2; i < argc; i++, word++) {
+			if (strtou32(argv[i], 16, &val))
+				return CMD_RET_USAGE;
+
+			printf("Programming bank %u word 0x%.8x to 0x%.8x...\n",
+					bank, word, val);
+			if (!confirmed && !confirm_prog())
+				return CMD_RET_FAILURE;
+			ret = fuse_prog(bank, word, val);
+			if (ret)
+				goto err;
+		}
+	} else if (!strcmp(op, "override")) {
+		if (argc < 3)
+			return CMD_RET_USAGE;
+
+		for (i = 2; i < argc; i++, word++) {
+			if (strtou32(argv[i], 16, &val))
+				return CMD_RET_USAGE;
+
+			printf("Overriding bank %u word 0x%.8x with "
+					"0x%.8x...\n", bank, word, val);
+			ret = fuse_override(bank, word, val);
+			if (ret)
+				goto err;
+		}
+	} else {
+		return CMD_RET_USAGE;
+	}
+
+	return 0;
+
+err:
+	puts("ERROR\n");
+	return ret;
+}
+
+U_BOOT_CMD(
+	fuse, CONFIG_SYS_MAXARGS, 0, do_fuse,
+	"Fuse sub-system",
+	     "read <bank> <word> [<cnt>] - read 1 or 'cnt' fuse words,\n"
+	"    starting at 'word'\n"
+	"fuse sense <bank> <word> [<cnt>] - sense 1 or 'cnt' fuse words,\n"
+	"    starting at 'word'\n"
+	"fuse prog [-y] <bank> <word> <hexval> [<hexval>...] - program 1 or\n"
+	"    several fuse words, starting at 'word' (PERMANENT)\n"
+	"fuse override <bank> <word> <hexval> [<hexval>...] - override 1 or\n"
+	"    several fuse words, starting at 'word'"
+);
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index 64dd76a..6df00b1 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -445,7 +445,7 @@
 #endif
 
 	bytes = size * count;
-	buf = map_sysmem(addr, bytes);
+	buf = map_sysmem(dest, bytes);
 	src = map_sysmem(addr, bytes);
 	while (count-- > 0) {
 		if (size == 4)
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index e9d3d3c..8b1e01a 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -62,8 +62,8 @@
 	ops.oobbuf = oobbuf;
 	ops.len = nand->writesize;
 	ops.ooblen = nand->oobsize;
-	ops.mode = MTD_OOB_RAW;
-	i = nand->read_oob(nand, addr, &ops);
+	ops.mode = MTD_OPS_RAW;
+	i = mtd_read_oob(nand, addr, &ops);
 	if (i < 0) {
 		printf("Error (%d) reading page %08lx\n", i, off);
 		free(datbuf);
@@ -404,13 +404,13 @@
 			.oobbuf = ((u8 *)addr) + nand->writesize,
 			.len = nand->writesize,
 			.ooblen = nand->oobsize,
-			.mode = MTD_OOB_RAW
+			.mode = MTD_OPS_RAW
 		};
 
 		if (read)
-			ret = nand->read_oob(nand, off, &ops);
+			ret = mtd_read_oob(nand, off, &ops);
 		else
-			ret = nand->write_oob(nand, off, &ops);
+			ret = mtd_write_oob(nand, off, &ops);
 
 		if (ret) {
 			printf("%s: error at offset %llx, ret %d\n",
@@ -425,6 +425,31 @@
 	return ret;
 }
 
+/* Adjust a chip/partition size down for bad blocks so we don't
+ * read/write/erase past the end of a chip/partition by accident.
+ */
+static void adjust_size_for_badblocks(loff_t *size, loff_t offset, int dev)
+{
+	/* We grab the nand info object here fresh because this is usually
+	 * called after arg_off_size() which can change the value of dev.
+	 */
+	nand_info_t *nand = &nand_info[dev];
+	loff_t maxoffset = offset + *size;
+	int badblocks = 0;
+
+	/* count badblocks in NAND from offset to offset + size */
+	for (; offset < maxoffset; offset += nand->erasesize) {
+		if (nand_block_isbad(nand, offset))
+			badblocks++;
+	}
+	/* adjust size if any bad blocks found */
+	if (badblocks) {
+		*size -= badblocks * nand->erasesize;
+		printf("size adjusted to 0x%llx (%d bad blocks)\n",
+		       (unsigned long long)*size, badblocks);
+	}
+}
+
 static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	int i, ret = 0;
@@ -521,6 +546,7 @@
 		int scrub = !strncmp(cmd, "scrub", 5);
 		int spread = 0;
 		int args = 2;
+		int adjust_size = 0;
 		const char *scrub_warn =
 			"Warning: "
 			"scrub option will erase all factory set bad blocks!\n"
@@ -537,8 +563,10 @@
 				spread = 1;
 			} else if (!strcmp(&cmd[5], ".part")) {
 				args = 1;
+				adjust_size = 1;
 			} else if (!strcmp(&cmd[5], ".chip")) {
 				args = 0;
+				adjust_size = 1;
 			} else {
 				goto usage;
 			}
@@ -558,6 +586,10 @@
 				 &maxsize) != 0)
 			return 1;
 
+		/* size is unspecified */
+		if (adjust_size && !scrub)
+			adjust_size_for_badblocks(&size, off, dev);
+
 		nand = &nand_info[dev];
 
 		memset(&opts, 0, sizeof(opts));
@@ -642,6 +674,9 @@
 						&off, &size, &maxsize) != 0)
 				return 1;
 
+			/* size is unspecified */
+			if (argc < 5)
+				adjust_size_for_badblocks(&size, off, dev);
 			rwsize = size;
 		}
 
@@ -680,13 +715,13 @@
 			mtd_oob_ops_t ops = {
 				.oobbuf = (u8 *)addr,
 				.ooblen = rwsize,
-				.mode = MTD_OOB_RAW
+				.mode = MTD_OPS_RAW
 			};
 
 			if (read)
-				ret = nand->read_oob(nand, off, &ops);
+				ret = mtd_read_oob(nand, off, &ops);
 			else
-				ret = nand->write_oob(nand, off, &ops);
+				ret = mtd_write_oob(nand, off, &ops);
 		} else if (raw) {
 			ret = raw_access(nand, addr, off, pagecount, read);
 		} else {
@@ -729,7 +764,7 @@
 		while (argc > 0) {
 			addr = simple_strtoul(*argv, NULL, 16);
 
-			if (nand->block_markbad(nand, addr)) {
+			if (mtd_block_markbad(nand, addr)) {
 				printf("block 0x%08lx NOT marked "
 					"as bad! ERROR %d\n",
 					addr, ret);
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index f8dc38e..2478c95 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -314,7 +314,7 @@
 /**
  * Set an environment variable to an integer value
  *
- * @param varname	Environmet variable to set
+ * @param varname	Environment variable to set
  * @param value		Value to set it to
  * @return 0 if ok, 1 on error
  */
@@ -329,7 +329,7 @@
 /**
  * Set an environment variable to an value in hex
  *
- * @param varname	Environmet variable to set
+ * @param varname	Environment variable to set
  * @param value		Value to set it to
  * @return 0 if ok, 1 on error
  */
diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c
index a0d25e5..06cc140 100644
--- a/common/cmd_onenand.c
+++ b/common/cmd_onenand.c
@@ -83,7 +83,7 @@
 		ops.len = blocksize;
 
 	while (blocks) {
-		ret = mtd->block_isbad(mtd, ofs);
+		ret = mtd_block_isbad(mtd, ofs);
 		if (ret) {
 			printk("Bad blocks %d at 0x%x\n",
 			       (u32)(ofs >> this->erase_shift), (u32)ofs);
@@ -97,7 +97,7 @@
 			ops.datbuf = buf;
 
 		ops.retlen = 0;
-		ret = mtd->read_oob(mtd, ofs, &ops);
+		ret = mtd_read_oob(mtd, ofs, &ops);
 		if (ret) {
 			printk("Read failed 0x%x, %d\n", (u32)ofs, ret);
 			ofs += blocksize;
@@ -118,7 +118,7 @@
 	struct mtd_oob_ops ops = {
 		.len = mtd->writesize,
 		.ooblen = mtd->oobsize,
-		.mode = MTD_OOB_AUTO,
+		.mode = MTD_OPS_AUTO_OOB,
 	};
 	int page, ret = 0;
 	for (page = 0; page < (mtd->erasesize / mtd->writesize); page ++) {
@@ -126,7 +126,7 @@
 		buf += mtd->writesize;
 		ops.oobbuf = (u_char *)buf;
 		buf += mtd->oobsize;
-		ret = mtd->write_oob(mtd, to, &ops);
+		ret = mtd_write_oob(mtd, to, &ops);
 		if (ret)
 			break;
 		to += mtd->writesize;
@@ -156,7 +156,7 @@
 	ofs = to;
 
 	while (blocks) {
-		ret = mtd->block_isbad(mtd, ofs);
+		ret = mtd_block_isbad(mtd, ofs);
 		if (ret) {
 			printk("Bad blocks %d at 0x%x\n",
 			       (u32)(ofs >> this->erase_shift), (u32)ofs);
@@ -165,7 +165,7 @@
 		}
 
 		if (!withoob)
-			ret = mtd->write(mtd, ofs, blocksize, &_retlen, buf);
+			ret = mtd_write(mtd, ofs, blocksize, &_retlen, buf);
 		else
 			ret = onenand_write_oneblock_withoob(ofs, buf, &_retlen);
 		if (ret) {
@@ -195,7 +195,7 @@
 	int blocksize = 1 << this->erase_shift;
 
 	for (ofs = start; ofs < (start + size); ofs += blocksize) {
-		ret = mtd->block_isbad(mtd, ofs);
+		ret = mtd_block_isbad(mtd, ofs);
 		if (ret && !force) {
 			printf("Skip erase bad block %d at 0x%x\n",
 			       (u32)(ofs >> this->erase_shift), (u32)ofs);
@@ -206,7 +206,7 @@
 		instr.len = blocksize;
 		instr.priv = force;
 		instr.mtd = mtd;
-		ret = mtd->erase(mtd, &instr);
+		ret = mtd_erase(mtd, &instr);
 		if (ret) {
 			printf("erase failed block %d at 0x%x\n",
 			       (u32)(ofs >> this->erase_shift), (u32)ofs);
@@ -261,7 +261,7 @@
 	while (blocks < end_block) {
 		printf("\rTesting block %d at 0x%x", (u32)(ofs >> this->erase_shift), (u32)ofs);
 
-		ret = mtd->block_isbad(mtd, ofs);
+		ret = mtd_block_isbad(mtd, ofs);
 		if (ret) {
 			printf("Skip erase bad block %d at 0x%x\n",
 			       (u32)(ofs >> this->erase_shift), (u32)ofs);
@@ -270,19 +270,19 @@
 
 		instr.addr = ofs;
 		instr.len = blocksize;
-		ret = mtd->erase(mtd, &instr);
+		ret = mtd_erase(mtd, &instr);
 		if (ret) {
 			printk("Erase failed 0x%x, %d\n", (u32)ofs, ret);
 			goto next;
 		}
 
-		ret = mtd->write(mtd, ofs, blocksize, &retlen, buf);
+		ret = mtd_write(mtd, ofs, blocksize, &retlen, buf);
 		if (ret) {
 			printk("Write failed 0x%x, %d\n", (u32)ofs, ret);
 			goto next;
 		}
 
-		ret = mtd->read(mtd, ofs, blocksize, &retlen, verify_buf);
+		ret = mtd_read(mtd, ofs, blocksize, &retlen, verify_buf);
 		if (ret) {
 			printk("Read failed 0x%x, %d\n", (u32)ofs, ret);
 			goto next;
@@ -324,7 +324,7 @@
 	ops.len = mtd->writesize;
 	ops.ooblen = mtd->oobsize;
 	ops.retlen = 0;
-	i = mtd->read_oob(mtd, addr, &ops);
+	i = mtd_read_oob(mtd, addr, &ops);
 	if (i < 0) {
 		printf("Error (%d) reading page %08lx\n", i, off);
 		free(datbuf);
@@ -373,7 +373,7 @@
 	/* Currently only one OneNAND device is supported */
 	printf("\nDevice %d bad blocks:\n", 0);
 	for (ofs = 0; ofs < mtd->size; ofs += mtd->erasesize) {
-		if (mtd->block_isbad(mtd, ofs))
+		if (mtd_block_isbad(mtd, ofs))
 			printf("  %08x\n", (u32)ofs);
 	}
 
@@ -530,7 +530,7 @@
 	while (argc > 0) {
 		addr = simple_strtoul(*argv, NULL, 16);
 
-		if (mtd->block_markbad(mtd, addr)) {
+		if (mtd_block_markbad(mtd, addr)) {
 			printf("block 0x%08lx NOT marked "
 				"as bad! ERROR %d\n",
 				addr, ret);
diff --git a/common/cmd_softswitch.c b/common/cmd_softswitch.c
new file mode 100644
index 0000000..f75d926
--- /dev/null
+++ b/common/cmd_softswitch.c
@@ -0,0 +1,41 @@
+/*
+ * cmd_softswitch.c - set the softswitch for bf60x
+ *
+ * Copyright (c) 2012 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/soft_switch.h>
+
+int do_softswitch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int switchaddr, value, pin, port;
+
+	if (argc != 5)
+		return CMD_RET_USAGE;
+
+	if (strcmp(argv[2], "GPA") == 0)
+		port = IO_PORT_A;
+	else if (strcmp(argv[2], "GPB") == 0)
+		port = IO_PORT_B;
+	else
+		return CMD_RET_USAGE;
+
+	switchaddr = simple_strtoul(argv[1], NULL, 16);
+	pin = simple_strtoul(argv[3], NULL, 16);
+	value = simple_strtoul(argv[4], NULL, 16);
+
+	config_switch_bit(switchaddr, port, (1 << pin), IO_PORT_OUTPUT, value);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	softswitch_output, 5, 1, do_softswitch,
+	"switchaddr GPA/GPB pin_offset value",
+	""
+);
diff --git a/common/cmd_source.c b/common/cmd_source.c
index f0d7f52..a440614 100644
--- a/common/cmd_source.c
+++ b/common/cmd_source.c
@@ -127,7 +127,7 @@
 
 		/* verify integrity */
 		if (verify) {
-			if (!fit_image_check_hashes (fit_hdr, noffset)) {
+			if (!fit_image_verify(fit_hdr, noffset)) {
 				puts ("Bad Data Hash\n");
 				return 1;
 			}
diff --git a/common/cmd_usb.c b/common/cmd_usb.c
index dacdc2d..70e803b 100644
--- a/common/cmd_usb.c
+++ b/common/cmd_usb.c
@@ -269,14 +269,42 @@
 	printf("\n");
 }
 
+static struct usb_device *usb_find_device(int devnum)
+{
+	struct usb_device *dev;
+	int d;
+
+	for (d = 0; d < USB_MAX_DEVICE; d++) {
+		dev = usb_get_dev_index(d);
+		if (dev == NULL)
+			return NULL;
+		if (dev->devnum == devnum)
+			return dev;
+	}
+
+	return NULL;
+}
+
 static inline char *portspeed(int speed)
 {
-	if (speed == USB_SPEED_HIGH)
-		return "480 Mb/s";
-	else if (speed == USB_SPEED_LOW)
-		return "1.5 Mb/s";
-	else
-		return "12 Mb/s";
+	char *speed_str;
+
+	switch (speed) {
+	case USB_SPEED_SUPER:
+		speed_str = "5 Gb/s";
+		break;
+	case USB_SPEED_HIGH:
+		speed_str = "480 Mb/s";
+		break;
+	case USB_SPEED_LOW:
+		speed_str = "1.5 Mb/s";
+		break;
+	default:
+		speed_str = "12 Mb/s";
+		break;
+	}
+
+	return speed_str;
 }
 
 /* shows the device tree recursively */
@@ -348,6 +376,66 @@
 	usb_show_tree_graph(dev, &preamble[0]);
 }
 
+static int usb_test(struct usb_device *dev, int port, char* arg)
+{
+	int mode;
+
+	if (port > dev->maxchild) {
+		printf("Device is no hub or does not have %d ports.\n", port);
+		return 1;
+	}
+
+	switch (arg[0]) {
+	case 'J':
+	case 'j':
+		printf("Setting Test_J mode");
+		mode = USB_TEST_MODE_J;
+		break;
+	case 'K':
+	case 'k':
+		printf("Setting Test_K mode");
+		mode = USB_TEST_MODE_K;
+		break;
+	case 'S':
+	case 's':
+		printf("Setting Test_SE0_NAK mode");
+		mode = USB_TEST_MODE_SE0_NAK;
+		break;
+	case 'P':
+	case 'p':
+		printf("Setting Test_Packet mode");
+		mode = USB_TEST_MODE_PACKET;
+		break;
+	case 'F':
+	case 'f':
+		printf("Setting Test_Force_Enable mode");
+		mode = USB_TEST_MODE_FORCE_ENABLE;
+		break;
+	default:
+		printf("Unrecognized test mode: %s\nAvailable modes: "
+		       "J, K, S[E0_NAK], P[acket], F[orce_Enable]\n", arg);
+		return 1;
+	}
+
+	if (port)
+		printf(" on downstream facing port %d...\n", port);
+	else
+		printf(" on upstream facing port...\n");
+
+	if (usb_control_msg(dev, usb_sndctrlpipe(dev, 0), USB_REQ_SET_FEATURE,
+			    port ? USB_RT_PORT : USB_RECIP_DEVICE,
+			    port ? USB_PORT_FEAT_TEST : USB_FEAT_TEST,
+			    (mode << 8) | port,
+			    NULL, 0, USB_CNTL_TIMEOUT) == -1) {
+		printf("Error during SET_FEATURE.\n");
+		return 1;
+	} else {
+		printf("Test mode successfully set. Use 'usb start' "
+		       "to return to normal operation.\n");
+		return 0;
+	}
+}
+
 
 /******************************************************************************
  * usb boot command intepreter. Derived from diskboot
@@ -441,17 +529,9 @@
 			}
 			return 0;
 		} else {
-			int d;
-
-			i = simple_strtoul(argv[2], NULL, 16);
+			i = simple_strtoul(argv[2], NULL, 10);
 			printf("config for device %d\n", i);
-			for (d = 0; d < USB_MAX_DEVICE; d++) {
-				dev = usb_get_dev_index(d);
-				if (dev == NULL)
-					break;
-				if (dev->devnum == i)
-					break;
-			}
+			dev = usb_find_device(i);
 			if (dev == NULL) {
 				printf("*** No device available ***\n");
 				return 0;
@@ -462,6 +542,18 @@
 		}
 		return 0;
 	}
+	if (strncmp(argv[1], "test", 4) == 0) {
+		if (argc < 5)
+			return CMD_RET_USAGE;
+		i = simple_strtoul(argv[2], NULL, 10);
+		dev = usb_find_device(i);
+		if (dev == NULL) {
+			printf("Device %d does not exist.\n", i);
+			return 1;
+		}
+		i = simple_strtoul(argv[3], NULL, 10);
+		return usb_test(dev, i, argv[4]);
+	}
 #ifdef CONFIG_USB_STORAGE
 	if (strncmp(argv[1], "stor", 4) == 0)
 		return usb_stor_info();
@@ -571,7 +663,6 @@
 	return CMD_RET_USAGE;
 }
 
-#ifdef CONFIG_USB_STORAGE
 U_BOOT_CMD(
 	usb,	5,	1,	do_usb,
 	"USB sub-system",
@@ -580,30 +671,26 @@
 	"usb stop [f] - stop USB [f]=force stop\n"
 	"usb tree - show USB device tree\n"
 	"usb info [dev] - show available USB devices\n"
+	"usb test [dev] [port] [mode] - set USB 2.0 test mode\n"
+	"    (specify port 0 to indicate the device's upstream port)\n"
+	"    Available modes: J, K, S[E0_NAK], P[acket], F[orce_Enable]\n"
+#ifdef CONFIG_USB_STORAGE
 	"usb storage - show details of USB storage devices\n"
 	"usb dev [dev] - show or set current USB storage device\n"
 	"usb part [dev] - print partition table of one or all USB storage"
-	" devices\n"
+	"    devices\n"
 	"usb read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
 	"    to memory address `addr'\n"
 	"usb write addr blk# cnt - write `cnt' blocks starting at block `blk#'\n"
 	"    from memory address `addr'"
+#endif /* CONFIG_USB_STORAGE */
 );
 
 
+#ifdef CONFIG_USB_STORAGE
 U_BOOT_CMD(
 	usbboot,	3,	1,	do_usbboot,
 	"boot from USB device",
 	"loadAddr dev:part"
 );
-
-#else
-U_BOOT_CMD(
-	usb,	5,	1,	do_usb,
-	"USB sub-system",
-	"start - start (scan) USB controller\n"
-	"usb reset - reset (rescan) USB controller\n"
-	"usb tree - show USB device tree\n"
-	"usb info [dev] - show available USB devices"
-);
-#endif
+#endif /* CONFIG_USB_STORAGE */
diff --git a/common/cmd_ximg.c b/common/cmd_ximg.c
index ea0a26e..270e803 100644
--- a/common/cmd_ximg.c
+++ b/common/cmd_ximg.c
@@ -58,7 +58,9 @@
 	const void	*fit_data;
 	size_t		fit_len;
 #endif
+#ifdef CONFIG_GZIP
 	uint		unc_len = CONFIG_SYS_XIMG_LEN;
+#endif
 	uint8_t		comp;
 
 	verify = getenv_yesno("verify");
@@ -160,7 +162,7 @@
 
 		/* verify integrity */
 		if (verify) {
-			if (!fit_image_check_hashes(fit_hdr, noffset)) {
+			if (!fit_image_verify(fit_hdr, noffset)) {
 				puts("Bad Data Hash\n");
 				return 1;
 			}
diff --git a/common/env_onenand.c b/common/env_onenand.c
index faa903d..e8bde37 100644
--- a/common/env_onenand.c
+++ b/common/env_onenand.c
@@ -68,7 +68,7 @@
 	/* Check OneNAND exist */
 	if (mtd->writesize)
 		/* Ignore read fail */
-		mtd->read(mtd, env_addr, ONENAND_MAX_ENV_SIZE,
+		mtd_read(mtd, env_addr, ONENAND_MAX_ENV_SIZE,
 				&retlen, (u_char *)buf);
 	else
 		mtd->writesize = MAX_ONENAND_PAGESIZE;
@@ -113,12 +113,12 @@
 #endif
 	instr.addr = env_addr;
 	instr.mtd = mtd;
-	if (mtd->erase(mtd, &instr)) {
+	if (mtd_erase(mtd, &instr)) {
 		printf("OneNAND: erase failed at 0x%08llx\n", env_addr);
 		return 1;
 	}
 
-	if (mtd->write(mtd, env_addr, ONENAND_MAX_ENV_SIZE, &retlen,
+	if (mtd_write(mtd, env_addr, ONENAND_MAX_ENV_SIZE, &retlen,
 			(u_char *)&env_new)) {
 		printf("OneNAND: write failed at 0x%llx\n", instr.addr);
 		return 2;
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 812acb4..416100e 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -387,7 +387,11 @@
 	}
 }
 
+#ifdef CONFIG_NR_DRAM_BANKS
+#define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
+#else
 #define MEMORY_BANKS_MAX 4
+#endif
 int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
 {
 	int err, nodeoffset;
diff --git a/common/hash.c b/common/hash.c
index c9ac33e..fe19b73 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -30,6 +30,7 @@
 #include <sha1.h>
 #include <sha256.h>
 #include <asm/io.h>
+#include <asm/errno.h>
 
 /*
  * These are the hash algorithms we support. Chips which support accelerated
@@ -238,6 +239,28 @@
 		printf("%02x", output[i]);
 }
 
+int hash_block(const char *algo_name, const void *data, unsigned int len,
+	       uint8_t *output, int *output_size)
+{
+	struct hash_algo *algo;
+
+	algo = find_hash_algo(algo_name);
+	if (!algo) {
+		debug("Unknown hash algorithm '%s'\n", algo_name);
+		return -EPROTONOSUPPORT;
+	}
+	if (output_size && *output_size < algo->digest_size) {
+		debug("Output buffer size %d too small (need %d bytes)",
+		      *output_size, algo->digest_size);
+		return -ENOSPC;
+	}
+	if (output_size)
+		*output_size = algo->digest_size;
+	algo->hash_func_ws(data, len, output, algo->chunk_size);
+
+	return 0;
+}
+
 int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag,
 		 int argc, char * const argv[])
 {
diff --git a/common/image-fdt.c b/common/image-fdt.c
new file mode 100644
index 0000000..0d421d9
--- /dev/null
+++ b/common/image-fdt.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <errno.h>
+#include <image.h>
+#include <libfdt.h>
+#include <asm/io.h>
+
+#ifndef CONFIG_SYS_FDT_PAD
+#define CONFIG_SYS_FDT_PAD 0x3000
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void fdt_error(const char *msg)
+{
+	puts("ERROR: ");
+	puts(msg);
+	puts(" - must RESET the board to recover.\n");
+}
+
+static const image_header_t *image_get_fdt(ulong fdt_addr)
+{
+	const image_header_t *fdt_hdr = map_sysmem(fdt_addr, 0);
+
+	image_print_contents(fdt_hdr);
+
+	puts("   Verifying Checksum ... ");
+	if (!image_check_hcrc(fdt_hdr)) {
+		fdt_error("fdt header checksum invalid");
+		return NULL;
+	}
+
+	if (!image_check_dcrc(fdt_hdr)) {
+		fdt_error("fdt checksum invalid");
+		return NULL;
+	}
+	puts("OK\n");
+
+	if (!image_check_type(fdt_hdr, IH_TYPE_FLATDT)) {
+		fdt_error("uImage is not a fdt");
+		return NULL;
+	}
+	if (image_get_comp(fdt_hdr) != IH_COMP_NONE) {
+		fdt_error("uImage is compressed");
+		return NULL;
+	}
+	if (fdt_check_header((char *)image_get_data(fdt_hdr)) != 0) {
+		fdt_error("uImage data is not a fdt");
+		return NULL;
+	}
+	return fdt_hdr;
+}
+
+/**
+ * boot_fdt_add_mem_rsv_regions - Mark the memreserve sections as unusable
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @fdt_blob: pointer to fdt blob base address
+ *
+ * Adds the memreserve regions in the dtb to the lmb block.  Adding the
+ * memreserve regions prevents u-boot from using them to store the initrd
+ * or the fdt blob.
+ */
+void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob)
+{
+	uint64_t addr, size;
+	int i, total;
+
+	if (fdt_check_header(fdt_blob) != 0)
+		return;
+
+	total = fdt_num_mem_rsv(fdt_blob);
+	for (i = 0; i < total; i++) {
+		if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
+			continue;
+		printf("   reserving fdt memory region: addr=%llx size=%llx\n",
+		       (unsigned long long)addr, (unsigned long long)size);
+		lmb_reserve(lmb, addr, size);
+	}
+}
+
+/**
+ * boot_relocate_fdt - relocate flat device tree
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @of_flat_tree: pointer to a char* variable, will hold fdt start address
+ * @of_size: pointer to a ulong variable, will hold fdt length
+ *
+ * boot_relocate_fdt() allocates a region of memory within the bootmap and
+ * relocates the of_flat_tree into that region, even if the fdt is already in
+ * the bootmap.  It also expands the size of the fdt by CONFIG_SYS_FDT_PAD
+ * bytes.
+ *
+ * of_flat_tree and of_size are set to final (after relocation) values
+ *
+ * returns:
+ *      0 - success
+ *      1 - failure
+ */
+int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size)
+{
+	void	*fdt_blob = *of_flat_tree;
+	void	*of_start = NULL;
+	char	*fdt_high;
+	ulong	of_len = 0;
+	int	err;
+	int	disable_relocation = 0;
+
+	/* nothing to do */
+	if (*of_size == 0)
+		return 0;
+
+	if (fdt_check_header(fdt_blob) != 0) {
+		fdt_error("image is not a fdt");
+		goto error;
+	}
+
+	/* position on a 4K boundary before the alloc_current */
+	/* Pad the FDT by a specified amount */
+	of_len = *of_size + CONFIG_SYS_FDT_PAD;
+
+	/* If fdt_high is set use it to select the relocation address */
+	fdt_high = getenv("fdt_high");
+	if (fdt_high) {
+		void *desired_addr = (void *)simple_strtoul(fdt_high, NULL, 16);
+
+		if (((ulong) desired_addr) == ~0UL) {
+			/* All ones means use fdt in place */
+			of_start = fdt_blob;
+			lmb_reserve(lmb, (ulong)of_start, of_len);
+			disable_relocation = 1;
+		} else if (desired_addr) {
+			of_start =
+			    (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
+							   (ulong)desired_addr);
+			if (of_start == NULL) {
+				puts("Failed using fdt_high value for Device Tree");
+				goto error;
+			}
+		} else {
+			of_start =
+			    (void *)(ulong) lmb_alloc(lmb, of_len, 0x1000);
+		}
+	} else {
+		of_start =
+		    (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
+						   getenv_bootm_mapsize()
+						   + getenv_bootm_low());
+	}
+
+	if (of_start == NULL) {
+		puts("device tree - allocation error\n");
+		goto error;
+	}
+
+	if (disable_relocation) {
+		/*
+		 * We assume there is space after the existing fdt to use
+		 * for padding
+		 */
+		fdt_set_totalsize(of_start, of_len);
+		printf("   Using Device Tree in place at %p, end %p\n",
+		       of_start, of_start + of_len - 1);
+	} else {
+		debug("## device tree at %p ... %p (len=%ld [0x%lX])\n",
+		      fdt_blob, fdt_blob + *of_size - 1, of_len, of_len);
+
+		printf("   Loading Device Tree to %p, end %p ... ",
+		       of_start, of_start + of_len - 1);
+
+		err = fdt_open_into(fdt_blob, of_start, of_len);
+		if (err != 0) {
+			fdt_error("fdt move failed");
+			goto error;
+		}
+		puts("OK\n");
+	}
+
+	*of_flat_tree = of_start;
+	*of_size = of_len;
+
+	set_working_fdt_addr(*of_flat_tree);
+	return 0;
+
+error:
+	return 1;
+}
+
+/**
+ * boot_get_fdt - main fdt handling routine
+ * @argc: command argument count
+ * @argv: command argument list
+ * @arch: architecture (IH_ARCH_...)
+ * @images: pointer to the bootm images structure
+ * @of_flat_tree: pointer to a char* variable, will hold fdt start address
+ * @of_size: pointer to a ulong variable, will hold fdt length
+ *
+ * boot_get_fdt() is responsible for finding a valid flat device tree image.
+ * Curently supported are the following ramdisk sources:
+ *      - multicomponent kernel/ramdisk image,
+ *      - commandline provided address of decicated ramdisk image.
+ *
+ * returns:
+ *     0, if fdt image was found and valid, or skipped
+ *     of_flat_tree and of_size are set to fdt start address and length if
+ *     fdt image is found and valid
+ *
+ *     1, if fdt image is found but corrupted
+ *     of_flat_tree and of_size are set to 0 if no fdt exists
+ */
+int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
+		bootm_headers_t *images, char **of_flat_tree, ulong *of_size)
+{
+	const image_header_t *fdt_hdr;
+	ulong		fdt_addr;
+	char		*fdt_blob = NULL;
+	ulong		image_start, image_data, image_end;
+	ulong		load, load_end;
+	void		*buf;
+#if defined(CONFIG_FIT)
+	const char	*fit_uname_config = NULL;
+	const char	*fit_uname_fdt = NULL;
+	ulong		default_addr;
+	int		fdt_noffset;
+#endif
+
+	*of_flat_tree = NULL;
+	*of_size = 0;
+
+	if (argc > 3 || genimg_has_config(images)) {
+#if defined(CONFIG_FIT)
+		if (argc > 3) {
+			/*
+			 * If the FDT blob comes from the FIT image and the
+			 * FIT image address is omitted in the command line
+			 * argument, try to use ramdisk or os FIT image
+			 * address or default load address.
+			 */
+			if (images->fit_uname_rd)
+				default_addr = (ulong)images->fit_hdr_rd;
+			else if (images->fit_uname_os)
+				default_addr = (ulong)images->fit_hdr_os;
+			else
+				default_addr = load_addr;
+
+			if (fit_parse_conf(argv[3], default_addr,
+					   &fdt_addr, &fit_uname_config)) {
+				debug("*  fdt: config '%s' from image at 0x%08lx\n",
+				      fit_uname_config, fdt_addr);
+			} else if (fit_parse_subimage(argv[3], default_addr,
+				   &fdt_addr, &fit_uname_fdt)) {
+				debug("*  fdt: subimage '%s' from image at 0x%08lx\n",
+				      fit_uname_fdt, fdt_addr);
+			} else
+#endif
+			{
+				fdt_addr = simple_strtoul(argv[3], NULL, 16);
+				debug("*  fdt: cmdline image address = 0x%08lx\n",
+				      fdt_addr);
+			}
+#if defined(CONFIG_FIT)
+		} else {
+			/* use FIT configuration provided in first bootm
+			 * command argument
+			 */
+			fdt_addr = map_to_sysmem(images->fit_hdr_os);
+			fdt_noffset = fit_get_node_from_config(images,
+							       FIT_FDT_PROP,
+							       fdt_addr);
+			if (fdt_noffset == -ENOLINK)
+				return 0;
+			else if (fdt_noffset < 0)
+				return 1;
+		}
+#endif
+		debug("## Checking for 'FDT'/'FDT Image' at %08lx\n",
+		      fdt_addr);
+
+		/* copy from dataflash if needed */
+		fdt_addr = genimg_get_image(fdt_addr);
+
+		/*
+		 * Check if there is an FDT image at the
+		 * address provided in the second bootm argument
+		 * check image type, for FIT images get a FIT node.
+		 */
+		buf = map_sysmem(fdt_addr, 0);
+		switch (genimg_get_format(buf)) {
+		case IMAGE_FORMAT_LEGACY:
+			/* verify fdt_addr points to a valid image header */
+			printf("## Flattened Device Tree from Legacy Image at %08lx\n",
+			       fdt_addr);
+			fdt_hdr = image_get_fdt(fdt_addr);
+			if (!fdt_hdr)
+				goto error;
+
+			/*
+			 * move image data to the load address,
+			 * make sure we don't overwrite initial image
+			 */
+			image_start = (ulong)fdt_hdr;
+			image_data = (ulong)image_get_data(fdt_hdr);
+			image_end = image_get_image_end(fdt_hdr);
+
+			load = image_get_load(fdt_hdr);
+			load_end = load + image_get_data_size(fdt_hdr);
+
+			if (load == image_start ||
+			    load == image_data) {
+				fdt_blob = (char *)image_data;
+				break;
+			}
+
+			if ((load < image_end) && (load_end > image_start)) {
+				fdt_error("fdt overwritten");
+				goto error;
+			}
+
+			debug("   Loading FDT from 0x%08lx to 0x%08lx\n",
+			      image_data, load);
+
+			memmove((void *)load,
+				(void *)image_data,
+				image_get_data_size(fdt_hdr));
+
+			fdt_addr = load;
+			break;
+		case IMAGE_FORMAT_FIT:
+			/*
+			 * This case will catch both: new uImage format
+			 * (libfdt based) and raw FDT blob (also libfdt
+			 * based).
+			 */
+#if defined(CONFIG_FIT)
+			/* check FDT blob vs FIT blob */
+			if (fit_check_format(buf)) {
+				ulong load, len;
+
+				fdt_noffset = fit_image_load(images,
+					FIT_FDT_PROP,
+					fdt_addr, &fit_uname_fdt,
+					fit_uname_config,
+					arch, IH_TYPE_FLATDT,
+					BOOTSTAGE_ID_FIT_FDT_START,
+					FIT_LOAD_OPTIONAL, &load, &len);
+
+				images->fit_hdr_fdt = map_sysmem(fdt_addr, 0);
+				images->fit_uname_fdt = fit_uname_fdt;
+				images->fit_noffset_fdt = fdt_noffset;
+				fdt_addr = load;
+				break;
+			} else
+#endif
+			{
+				/*
+				 * FDT blob
+				 */
+				debug("*  fdt: raw FDT blob\n");
+				printf("## Flattened Device Tree blob at %08lx\n",
+				       (long)fdt_addr);
+			}
+			break;
+		default:
+			puts("ERROR: Did not find a cmdline Flattened Device Tree\n");
+			goto error;
+		}
+
+		printf("   Booting using the fdt blob at %#08lx\n", fdt_addr);
+		fdt_blob = map_sysmem(fdt_addr, 0);
+	} else if (images->legacy_hdr_valid &&
+			image_check_type(&images->legacy_hdr_os_copy,
+					 IH_TYPE_MULTI)) {
+		ulong fdt_data, fdt_len;
+
+		/*
+		 * Now check if we have a legacy multi-component image,
+		 * get second entry data start address and len.
+		 */
+		printf("## Flattened Device Tree from multi component Image at %08lX\n",
+		       (ulong)images->legacy_hdr_os);
+
+		image_multi_getimg(images->legacy_hdr_os, 2, &fdt_data,
+				   &fdt_len);
+		if (fdt_len) {
+			fdt_blob = (char *)fdt_data;
+			printf("   Booting using the fdt at 0x%p\n", fdt_blob);
+
+			if (fdt_check_header(fdt_blob) != 0) {
+				fdt_error("image is not a fdt");
+				goto error;
+			}
+
+			if (fdt_totalsize(fdt_blob) != fdt_len) {
+				fdt_error("fdt size != image size");
+				goto error;
+			}
+		} else {
+			debug("## No Flattened Device Tree\n");
+			return 0;
+		}
+	} else {
+		debug("## No Flattened Device Tree\n");
+		return 0;
+	}
+
+	*of_flat_tree = fdt_blob;
+	*of_size = fdt_totalsize(fdt_blob);
+	debug("   of_flat_tree at 0x%08lx size 0x%08lx\n",
+	      (ulong)*of_flat_tree, *of_size);
+
+	return 0;
+
+error:
+	*of_flat_tree = NULL;
+	*of_size = 0;
+	return 1;
+}
+
+/*
+ * Verify the device tree.
+ *
+ * This function is called after all device tree fix-ups have been enacted,
+ * so that the final device tree can be verified.  The definition of "verified"
+ * is up to the specific implementation.  However, it generally means that the
+ * addresses of some of the devices in the device tree are compared with the
+ * actual addresses at which U-Boot has placed them.
+ *
+ * Returns 1 on success, 0 on failure.  If 0 is returned, U-boot will halt the
+ * boot process.
+ */
+__weak int ft_verify_fdt(void *fdt)
+{
+	return 1;
+}
+
+__weak int arch_fixup_memory_node(void *blob)
+{
+	return 0;
+}
+
+int image_setup_libfdt(bootm_headers_t *images, void *blob,
+		       int of_size, struct lmb *lmb)
+{
+	ulong *initrd_start = &images->initrd_start;
+	ulong *initrd_end = &images->initrd_end;
+	int ret;
+
+	if (fdt_chosen(blob, 1) < 0) {
+		puts("ERROR: /chosen node create failed");
+		puts(" - must RESET the board to recover.\n");
+		return -1;
+	}
+	arch_fixup_memory_node(blob);
+	if (IMAAGE_OF_BOARD_SETUP)
+		ft_board_setup(blob, gd->bd);
+	fdt_fixup_ethernet(blob);
+
+	/* Delete the old LMB reservation */
+	lmb_free(lmb, (phys_addr_t)(u32)(uintptr_t)blob,
+		 (phys_size_t)fdt_totalsize(blob));
+
+	ret = fdt_resize(blob);
+	if (ret < 0)
+		return ret;
+	of_size = ret;
+
+	if (*initrd_start && *initrd_end) {
+		of_size += FDT_RAMDISK_OVERHEAD;
+		fdt_set_totalsize(blob, of_size);
+	}
+	/* Create a new LMB reservation */
+	lmb_reserve(lmb, (ulong)blob, of_size);
+
+	fdt_initrd(blob, *initrd_start, *initrd_end, 1);
+	if (!ft_verify_fdt(blob))
+		return -1;
+
+	return 0;
+}
diff --git a/common/image-fit.c b/common/image-fit.c
new file mode 100644
index 0000000..7bf82d3
--- /dev/null
+++ b/common/image-fit.c
@@ -0,0 +1,1626 @@
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifdef USE_HOSTCC
+#include "mkimage.h"
+#include <image.h>
+#include <time.h>
+#else
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+#endif /* !USE_HOSTCC*/
+
+#include <bootstage.h>
+#include <sha1.h>
+#include <u-boot/crc.h>
+#include <u-boot/md5.h>
+
+/*****************************************************************************/
+/* New uImage format routines */
+/*****************************************************************************/
+#ifndef USE_HOSTCC
+static int fit_parse_spec(const char *spec, char sepc, ulong addr_curr,
+		ulong *addr, const char **name)
+{
+	const char *sep;
+
+	*addr = addr_curr;
+	*name = NULL;
+
+	sep = strchr(spec, sepc);
+	if (sep) {
+		if (sep - spec > 0)
+			*addr = simple_strtoul(spec, NULL, 16);
+
+		*name = sep + 1;
+		return 1;
+	}
+
+	return 0;
+}
+
+/**
+ * fit_parse_conf - parse FIT configuration spec
+ * @spec: input string, containing configuration spec
+ * @add_curr: current image address (to be used as a possible default)
+ * @addr: pointer to a ulong variable, will hold FIT image address of a given
+ * configuration
+ * @conf_name double pointer to a char, will hold pointer to a configuration
+ * unit name
+ *
+ * fit_parse_conf() expects configuration spec in the for of [<addr>]#<conf>,
+ * where <addr> is a FIT image address that contains configuration
+ * with a <conf> unit name.
+ *
+ * Address part is optional, and if omitted default add_curr will
+ * be used instead.
+ *
+ * returns:
+ *     1 if spec is a valid configuration string,
+ *     addr and conf_name are set accordingly
+ *     0 otherwise
+ */
+int fit_parse_conf(const char *spec, ulong addr_curr,
+		ulong *addr, const char **conf_name)
+{
+	return fit_parse_spec(spec, '#', addr_curr, addr, conf_name);
+}
+
+/**
+ * fit_parse_subimage - parse FIT subimage spec
+ * @spec: input string, containing subimage spec
+ * @add_curr: current image address (to be used as a possible default)
+ * @addr: pointer to a ulong variable, will hold FIT image address of a given
+ * subimage
+ * @image_name: double pointer to a char, will hold pointer to a subimage name
+ *
+ * fit_parse_subimage() expects subimage spec in the for of
+ * [<addr>]:<subimage>, where <addr> is a FIT image address that contains
+ * subimage with a <subimg> unit name.
+ *
+ * Address part is optional, and if omitted default add_curr will
+ * be used instead.
+ *
+ * returns:
+ *     1 if spec is a valid subimage string,
+ *     addr and image_name are set accordingly
+ *     0 otherwise
+ */
+int fit_parse_subimage(const char *spec, ulong addr_curr,
+		ulong *addr, const char **image_name)
+{
+	return fit_parse_spec(spec, ':', addr_curr, addr, image_name);
+}
+#endif /* !USE_HOSTCC */
+
+static void fit_get_debug(const void *fit, int noffset,
+		char *prop_name, int err)
+{
+	debug("Can't get '%s' property from FIT 0x%08lx, node: offset %d, name %s (%s)\n",
+	      prop_name, (ulong)fit, noffset, fit_get_name(fit, noffset, NULL),
+	      fdt_strerror(err));
+}
+
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_FIT_SPL_PRINT)
+/**
+ * fit_print_contents - prints out the contents of the FIT format image
+ * @fit: pointer to the FIT format image header
+ * @p: pointer to prefix string
+ *
+ * fit_print_contents() formats a multi line FIT image contents description.
+ * The routine prints out FIT image properties (root node level) follwed by
+ * the details of each component image.
+ *
+ * returns:
+ *     no returned results
+ */
+void fit_print_contents(const void *fit)
+{
+	char *desc;
+	char *uname;
+	int images_noffset;
+	int confs_noffset;
+	int noffset;
+	int ndepth;
+	int count = 0;
+	int ret;
+	const char *p;
+	time_t timestamp;
+
+	/* Indent string is defined in header image.h */
+	p = IMAGE_INDENT_STRING;
+
+	/* Root node properties */
+	ret = fit_get_desc(fit, 0, &desc);
+	printf("%sFIT description: ", p);
+	if (ret)
+		printf("unavailable\n");
+	else
+		printf("%s\n", desc);
+
+	if (IMAGE_ENABLE_TIMESTAMP) {
+		ret = fit_get_timestamp(fit, 0, &timestamp);
+		printf("%sCreated:         ", p);
+		if (ret)
+			printf("unavailable\n");
+		else
+			genimg_print_time(timestamp);
+	}
+
+	/* Find images parent node offset */
+	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
+	if (images_noffset < 0) {
+		printf("Can't find images parent node '%s' (%s)\n",
+		       FIT_IMAGES_PATH, fdt_strerror(images_noffset));
+		return;
+	}
+
+	/* Process its subnodes, print out component images details */
+	for (ndepth = 0, count = 0,
+		noffset = fdt_next_node(fit, images_noffset, &ndepth);
+	     (noffset >= 0) && (ndepth > 0);
+	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/*
+			 * Direct child node of the images parent node,
+			 * i.e. component image node.
+			 */
+			printf("%s Image %u (%s)\n", p, count++,
+			       fit_get_name(fit, noffset, NULL));
+
+			fit_image_print(fit, noffset, p);
+		}
+	}
+
+	/* Find configurations parent node offset */
+	confs_noffset = fdt_path_offset(fit, FIT_CONFS_PATH);
+	if (confs_noffset < 0) {
+		debug("Can't get configurations parent node '%s' (%s)\n",
+		      FIT_CONFS_PATH, fdt_strerror(confs_noffset));
+		return;
+	}
+
+	/* get default configuration unit name from default property */
+	uname = (char *)fdt_getprop(fit, noffset, FIT_DEFAULT_PROP, NULL);
+	if (uname)
+		printf("%s Default Configuration: '%s'\n", p, uname);
+
+	/* Process its subnodes, print out configurations details */
+	for (ndepth = 0, count = 0,
+		noffset = fdt_next_node(fit, confs_noffset, &ndepth);
+	     (noffset >= 0) && (ndepth > 0);
+	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/*
+			 * Direct child node of the configurations parent node,
+			 * i.e. configuration node.
+			 */
+			printf("%s Configuration %u (%s)\n", p, count++,
+			       fit_get_name(fit, noffset, NULL));
+
+			fit_conf_print(fit, noffset, p);
+		}
+	}
+}
+
+/**
+ * fit_image_print_data() - prints out the hash node details
+ * @fit: pointer to the FIT format image header
+ * @noffset: offset of the hash node
+ * @p: pointer to prefix string
+ *
+ * fit_image_print_data() lists properies for the processed hash node
+ *
+ * returns:
+ *     no returned results
+ */
+static void fit_image_print_data(const void *fit, int noffset, const char *p)
+{
+	char *algo;
+	uint8_t *value;
+	int value_len;
+	int i, ret;
+
+	/*
+	 * Check subnode name, must be equal to "hash".
+	 * Multiple hash nodes require unique unit node
+	 * names, e.g. hash@1, hash@2, etc.
+	 */
+	if (strncmp(fit_get_name(fit, noffset, NULL),
+		    FIT_HASH_NODENAME,
+		    strlen(FIT_HASH_NODENAME)) != 0)
+		return;
+
+	debug("%s  Hash node:    '%s'\n", p,
+	      fit_get_name(fit, noffset, NULL));
+
+	printf("%s  Hash algo:    ", p);
+	if (fit_image_hash_get_algo(fit, noffset, &algo)) {
+		printf("invalid/unsupported\n");
+		return;
+	}
+	printf("%s\n", algo);
+
+	ret = fit_image_hash_get_value(fit, noffset, &value,
+					&value_len);
+	printf("%s  Hash value:   ", p);
+	if (ret) {
+		printf("unavailable\n");
+	} else {
+		for (i = 0; i < value_len; i++)
+			printf("%02x", value[i]);
+		printf("\n");
+	}
+
+	debug("%s  Hash len:     %d\n", p, value_len);
+}
+
+/**
+ * fit_image_print_verification_data() - prints out the hash/signature details
+ * @fit: pointer to the FIT format image header
+ * @noffset: offset of the hash or signature node
+ * @p: pointer to prefix string
+ *
+ * This lists properies for the processed hash node
+ *
+ * returns:
+ *     no returned results
+ */
+static void fit_image_print_verification_data(const void *fit, int noffset,
+				       const char *p)
+{
+	const char *name;
+
+	/*
+	 * Check subnode name, must be equal to "hash" or "signature".
+	 * Multiple hash/signature nodes require unique unit node
+	 * names, e.g. hash@1, hash@2, signature@1, signature@2, etc.
+	 */
+	name = fit_get_name(fit, noffset, NULL);
+	if (!strncmp(name, FIT_HASH_NODENAME, strlen(FIT_HASH_NODENAME)))
+		fit_image_print_data(fit, noffset, p);
+}
+
+/**
+ * fit_image_print - prints out the FIT component image details
+ * @fit: pointer to the FIT format image header
+ * @image_noffset: offset of the component image node
+ * @p: pointer to prefix string
+ *
+ * fit_image_print() lists all mandatory properies for the processed component
+ * image. If present, hash nodes are printed out as well. Load
+ * address for images of type firmware is also printed out. Since the load
+ * address is not mandatory for firmware images, it will be output as
+ * "unavailable" when not present.
+ *
+ * returns:
+ *     no returned results
+ */
+void fit_image_print(const void *fit, int image_noffset, const char *p)
+{
+	char *desc;
+	uint8_t type, arch, os, comp;
+	size_t size;
+	ulong load, entry;
+	const void *data;
+	int noffset;
+	int ndepth;
+	int ret;
+
+	/* Mandatory properties */
+	ret = fit_get_desc(fit, image_noffset, &desc);
+	printf("%s  Description:  ", p);
+	if (ret)
+		printf("unavailable\n");
+	else
+		printf("%s\n", desc);
+
+	fit_image_get_type(fit, image_noffset, &type);
+	printf("%s  Type:         %s\n", p, genimg_get_type_name(type));
+
+	fit_image_get_comp(fit, image_noffset, &comp);
+	printf("%s  Compression:  %s\n", p, genimg_get_comp_name(comp));
+
+	ret = fit_image_get_data(fit, image_noffset, &data, &size);
+
+#ifndef USE_HOSTCC
+	printf("%s  Data Start:   ", p);
+	if (ret) {
+		printf("unavailable\n");
+	} else {
+		void *vdata = (void *)data;
+
+		printf("0x%08lx\n", (ulong)map_to_sysmem(vdata));
+	}
+#endif
+
+	printf("%s  Data Size:    ", p);
+	if (ret)
+		printf("unavailable\n");
+	else
+		genimg_print_size(size);
+
+	/* Remaining, type dependent properties */
+	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
+	    (type == IH_TYPE_RAMDISK) || (type == IH_TYPE_FIRMWARE) ||
+	    (type == IH_TYPE_FLATDT)) {
+		fit_image_get_arch(fit, image_noffset, &arch);
+		printf("%s  Architecture: %s\n", p, genimg_get_arch_name(arch));
+	}
+
+	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_RAMDISK)) {
+		fit_image_get_os(fit, image_noffset, &os);
+		printf("%s  OS:           %s\n", p, genimg_get_os_name(os));
+	}
+
+	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
+	    (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK)) {
+		ret = fit_image_get_load(fit, image_noffset, &load);
+		printf("%s  Load Address: ", p);
+		if (ret)
+			printf("unavailable\n");
+		else
+			printf("0x%08lx\n", load);
+	}
+
+	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
+	    (type == IH_TYPE_RAMDISK)) {
+		fit_image_get_entry(fit, image_noffset, &entry);
+		printf("%s  Entry Point:  ", p);
+		if (ret)
+			printf("unavailable\n");
+		else
+			printf("0x%08lx\n", entry);
+	}
+
+	/* Process all hash subnodes of the component image node */
+	for (ndepth = 0, noffset = fdt_next_node(fit, image_noffset, &ndepth);
+	     (noffset >= 0) && (ndepth > 0);
+	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/* Direct child node of the component image node */
+			fit_image_print_verification_data(fit, noffset, p);
+		}
+	}
+}
+#endif
+
+/**
+ * fit_get_desc - get node description property
+ * @fit: pointer to the FIT format image header
+ * @noffset: node offset
+ * @desc: double pointer to the char, will hold pointer to the descrption
+ *
+ * fit_get_desc() reads description property from a given node, if
+ * description is found pointer to it is returened in third call argument.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_get_desc(const void *fit, int noffset, char **desc)
+{
+	int len;
+
+	*desc = (char *)fdt_getprop(fit, noffset, FIT_DESC_PROP, &len);
+	if (*desc == NULL) {
+		fit_get_debug(fit, noffset, FIT_DESC_PROP, len);
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * fit_get_timestamp - get node timestamp property
+ * @fit: pointer to the FIT format image header
+ * @noffset: node offset
+ * @timestamp: pointer to the time_t, will hold read timestamp
+ *
+ * fit_get_timestamp() reads timestamp poperty from given node, if timestamp
+ * is found and has a correct size its value is retured in third call
+ * argument.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on property read failure
+ *     -2, on wrong timestamp size
+ */
+int fit_get_timestamp(const void *fit, int noffset, time_t *timestamp)
+{
+	int len;
+	const void *data;
+
+	data = fdt_getprop(fit, noffset, FIT_TIMESTAMP_PROP, &len);
+	if (data == NULL) {
+		fit_get_debug(fit, noffset, FIT_TIMESTAMP_PROP, len);
+		return -1;
+	}
+	if (len != sizeof(uint32_t)) {
+		debug("FIT timestamp with incorrect size of (%u)\n", len);
+		return -2;
+	}
+
+	*timestamp = uimage_to_cpu(*((uint32_t *)data));
+	return 0;
+}
+
+/**
+ * fit_image_get_node - get node offset for component image of a given unit name
+ * @fit: pointer to the FIT format image header
+ * @image_uname: component image node unit name
+ *
+ * fit_image_get_node() finds a component image (withing the '/images'
+ * node) of a provided unit name. If image is found its node offset is
+ * returned to the caller.
+ *
+ * returns:
+ *     image node offset when found (>=0)
+ *     negative number on failure (FDT_ERR_* code)
+ */
+int fit_image_get_node(const void *fit, const char *image_uname)
+{
+	int noffset, images_noffset;
+
+	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
+	if (images_noffset < 0) {
+		debug("Can't find images parent node '%s' (%s)\n",
+		      FIT_IMAGES_PATH, fdt_strerror(images_noffset));
+		return images_noffset;
+	}
+
+	noffset = fdt_subnode_offset(fit, images_noffset, image_uname);
+	if (noffset < 0) {
+		debug("Can't get node offset for image unit name: '%s' (%s)\n",
+		      image_uname, fdt_strerror(noffset));
+	}
+
+	return noffset;
+}
+
+/**
+ * fit_image_get_os - get os id for a given component image node
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @os: pointer to the uint8_t, will hold os numeric id
+ *
+ * fit_image_get_os() finds os property in a given component image node.
+ * If the property is found, its (string) value is translated to the numeric
+ * id which is returned to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_get_os(const void *fit, int noffset, uint8_t *os)
+{
+	int len;
+	const void *data;
+
+	/* Get OS name from property data */
+	data = fdt_getprop(fit, noffset, FIT_OS_PROP, &len);
+	if (data == NULL) {
+		fit_get_debug(fit, noffset, FIT_OS_PROP, len);
+		*os = -1;
+		return -1;
+	}
+
+	/* Translate OS name to id */
+	*os = genimg_get_os_id(data);
+	return 0;
+}
+
+/**
+ * fit_image_get_arch - get arch id for a given component image node
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @arch: pointer to the uint8_t, will hold arch numeric id
+ *
+ * fit_image_get_arch() finds arch property in a given component image node.
+ * If the property is found, its (string) value is translated to the numeric
+ * id which is returned to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_get_arch(const void *fit, int noffset, uint8_t *arch)
+{
+	int len;
+	const void *data;
+
+	/* Get architecture name from property data */
+	data = fdt_getprop(fit, noffset, FIT_ARCH_PROP, &len);
+	if (data == NULL) {
+		fit_get_debug(fit, noffset, FIT_ARCH_PROP, len);
+		*arch = -1;
+		return -1;
+	}
+
+	/* Translate architecture name to id */
+	*arch = genimg_get_arch_id(data);
+	return 0;
+}
+
+/**
+ * fit_image_get_type - get type id for a given component image node
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @type: pointer to the uint8_t, will hold type numeric id
+ *
+ * fit_image_get_type() finds type property in a given component image node.
+ * If the property is found, its (string) value is translated to the numeric
+ * id which is returned to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_get_type(const void *fit, int noffset, uint8_t *type)
+{
+	int len;
+	const void *data;
+
+	/* Get image type name from property data */
+	data = fdt_getprop(fit, noffset, FIT_TYPE_PROP, &len);
+	if (data == NULL) {
+		fit_get_debug(fit, noffset, FIT_TYPE_PROP, len);
+		*type = -1;
+		return -1;
+	}
+
+	/* Translate image type name to id */
+	*type = genimg_get_type_id(data);
+	return 0;
+}
+
+/**
+ * fit_image_get_comp - get comp id for a given component image node
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @comp: pointer to the uint8_t, will hold comp numeric id
+ *
+ * fit_image_get_comp() finds comp property in a given component image node.
+ * If the property is found, its (string) value is translated to the numeric
+ * id which is returned to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_get_comp(const void *fit, int noffset, uint8_t *comp)
+{
+	int len;
+	const void *data;
+
+	/* Get compression name from property data */
+	data = fdt_getprop(fit, noffset, FIT_COMP_PROP, &len);
+	if (data == NULL) {
+		fit_get_debug(fit, noffset, FIT_COMP_PROP, len);
+		*comp = -1;
+		return -1;
+	}
+
+	/* Translate compression name to id */
+	*comp = genimg_get_comp_id(data);
+	return 0;
+}
+
+/**
+ * fit_image_get_load() - get load addr property for given component image node
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @load: pointer to the uint32_t, will hold load address
+ *
+ * fit_image_get_load() finds load address property in a given component
+ * image node. If the property is found, its value is returned to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_get_load(const void *fit, int noffset, ulong *load)
+{
+	int len;
+	const uint32_t *data;
+
+	data = fdt_getprop(fit, noffset, FIT_LOAD_PROP, &len);
+	if (data == NULL) {
+		fit_get_debug(fit, noffset, FIT_LOAD_PROP, len);
+		return -1;
+	}
+
+	*load = uimage_to_cpu(*data);
+	return 0;
+}
+
+/**
+ * fit_image_get_entry() - get entry point address property
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @entry: pointer to the uint32_t, will hold entry point address
+ *
+ * This gets the entry point address property for a given component image
+ * node.
+ *
+ * fit_image_get_entry() finds entry point address property in a given
+ * component image node.  If the property is found, its value is returned
+ * to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_get_entry(const void *fit, int noffset, ulong *entry)
+{
+	int len;
+	const uint32_t *data;
+
+	data = fdt_getprop(fit, noffset, FIT_ENTRY_PROP, &len);
+	if (data == NULL) {
+		fit_get_debug(fit, noffset, FIT_ENTRY_PROP, len);
+		return -1;
+	}
+
+	*entry = uimage_to_cpu(*data);
+	return 0;
+}
+
+/**
+ * fit_image_get_data - get data property and its size for a given component image node
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @data: double pointer to void, will hold data property's data address
+ * @size: pointer to size_t, will hold data property's data size
+ *
+ * fit_image_get_data() finds data property in a given component image node.
+ * If the property is found its data start address and size are returned to
+ * the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_get_data(const void *fit, int noffset,
+		const void **data, size_t *size)
+{
+	int len;
+
+	*data = fdt_getprop(fit, noffset, FIT_DATA_PROP, &len);
+	if (*data == NULL) {
+		fit_get_debug(fit, noffset, FIT_DATA_PROP, len);
+		*size = 0;
+		return -1;
+	}
+
+	*size = len;
+	return 0;
+}
+
+/**
+ * fit_image_hash_get_algo - get hash algorithm name
+ * @fit: pointer to the FIT format image header
+ * @noffset: hash node offset
+ * @algo: double pointer to char, will hold pointer to the algorithm name
+ *
+ * fit_image_hash_get_algo() finds hash algorithm property in a given hash node.
+ * If the property is found its data start address is returned to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_hash_get_algo(const void *fit, int noffset, char **algo)
+{
+	int len;
+
+	*algo = (char *)fdt_getprop(fit, noffset, FIT_ALGO_PROP, &len);
+	if (*algo == NULL) {
+		fit_get_debug(fit, noffset, FIT_ALGO_PROP, len);
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * fit_image_hash_get_value - get hash value and length
+ * @fit: pointer to the FIT format image header
+ * @noffset: hash node offset
+ * @value: double pointer to uint8_t, will hold address of a hash value data
+ * @value_len: pointer to an int, will hold hash data length
+ *
+ * fit_image_hash_get_value() finds hash value property in a given hash node.
+ * If the property is found its data start address and size are returned to
+ * the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value,
+				int *value_len)
+{
+	int len;
+
+	*value = (uint8_t *)fdt_getprop(fit, noffset, FIT_VALUE_PROP, &len);
+	if (*value == NULL) {
+		fit_get_debug(fit, noffset, FIT_VALUE_PROP, len);
+		*value_len = 0;
+		return -1;
+	}
+
+	*value_len = len;
+	return 0;
+}
+
+/**
+ * fit_image_hash_get_ignore - get hash ignore flag
+ * @fit: pointer to the FIT format image header
+ * @noffset: hash node offset
+ * @ignore: pointer to an int, will hold hash ignore flag
+ *
+ * fit_image_hash_get_ignore() finds hash ignore property in a given hash node.
+ * If the property is found and non-zero, the hash algorithm is not verified by
+ * u-boot automatically.
+ *
+ * returns:
+ *     0, on ignore not found
+ *     value, on ignore found
+ */
+static int fit_image_hash_get_ignore(const void *fit, int noffset, int *ignore)
+{
+	int len;
+	int *value;
+
+	value = (int *)fdt_getprop(fit, noffset, FIT_IGNORE_PROP, &len);
+	if (value == NULL || len != sizeof(int))
+		*ignore = 0;
+	else
+		*ignore = *value;
+
+	return 0;
+}
+
+/**
+ * fit_set_timestamp - set node timestamp property
+ * @fit: pointer to the FIT format image header
+ * @noffset: node offset
+ * @timestamp: timestamp value to be set
+ *
+ * fit_set_timestamp() attempts to set timestamp property in the requested
+ * node and returns operation status to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on property read failure
+ */
+int fit_set_timestamp(void *fit, int noffset, time_t timestamp)
+{
+	uint32_t t;
+	int ret;
+
+	t = cpu_to_uimage(timestamp);
+	ret = fdt_setprop(fit, noffset, FIT_TIMESTAMP_PROP, &t,
+				sizeof(uint32_t));
+	if (ret) {
+		printf("Can't set '%s' property for '%s' node (%s)\n",
+		       FIT_TIMESTAMP_PROP, fit_get_name(fit, noffset, NULL),
+		       fdt_strerror(ret));
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * calculate_hash - calculate and return hash for provided input data
+ * @data: pointer to the input data
+ * @data_len: data length
+ * @algo: requested hash algorithm
+ * @value: pointer to the char, will hold hash value data (caller must
+ * allocate enough free space)
+ * value_len: length of the calculated hash
+ *
+ * calculate_hash() computes input data hash according to the requested
+ * algorithm.
+ * Resulting hash value is placed in caller provided 'value' buffer, length
+ * of the calculated hash is returned via value_len pointer argument.
+ *
+ * returns:
+ *     0, on success
+ *    -1, when algo is unsupported
+ */
+int calculate_hash(const void *data, int data_len, const char *algo,
+			uint8_t *value, int *value_len)
+{
+	if (IMAGE_ENABLE_CRC32 && strcmp(algo, "crc32") == 0) {
+		*((uint32_t *)value) = crc32_wd(0, data, data_len,
+							CHUNKSZ_CRC32);
+		*((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value));
+		*value_len = 4;
+	} else if (IMAGE_ENABLE_SHA1 && strcmp(algo, "sha1") == 0) {
+		sha1_csum_wd((unsigned char *)data, data_len,
+			     (unsigned char *)value, CHUNKSZ_SHA1);
+		*value_len = 20;
+	} else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) {
+		md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5);
+		*value_len = 16;
+	} else {
+		debug("Unsupported hash alogrithm\n");
+		return -1;
+	}
+	return 0;
+}
+
+static int fit_image_check_hash(const void *fit, int noffset, const void *data,
+				size_t size, char **err_msgp)
+{
+	uint8_t value[FIT_MAX_HASH_LEN];
+	int value_len;
+	char *algo;
+	uint8_t *fit_value;
+	int fit_value_len;
+	int ignore;
+
+	*err_msgp = NULL;
+
+	if (fit_image_hash_get_algo(fit, noffset, &algo)) {
+		*err_msgp = "Can't get hash algo property";
+		return -1;
+	}
+	printf("%s", algo);
+
+	if (IMAGE_ENABLE_IGNORE) {
+		fit_image_hash_get_ignore(fit, noffset, &ignore);
+		if (ignore) {
+			printf("-skipped ");
+			return 0;
+		}
+	}
+
+	if (fit_image_hash_get_value(fit, noffset, &fit_value,
+				     &fit_value_len)) {
+		*err_msgp = "Can't get hash value property";
+		return -1;
+	}
+
+	if (calculate_hash(data, size, algo, value, &value_len)) {
+		*err_msgp = "Unsupported hash algorithm";
+		return -1;
+	}
+
+	if (value_len != fit_value_len) {
+		*err_msgp = "Bad hash value len";
+		return -1;
+	} else if (memcmp(value, fit_value, value_len) != 0) {
+		*err_msgp = "Bad hash value";
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * fit_image_verify - verify data intergity
+ * @fit: pointer to the FIT format image header
+ * @image_noffset: component image node offset
+ *
+ * fit_image_verify() goes over component image hash nodes,
+ * re-calculates each data hash and compares with the value stored in hash
+ * node.
+ *
+ * returns:
+ *     1, if all hashes are valid
+ *     0, otherwise (or on error)
+ */
+int fit_image_verify(const void *fit, int image_noffset)
+{
+	const void	*data;
+	size_t		size;
+	int		noffset;
+	char		*err_msg = "";
+
+	/* Get image data and data length */
+	if (fit_image_get_data(fit, image_noffset, &data, &size)) {
+		err_msg = "Can't get image data/size";
+		return 0;
+	}
+
+	/* Process all hash subnodes of the component image node */
+	for (noffset = fdt_first_subnode(fit, image_noffset);
+	     noffset >= 0;
+	     noffset = fdt_next_subnode(fit, noffset)) {
+		const char *name = fit_get_name(fit, noffset, NULL);
+
+		/*
+		 * Check subnode name, must be equal to "hash".
+		 * Multiple hash nodes require unique unit node
+		 * names, e.g. hash@1, hash@2, etc.
+		 */
+		if (!strncmp(name, FIT_HASH_NODENAME,
+			     strlen(FIT_HASH_NODENAME))) {
+			if (fit_image_check_hash(fit, noffset, data, size,
+						 &err_msg))
+				goto error;
+			puts("+ ");
+		}
+	}
+
+	if (noffset == -FDT_ERR_TRUNCATED || noffset == -FDT_ERR_BADSTRUCTURE) {
+		err_msg = "Corrupted or truncated tree";
+		goto error;
+	}
+
+	return 1;
+
+error:
+	printf(" error!\n%s for '%s' hash node in '%s' image node\n",
+	       err_msg, fit_get_name(fit, noffset, NULL),
+	       fit_get_name(fit, image_noffset, NULL));
+	return 0;
+}
+
+/**
+ * fit_all_image_verify - verify data intergity for all images
+ * @fit: pointer to the FIT format image header
+ *
+ * fit_all_image_verify() goes over all images in the FIT and
+ * for every images checks if all it's hashes are valid.
+ *
+ * returns:
+ *     1, if all hashes of all images are valid
+ *     0, otherwise (or on error)
+ */
+int fit_all_image_verify(const void *fit)
+{
+	int images_noffset;
+	int noffset;
+	int ndepth;
+	int count;
+
+	/* Find images parent node offset */
+	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
+	if (images_noffset < 0) {
+		printf("Can't find images parent node '%s' (%s)\n",
+		       FIT_IMAGES_PATH, fdt_strerror(images_noffset));
+		return 0;
+	}
+
+	/* Process all image subnodes, check hashes for each */
+	printf("## Checking hash(es) for FIT Image at %08lx ...\n",
+	       (ulong)fit);
+	for (ndepth = 0, count = 0,
+	     noffset = fdt_next_node(fit, images_noffset, &ndepth);
+			(noffset >= 0) && (ndepth > 0);
+			noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/*
+			 * Direct child node of the images parent node,
+			 * i.e. component image node.
+			 */
+			printf("   Hash(es) for Image %u (%s): ", count++,
+			       fit_get_name(fit, noffset, NULL));
+
+			if (!fit_image_verify(fit, noffset))
+				return 0;
+			printf("\n");
+		}
+	}
+	return 1;
+}
+
+/**
+ * fit_image_check_os - check whether image node is of a given os type
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @os: requested image os
+ *
+ * fit_image_check_os() reads image os property and compares its numeric
+ * id with the requested os. Comparison result is returned to the caller.
+ *
+ * returns:
+ *     1 if image is of given os type
+ *     0 otherwise (or on error)
+ */
+int fit_image_check_os(const void *fit, int noffset, uint8_t os)
+{
+	uint8_t image_os;
+
+	if (fit_image_get_os(fit, noffset, &image_os))
+		return 0;
+	return (os == image_os);
+}
+
+/**
+ * fit_image_check_arch - check whether image node is of a given arch
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @arch: requested imagearch
+ *
+ * fit_image_check_arch() reads image arch property and compares its numeric
+ * id with the requested arch. Comparison result is returned to the caller.
+ *
+ * returns:
+ *     1 if image is of given arch
+ *     0 otherwise (or on error)
+ */
+int fit_image_check_arch(const void *fit, int noffset, uint8_t arch)
+{
+	uint8_t image_arch;
+
+	if (fit_image_get_arch(fit, noffset, &image_arch))
+		return 0;
+	return (arch == image_arch);
+}
+
+/**
+ * fit_image_check_type - check whether image node is of a given type
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @type: requested image type
+ *
+ * fit_image_check_type() reads image type property and compares its numeric
+ * id with the requested type. Comparison result is returned to the caller.
+ *
+ * returns:
+ *     1 if image is of given type
+ *     0 otherwise (or on error)
+ */
+int fit_image_check_type(const void *fit, int noffset, uint8_t type)
+{
+	uint8_t image_type;
+
+	if (fit_image_get_type(fit, noffset, &image_type))
+		return 0;
+	return (type == image_type);
+}
+
+/**
+ * fit_image_check_comp - check whether image node uses given compression
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @comp: requested image compression type
+ *
+ * fit_image_check_comp() reads image compression property and compares its
+ * numeric id with the requested compression type. Comparison result is
+ * returned to the caller.
+ *
+ * returns:
+ *     1 if image uses requested compression
+ *     0 otherwise (or on error)
+ */
+int fit_image_check_comp(const void *fit, int noffset, uint8_t comp)
+{
+	uint8_t image_comp;
+
+	if (fit_image_get_comp(fit, noffset, &image_comp))
+		return 0;
+	return (comp == image_comp);
+}
+
+/**
+ * fit_check_format - sanity check FIT image format
+ * @fit: pointer to the FIT format image header
+ *
+ * fit_check_format() runs a basic sanity FIT image verification.
+ * Routine checks for mandatory properties, nodes, etc.
+ *
+ * returns:
+ *     1, on success
+ *     0, on failure
+ */
+int fit_check_format(const void *fit)
+{
+	/* mandatory / node 'description' property */
+	if (fdt_getprop(fit, 0, FIT_DESC_PROP, NULL) == NULL) {
+		debug("Wrong FIT format: no description\n");
+		return 0;
+	}
+
+	if (IMAGE_ENABLE_TIMESTAMP) {
+		/* mandatory / node 'timestamp' property */
+		if (fdt_getprop(fit, 0, FIT_TIMESTAMP_PROP, NULL) == NULL) {
+			debug("Wrong FIT format: no timestamp\n");
+			return 0;
+		}
+	}
+
+	/* mandatory subimages parent '/images' node */
+	if (fdt_path_offset(fit, FIT_IMAGES_PATH) < 0) {
+		debug("Wrong FIT format: no images parent node\n");
+		return 0;
+	}
+
+	return 1;
+}
+
+
+/**
+ * fit_conf_find_compat
+ * @fit: pointer to the FIT format image header
+ * @fdt: pointer to the device tree to compare against
+ *
+ * fit_conf_find_compat() attempts to find the configuration whose fdt is the
+ * most compatible with the passed in device tree.
+ *
+ * Example:
+ *
+ * / o image-tree
+ *   |-o images
+ *   | |-o fdt@1
+ *   | |-o fdt@2
+ *   |
+ *   |-o configurations
+ *     |-o config@1
+ *     | |-fdt = fdt@1
+ *     |
+ *     |-o config@2
+ *       |-fdt = fdt@2
+ *
+ * / o U-Boot fdt
+ *   |-compatible = "foo,bar", "bim,bam"
+ *
+ * / o kernel fdt1
+ *   |-compatible = "foo,bar",
+ *
+ * / o kernel fdt2
+ *   |-compatible = "bim,bam", "baz,biz"
+ *
+ * Configuration 1 would be picked because the first string in U-Boot's
+ * compatible list, "foo,bar", matches a compatible string in the root of fdt1.
+ * "bim,bam" in fdt2 matches the second string which isn't as good as fdt1.
+ *
+ * returns:
+ *     offset to the configuration to use if one was found
+ *     -1 otherwise
+ */
+int fit_conf_find_compat(const void *fit, const void *fdt)
+{
+	int ndepth = 0;
+	int noffset, confs_noffset, images_noffset;
+	const void *fdt_compat;
+	int fdt_compat_len;
+	int best_match_offset = 0;
+	int best_match_pos = 0;
+
+	confs_noffset = fdt_path_offset(fit, FIT_CONFS_PATH);
+	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
+	if (confs_noffset < 0 || images_noffset < 0) {
+		debug("Can't find configurations or images nodes.\n");
+		return -1;
+	}
+
+	fdt_compat = fdt_getprop(fdt, 0, "compatible", &fdt_compat_len);
+	if (!fdt_compat) {
+		debug("Fdt for comparison has no \"compatible\" property.\n");
+		return -1;
+	}
+
+	/*
+	 * Loop over the configurations in the FIT image.
+	 */
+	for (noffset = fdt_next_node(fit, confs_noffset, &ndepth);
+			(noffset >= 0) && (ndepth > 0);
+			noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		const void *kfdt;
+		const char *kfdt_name;
+		int kfdt_noffset;
+		const char *cur_fdt_compat;
+		int len;
+		size_t size;
+		int i;
+
+		if (ndepth > 1)
+			continue;
+
+		kfdt_name = fdt_getprop(fit, noffset, "fdt", &len);
+		if (!kfdt_name) {
+			debug("No fdt property found.\n");
+			continue;
+		}
+		kfdt_noffset = fdt_subnode_offset(fit, images_noffset,
+						  kfdt_name);
+		if (kfdt_noffset < 0) {
+			debug("No image node named \"%s\" found.\n",
+			      kfdt_name);
+			continue;
+		}
+		/*
+		 * Get a pointer to this configuration's fdt.
+		 */
+		if (fit_image_get_data(fit, kfdt_noffset, &kfdt, &size)) {
+			debug("Failed to get fdt \"%s\".\n", kfdt_name);
+			continue;
+		}
+
+		len = fdt_compat_len;
+		cur_fdt_compat = fdt_compat;
+		/*
+		 * Look for a match for each U-Boot compatibility string in
+		 * turn in this configuration's fdt.
+		 */
+		for (i = 0; len > 0 &&
+		     (!best_match_offset || best_match_pos > i); i++) {
+			int cur_len = strlen(cur_fdt_compat) + 1;
+
+			if (!fdt_node_check_compatible(kfdt, 0,
+						       cur_fdt_compat)) {
+				best_match_offset = noffset;
+				best_match_pos = i;
+				break;
+			}
+			len -= cur_len;
+			cur_fdt_compat += cur_len;
+		}
+	}
+	if (!best_match_offset) {
+		debug("No match found.\n");
+		return -1;
+	}
+
+	return best_match_offset;
+}
+
+/**
+ * fit_conf_get_node - get node offset for configuration of a given unit name
+ * @fit: pointer to the FIT format image header
+ * @conf_uname: configuration node unit name
+ *
+ * fit_conf_get_node() finds a configuration (withing the '/configurations'
+ * parant node) of a provided unit name. If configuration is found its node
+ * offset is returned to the caller.
+ *
+ * When NULL is provided in second argument fit_conf_get_node() will search
+ * for a default configuration node instead. Default configuration node unit
+ * name is retrived from FIT_DEFAULT_PROP property of the '/configurations'
+ * node.
+ *
+ * returns:
+ *     configuration node offset when found (>=0)
+ *     negative number on failure (FDT_ERR_* code)
+ */
+int fit_conf_get_node(const void *fit, const char *conf_uname)
+{
+	int noffset, confs_noffset;
+	int len;
+
+	confs_noffset = fdt_path_offset(fit, FIT_CONFS_PATH);
+	if (confs_noffset < 0) {
+		debug("Can't find configurations parent node '%s' (%s)\n",
+		      FIT_CONFS_PATH, fdt_strerror(confs_noffset));
+		return confs_noffset;
+	}
+
+	if (conf_uname == NULL) {
+		/* get configuration unit name from the default property */
+		debug("No configuration specified, trying default...\n");
+		conf_uname = (char *)fdt_getprop(fit, confs_noffset,
+						 FIT_DEFAULT_PROP, &len);
+		if (conf_uname == NULL) {
+			fit_get_debug(fit, confs_noffset, FIT_DEFAULT_PROP,
+				      len);
+			return len;
+		}
+		debug("Found default configuration: '%s'\n", conf_uname);
+	}
+
+	noffset = fdt_subnode_offset(fit, confs_noffset, conf_uname);
+	if (noffset < 0) {
+		debug("Can't get node offset for configuration unit name: '%s' (%s)\n",
+		      conf_uname, fdt_strerror(noffset));
+	}
+
+	return noffset;
+}
+
+int fit_conf_get_prop_node(const void *fit, int noffset,
+		const char *prop_name)
+{
+	char *uname;
+	int len;
+
+	/* get kernel image unit name from configuration kernel property */
+	uname = (char *)fdt_getprop(fit, noffset, prop_name, &len);
+	if (uname == NULL)
+		return len;
+
+	return fit_image_get_node(fit, uname);
+}
+
+/**
+ * fit_conf_print - prints out the FIT configuration details
+ * @fit: pointer to the FIT format image header
+ * @noffset: offset of the configuration node
+ * @p: pointer to prefix string
+ *
+ * fit_conf_print() lists all mandatory properies for the processed
+ * configuration node.
+ *
+ * returns:
+ *     no returned results
+ */
+void fit_conf_print(const void *fit, int noffset, const char *p)
+{
+	char *desc;
+	char *uname;
+	int ret;
+
+	/* Mandatory properties */
+	ret = fit_get_desc(fit, noffset, &desc);
+	printf("%s  Description:  ", p);
+	if (ret)
+		printf("unavailable\n");
+	else
+		printf("%s\n", desc);
+
+	uname = (char *)fdt_getprop(fit, noffset, FIT_KERNEL_PROP, NULL);
+	printf("%s  Kernel:       ", p);
+	if (uname == NULL)
+		printf("unavailable\n");
+	else
+		printf("%s\n", uname);
+
+	/* Optional properties */
+	uname = (char *)fdt_getprop(fit, noffset, FIT_RAMDISK_PROP, NULL);
+	if (uname)
+		printf("%s  Init Ramdisk: %s\n", p, uname);
+
+	uname = (char *)fdt_getprop(fit, noffset, FIT_FDT_PROP, NULL);
+	if (uname)
+		printf("%s  FDT:          %s\n", p, uname);
+}
+
+int fit_image_select(const void *fit, int rd_noffset, int verify)
+{
+	fit_image_print(fit, rd_noffset, "   ");
+
+	if (verify) {
+		puts("   Verifying Hash Integrity ... ");
+		if (!fit_image_verify(fit, rd_noffset)) {
+			puts("Bad Data Hash\n");
+			return -EACCES;
+		}
+		puts("OK\n");
+	}
+
+	return 0;
+}
+
+int fit_get_node_from_config(bootm_headers_t *images, const char *prop_name,
+			ulong addr)
+{
+	int cfg_noffset;
+	void *fit_hdr;
+	int noffset;
+
+	debug("*  %s: using config '%s' from image at 0x%08lx\n",
+	      prop_name, images->fit_uname_cfg, addr);
+
+	/* Check whether configuration has this property defined */
+	fit_hdr = map_sysmem(addr, 0);
+	cfg_noffset = fit_conf_get_node(fit_hdr, images->fit_uname_cfg);
+	if (cfg_noffset < 0) {
+		debug("*  %s: no such config\n", prop_name);
+		return -ENOENT;
+	}
+
+	noffset = fit_conf_get_prop_node(fit_hdr, cfg_noffset, prop_name);
+	if (noffset < 0) {
+		debug("*  %s: no '%s' in config\n", prop_name, prop_name);
+		return -ENOLINK;
+	}
+
+	return noffset;
+}
+
+int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr,
+		   const char **fit_unamep, const char *fit_uname_config,
+		   int arch, int image_type, int bootstage_id,
+		   enum fit_load_op load_op, ulong *datap, ulong *lenp)
+{
+	int cfg_noffset, noffset;
+	const char *fit_uname;
+	const void *fit;
+	const void *buf;
+	size_t size;
+	int type_ok, os_ok;
+	ulong load, data, len;
+	int ret;
+
+	fit = map_sysmem(addr, 0);
+	fit_uname = fit_unamep ? *fit_unamep : NULL;
+	printf("## Loading %s from FIT Image at %08lx ...\n", prop_name, addr);
+
+	bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT);
+	if (!fit_check_format(fit)) {
+		printf("Bad FIT %s image format!\n", prop_name);
+		bootstage_error(bootstage_id + BOOTSTAGE_SUB_FORMAT);
+		return -ENOEXEC;
+	}
+	bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT_OK);
+	if (fit_uname) {
+		/* get ramdisk component image node offset */
+		bootstage_mark(bootstage_id + BOOTSTAGE_SUB_UNIT_NAME);
+		noffset = fit_image_get_node(fit, fit_uname);
+	} else {
+		/*
+		 * no image node unit name, try to get config
+		 * node first. If config unit node name is NULL
+		 * fit_conf_get_node() will try to find default config node
+		 */
+		bootstage_mark(bootstage_id + BOOTSTAGE_SUB_NO_UNIT_NAME);
+		if (IMAGE_ENABLE_BEST_MATCH && !fit_uname_config) {
+			cfg_noffset = fit_conf_find_compat(fit, gd_fdt_blob());
+		} else {
+			cfg_noffset = fit_conf_get_node(fit,
+							fit_uname_config);
+		}
+		if (cfg_noffset < 0) {
+			puts("Could not find configuration node\n");
+			bootstage_error(bootstage_id +
+					BOOTSTAGE_SUB_NO_UNIT_NAME);
+			return -ENOENT;
+		}
+		fit_uname_config = fdt_get_name(fit, cfg_noffset, NULL);
+		printf("   Using '%s' configuration\n", fit_uname_config);
+		if (image_type == IH_TYPE_KERNEL) {
+			/* Remember (and possibly verify) this config */
+			images->fit_uname_cfg = fit_uname_config;
+			if (IMAGE_ENABLE_VERIFY && images->verify) {
+				puts("   Verifying Hash Integrity ... ");
+				if (!fit_config_verify(fit, cfg_noffset)) {
+					puts("Bad Data Hash\n");
+					bootstage_error(bootstage_id +
+						BOOTSTAGE_SUB_HASH);
+					return -EACCES;
+				}
+				puts("OK\n");
+			}
+			bootstage_mark(BOOTSTAGE_ID_FIT_CONFIG);
+		}
+
+		noffset = fit_conf_get_prop_node(fit, cfg_noffset,
+						 prop_name);
+		fit_uname = fit_get_name(fit, noffset, NULL);
+	}
+	if (noffset < 0) {
+		puts("Could not find subimage node\n");
+		bootstage_error(bootstage_id + BOOTSTAGE_SUB_SUBNODE);
+		return -ENOENT;
+	}
+
+	printf("   Trying '%s' %s subimage\n", fit_uname, prop_name);
+
+	ret = fit_image_select(fit, noffset, images->verify);
+	if (ret) {
+		bootstage_error(bootstage_id + BOOTSTAGE_SUB_HASH);
+		return ret;
+	}
+
+	bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
+	if (!fit_image_check_target_arch(fit, noffset)) {
+		puts("Unsupported Architecture\n");
+		bootstage_error(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
+		return -ENOEXEC;
+	}
+
+	if (image_type == IH_TYPE_FLATDT &&
+	    !fit_image_check_comp(fit, noffset, IH_COMP_NONE)) {
+		puts("FDT image is compressed");
+		return -EPROTONOSUPPORT;
+	}
+
+	bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL);
+	type_ok = fit_image_check_type(fit, noffset, image_type) ||
+		(image_type == IH_TYPE_KERNEL &&
+			fit_image_check_type(fit, noffset,
+					     IH_TYPE_KERNEL_NOLOAD));
+	os_ok = image_type == IH_TYPE_FLATDT ||
+		fit_image_check_os(fit, noffset, IH_OS_LINUX);
+	if (!type_ok || !os_ok) {
+		printf("No Linux %s %s Image\n", genimg_get_arch_name(arch),
+		       genimg_get_type_name(image_type));
+		bootstage_error(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL);
+		return -EIO;
+	}
+
+	bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL_OK);
+
+	/* get image data address and length */
+	if (fit_image_get_data(fit, noffset, &buf, &size)) {
+		printf("Could not find %s subimage data!\n", prop_name);
+		bootstage_error(bootstage_id + BOOTSTAGE_SUB_GET_DATA);
+		return -ENOMEDIUM;
+	}
+	len = (ulong)size;
+
+	/* verify that image data is a proper FDT blob */
+	if (image_type == IH_TYPE_FLATDT && fdt_check_header((char *)buf)) {
+		puts("Subimage data is not a FDT");
+		return -ENOEXEC;
+	}
+
+	bootstage_mark(bootstage_id + BOOTSTAGE_SUB_GET_DATA_OK);
+
+	/*
+	 * Work-around for eldk-4.2 which gives this warning if we try to
+	 * case in the unmap_sysmem() call:
+	 * warning: initialization discards qualifiers from pointer target type
+	 */
+	{
+		void *vbuf = (void *)buf;
+
+		data = map_to_sysmem(vbuf);
+	}
+
+	if (load_op == FIT_LOAD_IGNORED) {
+		/* Don't load */
+	} else if (fit_image_get_load(fit, noffset, &load)) {
+		if (load_op == FIT_LOAD_REQUIRED) {
+			printf("Can't get %s subimage load address!\n",
+			       prop_name);
+			bootstage_error(bootstage_id + BOOTSTAGE_SUB_LOAD);
+			return -EBADF;
+		}
+	} else {
+		ulong image_start, image_end;
+		ulong load_end;
+		void *dst;
+
+		/*
+		 * move image data to the load address,
+		 * make sure we don't overwrite initial image
+		 */
+		image_start = addr;
+		image_end = addr + fit_get_size(fit);
+
+		load_end = load + len;
+		if (image_type != IH_TYPE_KERNEL &&
+		    load < image_end && load_end > image_start) {
+			printf("Error: %s overwritten\n", prop_name);
+			return -EXDEV;
+		}
+
+		printf("   Loading %s from 0x%08lx to 0x%08lx\n",
+		       prop_name, data, load);
+
+		dst = map_sysmem(load, len);
+		memmove(dst, buf, len);
+		data = load;
+	}
+	bootstage_mark(bootstage_id + BOOTSTAGE_SUB_LOAD);
+
+	*datap = data;
+	*lenp = len;
+	if (fit_unamep)
+		*fit_unamep = (char *)fit_uname;
+
+	return noffset;
+}
diff --git a/common/image.c b/common/image.c
index 60c2127..f863502 100644
--- a/common/image.c
+++ b/common/image.c
@@ -39,9 +39,7 @@
 #include <logbuff.h>
 #endif
 
-#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE)
 #include <rtc.h>
-#endif
 
 #include <environment.h>
 #include <image.h>
@@ -51,13 +49,10 @@
 #include <fdt_support.h>
 #endif
 
-#if defined(CONFIG_FIT)
 #include <u-boot/md5.h>
 #include <sha1.h>
-
-static int fit_check_ramdisk(const void *fit, int os_noffset,
-		uint8_t arch, int verify);
-#endif
+#include <asm/errno.h>
+#include <asm/io.h>
 
 #ifdef CONFIG_CMD_BDI
 extern int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
@@ -76,6 +71,10 @@
 
 #include <u-boot/crc.h>
 
+#ifndef CONFIG_SYS_BARGSIZE
+#define CONFIG_SYS_BARGSIZE 512
+#endif
+
 static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_INVALID,	NULL,		"Invalid ARCH",	},
 	{	IH_ARCH_ALPHA,		"alpha",	"Alpha",	},
@@ -97,6 +96,7 @@
 	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
 	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
 	{	IH_ARCH_OPENRISC,	"or1k",		"OpenRISC 1000",},
+	{	IH_ARCH_SANDBOX,	"sandbox",	"Sandbox",	},
 	{	-1,			"",		"",		},
 };
 
@@ -163,10 +163,6 @@
 	{	-1,		"",		"",			},
 };
 
-#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
-static void genimg_print_time(time_t timestamp);
-#endif
-
 /*****************************************************************************/
 /* Legacy format routines */
 /*****************************************************************************/
@@ -305,17 +301,12 @@
 	const image_header_t *hdr = (const image_header_t *)ptr;
 	const char *p;
 
-#ifdef USE_HOSTCC
-	p = "";
-#else
-	p = "   ";
-#endif
-
+	p = IMAGE_INDENT_STRING;
 	printf("%sImage Name:   %.*s\n", p, IH_NMLEN, image_get_name(hdr));
-#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
-	printf("%sCreated:      ", p);
-	genimg_print_time((time_t)image_get_time(hdr));
-#endif
+	if (IMAGE_ENABLE_TIMESTAMP) {
+		printf("%sCreated:      ", p);
+		genimg_print_time((time_t)image_get_time(hdr));
+	}
 	printf("%sImage Type:   ", p);
 	image_print_type(hdr);
 	printf("%sData Size:    ", p);
@@ -524,8 +515,8 @@
 #endif
 }
 
-#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
-static void genimg_print_time(time_t timestamp)
+#if IMAGE_ENABLE_TIMESTAMP
+void genimg_print_time(time_t timestamp)
 {
 #ifndef USE_HOSTCC
 	struct rtc_time tm;
@@ -538,7 +529,7 @@
 	printf("%s", ctime(&timestamp));
 #endif
 }
-#endif /* CONFIG_TIMESTAMP || CONFIG_CMD_DATE || USE_HOSTCC */
+#endif
 
 /**
  * get_table_entry_name - translate entry id to long name
@@ -672,7 +663,7 @@
  * returns:
  *     image format type or IMAGE_FORMAT_INVALID if no image is present
  */
-int genimg_get_format(void *img_addr)
+int genimg_get_format(const void *img_addr)
 {
 	ulong format = IMAGE_FORMAT_INVALID;
 	const image_header_t *hdr;
@@ -712,6 +703,8 @@
 	ulong h_size, d_size;
 
 	if (addr_dataflash(img_addr)) {
+		void *buf;
+
 		/* ger RAM address */
 		ram_addr = CONFIG_SYS_LOAD_ADDR;
 
@@ -726,20 +719,20 @@
 		debug("   Reading image header from dataflash address "
 			"%08lx to RAM address %08lx\n", img_addr, ram_addr);
 
-		read_dataflash(img_addr, h_size, (char *)ram_addr);
+		buf = map_sysmem(ram_addr, 0);
+		read_dataflash(img_addr, h_size, buf);
 
 		/* get data size */
-		switch (genimg_get_format((void *)ram_addr)) {
+		switch (genimg_get_format(buf)) {
 		case IMAGE_FORMAT_LEGACY:
-			d_size = image_get_data_size(
-					(const image_header_t *)ram_addr);
+			d_size = image_get_data_size(buf);
 			debug("   Legacy format image found at 0x%08lx, "
 					"size 0x%08lx\n",
 					ram_addr, d_size);
 			break;
 #if defined(CONFIG_FIT)
 		case IMAGE_FORMAT_FIT:
-			d_size = fit_get_size((const void *)ram_addr) - h_size;
+			d_size = fit_get_size(buf) - h_size;
 			debug("   FIT/FDT format image found at 0x%08lx, "
 					"size 0x%08lx\n",
 					ram_addr, d_size);
@@ -757,7 +750,7 @@
 			ram_addr + h_size);
 
 		read_dataflash(img_addr + h_size, d_size,
-				(char *)(ram_addr + h_size));
+				(char *)(buf + h_size));
 
 	}
 #endif /* CONFIG_HAS_DATAFLASH */
@@ -813,18 +806,15 @@
 	ulong rd_addr, rd_load;
 	ulong rd_data, rd_len;
 	const image_header_t *rd_hdr;
+	void *buf;
 #ifdef CONFIG_SUPPORT_RAW_INITRD
 	char *end;
 #endif
 #if defined(CONFIG_FIT)
-	void		*fit_hdr;
 	const char	*fit_uname_config = NULL;
 	const char	*fit_uname_ramdisk = NULL;
 	ulong		default_addr;
 	int		rd_noffset;
-	int		cfg_noffset;
-	const void	*data;
-	size_t		size;
 #endif
 
 	*rd_start = 0;
@@ -872,32 +862,16 @@
 #if defined(CONFIG_FIT)
 		} else {
 			/* use FIT configuration provided in first bootm
-			 * command argument
+			 * command argument. If the property is not defined,
+			 * quit silently.
 			 */
-			rd_addr = (ulong)images->fit_hdr_os;
-			fit_uname_config = images->fit_uname_cfg;
-			debug("*  ramdisk: using config '%s' from image "
-					"at 0x%08lx\n",
-					fit_uname_config, rd_addr);
-
-			/*
-			 * Check whether configuration has ramdisk defined,
-			 * if not, don't try to use it, quit silently.
-			 */
-			fit_hdr = (void *)rd_addr;
-			cfg_noffset = fit_conf_get_node(fit_hdr,
-							fit_uname_config);
-			if (cfg_noffset < 0) {
-				debug("*  ramdisk: no such config\n");
-				return 1;
-			}
-
-			rd_noffset = fit_conf_get_ramdisk_node(fit_hdr,
-								cfg_noffset);
-			if (rd_noffset < 0) {
-				debug("*  ramdisk: no ramdisk in config\n");
+			rd_addr = map_to_sysmem(images->fit_hdr_os);
+			rd_noffset = fit_get_node_from_config(images,
+					FIT_RAMDISK_PROP, rd_addr);
+			if (rd_noffset == -ENOLINK)
 				return 0;
-			}
+			else if (rd_noffset < 0)
+				return 1;
 		}
 #endif
 
@@ -909,7 +883,8 @@
 		 * address provided in the second bootm argument
 		 * check image type, for FIT images get FIT node.
 		 */
-		switch (genimg_get_format((void *)rd_addr)) {
+		buf = map_sysmem(rd_addr, 0);
+		switch (genimg_get_format(buf)) {
 		case IMAGE_FORMAT_LEGACY:
 			printf("## Loading init Ramdisk from Legacy "
 					"Image at %08lx ...\n", rd_addr);
@@ -927,87 +902,16 @@
 			break;
 #if defined(CONFIG_FIT)
 		case IMAGE_FORMAT_FIT:
-			fit_hdr = (void *)rd_addr;
-			printf("## Loading init Ramdisk from FIT "
-					"Image at %08lx ...\n", rd_addr);
-
-			bootstage_mark(BOOTSTAGE_ID_FIT_RD_FORMAT);
-			if (!fit_check_format(fit_hdr)) {
-				puts("Bad FIT ramdisk image format!\n");
-				bootstage_error(
-					BOOTSTAGE_ID_FIT_RD_FORMAT);
-				return 1;
-			}
-			bootstage_mark(BOOTSTAGE_ID_FIT_RD_FORMAT_OK);
-
-			if (!fit_uname_ramdisk) {
-				/*
-				 * no ramdisk image node unit name, try to get config
-				 * node first. If config unit node name is NULL
-				 * fit_conf_get_node() will try to find default config node
-				 */
-				bootstage_mark(
-					BOOTSTAGE_ID_FIT_RD_NO_UNIT_NAME);
-				cfg_noffset = fit_conf_get_node(fit_hdr,
-							fit_uname_config);
-				if (cfg_noffset < 0) {
-					puts("Could not find configuration "
-						"node\n");
-					bootstage_error(
-					BOOTSTAGE_ID_FIT_RD_NO_UNIT_NAME);
-					return 1;
-				}
-				fit_uname_config = fdt_get_name(fit_hdr,
-							cfg_noffset, NULL);
-				printf("   Using '%s' configuration\n",
-					fit_uname_config);
-
-				rd_noffset = fit_conf_get_ramdisk_node(fit_hdr,
-							cfg_noffset);
-				fit_uname_ramdisk = fit_get_name(fit_hdr,
-							rd_noffset, NULL);
-			} else {
-				/* get ramdisk component image node offset */
-				bootstage_mark(
-					BOOTSTAGE_ID_FIT_RD_UNIT_NAME);
-				rd_noffset = fit_image_get_node(fit_hdr,
-						fit_uname_ramdisk);
-			}
-			if (rd_noffset < 0) {
-				puts("Could not find subimage node\n");
-				bootstage_error(BOOTSTAGE_ID_FIT_RD_SUBNODE);
-				return 1;
-			}
-
-			printf("   Trying '%s' ramdisk subimage\n",
-				fit_uname_ramdisk);
-
-			bootstage_mark(BOOTSTAGE_ID_FIT_RD_CHECK);
-			if (!fit_check_ramdisk(fit_hdr, rd_noffset, arch,
-						images->verify))
+			rd_noffset = fit_image_load(images, FIT_RAMDISK_PROP,
+					rd_addr, &fit_uname_ramdisk,
+					fit_uname_config, arch,
+					IH_TYPE_RAMDISK,
+					BOOTSTAGE_ID_FIT_RD_START,
+					FIT_LOAD_REQUIRED, &rd_data, &rd_len);
+			if (rd_noffset < 0)
 				return 1;
 
-			/* get ramdisk image data address and length */
-			if (fit_image_get_data(fit_hdr, rd_noffset, &data,
-						&size)) {
-				puts("Could not find ramdisk subimage data!\n");
-				bootstage_error(BOOTSTAGE_ID_FIT_RD_GET_DATA);
-				return 1;
-			}
-			bootstage_mark(BOOTSTAGE_ID_FIT_RD_GET_DATA_OK);
-
-			rd_data = (ulong)data;
-			rd_len = size;
-
-			if (fit_image_get_load(fit_hdr, rd_noffset, &rd_load)) {
-				puts("Can't get ramdisk subimage load "
-					"address!\n");
-				bootstage_error(BOOTSTAGE_ID_FIT_RD_LOAD);
-				return 1;
-			}
-			bootstage_mark(BOOTSTAGE_ID_FIT_RD_LOAD);
-
-			images->fit_hdr_rd = fit_hdr;
+			images->fit_hdr_rd = map_sysmem(rd_addr, 0);
 			images->fit_uname_rd = fit_uname_ramdisk;
 			images->fit_noffset_rd = rd_noffset;
 			break;
@@ -1160,570 +1064,6 @@
 }
 #endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */
 
-#ifdef CONFIG_OF_LIBFDT
-static void fdt_error(const char *msg)
-{
-	puts("ERROR: ");
-	puts(msg);
-	puts(" - must RESET the board to recover.\n");
-}
-
-static const image_header_t *image_get_fdt(ulong fdt_addr)
-{
-	const image_header_t *fdt_hdr = (const image_header_t *)fdt_addr;
-
-	image_print_contents(fdt_hdr);
-
-	puts("   Verifying Checksum ... ");
-	if (!image_check_hcrc(fdt_hdr)) {
-		fdt_error("fdt header checksum invalid");
-		return NULL;
-	}
-
-	if (!image_check_dcrc(fdt_hdr)) {
-		fdt_error("fdt checksum invalid");
-		return NULL;
-	}
-	puts("OK\n");
-
-	if (!image_check_type(fdt_hdr, IH_TYPE_FLATDT)) {
-		fdt_error("uImage is not a fdt");
-		return NULL;
-	}
-	if (image_get_comp(fdt_hdr) != IH_COMP_NONE) {
-		fdt_error("uImage is compressed");
-		return NULL;
-	}
-	if (fdt_check_header((char *)image_get_data(fdt_hdr)) != 0) {
-		fdt_error("uImage data is not a fdt");
-		return NULL;
-	}
-	return fdt_hdr;
-}
-
-/**
- * fit_check_fdt - verify FIT format FDT subimage
- * @fit_hdr: pointer to the FIT  header
- * fdt_noffset: FDT subimage node offset within FIT image
- * @verify: data CRC verification flag
- *
- * fit_check_fdt() verifies integrity of the FDT subimage and from
- * specified FIT image.
- *
- * returns:
- *     1, on success
- *     0, on failure
- */
-#if defined(CONFIG_FIT)
-static int fit_check_fdt(const void *fit, int fdt_noffset, int verify)
-{
-	fit_image_print(fit, fdt_noffset, "   ");
-
-	if (verify) {
-		puts("   Verifying Hash Integrity ... ");
-		if (!fit_image_check_hashes(fit, fdt_noffset)) {
-			fdt_error("Bad Data Hash");
-			return 0;
-		}
-		puts("OK\n");
-	}
-
-	if (!fit_image_check_type(fit, fdt_noffset, IH_TYPE_FLATDT)) {
-		fdt_error("Not a FDT image");
-		return 0;
-	}
-
-	if (!fit_image_check_comp(fit, fdt_noffset, IH_COMP_NONE)) {
-		fdt_error("FDT image is compressed");
-		return 0;
-	}
-
-	return 1;
-}
-#endif /* CONFIG_FIT */
-
-#ifndef CONFIG_SYS_FDT_PAD
-#define CONFIG_SYS_FDT_PAD 0x3000
-#endif
-
-#if defined(CONFIG_OF_LIBFDT)
-/**
- * boot_fdt_add_mem_rsv_regions - Mark the memreserve sections as unusable
- * @lmb: pointer to lmb handle, will be used for memory mgmt
- * @fdt_blob: pointer to fdt blob base address
- *
- * Adds the memreserve regions in the dtb to the lmb block.  Adding the
- * memreserve regions prevents u-boot from using them to store the initrd
- * or the fdt blob.
- */
-void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob)
-{
-	uint64_t addr, size;
-	int i, total;
-
-	if (fdt_check_header(fdt_blob) != 0)
-		return;
-
-	total = fdt_num_mem_rsv(fdt_blob);
-	for (i = 0; i < total; i++) {
-		if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
-			continue;
-		printf("   reserving fdt memory region: addr=%llx size=%llx\n",
-			(unsigned long long)addr, (unsigned long long)size);
-		lmb_reserve(lmb, addr, size);
-	}
-}
-
-/**
- * boot_relocate_fdt - relocate flat device tree
- * @lmb: pointer to lmb handle, will be used for memory mgmt
- * @of_flat_tree: pointer to a char* variable, will hold fdt start address
- * @of_size: pointer to a ulong variable, will hold fdt length
- *
- * boot_relocate_fdt() allocates a region of memory within the bootmap and
- * relocates the of_flat_tree into that region, even if the fdt is already in
- * the bootmap.  It also expands the size of the fdt by CONFIG_SYS_FDT_PAD
- * bytes.
- *
- * of_flat_tree and of_size are set to final (after relocation) values
- *
- * returns:
- *      0 - success
- *      1 - failure
- */
-int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size)
-{
-	void	*fdt_blob = *of_flat_tree;
-	void	*of_start = NULL;
-	char	*fdt_high;
-	ulong	of_len = 0;
-	int	err;
-	int	disable_relocation = 0;
-
-	/* nothing to do */
-	if (*of_size == 0)
-		return 0;
-
-	if (fdt_check_header(fdt_blob) != 0) {
-		fdt_error("image is not a fdt");
-		goto error;
-	}
-
-	/* position on a 4K boundary before the alloc_current */
-	/* Pad the FDT by a specified amount */
-	of_len = *of_size + CONFIG_SYS_FDT_PAD;
-
-	/* If fdt_high is set use it to select the relocation address */
-	fdt_high = getenv("fdt_high");
-	if (fdt_high) {
-		void *desired_addr = (void *)simple_strtoul(fdt_high, NULL, 16);
-
-		if (((ulong) desired_addr) == ~0UL) {
-			/* All ones means use fdt in place */
-			of_start = fdt_blob;
-			lmb_reserve(lmb, (ulong)of_start, of_len);
-			disable_relocation = 1;
-		} else if (desired_addr) {
-			of_start =
-			    (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
-							   (ulong)desired_addr);
-			if (of_start == NULL) {
-				puts("Failed using fdt_high value for Device Tree");
-				goto error;
-			}
-		} else {
-			of_start =
-			    (void *)(ulong) lmb_alloc(lmb, of_len, 0x1000);
-		}
-	} else {
-		of_start =
-		    (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
-						   getenv_bootm_mapsize()
-						   + getenv_bootm_low());
-	}
-
-	if (of_start == NULL) {
-		puts("device tree - allocation error\n");
-		goto error;
-	}
-
-	if (disable_relocation) {
-		/* We assume there is space after the existing fdt to use for padding */
-		fdt_set_totalsize(of_start, of_len);
-		printf("   Using Device Tree in place at %p, end %p\n",
-		       of_start, of_start + of_len - 1);
-	} else {
-		debug("## device tree at %p ... %p (len=%ld [0x%lX])\n",
-			fdt_blob, fdt_blob + *of_size - 1, of_len, of_len);
-
-		printf("   Loading Device Tree to %p, end %p ... ",
-			of_start, of_start + of_len - 1);
-
-		err = fdt_open_into(fdt_blob, of_start, of_len);
-		if (err != 0) {
-			fdt_error("fdt move failed");
-			goto error;
-		}
-		puts("OK\n");
-	}
-
-	*of_flat_tree = of_start;
-	*of_size = of_len;
-
-	set_working_fdt_addr(*of_flat_tree);
-	return 0;
-
-error:
-	return 1;
-}
-#endif /* CONFIG_OF_LIBFDT */
-
-/**
- * boot_get_fdt - main fdt handling routine
- * @argc: command argument count
- * @argv: command argument list
- * @images: pointer to the bootm images structure
- * @of_flat_tree: pointer to a char* variable, will hold fdt start address
- * @of_size: pointer to a ulong variable, will hold fdt length
- *
- * boot_get_fdt() is responsible for finding a valid flat device tree image.
- * Curently supported are the following ramdisk sources:
- *      - multicomponent kernel/ramdisk image,
- *      - commandline provided address of decicated ramdisk image.
- *
- * returns:
- *     0, if fdt image was found and valid, or skipped
- *     of_flat_tree and of_size are set to fdt start address and length if
- *     fdt image is found and valid
- *
- *     1, if fdt image is found but corrupted
- *     of_flat_tree and of_size are set to 0 if no fdt exists
- */
-int boot_get_fdt(int flag, int argc, char * const argv[],
-		bootm_headers_t *images, char **of_flat_tree, ulong *of_size)
-{
-	const image_header_t *fdt_hdr;
-	ulong		fdt_addr;
-	char		*fdt_blob = NULL;
-	ulong		image_start, image_data, image_end;
-	ulong		load_start, load_end;
-#if defined(CONFIG_FIT)
-	void		*fit_hdr;
-	const char	*fit_uname_config = NULL;
-	const char	*fit_uname_fdt = NULL;
-	ulong		default_addr;
-	int		cfg_noffset;
-	int		fdt_noffset;
-	const void	*data;
-	size_t		size;
-#endif
-
-	*of_flat_tree = NULL;
-	*of_size = 0;
-
-	if (argc > 3 || genimg_has_config(images)) {
-#if defined(CONFIG_FIT)
-		if (argc > 3) {
-			/*
-			 * If the FDT blob comes from the FIT image and the
-			 * FIT image address is omitted in the command line
-			 * argument, try to use ramdisk or os FIT image
-			 * address or default load address.
-			 */
-			if (images->fit_uname_rd)
-				default_addr = (ulong)images->fit_hdr_rd;
-			else if (images->fit_uname_os)
-				default_addr = (ulong)images->fit_hdr_os;
-			else
-				default_addr = load_addr;
-
-			if (fit_parse_conf(argv[3], default_addr,
-						&fdt_addr, &fit_uname_config)) {
-				debug("*  fdt: config '%s' from image at "
-						"0x%08lx\n",
-						fit_uname_config, fdt_addr);
-			} else if (fit_parse_subimage(argv[3], default_addr,
-						&fdt_addr, &fit_uname_fdt)) {
-				debug("*  fdt: subimage '%s' from image at "
-						"0x%08lx\n",
-						fit_uname_fdt, fdt_addr);
-			} else
-#endif
-			{
-				fdt_addr = simple_strtoul(argv[3], NULL, 16);
-				debug("*  fdt: cmdline image address = "
-						"0x%08lx\n",
-						fdt_addr);
-			}
-#if defined(CONFIG_FIT)
-		} else {
-			/* use FIT configuration provided in first bootm
-			 * command argument
-			 */
-			fdt_addr = (ulong)images->fit_hdr_os;
-			fit_uname_config = images->fit_uname_cfg;
-			debug("*  fdt: using config '%s' from image "
-					"at 0x%08lx\n",
-					fit_uname_config, fdt_addr);
-
-			/*
-			 * Check whether configuration has FDT blob defined,
-			 * if not quit silently.
-			 */
-			fit_hdr = (void *)fdt_addr;
-			cfg_noffset = fit_conf_get_node(fit_hdr,
-					fit_uname_config);
-			if (cfg_noffset < 0) {
-				debug("*  fdt: no such config\n");
-				return 0;
-			}
-
-			fdt_noffset = fit_conf_get_fdt_node(fit_hdr,
-					cfg_noffset);
-			if (fdt_noffset < 0) {
-				debug("*  fdt: no fdt in config\n");
-				return 0;
-			}
-		}
-#endif
-
-		debug("## Checking for 'FDT'/'FDT Image' at %08lx\n",
-				fdt_addr);
-
-		/* copy from dataflash if needed */
-		fdt_addr = genimg_get_image(fdt_addr);
-
-		/*
-		 * Check if there is an FDT image at the
-		 * address provided in the second bootm argument
-		 * check image type, for FIT images get a FIT node.
-		 */
-		switch (genimg_get_format((void *)fdt_addr)) {
-		case IMAGE_FORMAT_LEGACY:
-			/* verify fdt_addr points to a valid image header */
-			printf("## Flattened Device Tree from Legacy Image "
-					"at %08lx\n",
-					fdt_addr);
-			fdt_hdr = image_get_fdt(fdt_addr);
-			if (!fdt_hdr)
-				goto error;
-
-			/*
-			 * move image data to the load address,
-			 * make sure we don't overwrite initial image
-			 */
-			image_start = (ulong)fdt_hdr;
-			image_data = (ulong)image_get_data(fdt_hdr);
-			image_end = image_get_image_end(fdt_hdr);
-
-			load_start = image_get_load(fdt_hdr);
-			load_end = load_start + image_get_data_size(fdt_hdr);
-
-			if (load_start == image_start ||
-			    load_start == image_data) {
-				fdt_blob = (char *)image_data;
-				break;
-			}
-
-			if ((load_start < image_end) && (load_end > image_start)) {
-				fdt_error("fdt overwritten");
-				goto error;
-			}
-
-			debug("   Loading FDT from 0x%08lx to 0x%08lx\n",
-					image_data, load_start);
-
-			memmove((void *)load_start,
-					(void *)image_data,
-					image_get_data_size(fdt_hdr));
-
-			fdt_blob = (char *)load_start;
-			break;
-		case IMAGE_FORMAT_FIT:
-			/*
-			 * This case will catch both: new uImage format
-			 * (libfdt based) and raw FDT blob (also libfdt
-			 * based).
-			 */
-#if defined(CONFIG_FIT)
-			/* check FDT blob vs FIT blob */
-			if (fit_check_format((const void *)fdt_addr)) {
-				/*
-				 * FIT image
-				 */
-				fit_hdr = (void *)fdt_addr;
-				printf("## Flattened Device Tree from FIT "
-						"Image at %08lx\n",
-						fdt_addr);
-
-				if (!fit_uname_fdt) {
-					/*
-					 * no FDT blob image node unit name,
-					 * try to get config node first. If
-					 * config unit node name is NULL
-					 * fit_conf_get_node() will try to
-					 * find default config node
-					 */
-					cfg_noffset = fit_conf_get_node(fit_hdr,
-							fit_uname_config);
-
-					if (cfg_noffset < 0) {
-						fdt_error("Could not find "
-							    "configuration "
-							    "node\n");
-						goto error;
-					}
-
-					fit_uname_config = fdt_get_name(fit_hdr,
-							cfg_noffset, NULL);
-					printf("   Using '%s' configuration\n",
-							fit_uname_config);
-
-					fdt_noffset = fit_conf_get_fdt_node(
-							fit_hdr,
-							cfg_noffset);
-					fit_uname_fdt = fit_get_name(fit_hdr,
-							fdt_noffset, NULL);
-				} else {
-					/* get FDT component image node offset */
-					fdt_noffset = fit_image_get_node(
-								fit_hdr,
-								fit_uname_fdt);
-				}
-				if (fdt_noffset < 0) {
-					fdt_error("Could not find subimage "
-							"node\n");
-					goto error;
-				}
-
-				printf("   Trying '%s' FDT blob subimage\n",
-						fit_uname_fdt);
-
-				if (!fit_check_fdt(fit_hdr, fdt_noffset,
-							images->verify))
-					goto error;
-
-				/* get ramdisk image data address and length */
-				if (fit_image_get_data(fit_hdr, fdt_noffset,
-							&data, &size)) {
-					fdt_error("Could not find FDT "
-							"subimage data");
-					goto error;
-				}
-
-				/* verift that image data is a proper FDT blob */
-				if (fdt_check_header((char *)data) != 0) {
-					fdt_error("Subimage data is not a FTD");
-					goto error;
-				}
-
-				/*
-				 * move image data to the load address,
-				 * make sure we don't overwrite initial image
-				 */
-				image_start = (ulong)fit_hdr;
-				image_end = fit_get_end(fit_hdr);
-
-				if (fit_image_get_load(fit_hdr, fdt_noffset,
-							&load_start) == 0) {
-					load_end = load_start + size;
-
-					if ((load_start < image_end) &&
-							(load_end > image_start)) {
-						fdt_error("FDT overwritten");
-						goto error;
-					}
-
-					printf("   Loading FDT from 0x%08lx "
-							"to 0x%08lx\n",
-							(ulong)data,
-							load_start);
-
-					memmove((void *)load_start,
-							(void *)data, size);
-
-					fdt_blob = (char *)load_start;
-				} else {
-					fdt_blob = (char *)data;
-				}
-
-				images->fit_hdr_fdt = fit_hdr;
-				images->fit_uname_fdt = fit_uname_fdt;
-				images->fit_noffset_fdt = fdt_noffset;
-				break;
-			} else
-#endif
-			{
-				/*
-				 * FDT blob
-				 */
-				fdt_blob = (char *)fdt_addr;
-				debug("*  fdt: raw FDT blob\n");
-				printf("## Flattened Device Tree blob at "
-					"%08lx\n", (long)fdt_blob);
-			}
-			break;
-		default:
-			puts("ERROR: Did not find a cmdline Flattened Device "
-				"Tree\n");
-			goto error;
-		}
-
-		printf("   Booting using the fdt blob at 0x%p\n", fdt_blob);
-
-	} else if (images->legacy_hdr_valid &&
-			image_check_type(&images->legacy_hdr_os_copy,
-						IH_TYPE_MULTI)) {
-
-		ulong fdt_data, fdt_len;
-
-		/*
-		 * Now check if we have a legacy multi-component image,
-		 * get second entry data start address and len.
-		 */
-		printf("## Flattened Device Tree from multi "
-			"component Image at %08lX\n",
-			(ulong)images->legacy_hdr_os);
-
-		image_multi_getimg(images->legacy_hdr_os, 2, &fdt_data,
-					&fdt_len);
-		if (fdt_len) {
-
-			fdt_blob = (char *)fdt_data;
-			printf("   Booting using the fdt at 0x%p\n", fdt_blob);
-
-			if (fdt_check_header(fdt_blob) != 0) {
-				fdt_error("image is not a fdt");
-				goto error;
-			}
-
-			if (fdt_totalsize(fdt_blob) != fdt_len) {
-				fdt_error("fdt size != image size");
-				goto error;
-			}
-		} else {
-			debug("## No Flattened Device Tree\n");
-			return 0;
-		}
-	} else {
-		debug("## No Flattened Device Tree\n");
-		return 0;
-	}
-
-	*of_flat_tree = fdt_blob;
-	*of_size = fdt_totalsize(fdt_blob);
-	debug("   of_flat_tree at 0x%08lx size 0x%08lx\n",
-			(ulong)*of_flat_tree, *of_size);
-
-	return 0;
-
-error:
-	*of_flat_tree = NULL;
-	*of_size = 0;
-	return 1;
-}
-#endif /* CONFIG_OF_LIBFDT */
-
 #ifdef CONFIG_SYS_BOOT_GET_CMDLINE
 /**
  * boot_get_cmdline - allocate and initialize kernel cmdline
@@ -1797,1608 +1137,50 @@
 	return 0;
 }
 #endif /* CONFIG_SYS_BOOT_GET_KBD */
-#endif /* !USE_HOSTCC */
 
-#if defined(CONFIG_FIT)
-/*****************************************************************************/
-/* New uImage format routines */
-/*****************************************************************************/
-#ifndef USE_HOSTCC
-static int fit_parse_spec(const char *spec, char sepc, ulong addr_curr,
-		ulong *addr, const char **name)
+#ifdef CONFIG_LMB
+int image_setup_linux(bootm_headers_t *images)
 {
-	const char *sep;
-
-	*addr = addr_curr;
-	*name = NULL;
-
-	sep = strchr(spec, sepc);
-	if (sep) {
-		if (sep - spec > 0)
-			*addr = simple_strtoul(spec, NULL, 16);
-
-		*name = sep + 1;
-		return 1;
-	}
-
-	return 0;
-}
-
-/**
- * fit_parse_conf - parse FIT configuration spec
- * @spec: input string, containing configuration spec
- * @add_curr: current image address (to be used as a possible default)
- * @addr: pointer to a ulong variable, will hold FIT image address of a given
- * configuration
- * @conf_name double pointer to a char, will hold pointer to a configuration
- * unit name
- *
- * fit_parse_conf() expects configuration spec in the for of [<addr>]#<conf>,
- * where <addr> is a FIT image address that contains configuration
- * with a <conf> unit name.
- *
- * Address part is optional, and if omitted default add_curr will
- * be used instead.
- *
- * returns:
- *     1 if spec is a valid configuration string,
- *     addr and conf_name are set accordingly
- *     0 otherwise
- */
-int fit_parse_conf(const char *spec, ulong addr_curr,
-		ulong *addr, const char **conf_name)
-{
-	return fit_parse_spec(spec, '#', addr_curr, addr, conf_name);
-}
-
-/**
- * fit_parse_subimage - parse FIT subimage spec
- * @spec: input string, containing subimage spec
- * @add_curr: current image address (to be used as a possible default)
- * @addr: pointer to a ulong variable, will hold FIT image address of a given
- * subimage
- * @image_name: double pointer to a char, will hold pointer to a subimage name
- *
- * fit_parse_subimage() expects subimage spec in the for of
- * [<addr>]:<subimage>, where <addr> is a FIT image address that contains
- * subimage with a <subimg> unit name.
- *
- * Address part is optional, and if omitted default add_curr will
- * be used instead.
- *
- * returns:
- *     1 if spec is a valid subimage string,
- *     addr and image_name are set accordingly
- *     0 otherwise
- */
-int fit_parse_subimage(const char *spec, ulong addr_curr,
-		ulong *addr, const char **image_name)
-{
-	return fit_parse_spec(spec, ':', addr_curr, addr, image_name);
-}
-#endif /* !USE_HOSTCC */
-
-static void fit_get_debug(const void *fit, int noffset,
-		char *prop_name, int err)
-{
-	debug("Can't get '%s' property from FIT 0x%08lx, "
-		"node: offset %d, name %s (%s)\n",
-		prop_name, (ulong)fit, noffset,
-		fit_get_name(fit, noffset, NULL),
-		fdt_strerror(err));
-}
-
-/**
- * fit_print_contents - prints out the contents of the FIT format image
- * @fit: pointer to the FIT format image header
- * @p: pointer to prefix string
- *
- * fit_print_contents() formats a multi line FIT image contents description.
- * The routine prints out FIT image properties (root node level) follwed by
- * the details of each component image.
- *
- * returns:
- *     no returned results
- */
-void fit_print_contents(const void *fit)
-{
-	char *desc;
-	char *uname;
-	int images_noffset;
-	int confs_noffset;
-	int noffset;
-	int ndepth;
-	int count = 0;
-	int ret;
-	const char *p;
-#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
-	time_t timestamp;
-#endif
-
-#ifdef USE_HOSTCC
-	p = "";
-#else
-	p = "   ";
-#endif
-
-	/* Root node properties */
-	ret = fit_get_desc(fit, 0, &desc);
-	printf("%sFIT description: ", p);
-	if (ret)
-		printf("unavailable\n");
-	else
-		printf("%s\n", desc);
-
-#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
-	ret = fit_get_timestamp(fit, 0, &timestamp);
-	printf("%sCreated:         ", p);
-	if (ret)
-		printf("unavailable\n");
-	else
-		genimg_print_time(timestamp);
-#endif
-
-	/* Find images parent node offset */
-	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
-	if (images_noffset < 0) {
-		printf("Can't find images parent node '%s' (%s)\n",
-			FIT_IMAGES_PATH, fdt_strerror(images_noffset));
-		return;
-	}
-
-	/* Process its subnodes, print out component images details */
-	for (ndepth = 0, count = 0,
-		noffset = fdt_next_node(fit, images_noffset, &ndepth);
-	     (noffset >= 0) && (ndepth > 0);
-	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
-		if (ndepth == 1) {
-			/*
-			 * Direct child node of the images parent node,
-			 * i.e. component image node.
-			 */
-			printf("%s Image %u (%s)\n", p, count++,
-					fit_get_name(fit, noffset, NULL));
-
-			fit_image_print(fit, noffset, p);
-		}
-	}
-
-	/* Find configurations parent node offset */
-	confs_noffset = fdt_path_offset(fit, FIT_CONFS_PATH);
-	if (confs_noffset < 0) {
-		debug("Can't get configurations parent node '%s' (%s)\n",
-			FIT_CONFS_PATH, fdt_strerror(confs_noffset));
-		return;
-	}
-
-	/* get default configuration unit name from default property */
-	uname = (char *)fdt_getprop(fit, noffset, FIT_DEFAULT_PROP, NULL);
-	if (uname)
-		printf("%s Default Configuration: '%s'\n", p, uname);
-
-	/* Process its subnodes, print out configurations details */
-	for (ndepth = 0, count = 0,
-		noffset = fdt_next_node(fit, confs_noffset, &ndepth);
-	     (noffset >= 0) && (ndepth > 0);
-	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
-		if (ndepth == 1) {
-			/*
-			 * Direct child node of the configurations parent node,
-			 * i.e. configuration node.
-			 */
-			printf("%s Configuration %u (%s)\n", p, count++,
-					fit_get_name(fit, noffset, NULL));
-
-			fit_conf_print(fit, noffset, p);
-		}
-	}
-}
-
-/**
- * fit_image_print - prints out the FIT component image details
- * @fit: pointer to the FIT format image header
- * @image_noffset: offset of the component image node
- * @p: pointer to prefix string
- *
- * fit_image_print() lists all mandatory properies for the processed component
- * image. If present, hash nodes are printed out as well. Load
- * address for images of type firmware is also printed out. Since the load
- * address is not mandatory for firmware images, it will be output as
- * "unavailable" when not present.
- *
- * returns:
- *     no returned results
- */
-void fit_image_print(const void *fit, int image_noffset, const char *p)
-{
-	char *desc;
-	uint8_t type, arch, os, comp;
-	size_t size;
-	ulong load, entry;
-	const void *data;
-	int noffset;
-	int ndepth;
+	ulong of_size = images->ft_len;
+	char **of_flat_tree = &images->ft_addr;
+	ulong *initrd_start = &images->initrd_start;
+	ulong *initrd_end = &images->initrd_end;
+	struct lmb *lmb = &images->lmb;
+	ulong rd_len;
 	int ret;
 
-	/* Mandatory properties */
-	ret = fit_get_desc(fit, image_noffset, &desc);
-	printf("%s  Description:  ", p);
-	if (ret)
-		printf("unavailable\n");
-	else
-		printf("%s\n", desc);
+	if (IMAGE_ENABLE_OF_LIBFDT)
+		boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
 
-	fit_image_get_type(fit, image_noffset, &type);
-	printf("%s  Type:         %s\n", p, genimg_get_type_name(type));
-
-	fit_image_get_comp(fit, image_noffset, &comp);
-	printf("%s  Compression:  %s\n", p, genimg_get_comp_name(comp));
-
-	ret = fit_image_get_data(fit, image_noffset, &data, &size);
-
-#ifndef USE_HOSTCC
-	printf("%s  Data Start:   ", p);
-	if (ret)
-		printf("unavailable\n");
-	else
-		printf("0x%08lx\n", (ulong)data);
-#endif
-
-	printf("%s  Data Size:    ", p);
-	if (ret)
-		printf("unavailable\n");
-	else
-		genimg_print_size(size);
-
-	/* Remaining, type dependent properties */
-	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
-	    (type == IH_TYPE_RAMDISK) || (type == IH_TYPE_FIRMWARE) ||
-	    (type == IH_TYPE_FLATDT)) {
-		fit_image_get_arch(fit, image_noffset, &arch);
-		printf("%s  Architecture: %s\n", p, genimg_get_arch_name(arch));
+	if (IMAGE_BOOT_GET_CMDLINE) {
+		ret = boot_get_cmdline(lmb, &images->cmdline_start,
+				&images->cmdline_end);
+		if (ret) {
+			puts("ERROR with allocation of cmdline\n");
+			return ret;
+		}
 	}
-
-	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_RAMDISK)) {
-		fit_image_get_os(fit, image_noffset, &os);
-		printf("%s  OS:           %s\n", p, genimg_get_os_name(os));
-	}
-
-	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
-		(type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK)) {
-		ret = fit_image_get_load(fit, image_noffset, &load);
-		printf("%s  Load Address: ", p);
+	if (IMAGE_ENABLE_RAMDISK_HIGH) {
+		rd_len = images->rd_end - images->rd_start;
+		ret = boot_ramdisk_high(lmb, images->rd_start, rd_len,
+				initrd_start, initrd_end);
 		if (ret)
-			printf("unavailable\n");
-		else
-			printf("0x%08lx\n", load);
+			return ret;
 	}
 
-	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
-		(type == IH_TYPE_RAMDISK)) {
-		fit_image_get_entry(fit, image_noffset, &entry);
-		printf("%s  Entry Point:  ", p);
+	if (IMAGE_ENABLE_OF_LIBFDT) {
+		ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
 		if (ret)
-			printf("unavailable\n");
-		else
-			printf("0x%08lx\n", entry);
+			return ret;
 	}
 
-	/* Process all hash subnodes of the component image node */
-	for (ndepth = 0, noffset = fdt_next_node(fit, image_noffset, &ndepth);
-	     (noffset >= 0) && (ndepth > 0);
-	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
-		if (ndepth == 1) {
-			/* Direct child node of the component image node */
-			fit_image_print_hash(fit, noffset, p);
-		}
-	}
-}
-
-/**
- * fit_image_print_hash - prints out the hash node details
- * @fit: pointer to the FIT format image header
- * @noffset: offset of the hash node
- * @p: pointer to prefix string
- *
- * fit_image_print_hash() lists properies for the processed hash node
- *
- * returns:
- *     no returned results
- */
-void fit_image_print_hash(const void *fit, int noffset, const char *p)
-{
-	char *algo;
-	uint8_t *value;
-	int value_len;
-	int i, ret;
-
-	/*
-	 * Check subnode name, must be equal to "hash".
-	 * Multiple hash nodes require unique unit node
-	 * names, e.g. hash@1, hash@2, etc.
-	 */
-	if (strncmp(fit_get_name(fit, noffset, NULL),
-			FIT_HASH_NODENAME,
-			strlen(FIT_HASH_NODENAME)) != 0)
-		return;
-
-	debug("%s  Hash node:    '%s'\n", p,
-			fit_get_name(fit, noffset, NULL));
-
-	printf("%s  Hash algo:    ", p);
-	if (fit_image_hash_get_algo(fit, noffset, &algo)) {
-		printf("invalid/unsupported\n");
-		return;
-	}
-	printf("%s\n", algo);
-
-	ret = fit_image_hash_get_value(fit, noffset, &value,
-					&value_len);
-	printf("%s  Hash value:   ", p);
-	if (ret) {
-		printf("unavailable\n");
-	} else {
-		for (i = 0; i < value_len; i++)
-			printf("%02x", value[i]);
-		printf("\n");
-	}
-
-	debug("%s  Hash len:     %d\n", p, value_len);
-}
-
-/**
- * fit_get_desc - get node description property
- * @fit: pointer to the FIT format image header
- * @noffset: node offset
- * @desc: double pointer to the char, will hold pointer to the descrption
- *
- * fit_get_desc() reads description property from a given node, if
- * description is found pointer to it is returened in third call argument.
- *
- * returns:
- *     0, on success
- *     -1, on failure
- */
-int fit_get_desc(const void *fit, int noffset, char **desc)
-{
-	int len;
-
-	*desc = (char *)fdt_getprop(fit, noffset, FIT_DESC_PROP, &len);
-	if (*desc == NULL) {
-		fit_get_debug(fit, noffset, FIT_DESC_PROP, len);
-		return -1;
+	if (IMAGE_ENABLE_OF_LIBFDT && of_size) {
+		ret = image_setup_libfdt(images, *of_flat_tree, of_size, lmb);
+		if (ret)
+			return ret;
 	}
 
 	return 0;
 }
-
-/**
- * fit_get_timestamp - get node timestamp property
- * @fit: pointer to the FIT format image header
- * @noffset: node offset
- * @timestamp: pointer to the time_t, will hold read timestamp
- *
- * fit_get_timestamp() reads timestamp poperty from given node, if timestamp
- * is found and has a correct size its value is retured in third call
- * argument.
- *
- * returns:
- *     0, on success
- *     -1, on property read failure
- *     -2, on wrong timestamp size
- */
-int fit_get_timestamp(const void *fit, int noffset, time_t *timestamp)
-{
-	int len;
-	const void *data;
-
-	data = fdt_getprop(fit, noffset, FIT_TIMESTAMP_PROP, &len);
-	if (data == NULL) {
-		fit_get_debug(fit, noffset, FIT_TIMESTAMP_PROP, len);
-		return -1;
-	}
-	if (len != sizeof(uint32_t)) {
-		debug("FIT timestamp with incorrect size of (%u)\n", len);
-		return -2;
-	}
-
-	*timestamp = uimage_to_cpu(*((uint32_t *)data));
-	return 0;
-}
-
-/**
- * fit_image_get_node - get node offset for component image of a given unit name
- * @fit: pointer to the FIT format image header
- * @image_uname: component image node unit name
- *
- * fit_image_get_node() finds a component image (withing the '/images'
- * node) of a provided unit name. If image is found its node offset is
- * returned to the caller.
- *
- * returns:
- *     image node offset when found (>=0)
- *     negative number on failure (FDT_ERR_* code)
- */
-int fit_image_get_node(const void *fit, const char *image_uname)
-{
-	int noffset, images_noffset;
-
-	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
-	if (images_noffset < 0) {
-		debug("Can't find images parent node '%s' (%s)\n",
-			FIT_IMAGES_PATH, fdt_strerror(images_noffset));
-		return images_noffset;
-	}
-
-	noffset = fdt_subnode_offset(fit, images_noffset, image_uname);
-	if (noffset < 0) {
-		debug("Can't get node offset for image unit name: '%s' (%s)\n",
-			image_uname, fdt_strerror(noffset));
-	}
-
-	return noffset;
-}
-
-/**
- * fit_image_get_os - get os id for a given component image node
- * @fit: pointer to the FIT format image header
- * @noffset: component image node offset
- * @os: pointer to the uint8_t, will hold os numeric id
- *
- * fit_image_get_os() finds os property in a given component image node.
- * If the property is found, its (string) value is translated to the numeric
- * id which is returned to the caller.
- *
- * returns:
- *     0, on success
- *     -1, on failure
- */
-int fit_image_get_os(const void *fit, int noffset, uint8_t *os)
-{
-	int len;
-	const void *data;
-
-	/* Get OS name from property data */
-	data = fdt_getprop(fit, noffset, FIT_OS_PROP, &len);
-	if (data == NULL) {
-		fit_get_debug(fit, noffset, FIT_OS_PROP, len);
-		*os = -1;
-		return -1;
-	}
-
-	/* Translate OS name to id */
-	*os = genimg_get_os_id(data);
-	return 0;
-}
-
-/**
- * fit_image_get_arch - get arch id for a given component image node
- * @fit: pointer to the FIT format image header
- * @noffset: component image node offset
- * @arch: pointer to the uint8_t, will hold arch numeric id
- *
- * fit_image_get_arch() finds arch property in a given component image node.
- * If the property is found, its (string) value is translated to the numeric
- * id which is returned to the caller.
- *
- * returns:
- *     0, on success
- *     -1, on failure
- */
-int fit_image_get_arch(const void *fit, int noffset, uint8_t *arch)
-{
-	int len;
-	const void *data;
-
-	/* Get architecture name from property data */
-	data = fdt_getprop(fit, noffset, FIT_ARCH_PROP, &len);
-	if (data == NULL) {
-		fit_get_debug(fit, noffset, FIT_ARCH_PROP, len);
-		*arch = -1;
-		return -1;
-	}
-
-	/* Translate architecture name to id */
-	*arch = genimg_get_arch_id(data);
-	return 0;
-}
-
-/**
- * fit_image_get_type - get type id for a given component image node
- * @fit: pointer to the FIT format image header
- * @noffset: component image node offset
- * @type: pointer to the uint8_t, will hold type numeric id
- *
- * fit_image_get_type() finds type property in a given component image node.
- * If the property is found, its (string) value is translated to the numeric
- * id which is returned to the caller.
- *
- * returns:
- *     0, on success
- *     -1, on failure
- */
-int fit_image_get_type(const void *fit, int noffset, uint8_t *type)
-{
-	int len;
-	const void *data;
-
-	/* Get image type name from property data */
-	data = fdt_getprop(fit, noffset, FIT_TYPE_PROP, &len);
-	if (data == NULL) {
-		fit_get_debug(fit, noffset, FIT_TYPE_PROP, len);
-		*type = -1;
-		return -1;
-	}
-
-	/* Translate image type name to id */
-	*type = genimg_get_type_id(data);
-	return 0;
-}
-
-/**
- * fit_image_get_comp - get comp id for a given component image node
- * @fit: pointer to the FIT format image header
- * @noffset: component image node offset
- * @comp: pointer to the uint8_t, will hold comp numeric id
- *
- * fit_image_get_comp() finds comp property in a given component image node.
- * If the property is found, its (string) value is translated to the numeric
- * id which is returned to the caller.
- *
- * returns:
- *     0, on success
- *     -1, on failure
- */
-int fit_image_get_comp(const void *fit, int noffset, uint8_t *comp)
-{
-	int len;
-	const void *data;
-
-	/* Get compression name from property data */
-	data = fdt_getprop(fit, noffset, FIT_COMP_PROP, &len);
-	if (data == NULL) {
-		fit_get_debug(fit, noffset, FIT_COMP_PROP, len);
-		*comp = -1;
-		return -1;
-	}
-
-	/* Translate compression name to id */
-	*comp = genimg_get_comp_id(data);
-	return 0;
-}
-
-/**
- * fit_image_get_load - get load address property for a given component image node
- * @fit: pointer to the FIT format image header
- * @noffset: component image node offset
- * @load: pointer to the uint32_t, will hold load address
- *
- * fit_image_get_load() finds load address property in a given component image node.
- * If the property is found, its value is returned to the caller.
- *
- * returns:
- *     0, on success
- *     -1, on failure
- */
-int fit_image_get_load(const void *fit, int noffset, ulong *load)
-{
-	int len;
-	const uint32_t *data;
-
-	data = fdt_getprop(fit, noffset, FIT_LOAD_PROP, &len);
-	if (data == NULL) {
-		fit_get_debug(fit, noffset, FIT_LOAD_PROP, len);
-		return -1;
-	}
-
-	*load = uimage_to_cpu(*data);
-	return 0;
-}
-
-/**
- * fit_image_get_entry - get entry point address property for a given component image node
- * @fit: pointer to the FIT format image header
- * @noffset: component image node offset
- * @entry: pointer to the uint32_t, will hold entry point address
- *
- * fit_image_get_entry() finds entry point address property in a given component image node.
- * If the property is found, its value is returned to the caller.
- *
- * returns:
- *     0, on success
- *     -1, on failure
- */
-int fit_image_get_entry(const void *fit, int noffset, ulong *entry)
-{
-	int len;
-	const uint32_t *data;
-
-	data = fdt_getprop(fit, noffset, FIT_ENTRY_PROP, &len);
-	if (data == NULL) {
-		fit_get_debug(fit, noffset, FIT_ENTRY_PROP, len);
-		return -1;
-	}
-
-	*entry = uimage_to_cpu(*data);
-	return 0;
-}
-
-/**
- * fit_image_get_data - get data property and its size for a given component image node
- * @fit: pointer to the FIT format image header
- * @noffset: component image node offset
- * @data: double pointer to void, will hold data property's data address
- * @size: pointer to size_t, will hold data property's data size
- *
- * fit_image_get_data() finds data property in a given component image node.
- * If the property is found its data start address and size are returned to
- * the caller.
- *
- * returns:
- *     0, on success
- *     -1, on failure
- */
-int fit_image_get_data(const void *fit, int noffset,
-		const void **data, size_t *size)
-{
-	int len;
-
-	*data = fdt_getprop(fit, noffset, FIT_DATA_PROP, &len);
-	if (*data == NULL) {
-		fit_get_debug(fit, noffset, FIT_DATA_PROP, len);
-		*size = 0;
-		return -1;
-	}
-
-	*size = len;
-	return 0;
-}
-
-/**
- * fit_image_hash_get_algo - get hash algorithm name
- * @fit: pointer to the FIT format image header
- * @noffset: hash node offset
- * @algo: double pointer to char, will hold pointer to the algorithm name
- *
- * fit_image_hash_get_algo() finds hash algorithm property in a given hash node.
- * If the property is found its data start address is returned to the caller.
- *
- * returns:
- *     0, on success
- *     -1, on failure
- */
-int fit_image_hash_get_algo(const void *fit, int noffset, char **algo)
-{
-	int len;
-
-	*algo = (char *)fdt_getprop(fit, noffset, FIT_ALGO_PROP, &len);
-	if (*algo == NULL) {
-		fit_get_debug(fit, noffset, FIT_ALGO_PROP, len);
-		return -1;
-	}
-
-	return 0;
-}
-
-/**
- * fit_image_hash_get_value - get hash value and length
- * @fit: pointer to the FIT format image header
- * @noffset: hash node offset
- * @value: double pointer to uint8_t, will hold address of a hash value data
- * @value_len: pointer to an int, will hold hash data length
- *
- * fit_image_hash_get_value() finds hash value property in a given hash node.
- * If the property is found its data start address and size are returned to
- * the caller.
- *
- * returns:
- *     0, on success
- *     -1, on failure
- */
-int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value,
-				int *value_len)
-{
-	int len;
-
-	*value = (uint8_t *)fdt_getprop(fit, noffset, FIT_VALUE_PROP, &len);
-	if (*value == NULL) {
-		fit_get_debug(fit, noffset, FIT_VALUE_PROP, len);
-		*value_len = 0;
-		return -1;
-	}
-
-	*value_len = len;
-	return 0;
-}
-
-#ifndef USE_HOSTCC
-/**
- * fit_image_hash_get_ignore - get hash ignore flag
- * @fit: pointer to the FIT format image header
- * @noffset: hash node offset
- * @ignore: pointer to an int, will hold hash ignore flag
- *
- * fit_image_hash_get_ignore() finds hash ignore property in a given hash node.
- * If the property is found and non-zero, the hash algorithm is not verified by
- * u-boot automatically.
- *
- * returns:
- *     0, on ignore not found
- *     value, on ignore found
- */
-int fit_image_hash_get_ignore(const void *fit, int noffset, int *ignore)
-{
-	int len;
-	int *value;
-
-	value = (int *)fdt_getprop(fit, noffset, FIT_IGNORE_PROP, &len);
-	if (value == NULL || len != sizeof(int))
-		*ignore = 0;
-	else
-		*ignore = *value;
-
-	return 0;
-}
-#endif
-
-/**
- * fit_set_timestamp - set node timestamp property
- * @fit: pointer to the FIT format image header
- * @noffset: node offset
- * @timestamp: timestamp value to be set
- *
- * fit_set_timestamp() attempts to set timestamp property in the requested
- * node and returns operation status to the caller.
- *
- * returns:
- *     0, on success
- *     -1, on property read failure
- */
-int fit_set_timestamp(void *fit, int noffset, time_t timestamp)
-{
-	uint32_t t;
-	int ret;
-
-	t = cpu_to_uimage(timestamp);
-	ret = fdt_setprop(fit, noffset, FIT_TIMESTAMP_PROP, &t,
-				sizeof(uint32_t));
-	if (ret) {
-		printf("Can't set '%s' property for '%s' node (%s)\n",
-			FIT_TIMESTAMP_PROP, fit_get_name(fit, noffset, NULL),
-			fdt_strerror(ret));
-		return -1;
-	}
-
-	return 0;
-}
-
-/**
- * calculate_hash - calculate and return hash for provided input data
- * @data: pointer to the input data
- * @data_len: data length
- * @algo: requested hash algorithm
- * @value: pointer to the char, will hold hash value data (caller must
- * allocate enough free space)
- * value_len: length of the calculated hash
- *
- * calculate_hash() computes input data hash according to the requested algorithm.
- * Resulting hash value is placed in caller provided 'value' buffer, length
- * of the calculated hash is returned via value_len pointer argument.
- *
- * returns:
- *     0, on success
- *    -1, when algo is unsupported
- */
-static int calculate_hash(const void *data, int data_len, const char *algo,
-			uint8_t *value, int *value_len)
-{
-	if (strcmp(algo, "crc32") == 0) {
-		*((uint32_t *)value) = crc32_wd(0, data, data_len,
-							CHUNKSZ_CRC32);
-		*((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value));
-		*value_len = 4;
-	} else if (strcmp(algo, "sha1") == 0) {
-		sha1_csum_wd((unsigned char *) data, data_len,
-				(unsigned char *) value, CHUNKSZ_SHA1);
-		*value_len = 20;
-	} else if (strcmp(algo, "md5") == 0) {
-		md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5);
-		*value_len = 16;
-	} else {
-		debug("Unsupported hash alogrithm\n");
-		return -1;
-	}
-	return 0;
-}
-
-#ifdef USE_HOSTCC
-/**
- * fit_set_hashes - process FIT component image nodes and calculate hashes
- * @fit: pointer to the FIT format image header
- *
- * fit_set_hashes() adds hash values for all component images in the FIT blob.
- * Hashes are calculated for all component images which have hash subnodes
- * with algorithm property set to one of the supported hash algorithms.
- *
- * returns
- *     0, on success
- *     libfdt error code, on failure
- */
-int fit_set_hashes(void *fit)
-{
-	int images_noffset;
-	int noffset;
-	int ndepth;
-	int ret;
-
-	/* Find images parent node offset */
-	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
-	if (images_noffset < 0) {
-		printf("Can't find images parent node '%s' (%s)\n",
-			FIT_IMAGES_PATH, fdt_strerror(images_noffset));
-		return images_noffset;
-	}
-
-	/* Process its subnodes, print out component images details */
-	for (ndepth = 0, noffset = fdt_next_node(fit, images_noffset, &ndepth);
-	     (noffset >= 0) && (ndepth > 0);
-	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
-		if (ndepth == 1) {
-			/*
-			 * Direct child node of the images parent node,
-			 * i.e. component image node.
-			 */
-			ret = fit_image_set_hashes(fit, noffset);
-			if (ret)
-				return ret;
-		}
-	}
-
-	return 0;
-}
-
-/**
- * fit_image_set_hashes - calculate/set hashes for given component image node
- * @fit: pointer to the FIT format image header
- * @image_noffset: requested component image node
- *
- * fit_image_set_hashes() adds hash values for an component image node. All
- * existing hash subnodes are checked, if algorithm property is set to one of
- * the supported hash algorithms, hash value is computed and corresponding
- * hash node property is set, for example:
- *
- * Input component image node structure:
- *
- * o image@1 (at image_noffset)
- *   | - data = [binary data]
- *   o hash@1
- *     |- algo = "sha1"
- *
- * Output component image node structure:
- *
- * o image@1 (at image_noffset)
- *   | - data = [binary data]
- *   o hash@1
- *     |- algo = "sha1"
- *     |- value = sha1(data)
- *
- * returns:
- *     0 on sucess
- *    <0 on failure
- */
-int fit_image_set_hashes(void *fit, int image_noffset)
-{
-	const void *data;
-	size_t size;
-	char *algo;
-	uint8_t value[FIT_MAX_HASH_LEN];
-	int value_len;
-	int noffset;
-	int ndepth;
-
-	/* Get image data and data length */
-	if (fit_image_get_data(fit, image_noffset, &data, &size)) {
-		printf("Can't get image data/size\n");
-		return -1;
-	}
-
-	/* Process all hash subnodes of the component image node */
-	for (ndepth = 0, noffset = fdt_next_node(fit, image_noffset, &ndepth);
-	     (noffset >= 0) && (ndepth > 0);
-	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
-		if (ndepth == 1) {
-			/* Direct child node of the component image node */
-
-			/*
-			 * Check subnode name, must be equal to "hash".
-			 * Multiple hash nodes require unique unit node
-			 * names, e.g. hash@1, hash@2, etc.
-			 */
-			if (strncmp(fit_get_name(fit, noffset, NULL),
-						FIT_HASH_NODENAME,
-						strlen(FIT_HASH_NODENAME)) != 0) {
-				/* Not a hash subnode, skip it */
-				continue;
-			}
-
-			if (fit_image_hash_get_algo(fit, noffset, &algo)) {
-				printf("Can't get hash algo property for "
-					"'%s' hash node in '%s' image node\n",
-					fit_get_name(fit, noffset, NULL),
-					fit_get_name(fit, image_noffset, NULL));
-				return -1;
-			}
-
-			if (calculate_hash(data, size, algo, value,
-						&value_len)) {
-				printf("Unsupported hash algorithm (%s) for "
-					"'%s' hash node in '%s' image node\n",
-					algo, fit_get_name(fit, noffset, NULL),
-					fit_get_name(fit, image_noffset,
-							NULL));
-				return -1;
-			}
-
-			if (fit_image_hash_set_value(fit, noffset, value,
-							value_len)) {
-				printf("Can't set hash value for "
-					"'%s' hash node in '%s' image node\n",
-					fit_get_name(fit, noffset, NULL),
-					fit_get_name(fit, image_noffset, NULL));
-				return -1;
-			}
-		}
-	}
-
-	return 0;
-}
-
-/**
- * fit_image_hash_set_value - set hash value in requested has node
- * @fit: pointer to the FIT format image header
- * @noffset: hash node offset
- * @value: hash value to be set
- * @value_len: hash value length
- *
- * fit_image_hash_set_value() attempts to set hash value in a node at offset
- * given and returns operation status to the caller.
- *
- * returns
- *     0, on success
- *     -1, on failure
- */
-int fit_image_hash_set_value(void *fit, int noffset, uint8_t *value,
-				int value_len)
-{
-	int ret;
-
-	ret = fdt_setprop(fit, noffset, FIT_VALUE_PROP, value, value_len);
-	if (ret) {
-		printf("Can't set hash '%s' property for '%s' node(%s)\n",
-			FIT_VALUE_PROP, fit_get_name(fit, noffset, NULL),
-			fdt_strerror(ret));
-		return -1;
-	}
-
-	return 0;
-}
-#endif /* USE_HOSTCC */
-
-/**
- * fit_image_check_hashes - verify data intergity
- * @fit: pointer to the FIT format image header
- * @image_noffset: component image node offset
- *
- * fit_image_check_hashes() goes over component image hash nodes,
- * re-calculates each data hash and compares with the value stored in hash
- * node.
- *
- * returns:
- *     1, if all hashes are valid
- *     0, otherwise (or on error)
- */
-int fit_image_check_hashes(const void *fit, int image_noffset)
-{
-	const void	*data;
-	size_t		size;
-	char		*algo;
-	uint8_t		*fit_value;
-	int		fit_value_len;
-#ifndef USE_HOSTCC
-	int		ignore;
-#endif
-	uint8_t		value[FIT_MAX_HASH_LEN];
-	int		value_len;
-	int		noffset;
-	int		ndepth;
-	char		*err_msg = "";
-
-	/* Get image data and data length */
-	if (fit_image_get_data(fit, image_noffset, &data, &size)) {
-		printf("Can't get image data/size\n");
-		return 0;
-	}
-
-	/* Process all hash subnodes of the component image node */
-	for (ndepth = 0, noffset = fdt_next_node(fit, image_noffset, &ndepth);
-	     (noffset >= 0) && (ndepth > 0);
-	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
-		if (ndepth == 1) {
-			/* Direct child node of the component image node */
-
-			/*
-			 * Check subnode name, must be equal to "hash".
-			 * Multiple hash nodes require unique unit node
-			 * names, e.g. hash@1, hash@2, etc.
-			 */
-			if (strncmp(fit_get_name(fit, noffset, NULL),
-					FIT_HASH_NODENAME,
-					strlen(FIT_HASH_NODENAME)) != 0)
-				continue;
-
-			if (fit_image_hash_get_algo(fit, noffset, &algo)) {
-				err_msg = " error!\nCan't get hash algo "
-						"property";
-				goto error;
-			}
-			printf("%s", algo);
-
-#ifndef USE_HOSTCC
-			fit_image_hash_get_ignore(fit, noffset, &ignore);
-			if (ignore) {
-				printf("-skipped ");
-				continue;
-			}
-#endif
-
-			if (fit_image_hash_get_value(fit, noffset, &fit_value,
-							&fit_value_len)) {
-				err_msg = " error!\nCan't get hash value "
-						"property";
-				goto error;
-			}
-
-			if (calculate_hash(data, size, algo, value,
-						&value_len)) {
-				err_msg = " error!\n"
-						"Unsupported hash algorithm";
-				goto error;
-			}
-
-			if (value_len != fit_value_len) {
-				err_msg = " error !\nBad hash value len";
-				goto error;
-			} else if (memcmp(value, fit_value, value_len) != 0) {
-				err_msg = " error!\nBad hash value";
-				goto error;
-			}
-			printf("+ ");
-		}
-	}
-
-	if (noffset == -FDT_ERR_TRUNCATED || noffset == -FDT_ERR_BADSTRUCTURE) {
-		err_msg = " error!\nCorrupted or truncated tree";
-		goto error;
-	}
-
-	return 1;
-
-error:
-	printf("%s for '%s' hash node in '%s' image node\n",
-			err_msg, fit_get_name(fit, noffset, NULL),
-			fit_get_name(fit, image_noffset, NULL));
-	return 0;
-}
-
-/**
- * fit_all_image_check_hashes - verify data intergity for all images
- * @fit: pointer to the FIT format image header
- *
- * fit_all_image_check_hashes() goes over all images in the FIT and
- * for every images checks if all it's hashes are valid.
- *
- * returns:
- *     1, if all hashes of all images are valid
- *     0, otherwise (or on error)
- */
-int fit_all_image_check_hashes(const void *fit)
-{
-	int images_noffset;
-	int noffset;
-	int ndepth;
-	int count;
-
-	/* Find images parent node offset */
-	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
-	if (images_noffset < 0) {
-		printf("Can't find images parent node '%s' (%s)\n",
-			FIT_IMAGES_PATH, fdt_strerror(images_noffset));
-		return 0;
-	}
-
-	/* Process all image subnodes, check hashes for each */
-	printf("## Checking hash(es) for FIT Image at %08lx ...\n",
-		(ulong)fit);
-	for (ndepth = 0, count = 0,
-		noffset = fdt_next_node(fit, images_noffset, &ndepth);
-		(noffset >= 0) && (ndepth > 0);
-		noffset = fdt_next_node(fit, noffset, &ndepth)) {
-		if (ndepth == 1) {
-			/*
-			 * Direct child node of the images parent node,
-			 * i.e. component image node.
-			 */
-			printf("   Hash(es) for Image %u (%s): ", count++,
-					fit_get_name(fit, noffset, NULL));
-
-			if (!fit_image_check_hashes(fit, noffset))
-				return 0;
-			printf("\n");
-		}
-	}
-	return 1;
-}
-
-/**
- * fit_image_check_os - check whether image node is of a given os type
- * @fit: pointer to the FIT format image header
- * @noffset: component image node offset
- * @os: requested image os
- *
- * fit_image_check_os() reads image os property and compares its numeric
- * id with the requested os. Comparison result is returned to the caller.
- *
- * returns:
- *     1 if image is of given os type
- *     0 otherwise (or on error)
- */
-int fit_image_check_os(const void *fit, int noffset, uint8_t os)
-{
-	uint8_t image_os;
-
-	if (fit_image_get_os(fit, noffset, &image_os))
-		return 0;
-	return (os == image_os);
-}
-
-/**
- * fit_image_check_arch - check whether image node is of a given arch
- * @fit: pointer to the FIT format image header
- * @noffset: component image node offset
- * @arch: requested imagearch
- *
- * fit_image_check_arch() reads image arch property and compares its numeric
- * id with the requested arch. Comparison result is returned to the caller.
- *
- * returns:
- *     1 if image is of given arch
- *     0 otherwise (or on error)
- */
-int fit_image_check_arch(const void *fit, int noffset, uint8_t arch)
-{
-	uint8_t image_arch;
-
-	if (fit_image_get_arch(fit, noffset, &image_arch))
-		return 0;
-	return (arch == image_arch);
-}
-
-/**
- * fit_image_check_type - check whether image node is of a given type
- * @fit: pointer to the FIT format image header
- * @noffset: component image node offset
- * @type: requested image type
- *
- * fit_image_check_type() reads image type property and compares its numeric
- * id with the requested type. Comparison result is returned to the caller.
- *
- * returns:
- *     1 if image is of given type
- *     0 otherwise (or on error)
- */
-int fit_image_check_type(const void *fit, int noffset, uint8_t type)
-{
-	uint8_t image_type;
-
-	if (fit_image_get_type(fit, noffset, &image_type))
-		return 0;
-	return (type == image_type);
-}
-
-/**
- * fit_image_check_comp - check whether image node uses given compression
- * @fit: pointer to the FIT format image header
- * @noffset: component image node offset
- * @comp: requested image compression type
- *
- * fit_image_check_comp() reads image compression property and compares its
- * numeric id with the requested compression type. Comparison result is
- * returned to the caller.
- *
- * returns:
- *     1 if image uses requested compression
- *     0 otherwise (or on error)
- */
-int fit_image_check_comp(const void *fit, int noffset, uint8_t comp)
-{
-	uint8_t image_comp;
-
-	if (fit_image_get_comp(fit, noffset, &image_comp))
-		return 0;
-	return (comp == image_comp);
-}
-
-/**
- * fit_check_format - sanity check FIT image format
- * @fit: pointer to the FIT format image header
- *
- * fit_check_format() runs a basic sanity FIT image verification.
- * Routine checks for mandatory properties, nodes, etc.
- *
- * returns:
- *     1, on success
- *     0, on failure
- */
-int fit_check_format(const void *fit)
-{
-	/* mandatory / node 'description' property */
-	if (fdt_getprop(fit, 0, FIT_DESC_PROP, NULL) == NULL) {
-		debug("Wrong FIT format: no description\n");
-		return 0;
-	}
-
-#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
-	/* mandatory / node 'timestamp' property */
-	if (fdt_getprop(fit, 0, FIT_TIMESTAMP_PROP, NULL) == NULL) {
-		debug("Wrong FIT format: no timestamp\n");
-		return 0;
-	}
-#endif
-
-	/* mandatory subimages parent '/images' node */
-	if (fdt_path_offset(fit, FIT_IMAGES_PATH) < 0) {
-		debug("Wrong FIT format: no images parent node\n");
-		return 0;
-	}
-
-	return 1;
-}
-
-
-/**
- * fit_conf_find_compat
- * @fit: pointer to the FIT format image header
- * @fdt: pointer to the device tree to compare against
- *
- * fit_conf_find_compat() attempts to find the configuration whose fdt is the
- * most compatible with the passed in device tree.
- *
- * Example:
- *
- * / o image-tree
- *   |-o images
- *   | |-o fdt@1
- *   | |-o fdt@2
- *   |
- *   |-o configurations
- *     |-o config@1
- *     | |-fdt = fdt@1
- *     |
- *     |-o config@2
- *       |-fdt = fdt@2
- *
- * / o U-Boot fdt
- *   |-compatible = "foo,bar", "bim,bam"
- *
- * / o kernel fdt1
- *   |-compatible = "foo,bar",
- *
- * / o kernel fdt2
- *   |-compatible = "bim,bam", "baz,biz"
- *
- * Configuration 1 would be picked because the first string in U-Boot's
- * compatible list, "foo,bar", matches a compatible string in the root of fdt1.
- * "bim,bam" in fdt2 matches the second string which isn't as good as fdt1.
- *
- * returns:
- *     offset to the configuration to use if one was found
- *     -1 otherwise
- */
-int fit_conf_find_compat(const void *fit, const void *fdt)
-{
-	int ndepth = 0;
-	int noffset, confs_noffset, images_noffset;
-	const void *fdt_compat;
-	int fdt_compat_len;
-	int best_match_offset = 0;
-	int best_match_pos = 0;
-
-	confs_noffset = fdt_path_offset(fit, FIT_CONFS_PATH);
-	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
-	if (confs_noffset < 0 || images_noffset < 0) {
-		debug("Can't find configurations or images nodes.\n");
-		return -1;
-	}
-
-	fdt_compat = fdt_getprop(fdt, 0, "compatible", &fdt_compat_len);
-	if (!fdt_compat) {
-		debug("Fdt for comparison has no \"compatible\" property.\n");
-		return -1;
-	}
-
-	/*
-	 * Loop over the configurations in the FIT image.
-	 */
-	for (noffset = fdt_next_node(fit, confs_noffset, &ndepth);
-			(noffset >= 0) && (ndepth > 0);
-			noffset = fdt_next_node(fit, noffset, &ndepth)) {
-		const void *kfdt;
-		const char *kfdt_name;
-		int kfdt_noffset;
-		const char *cur_fdt_compat;
-		int len;
-		size_t size;
-		int i;
-
-		if (ndepth > 1)
-			continue;
-
-		kfdt_name = fdt_getprop(fit, noffset, "fdt", &len);
-		if (!kfdt_name) {
-			debug("No fdt property found.\n");
-			continue;
-		}
-		kfdt_noffset = fdt_subnode_offset(fit, images_noffset,
-						  kfdt_name);
-		if (kfdt_noffset < 0) {
-			debug("No image node named \"%s\" found.\n",
-			      kfdt_name);
-			continue;
-		}
-		/*
-		 * Get a pointer to this configuration's fdt.
-		 */
-		if (fit_image_get_data(fit, kfdt_noffset, &kfdt, &size)) {
-			debug("Failed to get fdt \"%s\".\n", kfdt_name);
-			continue;
-		}
-
-		len = fdt_compat_len;
-		cur_fdt_compat = fdt_compat;
-		/*
-		 * Look for a match for each U-Boot compatibility string in
-		 * turn in this configuration's fdt.
-		 */
-		for (i = 0; len > 0 &&
-		     (!best_match_offset || best_match_pos > i); i++) {
-			int cur_len = strlen(cur_fdt_compat) + 1;
-
-			if (!fdt_node_check_compatible(kfdt, 0,
-						       cur_fdt_compat)) {
-				best_match_offset = noffset;
-				best_match_pos = i;
-				break;
-			}
-			len -= cur_len;
-			cur_fdt_compat += cur_len;
-		}
-	}
-	if (!best_match_offset) {
-		debug("No match found.\n");
-		return -1;
-	}
-
-	return best_match_offset;
-}
-
-/**
- * fit_conf_get_node - get node offset for configuration of a given unit name
- * @fit: pointer to the FIT format image header
- * @conf_uname: configuration node unit name
- *
- * fit_conf_get_node() finds a configuration (withing the '/configurations'
- * parant node) of a provided unit name. If configuration is found its node offset
- * is returned to the caller.
- *
- * When NULL is provided in second argument fit_conf_get_node() will search
- * for a default configuration node instead. Default configuration node unit name
- * is retrived from FIT_DEFAULT_PROP property of the '/configurations' node.
- *
- * returns:
- *     configuration node offset when found (>=0)
- *     negative number on failure (FDT_ERR_* code)
- */
-int fit_conf_get_node(const void *fit, const char *conf_uname)
-{
-	int noffset, confs_noffset;
-	int len;
-
-	confs_noffset = fdt_path_offset(fit, FIT_CONFS_PATH);
-	if (confs_noffset < 0) {
-		debug("Can't find configurations parent node '%s' (%s)\n",
-			FIT_CONFS_PATH, fdt_strerror(confs_noffset));
-		return confs_noffset;
-	}
-
-	if (conf_uname == NULL) {
-		/* get configuration unit name from the default property */
-		debug("No configuration specified, trying default...\n");
-		conf_uname = (char *)fdt_getprop(fit, confs_noffset,
-						 FIT_DEFAULT_PROP, &len);
-		if (conf_uname == NULL) {
-			fit_get_debug(fit, confs_noffset, FIT_DEFAULT_PROP,
-					len);
-			return len;
-		}
-		debug("Found default configuration: '%s'\n", conf_uname);
-	}
-
-	noffset = fdt_subnode_offset(fit, confs_noffset, conf_uname);
-	if (noffset < 0) {
-		debug("Can't get node offset for configuration unit name: "
-			"'%s' (%s)\n",
-			conf_uname, fdt_strerror(noffset));
-	}
-
-	return noffset;
-}
-
-static int __fit_conf_get_prop_node(const void *fit, int noffset,
-		const char *prop_name)
-{
-	char *uname;
-	int len;
-
-	/* get kernel image unit name from configuration kernel property */
-	uname = (char *)fdt_getprop(fit, noffset, prop_name, &len);
-	if (uname == NULL)
-		return len;
-
-	return fit_image_get_node(fit, uname);
-}
-
-/**
- * fit_conf_get_kernel_node - get kernel image node offset that corresponds to
- * a given configuration
- * @fit: pointer to the FIT format image header
- * @noffset: configuration node offset
- *
- * fit_conf_get_kernel_node() retrives kernel image node unit name from
- * configuration FIT_KERNEL_PROP property and translates it to the node
- * offset.
- *
- * returns:
- *     image node offset when found (>=0)
- *     negative number on failure (FDT_ERR_* code)
- */
-int fit_conf_get_kernel_node(const void *fit, int noffset)
-{
-	return __fit_conf_get_prop_node(fit, noffset, FIT_KERNEL_PROP);
-}
-
-/**
- * fit_conf_get_ramdisk_node - get ramdisk image node offset that corresponds to
- * a given configuration
- * @fit: pointer to the FIT format image header
- * @noffset: configuration node offset
- *
- * fit_conf_get_ramdisk_node() retrives ramdisk image node unit name from
- * configuration FIT_KERNEL_PROP property and translates it to the node
- * offset.
- *
- * returns:
- *     image node offset when found (>=0)
- *     negative number on failure (FDT_ERR_* code)
- */
-int fit_conf_get_ramdisk_node(const void *fit, int noffset)
-{
-	return __fit_conf_get_prop_node(fit, noffset, FIT_RAMDISK_PROP);
-}
-
-/**
- * fit_conf_get_fdt_node - get fdt image node offset that corresponds to
- * a given configuration
- * @fit: pointer to the FIT format image header
- * @noffset: configuration node offset
- *
- * fit_conf_get_fdt_node() retrives fdt image node unit name from
- * configuration FIT_KERNEL_PROP property and translates it to the node
- * offset.
- *
- * returns:
- *     image node offset when found (>=0)
- *     negative number on failure (FDT_ERR_* code)
- */
-int fit_conf_get_fdt_node(const void *fit, int noffset)
-{
-	return __fit_conf_get_prop_node(fit, noffset, FIT_FDT_PROP);
-}
-
-/**
- * fit_conf_print - prints out the FIT configuration details
- * @fit: pointer to the FIT format image header
- * @noffset: offset of the configuration node
- * @p: pointer to prefix string
- *
- * fit_conf_print() lists all mandatory properies for the processed
- * configuration node.
- *
- * returns:
- *     no returned results
- */
-void fit_conf_print(const void *fit, int noffset, const char *p)
-{
-	char *desc;
-	char *uname;
-	int ret;
-
-	/* Mandatory properties */
-	ret = fit_get_desc(fit, noffset, &desc);
-	printf("%s  Description:  ", p);
-	if (ret)
-		printf("unavailable\n");
-	else
-		printf("%s\n", desc);
-
-	uname = (char *)fdt_getprop(fit, noffset, FIT_KERNEL_PROP, NULL);
-	printf("%s  Kernel:       ", p);
-	if (uname == NULL)
-		printf("unavailable\n");
-	else
-		printf("%s\n", uname);
-
-	/* Optional properties */
-	uname = (char *)fdt_getprop(fit, noffset, FIT_RAMDISK_PROP, NULL);
-	if (uname)
-		printf("%s  Init Ramdisk: %s\n", p, uname);
-
-	uname = (char *)fdt_getprop(fit, noffset, FIT_FDT_PROP, NULL);
-	if (uname)
-		printf("%s  FDT:          %s\n", p, uname);
-}
-
-/**
- * fit_check_ramdisk - verify FIT format ramdisk subimage
- * @fit_hdr: pointer to the FIT ramdisk header
- * @rd_noffset: ramdisk subimage node offset within FIT image
- * @arch: requested ramdisk image architecture type
- * @verify: data CRC verification flag
- *
- * fit_check_ramdisk() verifies integrity of the ramdisk subimage and from
- * specified FIT image.
- *
- * returns:
- *     1, on success
- *     0, on failure
- */
-#ifndef USE_HOSTCC
-static int fit_check_ramdisk(const void *fit, int rd_noffset, uint8_t arch,
-				int verify)
-{
-	fit_image_print(fit, rd_noffset, "   ");
-
-	if (verify) {
-		puts("   Verifying Hash Integrity ... ");
-		if (!fit_image_check_hashes(fit, rd_noffset)) {
-			puts("Bad Data Hash\n");
-			bootstage_error(BOOTSTAGE_ID_FIT_RD_HASH);
-			return 0;
-		}
-		puts("OK\n");
-	}
-
-	bootstage_mark(BOOTSTAGE_ID_FIT_RD_CHECK_ALL);
-	if (!fit_image_check_os(fit, rd_noffset, IH_OS_LINUX) ||
-	    !fit_image_check_arch(fit, rd_noffset, arch) ||
-	    !fit_image_check_type(fit, rd_noffset, IH_TYPE_RAMDISK)) {
-		printf("No Linux %s Ramdisk Image\n",
-				genimg_get_arch_name(arch));
-		bootstage_error(BOOTSTAGE_ID_FIT_RD_CHECK_ALL);
-		return 0;
-	}
-
-	bootstage_mark(BOOTSTAGE_ID_FIT_RD_CHECK_ALL_OK);
-	return 1;
-}
-#endif /* USE_HOSTCC */
-#endif /* CONFIG_FIT */
+#endif /* CONFIG_LMB */
+#endif /* !USE_HOSTCC */
diff --git a/common/main.c b/common/main.c
index 953ef29..56da214 100644
--- a/common/main.c
+++ b/common/main.c
@@ -28,26 +28,15 @@
 /* #define	DEBUG	*/
 
 #include <common.h>
-#include <watchdog.h>
 #include <command.h>
 #include <fdtdec.h>
-#include <malloc.h>
-#include <version.h>
-#ifdef CONFIG_MODEM_SUPPORT
-#include <malloc.h>		/* for free() prototype */
-#endif
-
-#ifdef CONFIG_SYS_HUSH_PARSER
 #include <hush.h>
-#endif
-
-#ifdef CONFIG_OF_CONTROL
-#include <fdtdec.h>
-#endif
-
-#include <post.h>
-#include <linux/ctype.h>
+#include <malloc.h>
 #include <menu.h>
+#include <post.h>
+#include <version.h>
+#include <watchdog.h>
+#include <linux/ctype.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -57,13 +46,18 @@
 void inline __show_boot_progress (int val) {}
 void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress")));
 
-#if defined(CONFIG_UPDATE_TFTP)
-int update_tftp (ulong addr);
-#endif /* CONFIG_UPDATE_TFTP */
-
 #define MAX_DELAY_STOP_STR 32
 
-#undef DEBUG_PARSER
+#define DEBUG_PARSER	0	/* set to 1 to debug */
+
+#define debug_parser(fmt, args...)		\
+	debug_cond(DEBUG_PARSER, fmt, ##args)
+
+#ifndef DEBUG_BOOTKEYS
+#define DEBUG_BOOTKEYS 0
+#endif
+#define debug_bootkeys(fmt, args...)		\
+	debug_cond(DEBUG_BOOTKEYS, fmt, ##args)
 
 char        console_buffer[CONFIG_SYS_CBSIZE + 1];	/* console I/O buffer	*/
 
@@ -93,10 +87,7 @@
  */
 #if defined(CONFIG_BOOTDELAY)
 # if defined(CONFIG_AUTOBOOT_KEYED)
-#ifndef CONFIG_MENU
-static inline
-#endif
-int abortboot(int bootdelay)
+static int abortboot_keyed(int bootdelay)
 {
 	int abort = 0;
 	uint64_t etime = endtick(bootdelay);
@@ -152,11 +143,9 @@
 		presskey_max = presskey_max > delaykey[i].len ?
 				    presskey_max : delaykey[i].len;
 
-#  if DEBUG_BOOTKEYS
-		printf("%s key:<%s>\n",
-		       delaykey[i].retry ? "delay" : "stop",
-		       delaykey[i].str ? delaykey[i].str : "NULL");
-#  endif
+		debug_bootkeys("%s key:<%s>\n",
+			       delaykey[i].retry ? "delay" : "stop",
+			       delaykey[i].str ? delaykey[i].str : "NULL");
 	}
 
 	/* In order to keep up with incoming data, check timeout only
@@ -181,10 +170,9 @@
 			    memcmp (presskey + presskey_len - delaykey[i].len,
 				    delaykey[i].str,
 				    delaykey[i].len) == 0) {
-#  if DEBUG_BOOTKEYS
-				printf("got %skey\n",
-				       delaykey[i].retry ? "delay" : "stop");
-#  endif
+				debug_bootkeys("got %skey\n",
+					       delaykey[i].retry ? "delay" :
+					       "stop");
 
 #  ifdef CONFIG_BOOT_RETRY_TIME
 				/* don't retry auto boot */
@@ -196,10 +184,8 @@
 		}
 	} while (!abort && get_ticks() <= etime);
 
-#  if DEBUG_BOOTKEYS
 	if (!abort)
-		puts("key timeout\n");
-#  endif
+		debug_bootkeys("key timeout\n");
 
 #ifdef CONFIG_SILENT_CONSOLE
 	if (abort)
@@ -215,10 +201,7 @@
 static int menukey = 0;
 #endif
 
-#ifndef CONFIG_MENU
-static inline
-#endif
-int abortboot(int bootdelay)
+static int abortboot_normal(int bootdelay)
 {
 	int abort = 0;
 	unsigned long ts;
@@ -275,6 +258,15 @@
 	return abort;
 }
 # endif	/* CONFIG_AUTOBOOT_KEYED */
+
+static int abortboot(int bootdelay)
+{
+#ifdef CONFIG_AUTOBOOT_KEYED
+	return abortboot_keyed(bootdelay);
+#else
+	return abortboot_normal(bootdelay);
+#endif
+}
 #endif	/* CONFIG_BOOTDELAY */
 
 /*
@@ -342,93 +334,35 @@
 }
 #endif /* CONFIG_OF_CONTROL */
 
-
-/****************************************************************************/
-
-void main_loop (void)
+#ifdef CONFIG_BOOTDELAY
+static void process_boot_delay(void)
 {
-#ifndef CONFIG_SYS_HUSH_PARSER
-	static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, };
-	int len;
-	int rc = 1;
-	int flag;
-#endif
-#if defined(CONFIG_BOOTDELAY) && defined(CONFIG_OF_CONTROL)
+#ifdef CONFIG_OF_CONTROL
 	char *env;
 #endif
-#if defined(CONFIG_BOOTDELAY)
 	char *s;
 	int bootdelay;
-#endif
-#ifdef CONFIG_PREBOOT
-	char *p;
-#endif
 #ifdef CONFIG_BOOTCOUNT_LIMIT
 	unsigned long bootcount = 0;
 	unsigned long bootlimit = 0;
-	char *bcs;
-	char bcs_set[16];
 #endif /* CONFIG_BOOTCOUNT_LIMIT */
 
-	bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop");
-
 #ifdef CONFIG_BOOTCOUNT_LIMIT
 	bootcount = bootcount_load();
 	bootcount++;
 	bootcount_store (bootcount);
-	sprintf (bcs_set, "%lu", bootcount);
-	setenv ("bootcount", bcs_set);
-	bcs = getenv ("bootlimit");
-	bootlimit = bcs ? simple_strtoul (bcs, NULL, 10) : 0;
+	setenv_ulong("bootcount", bootcount);
+	bootlimit = getenv_ulong("bootlimit", 10, 0);
 #endif /* CONFIG_BOOTCOUNT_LIMIT */
 
-#ifdef CONFIG_MODEM_SUPPORT
-	debug ("DEBUG: main_loop:   do_mdm_init=%d\n", do_mdm_init);
-	if (do_mdm_init) {
-		char *str = strdup(getenv("mdm_cmd"));
-		setenv ("preboot", str);  /* set or delete definition */
-		if (str != NULL)
-			free (str);
-		mdm_init(); /* wait for modem connection */
-	}
-#endif  /* CONFIG_MODEM_SUPPORT */
-
-#ifdef CONFIG_VERSION_VARIABLE
-	{
-		setenv ("ver", version_string);  /* set version variable */
-	}
-#endif /* CONFIG_VERSION_VARIABLE */
-
-#ifdef CONFIG_SYS_HUSH_PARSER
-	u_boot_hush_start ();
-#endif
-
-#if defined(CONFIG_HUSH_INIT_VAR)
-	hush_init_var ();
-#endif
-
-#ifdef CONFIG_PREBOOT
-	if ((p = getenv ("preboot")) != NULL) {
-# ifdef CONFIG_AUTOBOOT_KEYED
-		int prev = disable_ctrlc(1);	/* disable Control C checking */
-# endif
-
-		run_command_list(p, -1, 0);
-
-# ifdef CONFIG_AUTOBOOT_KEYED
-		disable_ctrlc(prev);	/* restore Control C checking */
-# endif
-	}
-#endif /* CONFIG_PREBOOT */
-
-#if defined(CONFIG_UPDATE_TFTP)
-	update_tftp (0UL);
-#endif /* CONFIG_UPDATE_TFTP */
-
-#if defined(CONFIG_BOOTDELAY)
 	s = getenv ("bootdelay");
 	bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
 
+#ifdef CONFIG_OF_CONTROL
+	bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay",
+			bootdelay);
+#endif
+
 	debug ("### main_loop entered: bootdelay=%d\n\n", bootdelay);
 
 #if defined(CONFIG_MENU_SHOW)
@@ -474,26 +408,88 @@
 	debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
 
 	if (bootdelay != -1 && s && !abortboot(bootdelay)) {
-# ifdef CONFIG_AUTOBOOT_KEYED
+#ifdef CONFIG_AUTOBOOT_KEYED
 		int prev = disable_ctrlc(1);	/* disable Control C checking */
-# endif
+#endif
 
 		run_command_list(s, -1, 0);
 
-# ifdef CONFIG_AUTOBOOT_KEYED
+#ifdef CONFIG_AUTOBOOT_KEYED
 		disable_ctrlc(prev);	/* restore Control C checking */
-# endif
+#endif
 	}
 
-# ifdef CONFIG_MENUKEY
+#ifdef CONFIG_MENUKEY
 	if (menukey == CONFIG_MENUKEY) {
 		s = getenv("menucmd");
 		if (s)
 			run_command_list(s, -1, 0);
 	}
 #endif /* CONFIG_MENUKEY */
+}
 #endif /* CONFIG_BOOTDELAY */
 
+void main_loop(void)
+{
+#ifndef CONFIG_SYS_HUSH_PARSER
+	static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, };
+	int len;
+	int rc = 1;
+	int flag;
+#endif
+#ifdef CONFIG_PREBOOT
+	char *p;
+#endif
+
+	bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop");
+
+#ifdef CONFIG_MODEM_SUPPORT
+	debug("DEBUG: main_loop:   do_mdm_init=%d\n", do_mdm_init);
+	if (do_mdm_init) {
+		char *str = strdup(getenv("mdm_cmd"));
+		setenv("preboot", str);  /* set or delete definition */
+		if (str != NULL)
+			free(str);
+		mdm_init(); /* wait for modem connection */
+	}
+#endif  /* CONFIG_MODEM_SUPPORT */
+
+#ifdef CONFIG_VERSION_VARIABLE
+	{
+		setenv("ver", version_string);  /* set version variable */
+	}
+#endif /* CONFIG_VERSION_VARIABLE */
+
+#ifdef CONFIG_SYS_HUSH_PARSER
+	u_boot_hush_start();
+#endif
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+	hush_init_var();
+#endif
+
+#ifdef CONFIG_PREBOOT
+	p = getenv("preboot");
+	if (p != NULL) {
+# ifdef CONFIG_AUTOBOOT_KEYED
+		int prev = disable_ctrlc(1);	/* disable Control C checking */
+# endif
+
+		run_command_list(p, -1, 0);
+
+# ifdef CONFIG_AUTOBOOT_KEYED
+		disable_ctrlc(prev);	/* restore Control C checking */
+# endif
+	}
+#endif /* CONFIG_PREBOOT */
+
+#if defined(CONFIG_UPDATE_TFTP)
+	update_tftp(0UL);
+#endif /* CONFIG_UPDATE_TFTP */
+
+#ifdef CONFIG_BOOTDELAY
+	process_boot_delay();
+#endif
 	/*
 	 * Main Loop for Monitor Command Processing
 	 */
@@ -1080,20 +1076,20 @@
 		 * Special character handling
 		 */
 		switch (c) {
-		case '\r':				/* Enter		*/
+		case '\r':			/* Enter		*/
 		case '\n':
 			*p = '\0';
 			puts ("\r\n");
-			return (p - p_buf);
+			return p - p_buf;
 
-		case '\0':				/* nul			*/
+		case '\0':			/* nul			*/
 			continue;
 
-		case 0x03:				/* ^C - break		*/
+		case 0x03:			/* ^C - break		*/
 			p_buf[0] = '\0';	/* discard input */
-			return (-1);
+			return -1;
 
-		case 0x15:				/* ^U - erase line	*/
+		case 0x15:			/* ^U - erase line	*/
 			while (col > plen) {
 				puts (erase_seq);
 				--col;
@@ -1102,15 +1098,15 @@
 			n = 0;
 			continue;
 
-		case 0x17:				/* ^W - erase word	*/
+		case 0x17:			/* ^W - erase word	*/
 			p=delete_char(p_buf, p, &col, &n, plen);
 			while ((n > 0) && (*p != ' ')) {
 				p=delete_char(p_buf, p, &col, &n, plen);
 			}
 			continue;
 
-		case 0x08:				/* ^H  - backspace	*/
-		case 0x7F:				/* DEL - backspace	*/
+		case 0x08:			/* ^H  - backspace	*/
+		case 0x7F:			/* DEL - backspace	*/
 			p=delete_char(p_buf, p, &col, &n, plen);
 			continue;
 
@@ -1119,7 +1115,7 @@
 			 * Must be a normal character then
 			 */
 			if (n < CONFIG_SYS_CBSIZE-2) {
-				if (c == '\t') {	/* expand TABs		*/
+				if (c == '\t') {	/* expand TABs */
 #ifdef CONFIG_AUTO_COMPLETE
 					/* if auto completion triggered just continue */
 					*p = '\0';
@@ -1134,7 +1130,7 @@
 					char buf[2];
 
 					/*
-					 * Echo input using puts() to force am
+					 * Echo input using puts() to force an
 					 * LCD flush if we are using an LCD
 					 */
 					++col;
@@ -1192,9 +1188,7 @@
 {
 	int nargs = 0;
 
-#ifdef DEBUG_PARSER
-	printf ("parse_line: \"%s\"\n", line);
-#endif
+	debug_parser("parse_line: \"%s\"\n", line);
 	while (nargs < CONFIG_SYS_MAXARGS) {
 
 		/* skip any white space */
@@ -1203,10 +1197,8 @@
 
 		if (*line == '\0') {	/* end of line, no more args	*/
 			argv[nargs] = NULL;
-#ifdef DEBUG_PARSER
-		printf ("parse_line: nargs=%d\n", nargs);
-#endif
-			return (nargs);
+			debug_parser("parse_line: nargs=%d\n", nargs);
+			return nargs;
 		}
 
 		argv[nargs++] = line;	/* begin of argument string	*/
@@ -1217,10 +1209,8 @@
 
 		if (*line == '\0') {	/* end of line, no more args	*/
 			argv[nargs] = NULL;
-#ifdef DEBUG_PARSER
-		printf ("parse_line: nargs=%d\n", nargs);
-#endif
-			return (nargs);
+			debug_parser("parse_line: nargs=%d\n", nargs);
+			return nargs;
 		}
 
 		*line++ = '\0';		/* terminate current arg	 */
@@ -1228,9 +1218,7 @@
 
 	printf ("** Too many args (max. %d) **\n", CONFIG_SYS_MAXARGS);
 
-#ifdef DEBUG_PARSER
-	printf ("parse_line: nargs=%d\n", nargs);
-#endif
+	debug_parser("parse_line: nargs=%d\n", nargs);
 	return (nargs);
 }
 
@@ -1248,12 +1236,10 @@
 	/* 1 = waiting for '(' or '{' */
 	/* 2 = waiting for ')' or '}' */
 	/* 3 = waiting for '''  */
-#ifdef DEBUG_PARSER
 	char *output_start = output;
 
-	printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen (input),
-		input);
-#endif
+	debug_parser("[PROCESS_MACROS] INPUT len %zd: \"%s\"\n", strlen(input),
+		     input);
 
 	prev = '\0';		/* previous character   */
 
@@ -1341,10 +1327,8 @@
 	else
 		*(output - 1) = 0;
 
-#ifdef DEBUG_PARSER
-	printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n",
-		strlen (output_start), output_start);
-#endif
+	debug_parser("[PROCESS_MACROS] OUTPUT len %zd: \"%s\"\n",
+		     strlen(output_start), output_start);
 }
 
 /****************************************************************************
@@ -1375,12 +1359,12 @@
 	int repeatable = 1;
 	int rc = 0;
 
-#ifdef DEBUG_PARSER
-	printf ("[RUN_COMMAND] cmd[%p]=\"", cmd);
-	puts (cmd ? cmd : "NULL");	/* use puts - string may be loooong */
-	puts ("\"\n");
-#endif
-
+	debug_parser("[RUN_COMMAND] cmd[%p]=\"", cmd);
+	if (DEBUG_PARSER) {
+		/* use puts - string may be loooong */
+		puts(cmd ? cmd : "NULL");
+		puts("\"\n");
+	}
 	clear_ctrlc();		/* forget any previous Control C */
 
 	if (!cmd || !*cmd) {
@@ -1398,9 +1382,7 @@
 	 * repeatable commands
 	 */
 
-#ifdef DEBUG_PARSER
-	printf ("[PROCESS_SEPARATORS] %s\n", cmd);
-#endif
+	debug_parser("[PROCESS_SEPARATORS] %s\n", cmd);
 	while (*str) {
 
 		/*
@@ -1429,9 +1411,7 @@
 		}
 		else
 			str = sep;	/* no more commands for next pass */
-#ifdef DEBUG_PARSER
-		printf ("token: \"%s\"\n", token);
-#endif
+		debug_parser("token: \"%s\"\n", token);
 
 		/* find macros in this token and replace them */
 		process_macros (token, finaltoken);
diff --git a/common/spl/Makefile b/common/spl/Makefile
index da2afc1..a74563c 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -20,6 +20,7 @@
 COBJS-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
 COBJS-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o
 COBJS-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
+COBJS-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
 endif
 
 COBJS	:= $(sort $(COBJS-y))
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 7ce2d5f..628c399 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -118,17 +118,13 @@
 
 __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 {
-	typedef void __noreturn (*image_entry_noargs_t)(u32 *);
+	typedef void __noreturn (*image_entry_noargs_t)(void);
+
 	image_entry_noargs_t image_entry =
 			(image_entry_noargs_t) spl_image->entry_point;
 
 	debug("image entry point: 0x%X\n", spl_image->entry_point);
-	/* Pass the saved boot_params from rom code */
-#if defined(CONFIG_VIRTIO) || defined(CONFIG_ZEBU)
-	image_entry = (image_entry_noargs_t)0x80100000;
-#endif
-	u32 boot_params_ptr_addr = (u32)&boot_params_ptr;
-	image_entry((u32 *)boot_params_ptr_addr);
+	image_entry();
 }
 
 #ifdef CONFIG_SPL_RAM_DEVICE
diff --git a/drivers/mmc/spl_mmc.c b/common/spl/spl_mmc.c
similarity index 100%
rename from drivers/mmc/spl_mmc.c
rename to common/spl/spl_mmc.c
diff --git a/common/update.c b/common/update.c
index 94d6a82..87941ec 100644
--- a/common/update.c
+++ b/common/update.c
@@ -297,7 +297,7 @@
 		printf("Processing update '%s' :",
 			fit_get_name(fit, noffset, NULL));
 
-		if (!fit_image_check_hashes(fit, noffset)) {
+		if (!fit_image_verify(fit, noffset)) {
 			printf("Error: invalid update hash, aborting\n");
 			ret = 1;
 			goto next_node;
diff --git a/common/usb.c b/common/usb.c
index 6fc0fc1..55fff5b 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -57,17 +57,6 @@
 #include <asm/4xx_pci.h>
 #endif
 
-#ifdef DEBUG
-#define USB_DEBUG	1
-#define USB_HUB_DEBUG	1
-#else
-#define USB_DEBUG	0
-#define USB_HUB_DEBUG	0
-#endif
-
-#define USB_PRINTF(fmt, args...)	debug_cond(USB_DEBUG, fmt, ##args)
-#define USB_HUB_PRINTF(fmt, args...)	debug_cond(USB_HUB_DEBUG, fmt, ##args)
-
 #define USB_BUFSIZ	512
 
 static struct usb_device usb_dev[USB_MAX_DEVICE];
@@ -130,7 +119,7 @@
 		usb_started = 1;
 	}
 
-	USB_PRINTF("scan end\n");
+	debug("scan end\n");
 	/* if we were not able to find at least one working bus, bail out */
 	if (!usb_started) {
 		puts("USB error: all controllers failed lowlevel init\n");
@@ -216,9 +205,9 @@
 	setup_packet->value = cpu_to_le16(value);
 	setup_packet->index = cpu_to_le16(index);
 	setup_packet->length = cpu_to_le16(size);
-	USB_PRINTF("usb_control_msg: request: 0x%X, requesttype: 0x%X, " \
-		   "value 0x%X index 0x%X length 0x%X\n",
-		   request, requesttype, value, index, size);
+	debug("usb_control_msg: request: 0x%X, requesttype: 0x%X, " \
+	      "value 0x%X index 0x%X length 0x%X\n",
+	      request, requesttype, value, index, size);
 	dev->status = USB_ST_NOT_PROC; /*not yet processed */
 
 	if (submit_control_msg(dev, pipe, data, size, setup_packet) < 0)
@@ -314,22 +303,22 @@
 		/* Control => bidirectional */
 		dev->epmaxpacketout[b] = ep_wMaxPacketSize;
 		dev->epmaxpacketin[b] = ep_wMaxPacketSize;
-		USB_PRINTF("##Control EP epmaxpacketout/in[%d] = %d\n",
-			   b, dev->epmaxpacketin[b]);
+		debug("##Control EP epmaxpacketout/in[%d] = %d\n",
+		      b, dev->epmaxpacketin[b]);
 	} else {
 		if ((ep->bEndpointAddress & 0x80) == 0) {
 			/* OUT Endpoint */
 			if (ep_wMaxPacketSize > dev->epmaxpacketout[b]) {
 				dev->epmaxpacketout[b] = ep_wMaxPacketSize;
-				USB_PRINTF("##EP epmaxpacketout[%d] = %d\n",
-					   b, dev->epmaxpacketout[b]);
+				debug("##EP epmaxpacketout[%d] = %d\n",
+				      b, dev->epmaxpacketout[b]);
 			}
 		} else {
 			/* IN Endpoint */
 			if (ep_wMaxPacketSize > dev->epmaxpacketin[b]) {
 				dev->epmaxpacketin[b] = ep_wMaxPacketSize;
-				USB_PRINTF("##EP epmaxpacketin[%d] = %d\n",
-					   b, dev->epmaxpacketin[b]);
+				debug("##EP epmaxpacketin[%d] = %d\n",
+				      b, dev->epmaxpacketin[b]);
 			}
 		} /* if out */
 	} /* if control */
@@ -358,8 +347,8 @@
 {
 	struct usb_descriptor_header *head;
 	int index, ifno, epno, curr_if_num;
-	int i;
 	u16 ep_wMaxPacketSize;
+	struct usb_interface *if_desc = NULL;
 
 	ifno = -1;
 	epno = -1;
@@ -387,23 +376,27 @@
 			     &buffer[index])->bInterfaceNumber != curr_if_num) {
 				/* this is a new interface, copy new desc */
 				ifno = dev->config.no_of_if;
+				if_desc = &dev->config.if_desc[ifno];
 				dev->config.no_of_if++;
-				memcpy(&dev->config.if_desc[ifno],
-					&buffer[index], buffer[index]);
-				dev->config.if_desc[ifno].no_of_ep = 0;
-				dev->config.if_desc[ifno].num_altsetting = 1;
+				memcpy(if_desc,	&buffer[index], buffer[index]);
+				if_desc->no_of_ep = 0;
+				if_desc->num_altsetting = 1;
 				curr_if_num =
-				     dev->config.if_desc[ifno].desc.bInterfaceNumber;
+				     if_desc->desc.bInterfaceNumber;
 			} else {
 				/* found alternate setting for the interface */
-				dev->config.if_desc[ifno].num_altsetting++;
+				if (ifno >= 0) {
+					if_desc = &dev->config.if_desc[ifno];
+					if_desc->num_altsetting++;
+				}
 			}
 			break;
 		case USB_DT_ENDPOINT:
 			epno = dev->config.if_desc[ifno].no_of_ep;
+			if_desc = &dev->config.if_desc[ifno];
 			/* found an endpoint */
-			dev->config.if_desc[ifno].no_of_ep++;
-			memcpy(&dev->config.if_desc[ifno].ep_desc[epno],
+			if_desc->no_of_ep++;
+			memcpy(&if_desc->ep_desc[epno],
 				&buffer[index], buffer[index]);
 			ep_wMaxPacketSize = get_unaligned(&dev->config.\
 							if_desc[ifno].\
@@ -414,23 +407,30 @@
 					if_desc[ifno].\
 					ep_desc[epno].\
 					wMaxPacketSize);
-			USB_PRINTF("if %d, ep %d\n", ifno, epno);
+			debug("if %d, ep %d\n", ifno, epno);
+			break;
+		case USB_DT_SS_ENDPOINT_COMP:
+			if_desc = &dev->config.if_desc[ifno];
+			memcpy(&if_desc->ss_ep_comp_desc[epno],
+				&buffer[index], buffer[index]);
 			break;
 		default:
 			if (head->bLength == 0)
 				return 1;
 
-			USB_PRINTF("unknown Description Type : %x\n",
-				   head->bDescriptorType);
+			debug("unknown Description Type : %x\n",
+			      head->bDescriptorType);
 
+#ifdef DEBUG
 			{
-#ifdef USB_DEBUG
 				unsigned char *ch = (unsigned char *)head;
-#endif
+				int i;
+
 				for (i = 0; i < head->bLength; i++)
-					USB_PRINTF("%02X ", *ch++);
-				USB_PRINTF("\n\n\n");
+					debug("%02X ", *ch++);
+				debug("\n\n\n");
 			}
+#endif
 			break;
 		}
 		index += head->bLength;
@@ -514,8 +514,7 @@
 	}
 
 	result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, tmp);
-	USB_PRINTF("get_conf_no %d Result %d, wLength %d\n",
-		   cfgno, result, tmp);
+	debug("get_conf_no %d Result %d, wLength %d\n", cfgno, result, tmp);
 	return result;
 }
 
@@ -527,7 +526,7 @@
 {
 	int res;
 
-	USB_PRINTF("set address %d\n", dev->devnum);
+	debug("set address %d\n", dev->devnum);
 	res = usb_control_msg(dev, usb_snddefctrl(dev),
 				USB_REQ_SET_ADDRESS, 0,
 				(dev->devnum), 0,
@@ -579,7 +578,7 @@
 static int usb_set_configuration(struct usb_device *dev, int configuration)
 {
 	int res;
-	USB_PRINTF("set configuration %d\n", configuration);
+	debug("set configuration %d\n", configuration);
 	/* set setup command */
 	res = usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
 				USB_REQ_SET_CONFIGURATION, 0,
@@ -731,19 +730,19 @@
 	if (!dev->have_langid) {
 		err = usb_string_sub(dev, 0, 0, tbuf);
 		if (err < 0) {
-			USB_PRINTF("error getting string descriptor 0 " \
-				   "(error=%lx)\n", dev->status);
+			debug("error getting string descriptor 0 " \
+			      "(error=%lx)\n", dev->status);
 			return -1;
 		} else if (tbuf[0] < 4) {
-			USB_PRINTF("string descriptor 0 too short\n");
+			debug("string descriptor 0 too short\n");
 			return -1;
 		} else {
 			dev->have_langid = -1;
 			dev->string_langid = tbuf[2] | (tbuf[3] << 8);
 				/* always use the first langid listed */
-			USB_PRINTF("USB device number %d default " \
-				   "language ID 0x%x\n",
-				   dev->devnum, dev->string_langid);
+			debug("USB device number %d default " \
+			      "language ID 0x%x\n",
+			      dev->devnum, dev->string_langid);
 		}
 	}
 
@@ -789,7 +788,7 @@
 struct usb_device *usb_alloc_new_device(void *controller)
 {
 	int i;
-	USB_PRINTF("New Device %d\n", dev_index);
+	debug("New Device %d\n", dev_index);
 	if (dev_index == USB_MAX_DEVICE) {
 		printf("ERROR, too many USB Devices, max=%d\n", USB_MAX_DEVICE);
 		return NULL;
@@ -813,7 +812,7 @@
 void usb_free_device(void)
 {
 	dev_index--;
-	USB_PRINTF("Freeing device node: %d\n", dev_index);
+	debug("Freeing device node: %d\n", dev_index);
 	memset(&usb_dev[dev_index], 0, sizeof(struct usb_device));
 	usb_dev[dev_index].devnum = -1;
 }
@@ -880,11 +879,16 @@
 
 	err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64);
 	if (err < 0) {
-		USB_PRINTF("usb_new_device: usb_get_descriptor() failed\n");
+		debug("usb_new_device: usb_get_descriptor() failed\n");
 		return 1;
 	}
 
 	dev->descriptor.bMaxPacketSize0 = desc->bMaxPacketSize0;
+	/*
+	 * Fetch the device class, driver can use this info
+	 * to differentiate between HUB and DEVICE.
+	 */
+	dev->descriptor.bDeviceClass = desc->bDeviceClass;
 
 	/* find the port number we're at */
 	if (parent) {
@@ -973,9 +977,9 @@
 			"len %d, status %lX\n", dev->act_len, dev->status);
 		return -1;
 	}
-	USB_PRINTF("new device strings: Mfr=%d, Product=%d, SerialNumber=%d\n",
-		   dev->descriptor.iManufacturer, dev->descriptor.iProduct,
-		   dev->descriptor.iSerialNumber);
+	debug("new device strings: Mfr=%d, Product=%d, SerialNumber=%d\n",
+	      dev->descriptor.iManufacturer, dev->descriptor.iProduct,
+	      dev->descriptor.iSerialNumber);
 	memset(dev->mf, 0, sizeof(dev->mf));
 	memset(dev->prod, 0, sizeof(dev->prod));
 	memset(dev->serial, 0, sizeof(dev->serial));
@@ -988,9 +992,9 @@
 	if (dev->descriptor.iSerialNumber)
 		usb_string(dev, dev->descriptor.iSerialNumber,
 			   dev->serial, sizeof(dev->serial));
-	USB_PRINTF("Manufacturer %s\n", dev->mf);
-	USB_PRINTF("Product      %s\n", dev->prod);
-	USB_PRINTF("SerialNumber %s\n", dev->serial);
+	debug("Manufacturer %s\n", dev->mf);
+	debug("Product      %s\n", dev->prod);
+	debug("SerialNumber %s\n", dev->serial);
 	/* now prode if the device is a hub */
 	usb_hub_probe(dev, 0);
 	return 0;
diff --git a/common/usb_hub.c b/common/usb_hub.c
index b5eeb62..0d79ec3 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -53,17 +53,6 @@
 #include <asm/4xx_pci.h>
 #endif
 
-#ifdef DEBUG
-#define USB_DEBUG	1
-#define USB_HUB_DEBUG	1
-#else
-#define USB_DEBUG	0
-#define USB_HUB_DEBUG	0
-#endif
-
-#define USB_PRINTF(fmt, args...)	debug_cond(USB_DEBUG, fmt, ##args)
-#define USB_HUB_PRINTF(fmt, args...)	debug_cond(USB_HUB_DEBUG, fmt, ##args)
-
 #define USB_BUFSIZ	512
 
 static struct usb_hub_device hub_dev[USB_MAX_HUB];
@@ -111,13 +100,52 @@
 	int i;
 	struct usb_device *dev;
 	unsigned pgood_delay = hub->desc.bPwrOn2PwrGood * 2;
+	ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
+	unsigned short portstatus;
+	int ret;
 
 	dev = hub->pusb_dev;
-	/* Enable power to the ports */
-	USB_HUB_PRINTF("enabling power on all ports\n");
+
+	/*
+	 * Enable power to the ports:
+	 * Here we Power-cycle the ports: aka,
+	 * turning them off and turning on again.
+	 */
+	debug("enabling power on all ports\n");
+	for (i = 0; i < dev->maxchild; i++) {
+		usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
+		debug("port %d returns %lX\n", i + 1, dev->status);
+	}
+
+	/* Wait at least 2*bPwrOn2PwrGood for PP to change */
+	mdelay(pgood_delay);
+
+	for (i = 0; i < dev->maxchild; i++) {
+		ret = usb_get_port_status(dev, i + 1, portsts);
+		if (ret < 0) {
+			debug("port %d: get_port_status failed\n", i + 1);
+			return;
+		}
+
+		/*
+		 * Check to confirm the state of Port Power:
+		 * xHCI says "After modifying PP, s/w shall read
+		 * PP and confirm that it has reached the desired state
+		 * before modifying it again, undefined behavior may occur
+		 * if this procedure is not followed".
+		 * EHCI doesn't say anything like this, but no harm in keeping
+		 * this.
+		 */
+		portstatus = le16_to_cpu(portsts->wPortStatus);
+		if (portstatus & (USB_PORT_STAT_POWER << 1)) {
+			debug("port %d: Port power change failed\n", i + 1);
+			return;
+		}
+	}
+
 	for (i = 0; i < dev->maxchild; i++) {
 		usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
-		USB_HUB_PRINTF("port %d returns %lX\n", i + 1, dev->status);
+		debug("port %d returns %lX\n", i + 1, dev->status);
 	}
 
 	/* Wait at least 100 msec for power to become stable */
@@ -142,12 +170,24 @@
 
 static inline char *portspeed(int portstatus)
 {
-	if (portstatus & (1 << USB_PORT_FEAT_HIGHSPEED))
-		return "480 Mb/s";
-	else if (portstatus & (1 << USB_PORT_FEAT_LOWSPEED))
-		return "1.5 Mb/s";
-	else
-		return "12 Mb/s";
+	char *speed_str;
+
+	switch (portstatus & USB_PORT_STAT_SPEED_MASK) {
+	case USB_PORT_STAT_SUPER_SPEED:
+		speed_str = "5 Gb/s";
+		break;
+	case USB_PORT_STAT_HIGH_SPEED:
+		speed_str = "480 Mb/s";
+		break;
+	case USB_PORT_STAT_LOW_SPEED:
+		speed_str = "1.5 Mb/s";
+		break;
+	default:
+		speed_str = "12 Mb/s";
+		break;
+	}
+
+	return speed_str;
 }
 
 int hub_port_reset(struct usb_device *dev, int port,
@@ -157,29 +197,28 @@
 	ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
 	unsigned short portstatus, portchange;
 
-	USB_HUB_PRINTF("hub_port_reset: resetting port %d...\n", port);
+	debug("hub_port_reset: resetting port %d...\n", port);
 	for (tries = 0; tries < MAX_TRIES; tries++) {
 
 		usb_set_port_feature(dev, port + 1, USB_PORT_FEAT_RESET);
 		mdelay(200);
 
 		if (usb_get_port_status(dev, port + 1, portsts) < 0) {
-			USB_HUB_PRINTF("get_port_status failed status %lX\n",
-					dev->status);
+			debug("get_port_status failed status %lX\n",
+			      dev->status);
 			return -1;
 		}
 		portstatus = le16_to_cpu(portsts->wPortStatus);
 		portchange = le16_to_cpu(portsts->wPortChange);
 
-		USB_HUB_PRINTF("portstatus %x, change %x, %s\n",
-				portstatus, portchange,
-				portspeed(portstatus));
+		debug("portstatus %x, change %x, %s\n", portstatus, portchange,
+							portspeed(portstatus));
 
-		USB_HUB_PRINTF("STAT_C_CONNECTION = %d STAT_CONNECTION = %d" \
-			       "  USB_PORT_STAT_ENABLE %d\n",
-			(portchange & USB_PORT_STAT_C_CONNECTION) ? 1 : 0,
-			(portstatus & USB_PORT_STAT_CONNECTION) ? 1 : 0,
-			(portstatus & USB_PORT_STAT_ENABLE) ? 1 : 0);
+		debug("STAT_C_CONNECTION = %d STAT_CONNECTION = %d" \
+		      "  USB_PORT_STAT_ENABLE %d\n",
+		      (portchange & USB_PORT_STAT_C_CONNECTION) ? 1 : 0,
+		      (portstatus & USB_PORT_STAT_CONNECTION) ? 1 : 0,
+		      (portstatus & USB_PORT_STAT_ENABLE) ? 1 : 0);
 
 		if ((portchange & USB_PORT_STAT_C_CONNECTION) ||
 		    !(portstatus & USB_PORT_STAT_CONNECTION))
@@ -192,9 +231,9 @@
 	}
 
 	if (tries == MAX_TRIES) {
-		USB_HUB_PRINTF("Cannot enable port %i after %i retries, " \
-				"disabling port.\n", port + 1, MAX_TRIES);
-		USB_HUB_PRINTF("Maybe the USB cable is bad?\n");
+		debug("Cannot enable port %i after %i retries, " \
+		      "disabling port.\n", port + 1, MAX_TRIES);
+		debug("Maybe the USB cable is bad?\n");
 		return -1;
 	}
 
@@ -212,15 +251,15 @@
 
 	/* Check status */
 	if (usb_get_port_status(dev, port + 1, portsts) < 0) {
-		USB_HUB_PRINTF("get_port_status failed\n");
+		debug("get_port_status failed\n");
 		return;
 	}
 
 	portstatus = le16_to_cpu(portsts->wPortStatus);
-	USB_HUB_PRINTF("portstatus %x, change %x, %s\n",
-			portstatus,
-			le16_to_cpu(portsts->wPortChange),
-			portspeed(portstatus));
+	debug("portstatus %x, change %x, %s\n",
+	      portstatus,
+	      le16_to_cpu(portsts->wPortChange),
+	      portspeed(portstatus));
 
 	/* Clear the connection change status */
 	usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_CONNECTION);
@@ -228,7 +267,7 @@
 	/* Disconnect any existing devices under this port */
 	if (((!(portstatus & USB_PORT_STAT_CONNECTION)) &&
 	     (!(portstatus & USB_PORT_STAT_ENABLE))) || (dev->children[port])) {
-		USB_HUB_PRINTF("usb_disconnect(&hub->children[port]);\n");
+		debug("usb_disconnect(&hub->children[port]);\n");
 		/* Return now if nothing is connected */
 		if (!(portstatus & USB_PORT_STAT_CONNECTION))
 			return;
@@ -246,12 +285,20 @@
 	/* Allocate a new device struct for it */
 	usb = usb_alloc_new_device(dev->controller);
 
-	if (portstatus & USB_PORT_STAT_HIGH_SPEED)
+	switch (portstatus & USB_PORT_STAT_SPEED_MASK) {
+	case USB_PORT_STAT_SUPER_SPEED:
+		usb->speed = USB_SPEED_SUPER;
+		break;
+	case USB_PORT_STAT_HIGH_SPEED:
 		usb->speed = USB_SPEED_HIGH;
-	else if (portstatus & USB_PORT_STAT_LOW_SPEED)
+		break;
+	case USB_PORT_STAT_LOW_SPEED:
 		usb->speed = USB_SPEED_LOW;
-	else
+		break;
+	default:
 		usb->speed = USB_SPEED_FULL;
+		break;
+	}
 
 	dev->children[port] = usb;
 	usb->parent = dev;
@@ -261,7 +308,7 @@
 		/* Woops, disable the port */
 		usb_free_device();
 		dev->children[port] = NULL;
-		USB_HUB_PRINTF("hub: disabling port %d\n", port + 1);
+		debug("hub: disabling port %d\n", port + 1);
 		usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_ENABLE);
 	}
 }
@@ -275,9 +322,7 @@
 	short hubCharacteristics;
 	struct usb_hub_descriptor *descriptor;
 	struct usb_hub_device *hub;
-#ifdef USB_HUB_DEBUG
-	struct usb_hub_status *hubsts;
-#endif
+	__maybe_unused struct usb_hub_status *hubsts;
 
 	/* "allocate" Hub device */
 	hub = usb_hub_allocate();
@@ -286,8 +331,8 @@
 	hub->pusb_dev = dev;
 	/* Get the the hub descriptor */
 	if (usb_get_hub_descriptor(dev, buffer, 4) < 0) {
-		USB_HUB_PRINTF("usb_hub_configure: failed to get hub " \
-				   "descriptor, giving up %lX\n", dev->status);
+		debug("usb_hub_configure: failed to get hub " \
+		      "descriptor, giving up %lX\n", dev->status);
 		return -1;
 	}
 	descriptor = (struct usb_hub_descriptor *)buffer;
@@ -295,15 +340,14 @@
 	/* silence compiler warning if USB_BUFSIZ is > 256 [= sizeof(char)] */
 	i = descriptor->bLength;
 	if (i > USB_BUFSIZ) {
-		USB_HUB_PRINTF("usb_hub_configure: failed to get hub " \
-				"descriptor - too long: %d\n",
-				descriptor->bLength);
+		debug("usb_hub_configure: failed to get hub " \
+		      "descriptor - too long: %d\n", descriptor->bLength);
 		return -1;
 	}
 
 	if (usb_get_hub_descriptor(dev, buffer, descriptor->bLength) < 0) {
-		USB_HUB_PRINTF("usb_hub_configure: failed to get hub " \
-				"descriptor 2nd giving up %lX\n", dev->status);
+		debug("usb_hub_configure: failed to get hub " \
+		      "descriptor 2nd giving up %lX\n", dev->status);
 		return -1;
 	}
 	memcpy((unsigned char *)&hub->desc, buffer, descriptor->bLength);
@@ -325,74 +369,75 @@
 		hub->desc.PortPowerCtrlMask[i] = descriptor->PortPowerCtrlMask[i];
 
 	dev->maxchild = descriptor->bNbrPorts;
-	USB_HUB_PRINTF("%d ports detected\n", dev->maxchild);
+	debug("%d ports detected\n", dev->maxchild);
 
 	hubCharacteristics = get_unaligned(&hub->desc.wHubCharacteristics);
 	switch (hubCharacteristics & HUB_CHAR_LPSM) {
 	case 0x00:
-		USB_HUB_PRINTF("ganged power switching\n");
+		debug("ganged power switching\n");
 		break;
 	case 0x01:
-		USB_HUB_PRINTF("individual port power switching\n");
+		debug("individual port power switching\n");
 		break;
 	case 0x02:
 	case 0x03:
-		USB_HUB_PRINTF("unknown reserved power switching mode\n");
+		debug("unknown reserved power switching mode\n");
 		break;
 	}
 
 	if (hubCharacteristics & HUB_CHAR_COMPOUND)
-		USB_HUB_PRINTF("part of a compound device\n");
+		debug("part of a compound device\n");
 	else
-		USB_HUB_PRINTF("standalone hub\n");
+		debug("standalone hub\n");
 
 	switch (hubCharacteristics & HUB_CHAR_OCPM) {
 	case 0x00:
-		USB_HUB_PRINTF("global over-current protection\n");
+		debug("global over-current protection\n");
 		break;
 	case 0x08:
-		USB_HUB_PRINTF("individual port over-current protection\n");
+		debug("individual port over-current protection\n");
 		break;
 	case 0x10:
 	case 0x18:
-		USB_HUB_PRINTF("no over-current protection\n");
+		debug("no over-current protection\n");
 		break;
 	}
 
-	USB_HUB_PRINTF("power on to power good time: %dms\n",
-			descriptor->bPwrOn2PwrGood * 2);
-	USB_HUB_PRINTF("hub controller current requirement: %dmA\n",
-			descriptor->bHubContrCurrent);
+	debug("power on to power good time: %dms\n",
+	      descriptor->bPwrOn2PwrGood * 2);
+	debug("hub controller current requirement: %dmA\n",
+	      descriptor->bHubContrCurrent);
 
 	for (i = 0; i < dev->maxchild; i++)
-		USB_HUB_PRINTF("port %d is%s removable\n", i + 1,
-			hub->desc.DeviceRemovable[(i + 1) / 8] & \
-					   (1 << ((i + 1) % 8)) ? " not" : "");
+		debug("port %d is%s removable\n", i + 1,
+		      hub->desc.DeviceRemovable[(i + 1) / 8] & \
+		      (1 << ((i + 1) % 8)) ? " not" : "");
 
 	if (sizeof(struct usb_hub_status) > USB_BUFSIZ) {
-		USB_HUB_PRINTF("usb_hub_configure: failed to get Status - " \
-				"too long: %d\n", descriptor->bLength);
+		debug("usb_hub_configure: failed to get Status - " \
+		      "too long: %d\n", descriptor->bLength);
 		return -1;
 	}
 
 	if (usb_get_hub_status(dev, buffer) < 0) {
-		USB_HUB_PRINTF("usb_hub_configure: failed to get Status %lX\n",
-				dev->status);
+		debug("usb_hub_configure: failed to get Status %lX\n",
+		      dev->status);
 		return -1;
 	}
 
-#ifdef USB_HUB_DEBUG
+#ifdef DEBUG
 	hubsts = (struct usb_hub_status *)buffer;
 #endif
-	USB_HUB_PRINTF("get_hub_status returned status %X, change %X\n",
-			le16_to_cpu(hubsts->wHubStatus),
-			le16_to_cpu(hubsts->wHubChange));
-	USB_HUB_PRINTF("local power source is %s\n",
-		(le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? \
-		"lost (inactive)" : "good");
-	USB_HUB_PRINTF("%sover-current condition exists\n",
-		(le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? \
-		"" : "no ");
+
+	debug("get_hub_status returned status %X, change %X\n",
+	      le16_to_cpu(hubsts->wHubStatus),
+	      le16_to_cpu(hubsts->wHubChange));
+	debug("local power source is %s\n",
+	      (le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? \
+	      "lost (inactive)" : "good");
+	debug("%sover-current condition exists\n",
+	      (le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? \
+	      "" : "no ");
 	usb_hub_power_on(hub);
 
 	for (i = 0; i < dev->maxchild; i++) {
@@ -412,7 +457,7 @@
 		do {
 			ret = usb_get_port_status(dev, i + 1, portsts);
 			if (ret < 0) {
-				USB_HUB_PRINTF("get_port_status failed\n");
+				debug("get_port_status failed\n");
 				break;
 			}
 
@@ -423,22 +468,21 @@
 				(portstatus & USB_PORT_STAT_CONNECTION))
 				break;
 
-			mdelay(100);
 		} while (get_timer(start) < CONFIG_SYS_HZ * 10);
 
 		if (ret < 0)
 			continue;
 
-		USB_HUB_PRINTF("Port %d Status %X Change %X\n",
-				i + 1, portstatus, portchange);
+		debug("Port %d Status %X Change %X\n",
+		      i + 1, portstatus, portchange);
 
 		if (portchange & USB_PORT_STAT_C_CONNECTION) {
-			USB_HUB_PRINTF("port %d connection change\n", i + 1);
+			debug("port %d connection change\n", i + 1);
 			usb_hub_port_connect_change(dev, i);
 		}
 		if (portchange & USB_PORT_STAT_C_ENABLE) {
-			USB_HUB_PRINTF("port %d enable change, status %x\n",
-					i + 1, portstatus);
+			debug("port %d enable change, status %x\n",
+			      i + 1, portstatus);
 			usb_clear_port_feature(dev, i + 1,
 						USB_PORT_FEAT_C_ENABLE);
 
@@ -448,27 +492,27 @@
 			if (!(portstatus & USB_PORT_STAT_ENABLE) &&
 			     (portstatus & USB_PORT_STAT_CONNECTION) &&
 			     ((dev->children[i]))) {
-				USB_HUB_PRINTF("already running port %i "  \
-						"disabled by hub (EMI?), " \
-						"re-enabling...\n", i + 1);
-					usb_hub_port_connect_change(dev, i);
+				debug("already running port %i "  \
+				      "disabled by hub (EMI?), " \
+				      "re-enabling...\n", i + 1);
+				      usb_hub_port_connect_change(dev, i);
 			}
 		}
 		if (portstatus & USB_PORT_STAT_SUSPEND) {
-			USB_HUB_PRINTF("port %d suspend change\n", i + 1);
+			debug("port %d suspend change\n", i + 1);
 			usb_clear_port_feature(dev, i + 1,
 						USB_PORT_FEAT_SUSPEND);
 		}
 
 		if (portchange & USB_PORT_STAT_C_OVERCURRENT) {
-			USB_HUB_PRINTF("port %d over-current change\n", i + 1);
+			debug("port %d over-current change\n", i + 1);
 			usb_clear_port_feature(dev, i + 1,
 						USB_PORT_FEAT_C_OVER_CURRENT);
 			usb_hub_power_on(hub);
 		}
 
 		if (portchange & USB_PORT_STAT_C_RESET) {
-			USB_HUB_PRINTF("port %d reset change\n", i + 1);
+			debug("port %d reset change\n", i + 1);
 			usb_clear_port_feature(dev, i + 1,
 						USB_PORT_FEAT_C_RESET);
 		}
@@ -503,7 +547,7 @@
 	if ((ep->bmAttributes & 3) != 3)
 		return 0;
 	/* We found a hub */
-	USB_HUB_PRINTF("USB hub found\n");
+	debug("USB hub found\n");
 	ret = usb_hub_configure(dev);
 	return ret;
 }
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 4efbcfe..b962849 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -31,12 +31,6 @@
 
 #include <usb.h>
 
-#ifdef	USB_KBD_DEBUG
-#define USB_KBD_PRINTF(fmt, args...)	printf(fmt, ##args)
-#else
-#define USB_KBD_PRINTF(fmt, args...)
-#endif
-
 /*
  * If overwrite_console returns 1, the stdin, stderr and stdout
  * are switched to the serial port, else the settings in the
@@ -262,7 +256,7 @@
 
 	/* Report keycode if any */
 	if (keycode) {
-		USB_KBD_PRINTF("%c", keycode);
+		debug("%c", keycode);
 		usb_kbd_put_queue(data, keycode);
 	}
 
@@ -324,8 +318,8 @@
 static int usb_kbd_irq(struct usb_device *dev)
 {
 	if ((dev->irq_status != 0) || (dev->irq_act_len != 8)) {
-		USB_KBD_PRINTF("USB KBD: Error %lX, len %d\n",
-				dev->irq_status, dev->irq_act_len);
+		debug("USB KBD: Error %lX, len %d\n",
+		      dev->irq_status, dev->irq_act_len);
 		return 1;
 	}
 
@@ -437,7 +431,7 @@
 	if ((ep->bmAttributes & 3) != 3)
 		return 0;
 
-	USB_KBD_PRINTF("USB KBD: found set protocol...\n");
+	debug("USB KBD: found set protocol...\n");
 
 	data = malloc(sizeof(struct usb_kbd_pdata));
 	if (!data) {
@@ -463,10 +457,10 @@
 	/* We found a USB Keyboard, install it. */
 	usb_set_protocol(dev, iface->desc.bInterfaceNumber, 0);
 
-	USB_KBD_PRINTF("USB KBD: found set idle...\n");
+	debug("USB KBD: found set idle...\n");
 	usb_set_idle(dev, iface->desc.bInterfaceNumber, REPEAT_RATE, 0);
 
-	USB_KBD_PRINTF("USB KBD: enable interrupt pipe...\n");
+	debug("USB KBD: enable interrupt pipe...\n");
 	usb_submit_int_msg(dev, pipe, data->new, maxp > 8 ? 8 : maxp,
 				ep->bInterval);
 
@@ -497,16 +491,16 @@
 			continue;
 
 		/* We found a keyboard, check if it is already registered. */
-		USB_KBD_PRINTF("USB KBD: found set up device.\n");
+		debug("USB KBD: found set up device.\n");
 		old_dev = stdio_get_by_name(DEVNAME);
 		if (old_dev) {
 			/* Already registered, just return ok. */
-			USB_KBD_PRINTF("USB KBD: is already registered.\n");
+			debug("USB KBD: is already registered.\n");
 			return 1;
 		}
 
 		/* Register the keyboard */
-		USB_KBD_PRINTF("USB KBD: register.\n");
+		debug("USB KBD: register.\n");
 		memset(&usb_kbd_dev, 0, sizeof(struct stdio_dev));
 		strcpy(usb_kbd_dev.name, DEVNAME);
 		usb_kbd_dev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
diff --git a/common/usb_storage.c b/common/usb_storage.c
index c5db044..457970f 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -59,14 +59,6 @@
 #undef BBB_COMDAT_TRACE
 #undef BBB_XPORT_TRACE
 
-#ifdef	USB_STOR_DEBUG
-#define USB_BLK_DEBUG	1
-#else
-#define USB_BLK_DEBUG	0
-#endif
-
-#define USB_STOR_PRINTF(fmt, args...)	debug_cond(USB_BLK_DEBUG, fmt, ##args)
-
 #include <scsi.h>
 /* direction table -- this indicates the direction of the data
  * transfer for each command code -- a 1 indicates input
@@ -228,8 +220,7 @@
 			      0, us->ifnum,
 			      result, sizeof(char),
 			      USB_CNTL_TIMEOUT * 5);
-	USB_STOR_PRINTF("Get Max LUN -> len = %i, result = %i\n",
-			len, (int) *result);
+	debug("Get Max LUN -> len = %i, result = %i\n", len, (int) *result);
 	return (len > 0) ? *result : 0;
 }
 
@@ -262,7 +253,7 @@
 	usb_max_devs = 0;
 	for (i = 0; i < USB_MAX_DEVICE; i++) {
 		dev = usb_get_dev_index(i); /* get device */
-		USB_STOR_PRINTF("i=%d\n", i);
+		debug("i=%d\n", i);
 		if (dev == NULL)
 			break; /* no more devices available */
 
@@ -278,9 +269,9 @@
 			     lun++) {
 				usb_dev_desc[usb_max_devs].lun = lun;
 				if (usb_stor_get_info(dev, &usb_stor[start],
-						      &usb_dev_desc[usb_max_devs]) == 1) {
-				usb_max_devs++;
-		}
+				    &usb_dev_desc[usb_max_devs]) == 1) {
+					usb_max_devs++;
+				}
 			}
 		}
 		/* if storage device */
@@ -309,7 +300,7 @@
 }
 
 
-#ifdef	USB_STOR_DEBUG
+#ifdef	DEBUG
 
 static void usb_show_srb(ccb *pccb)
 {
@@ -361,45 +352,49 @@
 		/* set up the transfer loop */
 		do {
 			/* transfer the data */
-			USB_STOR_PRINTF("Bulk xfer 0x%x(%d) try #%d\n",
-				  (unsigned int)buf, this_xfer, 11 - maxtry);
+			debug("Bulk xfer 0x%x(%d) try #%d\n",
+			      (unsigned int)buf, this_xfer, 11 - maxtry);
 			result = usb_bulk_msg(us->pusb_dev, pipe, buf,
 					      this_xfer, &partial,
 					      USB_CNTL_TIMEOUT * 5);
-			USB_STOR_PRINTF("bulk_msg returned %d xferred %d/%d\n",
-				  result, partial, this_xfer);
+			debug("bulk_msg returned %d xferred %d/%d\n",
+			      result, partial, this_xfer);
 			if (us->pusb_dev->status != 0) {
 				/* if we stall, we need to clear it before
 				 * we go on
 				 */
-#ifdef USB_STOR_DEBUG
+#ifdef DEBUG
 				display_int_status(us->pusb_dev->status);
 #endif
 				if (us->pusb_dev->status & USB_ST_STALLED) {
-					USB_STOR_PRINTF("stalled ->clearing endpoint halt for pipe 0x%x\n", pipe);
+					debug("stalled ->clearing endpoint" \
+					      "halt for pipe 0x%x\n", pipe);
 					stat = us->pusb_dev->status;
 					usb_clear_halt(us->pusb_dev, pipe);
 					us->pusb_dev->status = stat;
 					if (this_xfer == partial) {
-						USB_STOR_PRINTF("bulk transferred with error %lX, but data ok\n", us->pusb_dev->status);
+						debug("bulk transferred" \
+						      "with error %lX," \
+						      " but data ok\n",
+						      us->pusb_dev->status);
 						return 0;
 					}
 					else
 						return result;
 				}
 				if (us->pusb_dev->status & USB_ST_NAK_REC) {
-					USB_STOR_PRINTF("Device NAKed bulk_msg\n");
+					debug("Device NAKed bulk_msg\n");
 					return result;
 				}
-				USB_STOR_PRINTF("bulk transferred with error");
+				debug("bulk transferred with error");
 				if (this_xfer == partial) {
-					USB_STOR_PRINTF(" %ld, but data ok\n",
-							us->pusb_dev->status);
+					debug(" %ld, but data ok\n",
+					      us->pusb_dev->status);
 					return 0;
 				}
 				/* if our try counter reaches 0, bail out */
-					USB_STOR_PRINTF(" %ld, data %d\n",
-						us->pusb_dev->status, partial);
+					debug(" %ld, data %d\n",
+					      us->pusb_dev->status, partial);
 				if (!maxtry--)
 						return result;
 			}
@@ -433,35 +428,34 @@
 	 *
 	 * This comment stolen from FreeBSD's /sys/dev/usb/umass.c.
 	 */
-	USB_STOR_PRINTF("BBB_reset\n");
+	debug("BBB_reset\n");
 	result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0),
 				 US_BBB_RESET,
 				 USB_TYPE_CLASS | USB_RECIP_INTERFACE,
 				 0, us->ifnum, NULL, 0, USB_CNTL_TIMEOUT * 5);
 
 	if ((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) {
-		USB_STOR_PRINTF("RESET:stall\n");
+		debug("RESET:stall\n");
 		return -1;
 	}
 
 	/* long wait for reset */
 	mdelay(150);
-	USB_STOR_PRINTF("BBB_reset result %d: status %lX reset\n", result,
-			us->pusb_dev->status);
+	debug("BBB_reset result %d: status %lX reset\n",
+	      result, us->pusb_dev->status);
 	pipe = usb_rcvbulkpipe(us->pusb_dev, us->ep_in);
 	result = usb_clear_halt(us->pusb_dev, pipe);
 	/* long wait for reset */
 	mdelay(150);
-	USB_STOR_PRINTF("BBB_reset result %d: status %lX clearing IN endpoint\n",
-			result, us->pusb_dev->status);
+	debug("BBB_reset result %d: status %lX clearing IN endpoint\n",
+	      result, us->pusb_dev->status);
 	/* long wait for reset */
 	pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
 	result = usb_clear_halt(us->pusb_dev, pipe);
 	mdelay(150);
-	USB_STOR_PRINTF("BBB_reset result %d: status %lX"
-			" clearing OUT endpoint\n", result,
-			us->pusb_dev->status);
-	USB_STOR_PRINTF("BBB_reset done\n");
+	debug("BBB_reset result %d: status %lX clearing OUT endpoint\n",
+	      result, us->pusb_dev->status);
+	debug("BBB_reset done\n");
 	return 0;
 }
 
@@ -474,7 +468,7 @@
 	unsigned char cmd[12];
 	int result;
 
-	USB_STOR_PRINTF("CB_reset\n");
+	debug("CB_reset\n");
 	memset(cmd, 0xff, sizeof(cmd));
 	cmd[0] = SCSI_SEND_DIAG;
 	cmd[1] = 4;
@@ -486,13 +480,12 @@
 
 	/* long wait for reset */
 	mdelay(1500);
-	USB_STOR_PRINTF("CB_reset result %d: status %lX"
-			" clearing endpoint halt\n", result,
-			us->pusb_dev->status);
+	debug("CB_reset result %d: status %lX clearing endpoint halt\n",
+	      result, us->pusb_dev->status);
 	usb_clear_halt(us->pusb_dev, usb_rcvbulkpipe(us->pusb_dev, us->ep_in));
 	usb_clear_halt(us->pusb_dev, usb_rcvbulkpipe(us->pusb_dev, us->ep_out));
 
-	USB_STOR_PRINTF("CB_reset done\n");
+	debug("CB_reset done\n");
 	return 0;
 }
 
@@ -511,7 +504,7 @@
 	dir_in = US_DIRECTION(srb->cmd[0]);
 
 #ifdef BBB_COMDAT_TRACE
-	printf("dir %d lun %d cmdlen %d cmd %p datalen %d pdata %p\n",
+	printf("dir %d lun %d cmdlen %d cmd %p datalen %lu pdata %p\n",
 		dir_in, srb->lun, srb->cmdlen, srb->cmd, srb->datalen,
 		srb->pdata);
 	if (srb->cmdlen) {
@@ -522,7 +515,7 @@
 #endif
 	/* sanity checks */
 	if (!(srb->cmdlen <= CBWCDBLENGTH)) {
-		USB_STOR_PRINTF("usb_stor_BBB_comdat:cmdlen too large\n");
+		debug("usb_stor_BBB_comdat:cmdlen too large\n");
 		return -1;
 	}
 
@@ -541,7 +534,7 @@
 	result = usb_bulk_msg(us->pusb_dev, pipe, cbw, UMASS_BBB_CBW_SIZE,
 			      &actlen, USB_CNTL_TIMEOUT * 5);
 	if (result < 0)
-		USB_STOR_PRINTF("usb_stor_BBB_comdat:usb_bulk_msg error\n");
+		debug("usb_stor_BBB_comdat:usb_bulk_msg error\n");
 	return result;
 }
 
@@ -564,8 +557,8 @@
 		pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
 
 	while (retry--) {
-		USB_STOR_PRINTF("CBI gets a command: Try %d\n", 5 - retry);
-#ifdef USB_STOR_DEBUG
+		debug("CBI gets a command: Try %d\n", 5 - retry);
+#ifdef DEBUG
 		usb_show_srb(srb);
 #endif
 		/* let's send the command via the control pipe */
@@ -576,35 +569,35 @@
 					 0, us->ifnum,
 					 srb->cmd, srb->cmdlen,
 					 USB_CNTL_TIMEOUT * 5);
-		USB_STOR_PRINTF("CB_transport: control msg returned %d,"
-				" status %lX\n", result, us->pusb_dev->status);
+		debug("CB_transport: control msg returned %d, status %lX\n",
+		      result, us->pusb_dev->status);
 		/* check the return code for the command */
 		if (result < 0) {
 			if (us->pusb_dev->status & USB_ST_STALLED) {
 				status = us->pusb_dev->status;
-				USB_STOR_PRINTF(" stall during command found,"
-						" clear pipe\n");
+				debug(" stall during command found," \
+				      " clear pipe\n");
 				usb_clear_halt(us->pusb_dev,
 					      usb_sndctrlpipe(us->pusb_dev, 0));
 				us->pusb_dev->status = status;
 			}
-			USB_STOR_PRINTF(" error during command %02X"
-					" Stat = %lX\n", srb->cmd[0],
-					us->pusb_dev->status);
+			debug(" error during command %02X" \
+			      " Stat = %lX\n", srb->cmd[0],
+			      us->pusb_dev->status);
 			return result;
 		}
 		/* transfer the data payload for this command, if one exists*/
 
-		USB_STOR_PRINTF("CB_transport: control msg returned %d,"
-				" direction is %s to go 0x%lx\n", result,
-				dir_in ? "IN" : "OUT", srb->datalen);
+		debug("CB_transport: control msg returned %d," \
+		      " direction is %s to go 0x%lx\n", result,
+		      dir_in ? "IN" : "OUT", srb->datalen);
 		if (srb->datalen) {
 			result = us_one_transfer(us, pipe, (char *)srb->pdata,
 						 srb->datalen);
-			USB_STOR_PRINTF("CBI attempted to transfer data,"
-					" result is %d status %lX, len %d\n",
-					result, us->pusb_dev->status,
-					us->pusb_dev->act_len);
+			debug("CBI attempted to transfer data," \
+			      " result is %d status %lX, len %d\n",
+			      result, us->pusb_dev->status,
+				us->pusb_dev->act_len);
 			if (!(us->pusb_dev->status & USB_ST_NAK_REC))
 				break;
 		} /* if (srb->datalen) */
@@ -635,10 +628,9 @@
 		us->ip_wanted = 0;
 		return USB_STOR_TRANSPORT_ERROR;
 	}
-	USB_STOR_PRINTF
-		("Got interrupt data 0x%x, transfered %d status 0x%lX\n",
-		 us->ip_data, us->pusb_dev->irq_act_len,
-		 us->pusb_dev->irq_status);
+	debug("Got interrupt data 0x%x, transfered %d status 0x%lX\n",
+	      us->ip_data, us->pusb_dev->irq_act_len,
+	      us->pusb_dev->irq_status);
 	/* UFI gives us ASC and ASCQ, like a request sense */
 	if (us->subclass == US_SC_UFI) {
 		if (srb->cmd[0] == SCSI_REQ_SENSE ||
@@ -691,11 +683,11 @@
 	dir_in = US_DIRECTION(srb->cmd[0]);
 
 	/* COMMAND phase */
-	USB_STOR_PRINTF("COMMAND phase\n");
+	debug("COMMAND phase\n");
 	result = usb_stor_BBB_comdat(srb, us);
 	if (result < 0) {
-		USB_STOR_PRINTF("failed to send CBW status %ld\n",
-			us->pusb_dev->status);
+		debug("failed to send CBW status %ld\n",
+		      us->pusb_dev->status);
 		usb_stor_BBB_reset(us);
 		return USB_STOR_TRANSPORT_FAILED;
 	}
@@ -708,7 +700,7 @@
 	/* no data, go immediately to the STATUS phase */
 	if (srb->datalen == 0)
 		goto st;
-	USB_STOR_PRINTF("DATA phase\n");
+	debug("DATA phase\n");
 	if (dir_in)
 		pipe = pipein;
 	else
@@ -717,7 +709,7 @@
 			      &data_actlen, USB_CNTL_TIMEOUT * 5);
 	/* special handling of STALL in DATA phase */
 	if ((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) {
-		USB_STOR_PRINTF("DATA:stall\n");
+		debug("DATA:stall\n");
 		/* clear the STALL on the endpoint */
 		result = usb_stor_BBB_clear_endpt_stall(us,
 					dir_in ? us->ep_in : us->ep_out);
@@ -726,8 +718,8 @@
 			goto st;
 	}
 	if (result < 0) {
-		USB_STOR_PRINTF("usb_bulk_msg error status %ld\n",
-			us->pusb_dev->status);
+		debug("usb_bulk_msg error status %ld\n",
+		      us->pusb_dev->status);
 		usb_stor_BBB_reset(us);
 		return USB_STOR_TRANSPORT_FAILED;
 	}
@@ -740,14 +732,14 @@
 st:
 	retry = 0;
 again:
-	USB_STOR_PRINTF("STATUS phase\n");
+	debug("STATUS phase\n");
 	result = usb_bulk_msg(us->pusb_dev, pipein, csw, UMASS_BBB_CSW_SIZE,
 				&actlen, USB_CNTL_TIMEOUT*5);
 
 	/* special handling of STALL in STATUS phase */
 	if ((result < 0) && (retry < 1) &&
 	    (us->pusb_dev->status & USB_ST_STALLED)) {
-		USB_STOR_PRINTF("STATUS:stall\n");
+		debug("STATUS:stall\n");
 		/* clear the STALL on the endpoint */
 		result = usb_stor_BBB_clear_endpt_stall(us, us->ep_in);
 		if (result >= 0 && (retry++ < 1))
@@ -755,8 +747,8 @@
 			goto again;
 	}
 	if (result < 0) {
-		USB_STOR_PRINTF("usb_bulk_msg error status %ld\n",
-			us->pusb_dev->status);
+		debug("usb_bulk_msg error status %ld\n",
+		      us->pusb_dev->status);
 		usb_stor_BBB_reset(us);
 		return USB_STOR_TRANSPORT_FAILED;
 	}
@@ -771,27 +763,27 @@
 	if (pipe == 0 && srb->datalen != 0 && srb->datalen - data_actlen != 0)
 		pipe = srb->datalen - data_actlen;
 	if (CSWSIGNATURE != le32_to_cpu(csw->dCSWSignature)) {
-		USB_STOR_PRINTF("!CSWSIGNATURE\n");
+		debug("!CSWSIGNATURE\n");
 		usb_stor_BBB_reset(us);
 		return USB_STOR_TRANSPORT_FAILED;
 	} else if ((CBWTag - 1) != le32_to_cpu(csw->dCSWTag)) {
-		USB_STOR_PRINTF("!Tag\n");
+		debug("!Tag\n");
 		usb_stor_BBB_reset(us);
 		return USB_STOR_TRANSPORT_FAILED;
 	} else if (csw->bCSWStatus > CSWSTATUS_PHASE) {
-		USB_STOR_PRINTF(">PHASE\n");
+		debug(">PHASE\n");
 		usb_stor_BBB_reset(us);
 		return USB_STOR_TRANSPORT_FAILED;
 	} else if (csw->bCSWStatus == CSWSTATUS_PHASE) {
-		USB_STOR_PRINTF("=PHASE\n");
+		debug("=PHASE\n");
 		usb_stor_BBB_reset(us);
 		return USB_STOR_TRANSPORT_FAILED;
 	} else if (data_actlen > srb->datalen) {
-		USB_STOR_PRINTF("transferred %dB instead of %ldB\n",
-			data_actlen, srb->datalen);
+		debug("transferred %dB instead of %ldB\n",
+		      data_actlen, srb->datalen);
 		return USB_STOR_TRANSPORT_FAILED;
 	} else if (csw->bCSWStatus == CSWSTATUS_FAILED) {
-		USB_STOR_PRINTF("FAILED\n");
+		debug("FAILED\n");
 		return USB_STOR_TRANSPORT_FAILED;
 	}
 
@@ -812,14 +804,14 @@
 	/* issue the command */
 do_retry:
 	result = usb_stor_CB_comdat(srb, us);
-	USB_STOR_PRINTF("command / Data returned %d, status %lX\n",
-			result, us->pusb_dev->status);
+	debug("command / Data returned %d, status %lX\n",
+	      result, us->pusb_dev->status);
 	/* if this is an CBI Protocol, get IRQ */
 	if (us->protocol == US_PR_CBI) {
 		status = usb_stor_CBI_get_status(srb, us);
 		/* if the status is error, report it */
 		if (status == USB_STOR_TRANSPORT_ERROR) {
-			USB_STOR_PRINTF(" USB CBI Command Error\n");
+			debug(" USB CBI Command Error\n");
 			return status;
 		}
 		srb->sense_buf[12] = (unsigned char)(us->ip_data >> 8);
@@ -827,7 +819,7 @@
 		if (!us->ip_data) {
 			/* if the status is good, report it */
 			if (status == USB_STOR_TRANSPORT_GOOD) {
-				USB_STOR_PRINTF(" USB CBI Command Good\n");
+				debug(" USB CBI Command Good\n");
 				return status;
 			}
 		}
@@ -835,7 +827,7 @@
 	/* do we have to issue an auto request? */
 	/* HERE we have to check the result */
 	if ((result < 0) && !(us->pusb_dev->status & USB_ST_STALLED)) {
-		USB_STOR_PRINTF("ERROR %lX\n", us->pusb_dev->status);
+		debug("ERROR %lX\n", us->pusb_dev->status);
 		us->transport_reset(us);
 		return USB_STOR_TRANSPORT_ERROR;
 	}
@@ -843,7 +835,7 @@
 	    ((srb->cmd[0] == SCSI_REQ_SENSE) ||
 	    (srb->cmd[0] == SCSI_INQUIRY))) {
 		/* do not issue an autorequest after request sense */
-		USB_STOR_PRINTF("No auto request and good\n");
+		debug("No auto request and good\n");
 		return USB_STOR_TRANSPORT_GOOD;
 	}
 	/* issue an request_sense */
@@ -856,19 +848,19 @@
 	psrb->cmdlen = 12;
 	/* issue the command */
 	result = usb_stor_CB_comdat(psrb, us);
-	USB_STOR_PRINTF("auto request returned %d\n", result);
+	debug("auto request returned %d\n", result);
 	/* if this is an CBI Protocol, get IRQ */
 	if (us->protocol == US_PR_CBI)
 		status = usb_stor_CBI_get_status(psrb, us);
 
 	if ((result < 0) && !(us->pusb_dev->status & USB_ST_STALLED)) {
-		USB_STOR_PRINTF(" AUTO REQUEST ERROR %ld\n",
-				us->pusb_dev->status);
+		debug(" AUTO REQUEST ERROR %ld\n",
+		      us->pusb_dev->status);
 		return USB_STOR_TRANSPORT_ERROR;
 	}
-	USB_STOR_PRINTF("autorequest returned 0x%02X 0x%02X 0x%02X 0x%02X\n",
-			srb->sense_buf[0], srb->sense_buf[2],
-			srb->sense_buf[12], srb->sense_buf[13]);
+	debug("autorequest returned 0x%02X 0x%02X 0x%02X 0x%02X\n",
+	      srb->sense_buf[0], srb->sense_buf[2],
+	      srb->sense_buf[12], srb->sense_buf[13]);
 	/* Check the auto request result */
 	if ((srb->sense_buf[2] == 0) &&
 	    (srb->sense_buf[12] == 0) &&
@@ -923,7 +915,7 @@
 		srb->datalen = 36;
 		srb->cmdlen = 12;
 		i = ss->transport(srb, ss);
-		USB_STOR_PRINTF("inquiry returns %d\n", i);
+		debug("inquiry returns %d\n", i);
 		if (i == 0)
 			break;
 	} while (--retry);
@@ -948,9 +940,9 @@
 	srb->pdata = &srb->sense_buf[0];
 	srb->cmdlen = 12;
 	ss->transport(srb, ss);
-	USB_STOR_PRINTF("Request Sense returned %02X %02X %02X\n",
-			srb->sense_buf[2], srb->sense_buf[12],
-			srb->sense_buf[13]);
+	debug("Request Sense returned %02X %02X %02X\n",
+	      srb->sense_buf[2], srb->sense_buf[12],
+	      srb->sense_buf[13]);
 	srb->pdata = (uchar *)ptr;
 	return 0;
 }
@@ -1017,7 +1009,7 @@
 	srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff;
 	srb->cmd[8] = (unsigned char) blocks & 0xff;
 	srb->cmdlen = 12;
-	USB_STOR_PRINTF("read10: start %lx blocks %x\n", start, blocks);
+	debug("read10: start %lx blocks %x\n", start, blocks);
 	return ss->transport(srb, ss);
 }
 
@@ -1034,7 +1026,7 @@
 	srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff;
 	srb->cmd[8] = (unsigned char) blocks & 0xff;
 	srb->cmdlen = 12;
-	USB_STOR_PRINTF("write10: start %lx blocks %x\n", start, blocks);
+	debug("write10: start %lx blocks %x\n", start, blocks);
 	return ss->transport(srb, ss);
 }
 
@@ -1078,7 +1070,7 @@
 
 	device &= 0xff;
 	/* Setup  device */
-	USB_STOR_PRINTF("\nusb_read: dev %d \n", device);
+	debug("\nusb_read: dev %d \n", device);
 	dev = NULL;
 	for (i = 0; i < USB_MAX_DEVICE; i++) {
 		dev = usb_get_dev_index(i);
@@ -1095,8 +1087,8 @@
 	start = blknr;
 	blks = blkcnt;
 
-	USB_STOR_PRINTF("\nusb_read: dev %d startblk " LBAF ", blccnt " LBAF
-			" buffer %lx\n", device, start, blks, buf_addr);
+	debug("\nusb_read: dev %d startblk " LBAF ", blccnt " LBAF
+	      " buffer %lx\n", device, start, blks, buf_addr);
 
 	do {
 		/* XXX need some comment here */
@@ -1112,7 +1104,7 @@
 		srb->datalen = usb_dev_desc[device].blksz * smallblks;
 		srb->pdata = (unsigned char *)buf_addr;
 		if (usb_read_10(srb, ss, start, smallblks)) {
-			USB_STOR_PRINTF("Read ERROR\n");
+			debug("Read ERROR\n");
 			usb_request_sense(srb, ss);
 			if (retry--)
 				goto retry_it;
@@ -1125,9 +1117,9 @@
 	} while (blks != 0);
 	ss->flags &= ~USB_READY;
 
-	USB_STOR_PRINTF("usb_read: end startblk " LBAF
-			", blccnt %x buffer %lx\n",
-			start, smallblks, buf_addr);
+	debug("usb_read: end startblk " LBAF
+	      ", blccnt %x buffer %lx\n",
+	      start, smallblks, buf_addr);
 
 	usb_disable_asynch(0); /* asynch transfer allowed */
 	if (blkcnt >= USB_MAX_XFER_BLK)
@@ -1151,7 +1143,7 @@
 
 	device &= 0xff;
 	/* Setup  device */
-	USB_STOR_PRINTF("\nusb_write: dev %d \n", device);
+	debug("\nusb_write: dev %d \n", device);
 	dev = NULL;
 	for (i = 0; i < USB_MAX_DEVICE; i++) {
 		dev = usb_get_dev_index(i);
@@ -1169,8 +1161,8 @@
 	start = blknr;
 	blks = blkcnt;
 
-	USB_STOR_PRINTF("\nusb_write: dev %d startblk " LBAF ", blccnt " LBAF
-			" buffer %lx\n", device, start, blks, buf_addr);
+	debug("\nusb_write: dev %d startblk " LBAF ", blccnt " LBAF
+	      " buffer %lx\n", device, start, blks, buf_addr);
 
 	do {
 		/* If write fails retry for max retry count else
@@ -1188,7 +1180,7 @@
 		srb->datalen = usb_dev_desc[device].blksz * smallblks;
 		srb->pdata = (unsigned char *)buf_addr;
 		if (usb_write_10(srb, ss, start, smallblks)) {
-			USB_STOR_PRINTF("Write ERROR\n");
+			debug("Write ERROR\n");
 			usb_request_sense(srb, ss);
 			if (retry--)
 				goto retry_it;
@@ -1201,9 +1193,8 @@
 	} while (blks != 0);
 	ss->flags &= ~USB_READY;
 
-	USB_STOR_PRINTF("usb_write: end startblk " LBAF
-			", blccnt %x buffer %lx\n",
-			start, smallblks, buf_addr);
+	debug("usb_write: end startblk " LBAF ", blccnt %x buffer %lx\n",
+	      start, smallblks, buf_addr);
 
 	usb_disable_asynch(0); /* asynch transfer allowed */
 	if (blkcnt >= USB_MAX_XFER_BLK)
@@ -1218,6 +1209,7 @@
 {
 	struct usb_interface *iface;
 	int i;
+	struct usb_endpoint_descriptor *ep_desc;
 	unsigned int flags = 0;
 
 	int protocol = 0;
@@ -1228,12 +1220,12 @@
 
 #if 0
 	/* this is the place to patch some storage devices */
-	USB_STOR_PRINTF("iVendor %X iProduct %X\n", dev->descriptor.idVendor,
+	debug("iVendor %X iProduct %X\n", dev->descriptor.idVendor,
 			dev->descriptor.idProduct);
 
 	if ((dev->descriptor.idVendor) == 0x066b &&
 	    (dev->descriptor.idProduct) == 0x0103) {
-		USB_STOR_PRINTF("patched for E-USB\n");
+		debug("patched for E-USB\n");
 		protocol = US_PR_CB;
 		subclass = US_SC_UFI;	    /* an assumption */
 	}
@@ -1250,7 +1242,7 @@
 	memset(ss, 0, sizeof(struct us_data));
 
 	/* At this point, we know we've got a live one */
-	USB_STOR_PRINTF("\n\nUSB Mass Storage device detected\n");
+	debug("\n\nUSB Mass Storage device detected\n");
 
 	/* Initialize the us_data structure with some useful info */
 	ss->flags = flags;
@@ -1270,21 +1262,21 @@
 	}
 
 	/* set the handler pointers based on the protocol */
-	USB_STOR_PRINTF("Transport: ");
+	debug("Transport: ");
 	switch (ss->protocol) {
 	case US_PR_CB:
-		USB_STOR_PRINTF("Control/Bulk\n");
+		debug("Control/Bulk\n");
 		ss->transport = usb_stor_CB_transport;
 		ss->transport_reset = usb_stor_CB_reset;
 		break;
 
 	case US_PR_CBI:
-		USB_STOR_PRINTF("Control/Bulk/Interrupt\n");
+		debug("Control/Bulk/Interrupt\n");
 		ss->transport = usb_stor_CB_transport;
 		ss->transport_reset = usb_stor_CB_reset;
 		break;
 	case US_PR_BULK:
-		USB_STOR_PRINTF("Bulk/Bulk/Bulk\n");
+		debug("Bulk/Bulk/Bulk\n");
 		ss->transport = usb_stor_BBB_transport;
 		ss->transport_reset = usb_stor_BBB_reset;
 		break;
@@ -1300,34 +1292,35 @@
 	 * We will ignore any others.
 	 */
 	for (i = 0; i < iface->desc.bNumEndpoints; i++) {
+		ep_desc = &iface->ep_desc[i];
 		/* is it an BULK endpoint? */
-		if ((iface->ep_desc[i].bmAttributes &
+		if ((ep_desc->bmAttributes &
 		     USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
-			if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
-				ss->ep_in = iface->ep_desc[i].bEndpointAddress &
-					USB_ENDPOINT_NUMBER_MASK;
+			if (ep_desc->bEndpointAddress & USB_DIR_IN)
+				ss->ep_in = ep_desc->bEndpointAddress &
+						USB_ENDPOINT_NUMBER_MASK;
 			else
 				ss->ep_out =
-					iface->ep_desc[i].bEndpointAddress &
+					ep_desc->bEndpointAddress &
 					USB_ENDPOINT_NUMBER_MASK;
 		}
 
 		/* is it an interrupt endpoint? */
-		if ((iface->ep_desc[i].bmAttributes &
-		    USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
-			ss->ep_int = iface->ep_desc[i].bEndpointAddress &
-				USB_ENDPOINT_NUMBER_MASK;
-			ss->irqinterval = iface->ep_desc[i].bInterval;
+		if ((ep_desc->bmAttributes &
+		     USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
+			ss->ep_int = ep_desc->bEndpointAddress &
+						USB_ENDPOINT_NUMBER_MASK;
+			ss->irqinterval = ep_desc->bInterval;
 		}
 	}
-	USB_STOR_PRINTF("Endpoints In %d Out %d Int %d\n",
-		  ss->ep_in, ss->ep_out, ss->ep_int);
+	debug("Endpoints In %d Out %d Int %d\n",
+	      ss->ep_in, ss->ep_out, ss->ep_int);
 
 	/* Do some basic sanity checks, and bail if we find a problem */
 	if (usb_set_interface(dev, iface->desc.bInterfaceNumber, 0) ||
 	    !ss->ep_in || !ss->ep_out ||
 	    (ss->protocol == US_PR_CBI && ss->ep_int == 0)) {
-		USB_STOR_PRINTF("Problems with device\n");
+		debug("Problems with device\n");
 		return 0;
 	}
 	/* set class specific stuff */
@@ -1366,7 +1359,7 @@
 
 	dev_desc->target = dev->devnum;
 	pccb->lun = dev_desc->lun;
-	USB_STOR_PRINTF(" address %d\n", dev_desc->target);
+	debug(" address %d\n", dev_desc->target);
 
 	if (usb_inquiry(pccb, ss))
 		return -1;
@@ -1392,8 +1385,8 @@
 	usb_bin_fixup(dev->descriptor, (uchar *)dev_desc->vendor,
 		      (uchar *)dev_desc->product);
 #endif /* CONFIG_USB_BIN_FIXUP */
-	USB_STOR_PRINTF("ISO Vers %X, Response Data %X\n", usb_stor_buf[2],
-			usb_stor_buf[3]);
+	debug("ISO Vers %X, Response Data %X\n", usb_stor_buf[2],
+	      usb_stor_buf[3]);
 	if (usb_test_unit_ready(pccb, ss)) {
 		printf("Device NOT ready\n"
 		       "   Request Sense returned %02X %02X %02X\n",
@@ -1413,8 +1406,7 @@
 		cap[1] = 0x200;
 	}
 	ss->flags &= ~USB_READY;
-	USB_STOR_PRINTF("Read Capacity returns: 0x%lx, 0x%lx\n", cap[0],
-			cap[1]);
+	debug("Read Capacity returns: 0x%lx, 0x%lx\n", cap[0], cap[1]);
 #if 0
 	if (cap[0] > (0x200000 * 10)) /* greater than 10 GByte */
 		cap[0] >>= 16;
@@ -1426,17 +1418,16 @@
 	cap[0] += 1;
 	capacity = &cap[0];
 	blksz = &cap[1];
-	USB_STOR_PRINTF("Capacity = 0x%lx, blocksz = 0x%lx\n",
-			*capacity, *blksz);
+	debug("Capacity = 0x%lx, blocksz = 0x%lx\n", *capacity, *blksz);
 	dev_desc->lba = *capacity;
 	dev_desc->blksz = *blksz;
 	dev_desc->log2blksz = LOG2(dev_desc->blksz);
 	dev_desc->type = perq;
-	USB_STOR_PRINTF(" address %d\n", dev_desc->target);
-	USB_STOR_PRINTF("partype: %d\n", dev_desc->part_type);
+	debug(" address %d\n", dev_desc->target);
+	debug("partype: %d\n", dev_desc->part_type);
 
 	init_part(dev_desc);
 
-	USB_STOR_PRINTF("partype: %d\n", dev_desc->part_type);
+	debug("partype: %d\n", dev_desc->part_type);
 	return 1;
 }
diff --git a/config.mk b/config.mk
index b427a4e..ddf350e 100644
--- a/config.mk
+++ b/config.mk
@@ -250,11 +250,10 @@
 CPPFLAGS += -fno-builtin -ffreestanding -nostdinc	\
 	-isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS)
 
-ifdef BUILD_TAG
-CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \
-	-DBUILD_TAG='"$(BUILD_TAG)"'
-else
 CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes
+
+ifdef BUILD_TAG
+CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"'
 endif
 
 CFLAGS_SSP := $(call cc-option,-fno-stack-protector)
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 5986589..fb5e9f0 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -372,7 +372,7 @@
 	u32 offset = (u32)le32_to_cpu(gpt_h->first_usable_lba);
 	ulong start;
 	int i, k;
-	size_t name_len;
+	size_t efiname_len, dosname_len;
 #ifdef CONFIG_PARTITION_UUIDS
 	char *str_uuid;
 #endif
@@ -420,9 +420,14 @@
 		       sizeof(gpt_entry_attributes));
 
 		/* partition name */
-		name_len = sizeof(gpt_e[i].partition_name)
+		efiname_len = sizeof(gpt_e[i].partition_name)
 			/ sizeof(efi_char16_t);
-		for (k = 0; k < name_len; k++)
+		dosname_len = sizeof(partitions[i].name);
+
+		memset(gpt_e[i].partition_name, 0,
+		       sizeof(gpt_e[i].partition_name));
+
+		for (k = 0; k < min(dosname_len, efiname_len); k++)
 			gpt_e[i].partition_name[k] =
 				(efi_char16_t)(partitions[i].name[k]);
 
diff --git a/doc/README.at91 b/doc/README.at91
index b51df00..6741213 100644
--- a/doc/README.at91
+++ b/doc/README.at91
@@ -1,6 +1,9 @@
 Atmel AT91 Evaluation kits
 
-http://atmel.com/dyn/products/tools.asp?family_id=605#1443
+Index
+  - I. Board mapping & boot media
+  - II. NAND partition table
+  - III. watchdog support
 
 I. Board mapping & boot media
 ------------------------------------------------------------------------------
@@ -10,7 +13,7 @@
 Memory map
 	0x20000000 - 23FFFFFF	SDRAM (64 MB)
 	0xC0000000 - Cxxxxxxx	Atmel Dataflash card (J13)
-	0xD0000000 - Dxxxxxxx	Soldered Atmel Dataflash
+	0xD0000000 - D07FFFFF	Soldered Atmel Dataflash (AT45DB642)
 
 Environment variables
 
@@ -20,7 +23,6 @@
 		- Nand flash.
 
 	You can choose your storage location at config step (here for at91sam9260ek) :
-		make at91sam9260ek_config		- use data flash (spi cs1) (default)
 		make at91sam9260ek_nandflash_config	- use nand flash
 		make at91sam9260ek_dataflash_cs0_config	- use data flash (spi cs0)
 		make at91sam9260ek_dataflash_cs1_config	- use data flash (spi cs1)
@@ -32,7 +34,7 @@
 
 Memory map
 	0x20000000 - 23FFFFFF	SDRAM (64 MB)
-	0xC0000000 - Cxxxxxxx	Soldered Atmel Dataflash
+	0xC0000000 - C07FFFFF	Soldered Atmel Dataflash (AT45DB642)
 	0xD0000000 - Dxxxxxxx	Atmel Dataflash card (J22)
 
 Environment variables
@@ -43,7 +45,6 @@
 		- Nand flash.
 
 	You can choose your storage location at config step (here for at91sam9260ek) :
-		make at91sam9261ek_config		- use data flash (spi cs0) (default)
 		make at91sam9261ek_nandflash_config	- use nand flash
 		make at91sam9261ek_dataflash_cs0_config	- use data flash (spi cs0)
 		make at91sam9261ek_dataflash_cs3_config	- use data flash (spi cs3)
@@ -65,7 +66,6 @@
 		- Nor flash (not populate by default)
 
 	You can choose your storage location at config step (here for at91sam9260ek) :
-		make at91sam9263ek_config		- use data flash (spi cs0) (default)
 		make at91sam9263ek_nandflash_config	- use nand flash
 		make at91sam9263ek_dataflash_cs0_config	- use data flash (spi cs0)
 		make at91sam9263ek_norflash_config	- use nor flash
@@ -79,19 +79,15 @@
 ------------------------------------------------------------------------------
 
 Memory map
-	0x20000000 - 23FFFFFF	SDRAM (64 MB)
-	0xC0000000 - Cxxxxxxx	Atmel Dataflash card (J12)
+	0x70000000 - 77FFFFFF	SDRAM (128 MB)
 
 Environment variables
 
 	U-Boot environment variables can be stored at different places:
-		- Dataflash on SPI chip select 0 (dataflash card)
 		- Nand flash.
 
 	You can choose your storage location at config step (here for at91sam9m10g45ek) :
-		make at91sam9m10g45ek_config			- use data flash (spi cs0) (default)
 		make at91sam9m10g45ek_nandflash_config		- use nand flash
-		make at91sam9m10g45ek_dataflash_cs0_config	- use data flash (spi cs0)
 
 
 ------------------------------------------------------------------------------
@@ -100,7 +96,7 @@
 
 Memory map
 	0x20000000 - 23FFFFFF	SDRAM (64 MB)
-	0xC0000000 - Cxxxxxxx	Soldered Atmel Dataflash
+	0xC0000000 - C07FFFFF   Soldered Atmel Dataflash (AT45DB642)
 
 Environment variables
 
@@ -108,12 +104,66 @@
 		- Dataflash on SPI chip select 0
 		- Nand flash.
 
-	You can choose your storage location at config step (here for at91sam9260ek) :
-		make at91sam9263ek_config		- use data flash (spi cs0) (default)
-		make at91sam9263ek_nandflash_config	- use nand flash
-		make at91sam9263ek_dataflash_cs0_config	- use data flash (spi cs0)
+	You can choose your storage location at config step (here for at91sam9rlek) :
+		make at91sam9rlek_nandflash_config	- use nand flash
 
-II. Watchdog support
+
+------------------------------------------------------------------------------
+AT91SAM9N12EK, AT91SAM9X5EK
+------------------------------------------------------------------------------
+
+Memory map
+	0x20000000 - 27FFFFFF	SDRAM (128 MB)
+
+Environment variables
+
+	U-Boot environment variables can be stored at different places:
+		- Nand flash.
+		- SD/MMC card
+		- Serialflash/Dataflash on SPI chip select 0
+
+	You can choose your storage location at config step (here for at91sam9x5ek) :
+		make at91sam9x5ek_dataflash_config	- use data flash
+		make at91sam9x5ek_mmc_config		- use sd/mmc card
+		make at91sam9x5ek_nandflash_config	- use nand flash
+		make at91sam9x5ek_spiflash_config	- use serial flash
+
+
+------------------------------------------------------------------------------
+SAMA5D3XEK
+------------------------------------------------------------------------------
+
+Memory map
+	0x20000000 - 3FFFFFFF	SDRAM (512 MB)
+
+Environment variables
+
+	U-Boot environment variables can be stored at different places:
+		- Nand flash.
+		- SD/MMC card
+		- Serialflash on SPI chip select 0
+
+	You can choose your storage location at config step (here for sama5d3xek) :
+		make sama5d3xek_mmc_config		- use SD/MMC card
+		make sama5d3xek_nandflash_config	- use nand flash
+		make sama5d3xek_serialflash_config	- use serial flash
+
+
+II. NAND partition table
+
+	All the board support boot from NAND flash will use the following NAND
+	partition table
+
+		0x00000000 - 0x0003FFFF	bootstrap	(256 KiB)
+		0x00040000 - 0x000BFFFF u-boot		(512 KiB)
+		0x000C0000 - 0x000FFFFF env		(256 KiB)
+		0x00100000 - 0x0013FFFF env_redundant	(256 KiB)
+		0x00140000 - 0x0017FFFF spare		(256 KiB)
+		0x00180000 - 0x001FFFFF dtb		(512 KiB)
+		0x00200000 - 0x007FFFFF kernel		(6 MiB)
+		0x00800000 - 0xxxxxxxxx rootfs		(All left)
+
+III. Watchdog support
 
 	For security reasons, the at91 watchdog is running at boot time and,
 	if deactivated, cannot be used anymore.
diff --git a/doc/README.b4860qds b/doc/README.b4860qds
index f6c5ff8..bd10a6d 100644
--- a/doc/README.b4860qds
+++ b/doc/README.b4860qds
@@ -185,7 +185,7 @@
 0xF_A0C0_0000 	0xF_DFFF_FFFF	Free		1012 MB
 0xF_A000_0000 	0xF_A0BF_FFFF	MAPLE0/1/2	12 MB
 0xF_0040_0000 	0xF_9FFF_FFFF	Free		12 GB
-0xF_0000_0000 	0xF_003F_FFFF	DCSR		4 MB
+0xF_0000_0000 	0xF_01FF_FFFF	DCSR		32 MB
 0xC_4000_0000 	0xE_FFFF_FFFF	Free		11 GB
 0xC_3000_0000 	0xC_3FFF_FFFF	sRIO-2 I/O 	256 MB
 0xC_2000_0000 	0xC_2FFF_FFFF	sRIO-1 I/O  	256 MB
@@ -215,7 +215,7 @@
 0xF_A0C0_0000 	0xF_DFFF_FFFF	Free		1012 MB
 0xF_A000_0000 	0xF_A0BF_FFFF	MAPLE0/1/2	12 MB
 0xF_0040_0000 	0xF_9FFF_FFFF	Free		12 GB
-0xF_0000_0000 	0xF_003F_FFFF	DCSR		4 MB
+0xF_0000_0000 	0xF_01FF_FFFF	DCSR		32 MB
 0xC_4000_0000 	0xE_FFFF_FFFF	Free		11 GB
 0xC_3000_0000 	0xC_3FFF_FFFF	sRIO-2 I/O 	256 MB
 0xC_2000_0000 	0xC_2FFF_FFFF	sRIO-1 I/O  	256 MB
diff --git a/doc/README.fdt-control b/doc/README.fdt-control
index 5963f78..95a88a7 100644
--- a/doc/README.fdt-control
+++ b/doc/README.fdt-control
@@ -49,6 +49,12 @@
 generic source base.
 
 To enable this feature, add CONFIG_OF_CONTROL to your board config file.
+It is currently supported on ARM, x86 and Microblaze - other architectures
+will need to add code to their arch/xxx/lib/board.c file to locate the
+FDT. Alternatively you can enable generic board support on your board
+(with CONFIG_SYS_GENERIC_BOARD) if this is available (as it is for
+PowerPC). For ARM, Tegra and Exynos5 have device trees available for
+common devices.
 
 
 What is a Flat Device Tree?
@@ -99,7 +105,8 @@
 	*   Bad configuration:	0
 	* Strange test result:	0
 
-You will also find a useful ftdump utility for decoding a binary file.
+You will also find a useful fdtdump utility for decoding a binary file, as
+well as fdtget/fdtput for reading and writing properties in a binary file.
 
 
 Where do I get an fdt file for my board?
diff --git a/doc/README.fsl_iim b/doc/README.fsl_iim
new file mode 100644
index 0000000..e087f5e
--- /dev/null
+++ b/doc/README.fsl_iim
@@ -0,0 +1,48 @@
+Driver implementing the fuse API for Freescale's IC Identification Module (IIM)
+
+This IP can be found on the following SoCs:
+ - MPC512x,
+ - i.MX25,
+ - i.MX27,
+ - i.MX31,
+ - i.MX35,
+ - i.MX51,
+ - i.MX53.
+
+The section numbers in this file refer to the i.MX25 Reference Manual.
+
+A fuse word contains 8 fuse bit slots, as explained in 30.4.2.2.1.
+
+A bank contains 256 fuse word slots, as shown by the memory map in 30.3.1.
+
+Some fuse bit or word slots may not have the corresponding fuses actually
+implemented in the fusebox.
+
+See the README files of the SoCs using this driver in order to know the
+conventions used by U-Boot to store some specific data in the fuses, e.g. MAC
+addresses.
+
+Fuse operations:
+
+   Read
+      Read operations are implemented as read accesses to the shadow registers,
+      using "Word y of Bank x" from the register summary in 30.3.2. This is
+      explained in detail in 30.4.5.1.
+
+   Sense
+      Sense operations are implemented as explained in 30.4.5.2.
+
+   Program
+      Program operations are implemented as explained in 30.4.5.3. Following
+      this operation, the shadow registers are reloaded by the hardware (not
+      immediately, but this does not make any difference for a user reading
+      these registers).
+
+   Override
+      Override operations are implemented as write accesses to the shadow
+      registers, as explained in 30.4.5.4.
+
+Configuration:
+
+   CONFIG_FSL_IIM
+      Define this to enable the fsl_iim driver.
diff --git a/doc/README.fuse b/doc/README.fuse
new file mode 100644
index 0000000..1bc91c4
--- /dev/null
+++ b/doc/README.fuse
@@ -0,0 +1,67 @@
+Fuse API functions and commands
+
+The fuse API allows to control a fusebox and how it is used by the upper
+hardware layers.
+
+A fuse corresponds to a single non-volatile memory bit that can be programmed
+(i.e. blown, set to 1) only once. The programming operation is irreversible. A
+fuse that has not been programmed reads 0.
+
+Fuses can be used by SoCs to store various permanent configuration and data,
+e.g. boot configuration, security configuration, MAC addresses, etc.
+
+A fuse word is the smallest group of fuses that can be read at once from the
+fusebox control IP registers. This is limited to 32 bits with the current API.
+
+A fuse bank is the smallest group of fuse words having a common ID, as defined
+by each SoC.
+
+Upon startup, the fusebox control IP reads the fuse values and stores them to a
+volatile shadow cache.
+
+See the README files of the drivers implementing this API in order to know the
+SoC- and implementation-specific details.
+
+Functions / commands:
+
+   int fuse_read(u32 bank, u32 word, u32 *val);
+   fuse read <bank> <word> [<cnt>]
+      Read fuse words from the shadow cache.
+
+   int fuse_sense(u32 bank, u32 word, u32 *val);
+   fuse sense <bank> <word> [<cnt>]
+      Sense - i.e. read directly from the fusebox, skipping the shadow cache -
+      fuse words. This operation does not update the shadow cache.
+
+      This is useful to know the true value of fuses if an override has been
+      performed (see below).
+
+   int fuse_prog(u32 bank, u32 word, u32 val);
+   fuse prog [-y] <bank> <word> <hexval> [<hexval>...]
+      Program fuse words. This operation directly affects the fusebox and is
+      irreversible. The shadow cache is updated accordingly or not, depending on
+      each IP.
+
+      Only the bits to be programmed should be set in the input value (i.e. for
+      fuse bits that have already been programmed and hence should be left
+      unchanged by a further programming, it is preferable to clear the
+      corresponding bits in the input value in order not to perform a new
+      hardware programming operation on these fuse bits).
+
+   int fuse_override(u32 bank, u32 word, u32 val);
+   fuse override <bank> <word> <hexval> [<hexval>...]
+      Override fuse words in the shadow cache.
+
+      The fusebox is unaffected, so following this operation, the shadow cache
+      may differ from the fusebox values. Read or sense operations can then be
+      used to get the values from the shadow cache or from the fusebox.
+
+      This is useful to change the behaviors linked to some cached fuse values,
+      either because this is needed only temporarily, or because some of the
+      fuses have already been programmed or are locked (if the SoC allows to
+      override a locked fuse).
+
+Configuration:
+
+   CONFIG_CMD_FUSE
+      Define this to enable the fuse commands.
diff --git a/doc/README.imx25 b/doc/README.imx25
new file mode 100644
index 0000000..0ca21b6
--- /dev/null
+++ b/doc/README.imx25
@@ -0,0 +1,10 @@
+U-Boot for Freescale i.MX25
+
+This file contains information for the port of U-Boot to the Freescale i.MX25
+SoC.
+
+1. CONVENTIONS FOR FUSE ASSIGNMENTS
+-----------------------------------
+
+1.1 MAC Address: It is stored in the words 26 to 31 of fuse bank 0, using the
+    natural MAC byte order (i.e. MSB first).
diff --git a/doc/README.imx27 b/doc/README.imx27
new file mode 100644
index 0000000..6f92cb4
--- /dev/null
+++ b/doc/README.imx27
@@ -0,0 +1,10 @@
+U-Boot for Freescale i.MX27
+
+This file contains information for the port of U-Boot to the Freescale i.MX27
+SoC.
+
+1. CONVENTIONS FOR FUSE ASSIGNMENTS
+-----------------------------------
+
+1.1 MAC Address: It is stored in the words 4 to 9 of fuse bank 0, using the
+    reversed MAC byte order (i.e. LSB first).
diff --git a/doc/README.imx5 b/doc/README.imx5
index e08941e..c5312b6 100644
--- a/doc/README.imx5
+++ b/doc/README.imx5
@@ -20,3 +20,9 @@
     This option should be enabled for boards having a SYS_ON_OFF_CTL signal
     connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
     reference designs.
+
+2. CONVENTIONS FOR FUSE ASSIGNMENTS
+-----------------------------------
+
+2.1 MAC Address: It is stored in the words 9 to 14 of fuse bank 1, using the
+    natural MAC byte order (i.e. MSB first).
diff --git a/doc/README.imx6 b/doc/README.imx6
new file mode 100644
index 0000000..513a06e
--- /dev/null
+++ b/doc/README.imx6
@@ -0,0 +1,10 @@
+U-Boot for Freescale i.MX6
+
+This file contains information for the port of U-Boot to the Freescale i.MX6
+SoC.
+
+1. CONVENTIONS FOR FUSE ASSIGNMENTS
+-----------------------------------
+
+1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the
+    16 msbs in word 3.
diff --git a/doc/README.imximage b/doc/README.imximage
index 073e3fc..802eb90 100644
--- a/doc/README.imximage
+++ b/doc/README.imximage
@@ -65,9 +65,27 @@
 				This command need appear the fist before
 				other valid commands in configuration file.
 
+	BOOT_OFFSET		value
+
+				This command is parallel to BOOT_FROM and
+				is preferred over BOOT_FROM.
+
+				value:  Offset of the image header, this
+					value shall be set to one of the
+					values found in the file:
+						arch/arm/include/asm/\
+						imx-common/imximage.cfg
+				Example:
+				BOOT_OFFSET FLASH_OFFSET_STANDARD
+
 	BOOT_FROM		nand/spi/sd/onenand/nor/sata
+
+				This command is parallel to BOOT_OFFSET and
+				is to be deprecated in favor of BOOT_OFFSET.
+
 				Example:
 				BOOT_FROM spi
+
 	DATA			type address value
 
 				type: word=4, halfword=2, byte=1
diff --git a/doc/README.mxc_ocotp b/doc/README.mxc_ocotp
new file mode 100644
index 0000000..9a53311
--- /dev/null
+++ b/doc/README.mxc_ocotp
@@ -0,0 +1,50 @@
+Driver implementing the fuse API for Freescale's On-Chip OTP Controller (OCOTP)
+on MXC
+
+This IP can be found on the following SoCs:
+ - i.MX6.
+
+Note that this IP is different from albeit similar to the IPs of the same name
+that can be found on the following SoCs:
+ - i.MX23,
+ - i.MX28,
+ - i.MX50.
+
+The section numbers in this file refer to the i.MX6 Reference Manual.
+
+A fuse word contains 32 fuse bit slots, as explained in 46.2.1.
+
+A bank contains 8 fuse word slots, as explained in 46.2.1 and shown by the
+memory map in 46.4.
+
+Some fuse bit or word slots may not have the corresponding fuses actually
+implemented in the fusebox.
+
+See the README files of the SoCs using this driver in order to know the
+conventions used by U-Boot to store some specific data in the fuses, e.g. MAC
+addresses.
+
+Fuse operations:
+
+   Read
+      Read operations are implemented as read accesses to the shadow registers,
+      using "Bankx Wordy" from the memory map in 46.4. This is explained in
+      detail by the first two paragraphs in 46.2.1.2.
+
+   Sense
+      Sense operations are implemented as the direct fusebox read explained by
+      the steps in 46.2.1.2.
+
+   Program
+      Program operations are implemented as explained by the steps in 46.2.1.3.
+      Following this operation, the shadow registers are not reloaded by the
+      hardware.
+
+   Override
+      Override operations are implemented as write accesses to the shadow
+      registers, as explained by the first paragraph in 46.2.1.3.
+
+Configuration:
+
+   CONFIG_MXC_OCOTP
+      Define this to enable the mxc_ocotp driver.
diff --git a/doc/README.omap-reset-time b/doc/README.omap-reset-time
new file mode 100644
index 0000000..0c974ba
--- /dev/null
+++ b/doc/README.omap-reset-time
@@ -0,0 +1,20 @@
+README on how reset time on OMAPs should be calculated
+
+CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC:
+Most OMAPs' provide a way to specify the time for
+which the reset should be held low while the voltages
+and Oscillator outputs stabilize.
+
+This time is mostly board and PMIC dependent. Hence the
+boards are expected to specify a pre-computed time
+using the above option, (the details on how to compute
+the value are given below) without which a default time
+as specified by CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC
+is used.
+
+The value for CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
+can be computed using a summation of the below 3 parameters
+-1- Time taken by the Osciallator to stop and restart
+-2- PMIC OTP time
+-3- Voltage ramp time, which can be derived using the
+PMIC slew rate and value of voltage ramp needed.
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 2cdb8a9..9223f6e 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,8 +11,11 @@
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
-smdk6400         arm         arm1176        -           -           Zhong Hongbo <bocui107@gmail.com>
-ns9750dev        arm         arm926ejs      -           -           Markus Pietrek <mpietrek@fsforth.de>
+Alaska8220       powerpc     mpc8220        -           -
+Yukon8220        powerpc     mpc8220        -           -
+sorcery          powerpc     mpc8220        -           -
+smdk6400         arm         arm1176        52587f1	2013-04-12  Zhong Hongbo <bocui107@gmail.com>
+ns9750dev        arm         arm926ejs      4cfc611	2013-02-28  Markus Pietrek <mpietrek@fsforth.de>
 AMX860           powerpc     mpc860         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
 c2mon            powerpc     mpc855         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
 ETX094           powerpc     mpc850         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
diff --git a/doc/README.t4240qds b/doc/README.t4240qds
index 677d120..a9841fb 100644
--- a/doc/README.t4240qds
+++ b/doc/README.t4240qds
@@ -86,7 +86,7 @@
 
 0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff   2GB DDR (more than 2GB is initialized but not mapped under with TLB)
 0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory
-0x0_f000_0000 (0xf_0000_0000) - 0x0_f03f_ffff  4MB  DCSR
+0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff  32MB DCSR (includes trace buffers)
 0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff  32MB BMan
 0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff  32MB QMan
 0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
@@ -96,3 +96,27 @@
 0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff   4KB Boot page translation for secondary cores
 
 The physical address of the last (boot page translation) varies with the actual DDR size.
+
+Voltage ID and VDD override
+--------------------
+T4240 has a VID feature. U-boot reads the VID efuses and adjust the voltage
+accordingly. The voltage can also be override by command vdd_override. The
+syntax is
+
+vdd_override <voltage in mV>, eg. 1050 is for 1.050v.
+
+Upon success, the actual voltage will be read back. The value is checked
+for safety and any invalid value will not adjust the voltage.
+
+Another way to override VDD is to use environmental variable, in case of using
+command is too late for some debugging. The syntax is
+
+setenv t4240qds_vdd_mv <voltage in mV>
+saveenv
+reset
+
+The override voltage takes effect when booting.
+
+Note: voltage adjustment needs to be done step by step. Changing voltage too
+rapidly may cause current surge. The voltage stepping is done by software.
+Users can set the final voltage directly.
diff --git a/doc/README.ubi b/doc/README.ubi
index da2dfac..3cf4ef2 100644
--- a/doc/README.ubi
+++ b/doc/README.ubi
@@ -2,7 +2,8 @@
 UBI usage in U-Boot
 -------------------
 
-Here the list of the currently implemented UBI commands:
+UBI support in U-Boot is broken down into five separate commands.
+The first is the ubi command, which has six subcommands:
 
 => help ubi
 ubi - ubi commands
@@ -142,3 +143,80 @@
 
 => cmp.b 800000 900000 80000
 Total of 524288 bytes were the same
+
+
+Next, the ubifsmount command allows you to access filesystems on the
+UBI partition which has been attached with the ubi part command:
+
+=> help ubifsmount
+ubifsmount - mount UBIFS volume
+
+Usage:
+ubifsmount <volume-name>
+    - mount 'volume-name' volume
+
+For example:
+
+=> ubifsmount ubi0:recovery
+UBIFS: mounted UBI device 0, volume 0, name "recovery"
+UBIFS: mounted read-only
+UBIFS: file system size:   46473216 bytes (45384 KiB, 44 MiB, 366 LEBs)
+UBIFS: journal size:       6348800 bytes (6200 KiB, 6 MiB, 50 LEBs)
+UBIFS: media format:       w4/r0 (latest is w4/r0)
+UBIFS: default compressor: LZO
+UBIFS: reserved for root:  0 bytes (0 KiB)
+
+Note that unlike Linux, U-Boot can only have one active UBI partition
+at a time, which can be referred to as ubi0, and must be supplied along
+with the name of the filesystem you are mounting.
+
+
+Once a UBI filesystem has been mounted, the ubifsls command allows you
+to list the contents of a directory in the filesystem:
+
+
+=> help ubifsls
+ubifsls - list files in a directory
+
+Usage:
+ubifsls [directory]
+    - list files in a 'directory' (default '/')
+
+For example:
+
+=> ubifsls
+            17442  Thu Jan 01 02:57:38 1970  imx28-evk.dtb
+          2998146  Thu Jan 01 02:57:43 1970  zImage
+
+
+And the ubifsload command allows you to load a file from a UBI
+filesystem:
+
+
+=> help ubifsload
+ubifsload - load file from an UBIFS filesystem
+
+Usage:
+ubifsload <addr> <filename> [bytes]
+    - load file 'filename' to address 'addr'
+
+For example:
+
+=> ubifsload ${loadaddr} zImage
+Loading file 'zImage' to addr 0x42000000 with size 2998146 (0x002dbf82)...
+Done
+
+
+Finally, you can unmount the UBI filesystem with the ubifsumount
+command:
+
+=> help ubifsumount
+ubifsumount - unmount UBIFS volume
+
+Usage:
+ubifsumount     - unmount current volume
+
+For example:
+
+=> ubifsumount
+Unmounting UBIFS volume recovery!
diff --git a/doc/README.watchdog b/doc/README.watchdog
index 33f31c2..59f306b 100644
--- a/doc/README.watchdog
+++ b/doc/README.watchdog
@@ -30,3 +30,6 @@
 
 CONFIG_XILINX_TB_WATCHDOG
 	Available for Xilinx Axi platforms to service timebase watchdog timer.
+
+CONFIG_BFIN_WATCHDOG
+	Available for bf5xx and bf6xx to service the watchdog.
diff --git a/doc/SPL/README.am335x-network b/doc/SPL/README.am335x-network
index e5a198f..9b63791 100644
--- a/doc/SPL/README.am335x-network
+++ b/doc/SPL/README.am335x-network
@@ -7,7 +7,7 @@
 
  I. Building the required images
   1. You have to enable generic SPL configuration options (see
-docs/README.SPL) as well as CONFIG_SPL_NET_SUPPORT,
+doc/README.SPL) as well as CONFIG_SPL_NET_SUPPORT,
 CONFIG_ETH_SUPPORT, CONFIG_SPL_LIBGENERIC_SUPPORT and
 CONFIG_SPL_LIBCOMMON_SUPPORT in your board configuration file to build
 SPL with support for booting over the network. Also you have to enable
diff --git a/doc/driver-model/UDM-pci.txt b/doc/driver-model/UDM-pci.txt
index c2cf2d5..6a592b3 100644
--- a/doc/driver-model/UDM-pci.txt
+++ b/doc/driver-model/UDM-pci.txt
@@ -201,11 +201,7 @@
     -----------------------------
       Standard driver, uses indirect functions.
 
-    12) powerpc/cpu/mpc8220/pci.c
-    -----------------------------
-      Standard driver, specifies all read/write functions separately.
-
-    13) powerpc/cpu/mpc85xx/pci.c
+    12) powerpc/cpu/mpc85xx/pci.c
     -----------------------------
       Standard driver, uses indirect functions, has two busses.
 
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 0c1cd83..510cb28 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -31,7 +31,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
+#include <asm/imx-common/regs-apbh.h>
 
 static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
 
@@ -226,7 +227,7 @@
 #if defined(CONFIG_MX23)
 	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
 	uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
-#elif defined(CONFIG_MX28)
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
 	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
 	uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
 #endif
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index b48f623..0b51dcd 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -30,6 +30,7 @@
 COBJS-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
 COBJS-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
 COBJS-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
+COBJS-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
 COBJS-$(CONFIG_FPGA_XILINX) += xilinx.o
 COBJS-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
 ifdef CONFIG_FPGA_ALTERA
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 26d2443..f70bff6 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -22,122 +22,99 @@
  *
  */
 
-/*
- *  Generic FPGA support
- */
+/* Generic FPGA support */
 #include <common.h>             /* core U-Boot definitions */
 #include <xilinx.h>             /* xilinx specific definitions */
 #include <altera.h>             /* altera specific definitions */
 #include <lattice.h>
 
-#if 0
-#define FPGA_DEBUG              /* define FPGA_DEBUG to get debug messages */
-#endif
-
 /* Local definitions */
 #ifndef CONFIG_MAX_FPGA_DEVICES
 #define CONFIG_MAX_FPGA_DEVICES		5
 #endif
 
-/* Enable/Disable debug console messages */
-#ifdef FPGA_DEBUG
-#define	PRINTF(fmt,args...)	printf (fmt ,##args)
-#else
-#define	PRINTF(fmt,args...)
-#endif
-
 /* Local static data */
 static int next_desc = FPGA_INVALID_DEVICE;
 static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES];
 
-/* Local static functions */
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum );
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf,
-					 size_t bsize, char *fn );
-static int fpga_dev_info( int devnum );
-
-
-/* ------------------------------------------------------------------------- */
-
-/* fpga_no_sup
+/*
+ * fpga_no_sup
  * 'no support' message function
  */
-static void fpga_no_sup( char *fn, char *msg )
+static void fpga_no_sup(char *fn, char *msg)
 {
-	if ( fn && msg ) {
-		printf( "%s: No support for %s.\n", fn, msg);
-	} else if ( msg ) {
-		printf( "No support for %s.\n", msg);
-	} else {
-		printf( "No FPGA suport!\n");
-	}
+	if (fn && msg)
+		printf("%s: No support for %s.\n", fn, msg);
+	else if (msg)
+		printf("No support for %s.\n", msg);
+	else
+		printf("No FPGA suport!\n");
 }
 
 
 /* fpga_get_desc
  *	map a device number to a descriptor
  */
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum )
+static const fpga_desc *const fpga_get_desc(int devnum)
 {
-	fpga_desc *desc = (fpga_desc * )NULL;
+	fpga_desc *desc = (fpga_desc *)NULL;
 
-	if (( devnum >= 0 ) && (devnum < next_desc )) {
+	if ((devnum >= 0) && (devnum < next_desc)) {
 		desc = &desc_table[devnum];
-		PRINTF( "%s: found fpga descriptor #%d @ 0x%p\n",
-				__FUNCTION__, devnum, desc );
+		debug("%s: found fpga descriptor #%d @ 0x%p\n",
+		      __func__, devnum, desc);
 	}
 
 	return desc;
 }
 
-
-/* fpga_validate
+/*
+ * fpga_validate
  *	generic parameter checking code
  */
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf,
-					 size_t bsize, char *fn )
+const fpga_desc *const fpga_validate(int devnum, const void *buf,
+				     size_t bsize, char *fn)
 {
-	fpga_desc * desc = fpga_get_desc( devnum );
+	const fpga_desc *desc = fpga_get_desc(devnum);
 
-	if ( !desc ) {
-		printf( "%s: Invalid device number %d\n", fn, devnum );
-	}
+	if (!desc)
+		printf("%s: Invalid device number %d\n", fn, devnum);
 
-	if ( !buf ) {
-		printf( "%s: Null buffer.\n", fn );
+	if (!buf) {
+		printf("%s: Null buffer.\n", fn);
 		return (fpga_desc * const)NULL;
 	}
 	return desc;
 }
 
-
-/* fpga_dev_info
+/*
+ * fpga_dev_info
  *	generic multiplexing code
  */
-static int fpga_dev_info( int devnum )
+static int fpga_dev_info(int devnum)
 {
-	int ret_val = FPGA_FAIL;           /* assume failure */
-	const fpga_desc * const desc = fpga_get_desc( devnum );
+	int ret_val = FPGA_FAIL; /* assume failure */
+	const fpga_desc * const desc = fpga_get_desc(devnum);
 
-	if ( desc ) {
-		PRINTF( "%s: Device Descriptor @ 0x%p\n",
-				__FUNCTION__, desc->devdesc );
+	if (desc) {
+		debug("%s: Device Descriptor @ 0x%p\n",
+		      __func__, desc->devdesc);
 
-		switch ( desc->devtype ) {
+		switch (desc->devtype) {
 		case fpga_xilinx:
 #if defined(CONFIG_FPGA_XILINX)
-			printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc );
-			ret_val = xilinx_info( desc->devdesc );
+			printf("Xilinx Device\nDescriptor @ 0x%p\n", desc);
+			ret_val = xilinx_info(desc->devdesc);
 #else
-			fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
+			fpga_no_sup((char *)__func__, "Xilinx devices");
 #endif
 			break;
 		case fpga_altera:
 #if defined(CONFIG_FPGA_ALTERA)
-			printf( "Altera Device\nDescriptor @ 0x%p\n", desc );
-			ret_val = altera_info( desc->devdesc );
+			printf("Altera Device\nDescriptor @ 0x%p\n", desc);
+			ret_val = altera_info(desc->devdesc);
 #else
-			fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
+			fpga_no_sup((char *)__func__, "Altera devices");
 #endif
 			break;
 		case fpga_lattice:
@@ -145,171 +122,183 @@
 			printf("Lattice Device\nDescriptor @ 0x%p\n", desc);
 			ret_val = lattice_info(desc->devdesc);
 #else
-			fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" );
+			fpga_no_sup((char *)__func__, "Lattice devices");
 #endif
 			break;
 		default:
-			printf( "%s: Invalid or unsupported device type %d\n",
-					__FUNCTION__, desc->devtype );
+			printf("%s: Invalid or unsupported device type %d\n",
+			       __func__, desc->devtype);
 		}
 	} else {
-		printf( "%s: Invalid device number %d\n",
-			__FUNCTION__, devnum );
+		printf("%s: Invalid device number %d\n", __func__, devnum);
 	}
 
 	return ret_val;
 }
 
-
-/* ------------------------------------------------------------------------- */
-/* fgpa_init is usually called from misc_init_r() and MUST be called
+/*
+ * fgpa_init is usually called from misc_init_r() and MUST be called
  * before any of the other fpga functions are used.
  */
 void fpga_init(void)
 {
 	next_desc = 0;
-	memset( desc_table, 0, sizeof(desc_table));
+	memset(desc_table, 0, sizeof(desc_table));
 
-	PRINTF( "%s: CONFIG_FPGA = 0x%x\n", __FUNCTION__, CONFIG_FPGA );
+	debug("%s\n", __func__);
 }
 
-/* fpga_count
+/*
+ * fpga_count
  * Basic interface function to get the current number of devices available.
  */
-int fpga_count( void )
+int fpga_count(void)
 {
 	return next_desc;
 }
 
-/* fpga_add
+/*
+ * fpga_add
  *	Add the device descriptor to the device table.
  */
-int fpga_add( fpga_type devtype, void *desc )
+int fpga_add(fpga_type devtype, void *desc)
 {
 	int devnum = FPGA_INVALID_DEVICE;
 
-	if ( next_desc  < 0 ) {
-		printf( "%s: FPGA support not initialized!\n", __FUNCTION__ );
-	} else if (( devtype > fpga_min_type ) && ( devtype < fpga_undefined )) {
-		if ( desc ) {
-			if ( next_desc < CONFIG_MAX_FPGA_DEVICES ) {
+	if (next_desc < 0) {
+		printf("%s: FPGA support not initialized!\n", __func__);
+	} else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) {
+		if (desc) {
+			if (next_desc < CONFIG_MAX_FPGA_DEVICES) {
 				devnum = next_desc;
 				desc_table[next_desc].devtype = devtype;
 				desc_table[next_desc++].devdesc = desc;
 			} else {
-				printf( "%s: Exceeded Max FPGA device count\n", __FUNCTION__ );
+				printf("%s: Exceeded Max FPGA device count\n",
+				       __func__);
 			}
 		} else {
-			printf( "%s: NULL device descriptor\n", __FUNCTION__ );
+			printf("%s: NULL device descriptor\n", __func__);
 		}
 	} else {
-		printf( "%s: Unsupported FPGA type %d\n", __FUNCTION__, devtype );
+		printf("%s: Unsupported FPGA type %d\n", __func__, devtype);
 	}
 
 	return devnum;
 }
 
 /*
- *	Generic multiplexing code
+ * Convert bitstream data and load into the fpga
+ */
+int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
+{
+	printf("Bitstream support not implemented for this FPGA device\n");
+	return FPGA_FAIL;
+}
+
+/*
+ * Generic multiplexing code
  */
 int fpga_load(int devnum, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;           /* assume failure */
-	fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ );
+	const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
+					      (char *)__func__);
 
-	if ( desc ) {
-		switch ( desc->devtype ) {
+	if (desc) {
+		switch (desc->devtype) {
 		case fpga_xilinx:
 #if defined(CONFIG_FPGA_XILINX)
-			ret_val = xilinx_load( desc->devdesc, buf, bsize );
+			ret_val = xilinx_load(desc->devdesc, buf, bsize);
 #else
-			fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
+			fpga_no_sup((char *)__func__, "Xilinx devices");
 #endif
 			break;
 		case fpga_altera:
 #if defined(CONFIG_FPGA_ALTERA)
-			ret_val = altera_load( desc->devdesc, buf, bsize );
+			ret_val = altera_load(desc->devdesc, buf, bsize);
 #else
-			fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
+			fpga_no_sup((char *)__func__, "Altera devices");
 #endif
 			break;
 		case fpga_lattice:
 #if defined(CONFIG_FPGA_LATTICE)
 			ret_val = lattice_load(desc->devdesc, buf, bsize);
 #else
-			fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" );
+			fpga_no_sup((char *)__func__, "Lattice devices");
 #endif
 			break;
 		default:
-			printf( "%s: Invalid or unsupported device type %d\n",
-				__FUNCTION__, desc->devtype );
+			printf("%s: Invalid or unsupported device type %d\n",
+			       __func__, desc->devtype);
 		}
 	}
 
 	return ret_val;
 }
 
-/* fpga_dump
+/*
+ * fpga_dump
  *	generic multiplexing code
  */
 int fpga_dump(int devnum, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;           /* assume failure */
-	fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ );
+	const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
+					      (char *)__func__);
 
-	if ( desc ) {
-		switch ( desc->devtype ) {
+	if (desc) {
+		switch (desc->devtype) {
 		case fpga_xilinx:
 #if defined(CONFIG_FPGA_XILINX)
-			ret_val = xilinx_dump( desc->devdesc, buf, bsize );
+			ret_val = xilinx_dump(desc->devdesc, buf, bsize);
 #else
-			fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
+			fpga_no_sup((char *)__func__, "Xilinx devices");
 #endif
 			break;
 		case fpga_altera:
 #if defined(CONFIG_FPGA_ALTERA)
-			ret_val = altera_dump( desc->devdesc, buf, bsize );
+			ret_val = altera_dump(desc->devdesc, buf, bsize);
 #else
-			fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
+			fpga_no_sup((char *)__func__, "Altera devices");
 #endif
 			break;
 		case fpga_lattice:
 #if defined(CONFIG_FPGA_LATTICE)
 			ret_val = lattice_dump(desc->devdesc, buf, bsize);
 #else
-			fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" );
+			fpga_no_sup((char *)__func__, "Lattice devices");
 #endif
 			break;
 		default:
-			printf( "%s: Invalid or unsupported device type %d\n",
-				__FUNCTION__, desc->devtype );
+			printf("%s: Invalid or unsupported device type %d\n",
+			       __func__, desc->devtype);
 		}
 	}
 
 	return ret_val;
 }
 
-
-/* fpga_info
+/*
+ * fpga_info
  *	front end to fpga_dev_info.  If devnum is invalid, report on all
  *	available devices.
  */
-int fpga_info( int devnum )
+int fpga_info(int devnum)
 {
-	if ( devnum == FPGA_INVALID_DEVICE ) {
-		if ( next_desc > 0 ) {
+	if (devnum == FPGA_INVALID_DEVICE) {
+		if (next_desc > 0) {
 			int dev;
 
-			for ( dev = 0; dev < next_desc; dev++ ) {
-				fpga_dev_info( dev );
-			}
+			for (dev = 0; dev < next_desc; dev++)
+				fpga_dev_info(dev);
+
 			return FPGA_SUCCESS;
 		} else {
-			printf( "%s: No FPGA devices available.\n", __FUNCTION__ );
+			printf("%s: No FPGA devices available.\n", __func__);
 			return FPGA_FAIL;
 		}
 	}
-	else return fpga_dev_info( devnum );
-}
 
-/* ------------------------------------------------------------------------- */
+	return fpga_dev_info(devnum);
+}
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index 32787b2..49e9437 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -1,4 +1,6 @@
 /*
+ * (C) Copyright 2012-2013, Xilinx, Michal Simek
+ *
  * (C) Copyright 2002
  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  * Keith Outwater, keith_outwater@mvis.com
@@ -28,9 +30,11 @@
  */
 
 #include <common.h>
+#include <fpga.h>
 #include <virtex2.h>
 #include <spartan2.h>
 #include <spartan3.h>
+#include <zynqpl.h>
 
 #if 0
 #define FPGA_DEBUG
@@ -48,6 +52,112 @@
 
 /* ------------------------------------------------------------------------- */
 
+int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
+{
+	unsigned int length;
+	unsigned int swapsize;
+	char buffer[80];
+	unsigned char *dataptr;
+	unsigned int i;
+	const fpga_desc *desc;
+	Xilinx_desc *xdesc;
+
+	dataptr = (unsigned char *)fpgadata;
+	/* Find out fpga_description */
+	desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
+	/* Assign xilinx device description */
+	xdesc = desc->devdesc;
+
+	/* skip the first bytes of the bitsteam, their meaning is unknown */
+	length = (*dataptr << 8) + *(dataptr + 1);
+	dataptr += 2;
+	dataptr += length;
+
+	/* get design name (identifier, length, string) */
+	length = (*dataptr << 8) + *(dataptr + 1);
+	dataptr += 2;
+	if (*dataptr++ != 0x61) {
+		debug("%s: Design name id not recognized in bitstream\n",
+		      __func__);
+		return FPGA_FAIL;
+	}
+
+	length = (*dataptr << 8) + *(dataptr + 1);
+	dataptr += 2;
+	for (i = 0; i < length; i++)
+		buffer[i] = *dataptr++;
+
+	printf("  design filename = \"%s\"\n", buffer);
+
+	/* get part number (identifier, length, string) */
+	if (*dataptr++ != 0x62) {
+		printf("%s: Part number id not recognized in bitstream\n",
+		       __func__);
+		return FPGA_FAIL;
+	}
+
+	length = (*dataptr << 8) + *(dataptr + 1);
+	dataptr += 2;
+	for (i = 0; i < length; i++)
+		buffer[i] = *dataptr++;
+
+	if (xdesc->name) {
+		i = strncmp(buffer, xdesc->name, strlen(xdesc->name));
+		if (i) {
+			printf("%s: Wrong bitstream ID for this device\n",
+			       __func__);
+			printf("%s: Bitstream ID %s, current device ID %d/%s\n",
+			       __func__, buffer, devnum, xdesc->name);
+			return FPGA_FAIL;
+		}
+	} else {
+		printf("%s: Please fill correct device ID to Xilinx_desc\n",
+		       __func__);
+	}
+	printf("  part number = \"%s\"\n", buffer);
+
+	/* get date (identifier, length, string) */
+	if (*dataptr++ != 0x63) {
+		printf("%s: Date identifier not recognized in bitstream\n",
+		       __func__);
+		return FPGA_FAIL;
+	}
+
+	length = (*dataptr << 8) + *(dataptr+1);
+	dataptr += 2;
+	for (i = 0; i < length; i++)
+		buffer[i] = *dataptr++;
+	printf("  date = \"%s\"\n", buffer);
+
+	/* get time (identifier, length, string) */
+	if (*dataptr++ != 0x64) {
+		printf("%s: Time identifier not recognized in bitstream\n",
+		       __func__);
+		return FPGA_FAIL;
+	}
+
+	length = (*dataptr << 8) + *(dataptr+1);
+	dataptr += 2;
+	for (i = 0; i < length; i++)
+		buffer[i] = *dataptr++;
+	printf("  time = \"%s\"\n", buffer);
+
+	/* get fpga data length (identifier, length) */
+	if (*dataptr++ != 0x65) {
+		printf("%s: Data length id not recognized in bitstream\n",
+		       __func__);
+		return FPGA_FAIL;
+	}
+	swapsize = ((unsigned int) *dataptr << 24) +
+		   ((unsigned int) *(dataptr + 1) << 16) +
+		   ((unsigned int) *(dataptr + 2) << 8) +
+		   ((unsigned int) *(dataptr + 3));
+	dataptr += 4;
+	printf("  bytes in bitstream = %d\n", swapsize);
+
+	return fpga_load(devnum, dataptr, swapsize);
+}
+
 int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume a failure */
@@ -86,6 +196,16 @@
 					__FUNCTION__);
 #endif
 			break;
+		case xilinx_zynq:
+#if defined(CONFIG_FPGA_ZYNQPL)
+			PRINTF("%s: Launching the Zynq PL Loader...\n",
+			       __func__);
+			ret_val = zynq_load(desc, buf, bsize);
+#else
+			printf("%s: No support for Zynq devices.\n",
+			       __func__);
+#endif
+			break;
 
 		default:
 			printf ("%s: Unsupported family type, %d\n",
@@ -133,6 +253,16 @@
 					__FUNCTION__);
 #endif
 			break;
+		case xilinx_zynq:
+#if defined(CONFIG_FPGA_ZYNQPL)
+			PRINTF("%s: Launching the Zynq PL Reader...\n",
+			       __func__);
+			ret_val = zynq_dump(desc, buf, bsize);
+#else
+			printf("%s: No support for Zynq devices.\n",
+			       __func__);
+#endif
+			break;
 
 		default:
 			printf ("%s: Unsupported family type, %d\n",
@@ -158,6 +288,9 @@
 		case Xilinx_Virtex2:
 			printf ("Virtex-II\n");
 			break;
+		case xilinx_zynq:
+			printf("Zynq PL\n");
+			break;
 			/* Add new family types here */
 		default:
 			printf ("Unknown family type, %d\n", desc->family);
@@ -183,6 +316,9 @@
 		case master_selectmap:
 			printf ("Master SelectMap Mode\n");
 			break;
+		case devcfg:
+			printf("Device configuration interface (Zynq)\n");
+			break;
 			/* Add new interface types here */
 		default:
 			printf ("Unsupported interface type, %d\n", desc->iface);
@@ -191,6 +327,8 @@
 		printf ("Device Size:   \t%d bytes\n"
 				"Cookie:        \t0x%x (%d)\n",
 				desc->size, desc->cookie, desc->cookie);
+		if (desc->name)
+			printf("Device name:   \t%s\n", desc->name);
 
 		if (desc->iface_fns) {
 			printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
@@ -222,6 +360,14 @@
 						__FUNCTION__);
 #endif
 				break;
+			case xilinx_zynq:
+#if defined(CONFIG_FPGA_ZYNQPL)
+				zynq_info(desc);
+#else
+				/* just in case */
+				printf("%s: No support for Zynq devices.\n",
+				       __func__);
+#endif
 				/* Add new family types here */
 			default:
 				/* we don't need a message here - we give one up above */
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
new file mode 100644
index 0000000..8feccde
--- /dev/null
+++ b/drivers/fpga/zynqpl.c
@@ -0,0 +1,355 @@
+/*
+ * (C) Copyright 2012-2013, Xilinx, Michal Simek
+ *
+ * (C) Copyright 2012
+ * Joe Hershberger <joe.hershberger@ni.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <zynqpl.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+#define DEVCFG_CTRL_PCFG_PROG_B		0x40000000
+#define DEVCFG_ISR_FATAL_ERROR_MASK	0x00740040
+#define DEVCFG_ISR_ERROR_FLAGS_MASK	0x00340840
+#define DEVCFG_ISR_RX_FIFO_OV		0x00040000
+#define DEVCFG_ISR_DMA_DONE		0x00002000
+#define DEVCFG_ISR_PCFG_DONE		0x00000004
+#define DEVCFG_STATUS_DMA_CMD_Q_F	0x80000000
+#define DEVCFG_STATUS_DMA_CMD_Q_E	0x40000000
+#define DEVCFG_STATUS_DMA_DONE_CNT_MASK	0x30000000
+#define DEVCFG_STATUS_PCFG_INIT		0x00000010
+#define DEVCFG_MCTRL_RFIFO_FLUSH	0x00000002
+#define DEVCFG_MCTRL_WFIFO_FLUSH	0x00000001
+
+#ifndef CONFIG_SYS_FPGA_WAIT
+#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
+#endif
+
+#ifndef CONFIG_SYS_FPGA_PROG_TIME
+#define CONFIG_SYS_FPGA_PROG_TIME CONFIG_SYS_HZ	/* 1 s */
+#endif
+
+int zynq_info(Xilinx_desc *desc)
+{
+	return FPGA_SUCCESS;
+}
+
+#define DUMMY_WORD	0xffffffff
+
+/* Xilinx binary format header */
+static const u32 bin_format[] = {
+	DUMMY_WORD, /* Dummy words */
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	0x000000bb, /* Sync word */
+	0x11220044, /* Sync word */
+	DUMMY_WORD,
+	DUMMY_WORD,
+	0xaa995566, /* Sync word */
+};
+
+#define SWAP_NO		1
+#define SWAP_DONE	2
+
+/*
+ * Load the whole word from unaligned buffer
+ * Keep in your mind that it is byte loading on little-endian system
+ */
+static u32 load_word(const void *buf, u32 swap)
+{
+	u32 word = 0;
+	u8 *bitc = (u8 *)buf;
+	int p;
+
+	if (swap == SWAP_NO) {
+		for (p = 0; p < 4; p++) {
+			word <<= 8;
+			word |= bitc[p];
+		}
+	} else {
+		for (p = 3; p >= 0; p--) {
+			word <<= 8;
+			word |= bitc[p];
+		}
+	}
+
+	return word;
+}
+
+static u32 check_header(const void *buf)
+{
+	u32 i, pattern;
+	int swap = SWAP_NO;
+	u32 *test = (u32 *)buf;
+
+	debug("%s: Let's check bitstream header\n", __func__);
+
+	/* Checking that passing bin is not a bitstream */
+	for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
+		pattern = load_word(&test[i], swap);
+
+		/*
+		 * Bitstreams in binary format are swapped
+		 * compare to regular bistream.
+		 * Do not swap dummy word but if swap is done assume
+		 * that parsing buffer is binary format
+		 */
+		if ((__swab32(pattern) != DUMMY_WORD) &&
+		    (__swab32(pattern) == bin_format[i])) {
+			pattern = __swab32(pattern);
+			swap = SWAP_DONE;
+			debug("%s: data swapped - let's swap\n", __func__);
+		}
+
+		debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
+		      (u32)&test[i], pattern, bin_format[i]);
+		if (pattern != bin_format[i]) {
+			debug("%s: Bitstream is not recognized\n", __func__);
+			return 0;
+		}
+	}
+	debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
+	      (u32)buf, swap == SWAP_NO ? "without" : "with");
+
+	return swap;
+}
+
+static void *check_data(u8 *buf, size_t bsize, u32 *swap)
+{
+	u32 word, p = 0; /* possition */
+
+	/* Because buf doesn't need to be aligned let's read it by chars */
+	for (p = 0; p < bsize; p++) {
+		word = load_word(&buf[p], SWAP_NO);
+		debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
+
+		/* Find the first bitstream dummy word */
+		if (word == DUMMY_WORD) {
+			debug("%s: Found dummy word at position %x/%x\n",
+			      __func__, p, (u32)&buf[p]);
+			*swap = check_header(&buf[p]);
+			if (*swap) {
+				/* FIXME add full bitstream checking here */
+				return &buf[p];
+			}
+		}
+		/* Loop can be huge - support CTRL + C */
+		if (ctrlc())
+			return 0;
+	}
+	return 0;
+}
+
+
+int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+{
+	unsigned long ts; /* Timestamp */
+	u32 partialbit = 0;
+	u32 i, control, isr_status, status, swap, diff;
+	u32 *buf_start;
+
+	/* Detect if we are going working with partial or full bitstream */
+	if (bsize != desc->size) {
+		printf("%s: Working with partial bitstream\n", __func__);
+		partialbit = 1;
+	}
+
+	buf_start = check_data((u8 *)buf, bsize, &swap);
+	if (!buf_start)
+		return FPGA_FAIL;
+
+	/* Check if data is postpone from start */
+	diff = (u32)buf_start - (u32)buf;
+	if (diff) {
+		printf("%s: Bitstream is not validated yet (diff %x)\n",
+		       __func__, diff);
+		return FPGA_FAIL;
+	}
+
+	if ((u32)buf_start & 0x3) {
+		u32 *new_buf = (u32 *)((u32)buf & ~0x3);
+
+		printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
+		       (u32)buf_start, (u32)new_buf, swap);
+
+		for (i = 0; i < (bsize/4); i++)
+			new_buf[i] = load_word(&buf_start[i], swap);
+
+		swap = SWAP_DONE;
+		buf = new_buf;
+	} else if (swap != SWAP_DONE) {
+		/* For bitstream which are aligned */
+		u32 *new_buf = (u32 *)buf;
+
+		printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
+		       swap);
+
+		for (i = 0; i < (bsize/4); i++)
+			new_buf[i] = load_word(&buf_start[i], swap);
+
+		swap = SWAP_DONE;
+	}
+
+	if (!partialbit) {
+		zynq_slcr_devcfg_disable();
+
+		/* Setting PCFG_PROG_B signal to high */
+		control = readl(&devcfg_base->ctrl);
+		writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
+		/* Setting PCFG_PROG_B signal to low */
+		writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
+
+		/* Polling the PCAP_INIT status for Reset */
+		ts = get_timer(0);
+		while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
+			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+				printf("%s: Timeout wait for INIT to clear\n",
+				       __func__);
+				return FPGA_FAIL;
+			}
+		}
+
+		/* Setting PCFG_PROG_B signal to high */
+		writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
+
+		/* Polling the PCAP_INIT status for Set */
+		ts = get_timer(0);
+		while (!(readl(&devcfg_base->status) &
+			DEVCFG_STATUS_PCFG_INIT)) {
+			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+				printf("%s: Timeout wait for INIT to set\n",
+				       __func__);
+				return FPGA_FAIL;
+			}
+		}
+	}
+
+	isr_status = readl(&devcfg_base->int_sts);
+
+	/* Clear it all, so if Boot ROM comes back, it can proceed */
+	writel(0xFFFFFFFF, &devcfg_base->int_sts);
+
+	if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
+		debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
+
+		/* If RX FIFO overflow, need to flush RX FIFO first */
+		if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
+			writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
+			writel(0xFFFFFFFF, &devcfg_base->int_sts);
+		}
+		return FPGA_FAIL;
+	}
+
+	status = readl(&devcfg_base->status);
+
+	debug("%s: Status = 0x%08X\n", __func__, status);
+
+	if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
+		debug("%s: Error: device busy\n", __func__);
+		return FPGA_FAIL;
+	}
+
+	debug("%s: Device ready\n", __func__);
+
+	if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
+		if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
+			/* Error state, transfer cannot occur */
+			debug("%s: ISR indicates error\n", __func__);
+			return FPGA_FAIL;
+		} else {
+			/* Clear out the status */
+			writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
+		}
+	}
+
+	if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
+		/* Clear the count of completed DMA transfers */
+		writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
+	}
+
+	debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
+	debug("%s: Size = %zu\n", __func__, bsize);
+
+	/* Set up the transfer */
+	writel((u32)buf | 1, &devcfg_base->dma_src_addr);
+	writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);
+	writel(bsize >> 2, &devcfg_base->dma_src_len);
+	writel(0, &devcfg_base->dma_dst_len);
+
+	isr_status = readl(&devcfg_base->int_sts);
+
+	/* Polling the PCAP_INIT status for Set */
+	ts = get_timer(0);
+	while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
+		if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
+			debug("%s: Error: isr = 0x%08X\n", __func__,
+			      isr_status);
+			debug("%s: Write count = 0x%08X\n", __func__,
+			      readl(&devcfg_base->write_count));
+			debug("%s: Read count = 0x%08X\n", __func__,
+			      readl(&devcfg_base->read_count));
+
+			return FPGA_FAIL;
+		}
+		if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
+			printf("%s: Timeout wait for DMA to complete\n",
+			       __func__);
+			return FPGA_FAIL;
+		}
+		isr_status = readl(&devcfg_base->int_sts);
+	}
+
+	debug("%s: DMA transfer is done\n", __func__);
+
+	/* Check FPGA configuration completion */
+	ts = get_timer(0);
+	while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
+		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+			printf("%s: Timeout wait for FPGA to config\n",
+			       __func__);
+			return FPGA_FAIL;
+		}
+		isr_status = readl(&devcfg_base->int_sts);
+	}
+
+	debug("%s: FPGA config done\n", __func__);
+
+	/* Clear out the DMA status */
+	writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
+
+	if (!partialbit)
+		zynq_slcr_devcfg_enable();
+
+	return FPGA_SUCCESS;
+}
+
+int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+{
+	return FPGA_FAIL;
+}
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 9df1e26..f77c1ec 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -47,6 +47,8 @@
 COBJS-$(CONFIG_DB8500_GPIO)	+= db8500_gpio.o
 COBJS-$(CONFIG_BCM2835_GPIO)	+= bcm2835_gpio.o
 COBJS-$(CONFIG_S3C2440_GPIO)	+= s3c2440_gpio.o
+COBJS-$(CONFIG_XILINX_GPIO)	+= xilinx_gpio.o
+COBJS-$(CONFIG_ADI_GPIO2)	+= adi_gpio2.o
 
 COBJS	:= $(COBJS-y)
 SRCS 	:= $(COBJS:.o=.c)
diff --git a/drivers/gpio/adi_gpio2.c b/drivers/gpio/adi_gpio2.c
new file mode 100644
index 0000000..7a034eb
--- /dev/null
+++ b/drivers/gpio/adi_gpio2.c
@@ -0,0 +1,440 @@
+/*
+ * ADI GPIO2 Abstraction Layer
+ * Support BF54x, BF60x and future processors.
+ *
+ * Copyright 2008-2013 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
+
+static struct gpio_port_t * const gpio_array[] = {
+	(struct gpio_port_t *)PORTA_FER,
+	(struct gpio_port_t *)PORTB_FER,
+	(struct gpio_port_t *)PORTC_FER,
+	(struct gpio_port_t *)PORTD_FER,
+	(struct gpio_port_t *)PORTE_FER,
+	(struct gpio_port_t *)PORTF_FER,
+	(struct gpio_port_t *)PORTG_FER,
+#if defined(CONFIG_BF54x)
+	(struct gpio_port_t *)PORTH_FER,
+	(struct gpio_port_t *)PORTI_FER,
+	(struct gpio_port_t *)PORTJ_FER,
+#endif
+};
+
+#define RESOURCE_LABEL_SIZE	16
+
+static struct str_ident {
+	char name[RESOURCE_LABEL_SIZE];
+} str_ident[MAX_RESOURCES];
+
+static void gpio_error(unsigned gpio)
+{
+	printf("adi_gpio2: GPIO %d wasn't requested!\n", gpio);
+}
+
+static void set_label(unsigned short ident, const char *label)
+{
+	if (label) {
+		strncpy(str_ident[ident].name, label,
+			RESOURCE_LABEL_SIZE);
+		str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
+	}
+}
+
+static char *get_label(unsigned short ident)
+{
+	return *str_ident[ident].name ? str_ident[ident].name : "UNKNOWN";
+}
+
+static int cmp_label(unsigned short ident, const char *label)
+{
+	if (label == NULL)
+		printf("adi_gpio2: please provide none-null label\n");
+
+	if (label)
+		return strcmp(str_ident[ident].name, label);
+	else
+		return -EINVAL;
+}
+
+#define map_entry(m, i)      reserved_##m##_map[gpio_bank(i)]
+#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i))
+#define reserve(m, i)        (map_entry(m, i) |= gpio_bit(i))
+#define unreserve(m, i)      (map_entry(m, i) &= ~gpio_bit(i))
+#define DECLARE_RESERVED_MAP(m, c) unsigned short reserved_##m##_map[c]
+
+static DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
+static DECLARE_RESERVED_MAP(peri, gpio_bank(MAX_RESOURCES));
+
+inline int check_gpio(unsigned gpio)
+{
+#if defined(CONFIG_BF54x)
+	if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 ||
+		gpio == GPIO_PH14 || gpio == GPIO_PH15 ||
+		gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
+		return -EINVAL;
+#endif
+	if (gpio >= MAX_GPIOS)
+		return -EINVAL;
+	return 0;
+}
+
+static void port_setup(unsigned gpio, unsigned short usage)
+{
+#if defined(CONFIG_BF54x)
+	if (usage == GPIO_USAGE)
+		gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
+	else
+		gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
+#else
+	if (usage == GPIO_USAGE)
+		gpio_array[gpio_bank(gpio)]->port_fer_clear = gpio_bit(gpio);
+	else
+		gpio_array[gpio_bank(gpio)]->port_fer_set = gpio_bit(gpio);
+#endif
+	SSYNC();
+}
+
+inline void portmux_setup(unsigned short per)
+{
+	u32 pmux;
+	u16 ident = P_IDENT(per);
+	u16 function = P_FUNCT2MUX(per);
+
+	pmux = gpio_array[gpio_bank(ident)]->port_mux;
+
+	pmux &= ~(0x3 << (2 * gpio_sub_n(ident)));
+	pmux |= (function & 0x3) << (2 * gpio_sub_n(ident));
+
+	gpio_array[gpio_bank(ident)]->port_mux = pmux;
+}
+
+inline u16 get_portmux(unsigned short per)
+{
+	u32 pmux;
+	u16 ident = P_IDENT(per);
+
+	pmux = gpio_array[gpio_bank(ident)]->port_mux;
+
+	return pmux >> (2 * gpio_sub_n(ident)) & 0x3;
+}
+
+unsigned short get_gpio_dir(unsigned gpio)
+{
+	return 0x01 &
+		(gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio));
+}
+
+/***********************************************************
+*
+* FUNCTIONS:	Peripheral Resource Allocation
+*		and PortMux Setup
+*
+* INPUTS/OUTPUTS:
+* per	Peripheral Identifier
+* label	String
+*
+* DESCRIPTION: Peripheral Resource Allocation and Setup API
+**************************************************************/
+
+int peripheral_request(unsigned short per, const char *label)
+{
+	unsigned short ident = P_IDENT(per);
+
+	/*
+	 * Don't cares are pins with only one dedicated function
+	 */
+
+	if (per & P_DONTCARE)
+		return 0;
+
+	if (!(per & P_DEFINED))
+		return -ENODEV;
+
+	BUG_ON(ident >= MAX_RESOURCES);
+
+	/* If a pin can be muxed as either GPIO or peripheral, make
+	 * sure it is not already a GPIO pin when we request it.
+	 */
+	if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) {
+		printf("%s: Peripheral %d is already reserved as GPIO by %s!\n",
+		       __func__, ident, get_label(ident));
+		return -EBUSY;
+	}
+
+	if (unlikely(is_reserved(peri, ident, 1))) {
+		/*
+		 * Pin functions like AMC address strobes my
+		 * be requested and used by several drivers
+		 */
+
+		if (!((per & P_MAYSHARE) &&
+			get_portmux(per) == P_FUNCT2MUX(per))) {
+			/*
+			 * Allow that the identical pin function can
+			 * be requested from the same driver twice
+			 */
+
+			if (cmp_label(ident, label) == 0)
+				goto anyway;
+
+			printf("%s: Peripheral %d function %d is already "
+				"reserved by %s!\n", __func__, ident,
+				P_FUNCT2MUX(per), get_label(ident));
+			return -EBUSY;
+		}
+	}
+
+ anyway:
+	reserve(peri, ident);
+
+	portmux_setup(per);
+	port_setup(ident, PERIPHERAL_USAGE);
+
+	set_label(ident, label);
+
+	return 0;
+}
+
+int peripheral_request_list(const unsigned short per[], const char *label)
+{
+	u16 cnt;
+	int ret;
+
+	for (cnt = 0; per[cnt] != 0; cnt++) {
+		ret = peripheral_request(per[cnt], label);
+
+		if (ret < 0) {
+			for (; cnt > 0; cnt--)
+				peripheral_free(per[cnt - 1]);
+
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+void peripheral_free(unsigned short per)
+{
+	unsigned short ident = P_IDENT(per);
+
+	if (per & P_DONTCARE)
+		return;
+
+	if (!(per & P_DEFINED))
+		return;
+
+	if (unlikely(!is_reserved(peri, ident, 0)))
+		return;
+
+	if (!(per & P_MAYSHARE))
+		port_setup(ident, GPIO_USAGE);
+
+	unreserve(peri, ident);
+
+	set_label(ident, "free");
+}
+
+void peripheral_free_list(const unsigned short per[])
+{
+	u16 cnt;
+	for (cnt = 0; per[cnt] != 0; cnt++)
+		peripheral_free(per[cnt]);
+}
+
+/***********************************************************
+*
+* FUNCTIONS: GPIO Driver
+*
+* INPUTS/OUTPUTS:
+* gpio	PIO Number between 0 and MAX_GPIOS
+* label	String
+*
+* DESCRIPTION: GPIO Driver API
+**************************************************************/
+
+int gpio_request(unsigned gpio, const char *label)
+{
+	if (check_gpio(gpio) < 0)
+		return -EINVAL;
+
+	/*
+	 * Allow that the identical GPIO can
+	 * be requested from the same driver twice
+	 * Do nothing and return -
+	 */
+
+	if (cmp_label(gpio, label) == 0)
+		return 0;
+
+	if (unlikely(is_reserved(gpio, gpio, 1))) {
+		printf("adi_gpio2: GPIO %d is already reserved by %s!\n",
+			gpio, get_label(gpio));
+		return -EBUSY;
+	}
+	if (unlikely(is_reserved(peri, gpio, 1))) {
+		printf("adi_gpio2: GPIO %d is already reserved as Peripheral "
+			"by %s!\n", gpio, get_label(gpio));
+		return -EBUSY;
+	}
+
+	reserve(gpio, gpio);
+	set_label(gpio, label);
+
+	port_setup(gpio, GPIO_USAGE);
+
+	return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+	if (check_gpio(gpio) < 0)
+		return -1;
+
+	if (unlikely(!is_reserved(gpio, gpio, 0))) {
+		gpio_error(gpio);
+		return -1;
+	}
+
+	unreserve(gpio, gpio);
+
+	set_label(gpio, "free");
+
+	return 0;
+}
+
+#ifdef ADI_SPECIAL_GPIO_BANKS
+static DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
+
+int special_gpio_request(unsigned gpio, const char *label)
+{
+	/*
+	 * Allow that the identical GPIO can
+	 * be requested from the same driver twice
+	 * Do nothing and return -
+	 */
+
+	if (cmp_label(gpio, label) == 0)
+		return 0;
+
+	if (unlikely(is_reserved(special_gpio, gpio, 1))) {
+		printf("adi_gpio2: GPIO %d is already reserved by %s!\n",
+			gpio, get_label(gpio));
+		return -EBUSY;
+	}
+	if (unlikely(is_reserved(peri, gpio, 1))) {
+		printf("adi_gpio2: GPIO %d is already reserved as Peripheral "
+			"by %s!\n", gpio, get_label(gpio));
+
+		return -EBUSY;
+	}
+
+	reserve(special_gpio, gpio);
+	reserve(peri, gpio);
+
+	set_label(gpio, label);
+	port_setup(gpio, GPIO_USAGE);
+
+	return 0;
+}
+
+void special_gpio_free(unsigned gpio)
+{
+	if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
+		gpio_error(gpio);
+		return;
+	}
+
+	reserve(special_gpio, gpio);
+	reserve(peri, gpio);
+	set_label(gpio, "free");
+}
+#endif
+
+static inline void __gpio_direction_input(unsigned gpio)
+{
+	gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
+#if defined(CONFIG_BF54x)
+	gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
+#else
+	gpio_array[gpio_bank(gpio)]->inen_set = gpio_bit(gpio);
+#endif
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+	unsigned long flags;
+
+	if (!is_reserved(gpio, gpio, 0)) {
+		gpio_error(gpio);
+		return -EINVAL;
+	}
+
+	local_irq_save(flags);
+	__gpio_direction_input(gpio);
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+int gpio_set_value(unsigned gpio, int arg)
+{
+	if (arg)
+		gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
+	else
+		gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
+
+	return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+	unsigned long flags;
+
+	if (!is_reserved(gpio, gpio, 0)) {
+		gpio_error(gpio);
+		return -EINVAL;
+	}
+
+	local_irq_save(flags);
+
+#if defined(CONFIG_BF54x)
+	gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
+#else
+	gpio_array[gpio_bank(gpio)]->inen_clear = gpio_bit(gpio);
+#endif
+	gpio_set_value(gpio, value);
+	gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
+
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+int gpio_get_value(unsigned gpio)
+{
+	return 1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio));
+}
+
+void gpio_labels(void)
+{
+	int c, gpio;
+
+	for (c = 0; c < MAX_RESOURCES; c++) {
+		gpio = is_reserved(gpio, c, 1);
+		if (!check_gpio(c) && gpio)
+			printf("GPIO_%d:\t%s\tGPIO %s\n", c, get_label(c),
+				get_gpio_dir(c) ? "OUTPUT" : "INPUT");
+		else if (is_reserved(peri, c, 1))
+			printf("GPIO_%d:\t%s\tPeripheral\n", c, get_label(c));
+		else
+			continue;
+	}
+}
diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c
new file mode 100644
index 0000000..37fb0c5
--- /dev/null
+++ b/drivers/gpio/xilinx_gpio.c
@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2013 Xilinx, Michal Simek
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <linux/list.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+static LIST_HEAD(gpio_list);
+
+enum gpio_direction {
+	GPIO_DIRECTION_OUT = 0,
+	GPIO_DIRECTION_IN = 1,
+};
+
+/* Gpio simple map */
+struct gpio_regs {
+	u32 gpiodata;
+	u32 gpiodir;
+};
+
+#define GPIO_NAME_SIZE	10
+
+struct gpio_names {
+	char name[GPIO_NAME_SIZE];
+};
+
+/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
+struct xilinx_gpio_priv {
+	struct gpio_regs *regs;
+	u32 gpio_min;
+	u32 gpio_max;
+	u32 gpiodata_store;
+	char name[GPIO_NAME_SIZE];
+	struct list_head list;
+	struct gpio_names *gpio_name;
+};
+
+/* Store number of allocated gpio pins */
+static u32 xilinx_gpio_max;
+
+/* Get associated gpio controller */
+static struct xilinx_gpio_priv *gpio_get_controller(unsigned gpio)
+{
+	struct list_head *entry;
+	struct xilinx_gpio_priv *priv = NULL;
+
+	list_for_each(entry, &gpio_list) {
+		priv = list_entry(entry, struct xilinx_gpio_priv, list);
+		if (gpio >= priv->gpio_min && gpio <= priv->gpio_max) {
+			debug("%s: reg: %x, min-max: %d-%d\n", __func__,
+			      (u32)priv->regs, priv->gpio_min, priv->gpio_max);
+			return priv;
+		}
+	}
+	puts("!!!Can't get gpio controller!!!\n");
+	return NULL;
+}
+
+/* Get gpio pin name if used/setup */
+static char *get_name(unsigned gpio)
+{
+	u32 gpio_priv;
+	struct xilinx_gpio_priv *priv;
+
+	debug("%s\n", __func__);
+
+	priv = gpio_get_controller(gpio);
+	if (priv) {
+		gpio_priv = gpio - priv->gpio_min;
+
+		return *priv->gpio_name[gpio_priv].name ?
+			priv->gpio_name[gpio_priv].name : "UNKNOWN";
+	}
+	return "UNKNOWN";
+}
+
+/* Get output value */
+static int gpio_get_output_value(unsigned gpio)
+{
+	u32 val, gpio_priv;
+	struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
+
+	if (priv) {
+		gpio_priv = gpio - priv->gpio_min;
+		val = !!(priv->gpiodata_store & (1 << gpio_priv));
+		debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
+		      (u32)priv->regs, gpio_priv, val);
+
+		return val;
+	}
+	return -1;
+}
+
+/* Get input value */
+static int gpio_get_input_value(unsigned gpio)
+{
+	u32 val, gpio_priv;
+	struct gpio_regs *regs;
+	struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
+
+	if (priv) {
+		regs = priv->regs;
+		gpio_priv = gpio - priv->gpio_min;
+		val = readl(&regs->gpiodata);
+		val = !!(val & (1 << gpio_priv));
+		debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
+		      (u32)priv->regs, gpio_priv, val);
+
+		return val;
+	}
+	return -1;
+}
+
+/* Set gpio direction */
+static int gpio_set_direction(unsigned gpio, enum gpio_direction direction)
+{
+	u32 val, gpio_priv;
+	struct gpio_regs *regs;
+	struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
+
+	if (priv) {
+		regs = priv->regs;
+		val = readl(&regs->gpiodir);
+
+		gpio_priv = gpio - priv->gpio_min;
+		if (direction == GPIO_DIRECTION_OUT)
+			val &= ~(1 << gpio_priv);
+		else
+			val |= 1 << gpio_priv;
+
+		writel(val, &regs->gpiodir);
+		debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
+		      (u32)priv->regs, gpio_priv, val);
+
+		return 0;
+	}
+
+	return -1;
+}
+
+/* Get gpio direction */
+static int gpio_get_direction(unsigned gpio)
+{
+	u32 val, gpio_priv;
+	struct gpio_regs *regs;
+	struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
+
+	if (priv) {
+		regs = priv->regs;
+		gpio_priv = gpio - priv->gpio_min;
+		val = readl(&regs->gpiodir);
+		val = !!(val & (1 << gpio_priv));
+		debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
+		      (u32)priv->regs, gpio_priv, val);
+
+		return val;
+	}
+
+	return -1;
+}
+
+/*
+ * Get input value
+ * for example gpio setup to output only can't get input value
+ * which is breaking gpio toggle command
+ */
+int gpio_get_value(unsigned gpio)
+{
+	u32 val;
+
+	if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
+		val = gpio_get_output_value(gpio);
+	else
+		val = gpio_get_input_value(gpio);
+
+	return val;
+}
+
+/* Set output value */
+static int gpio_set_output_value(unsigned gpio, int value)
+{
+	u32 val, gpio_priv;
+	struct gpio_regs *regs;
+	struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
+
+	if (priv) {
+		regs = priv->regs;
+		gpio_priv = gpio - priv->gpio_min;
+		val = priv->gpiodata_store;
+		if (value)
+			val |= 1 << gpio_priv;
+		else
+			val &= ~(1 << gpio_priv);
+
+		writel(val, &regs->gpiodata);
+		debug("%s: reg: %x, gpio_no: %d, output_val: %d\n", __func__,
+		      (u32)priv->regs, gpio_priv, val);
+		priv->gpiodata_store = val;
+
+		return 0;
+	}
+
+	return -1;
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+	if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
+		return gpio_set_output_value(gpio, value);
+
+	return -1;
+}
+
+/* Set GPIO as input */
+int gpio_direction_input(unsigned gpio)
+{
+	debug("%s\n", __func__);
+	return gpio_set_direction(gpio, GPIO_DIRECTION_IN);
+}
+
+/* Setup GPIO as output and set output value */
+int gpio_direction_output(unsigned gpio, int value)
+{
+	int ret = gpio_set_direction(gpio, GPIO_DIRECTION_OUT);
+
+	debug("%s\n", __func__);
+
+	if (ret < 0)
+		return ret;
+
+	return gpio_set_output_value(gpio, value);
+}
+
+/* Show gpio status */
+void gpio_info(void)
+{
+	unsigned gpio;
+
+	struct list_head *entry;
+	struct xilinx_gpio_priv *priv = NULL;
+
+	list_for_each(entry, &gpio_list) {
+		priv = list_entry(entry, struct xilinx_gpio_priv, list);
+		printf("\n%s: %s/%x (%d-%d)\n", __func__, priv->name,
+		       (u32)priv->regs, priv->gpio_min, priv->gpio_max);
+
+		for (gpio = priv->gpio_min; gpio <= priv->gpio_max; gpio++) {
+			printf("GPIO_%d:\t%s is an ", gpio, get_name(gpio));
+			if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
+				printf("OUTPUT value = %d\n",
+				       gpio_get_output_value(gpio));
+			else
+				printf("INPUT value = %d\n",
+				       gpio_get_input_value(gpio));
+		}
+	}
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+	u32 gpio_priv;
+	struct xilinx_gpio_priv *priv;
+
+	if (gpio >= xilinx_gpio_max)
+		return -EINVAL;
+
+	priv = gpio_get_controller(gpio);
+	if (priv) {
+		gpio_priv = gpio - priv->gpio_min;
+
+		if (label != NULL) {
+			strncpy(priv->gpio_name[gpio_priv].name, label,
+				GPIO_NAME_SIZE);
+			priv->gpio_name[gpio_priv].name[GPIO_NAME_SIZE - 1] =
+					'\0';
+		}
+		return 0;
+	}
+
+	return -1;
+}
+
+int gpio_free(unsigned gpio)
+{
+	u32 gpio_priv;
+	struct xilinx_gpio_priv *priv;
+
+	if (gpio >= xilinx_gpio_max)
+		return -EINVAL;
+
+	priv = gpio_get_controller(gpio);
+	if (priv) {
+		gpio_priv = gpio - priv->gpio_min;
+		priv->gpio_name[gpio_priv].name[0] = '\0';
+
+		/* Do nothing here */
+		return 0;
+	}
+
+	return -1;
+}
+
+int gpio_alloc(u32 baseaddr, const char *name, u32 gpio_no)
+{
+	struct xilinx_gpio_priv *priv;
+
+	priv = calloc(1, sizeof(struct xilinx_gpio_priv));
+
+	/* Setup gpio name */
+	if (name != NULL) {
+		strncpy(priv->name, name, GPIO_NAME_SIZE);
+		priv->name[GPIO_NAME_SIZE - 1] = '\0';
+	}
+	priv->regs = (struct gpio_regs *)baseaddr;
+
+	priv->gpio_min = xilinx_gpio_max;
+	xilinx_gpio_max = priv->gpio_min + gpio_no;
+	priv->gpio_max = xilinx_gpio_max - 1;
+
+	priv->gpio_name = calloc(gpio_no, sizeof(struct gpio_names));
+
+	INIT_LIST_HEAD(&priv->list);
+	list_add_tail(&priv->list, &gpio_list);
+
+	printf("%s: Add %s (%d-%d)\n", __func__, name,
+	       priv->gpio_min, priv->gpio_max);
+
+	/* Return the first gpio allocated for this device */
+	return priv->gpio_min;
+}
+
+/* Dual channel gpio is one IP with two independent channels */
+int gpio_alloc_dual(u32 baseaddr, const char *name, u32 gpio_no0, u32 gpio_no1)
+{
+	int ret;
+
+	ret = gpio_alloc(baseaddr, name, gpio_no0);
+	gpio_alloc(baseaddr + 8, strcat((char *)name, "_1"), gpio_no1);
+
+	/* Return the first gpio allocated for this device */
+	return ret;
+}
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 5dbdbe3..72e85a3 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -46,6 +46,7 @@
 COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
 COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
 COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
+COBJS-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c
new file mode 100644
index 0000000..ec49660
--- /dev/null
+++ b/drivers/i2c/zynq_i2c.c
@@ -0,0 +1,306 @@
+/*
+ * Driver for the Zynq-7000 PS I2C controller
+ * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
+ *
+ * Author: Joe Hershberger <joe.hershberger@ni.com>
+ * Copyright (c) 2012 Joe Hershberger.
+ *
+ * Copyright (c) 2012-2013 Xilinx, Michal Simek
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+
+/* i2c register set */
+struct zynq_i2c_registers {
+	u32 control;
+	u32 status;
+	u32 address;
+	u32 data;
+	u32 interrupt_status;
+	u32 transfer_size;
+	u32 slave_mon_pause;
+	u32 time_out;
+	u32 interrupt_mask;
+	u32 interrupt_enable;
+	u32 interrupt_disable;
+};
+
+/* Control register fields */
+#define ZYNQ_I2C_CONTROL_RW		0x00000001
+#define ZYNQ_I2C_CONTROL_MS		0x00000002
+#define ZYNQ_I2C_CONTROL_NEA		0x00000004
+#define ZYNQ_I2C_CONTROL_ACKEN		0x00000008
+#define ZYNQ_I2C_CONTROL_HOLD		0x00000010
+#define ZYNQ_I2C_CONTROL_SLVMON		0x00000020
+#define ZYNQ_I2C_CONTROL_CLR_FIFO	0x00000040
+#define ZYNQ_I2C_CONTROL_DIV_B_SHIFT	8
+#define ZYNQ_I2C_CONTROL_DIV_B_MASK	0x00003F00
+#define ZYNQ_I2C_CONTROL_DIV_A_SHIFT	14
+#define ZYNQ_I2C_CONTROL_DIV_A_MASK	0x0000C000
+
+/* Status register values */
+#define ZYNQ_I2C_STATUS_RXDV	0x00000020
+#define ZYNQ_I2C_STATUS_TXDV	0x00000040
+#define ZYNQ_I2C_STATUS_RXOVF	0x00000080
+#define ZYNQ_I2C_STATUS_BA	0x00000100
+
+/* Interrupt register fields */
+#define ZYNQ_I2C_INTERRUPT_COMP		0x00000001
+#define ZYNQ_I2C_INTERRUPT_DATA		0x00000002
+#define ZYNQ_I2C_INTERRUPT_NACK		0x00000004
+#define ZYNQ_I2C_INTERRUPT_TO		0x00000008
+#define ZYNQ_I2C_INTERRUPT_SLVRDY	0x00000010
+#define ZYNQ_I2C_INTERRUPT_RXOVF	0x00000020
+#define ZYNQ_I2C_INTERRUPT_TXOVF	0x00000040
+#define ZYNQ_I2C_INTERRUPT_RXUNF	0x00000080
+#define ZYNQ_I2C_INTERRUPT_ARBLOST	0x00000200
+
+#define ZYNQ_I2C_FIFO_DEPTH		16
+#define ZYNQ_I2C_TRANSFERT_SIZE_MAX	255 /* Controller transfer limit */
+
+#if defined(CONFIG_ZYNQ_I2C0)
+# define ZYNQ_I2C_BASE	ZYNQ_I2C_BASEADDR0
+#else
+# define ZYNQ_I2C_BASE	ZYNQ_I2C_BASEADDR1
+#endif
+
+static struct zynq_i2c_registers *zynq_i2c =
+	(struct zynq_i2c_registers *)ZYNQ_I2C_BASE;
+
+/* I2C init called by cmd_i2c when doing 'i2c reset'. */
+void i2c_init(int requested_speed, int slaveadd)
+{
+	/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
+	writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
+		(2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);
+
+	/* Enable master mode, ack, and 7-bit addressing */
+	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS |
+		ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA);
+}
+
+#ifdef DEBUG
+static void zynq_i2c_debug_status(void)
+{
+	int int_status;
+	int status;
+	int_status = readl(&zynq_i2c->interrupt_status);
+
+	status = readl(&zynq_i2c->status);
+	if (int_status || status) {
+		debug("Status: ");
+		if (int_status & ZYNQ_I2C_INTERRUPT_COMP)
+			debug("COMP ");
+		if (int_status & ZYNQ_I2C_INTERRUPT_DATA)
+			debug("DATA ");
+		if (int_status & ZYNQ_I2C_INTERRUPT_NACK)
+			debug("NACK ");
+		if (int_status & ZYNQ_I2C_INTERRUPT_TO)
+			debug("TO ");
+		if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY)
+			debug("SLVRDY ");
+		if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF)
+			debug("RXOVF ");
+		if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF)
+			debug("TXOVF ");
+		if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF)
+			debug("RXUNF ");
+		if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST)
+			debug("ARBLOST ");
+		if (status & ZYNQ_I2C_STATUS_RXDV)
+			debug("RXDV ");
+		if (status & ZYNQ_I2C_STATUS_TXDV)
+			debug("TXDV ");
+		if (status & ZYNQ_I2C_STATUS_RXOVF)
+			debug("RXOVF ");
+		if (status & ZYNQ_I2C_STATUS_BA)
+			debug("BA ");
+		debug("TS%d ", readl(&zynq_i2c->transfer_size));
+		debug("\n");
+	}
+}
+#endif
+
+/* Wait for an interrupt */
+static u32 zynq_i2c_wait(u32 mask)
+{
+	int timeout, int_status;
+
+	for (timeout = 0; timeout < 100; timeout++) {
+		udelay(100);
+		int_status = readl(&zynq_i2c->interrupt_status);
+		if (int_status & mask)
+			break;
+	}
+#ifdef DEBUG
+	zynq_i2c_debug_status();
+#endif
+	/* Clear interrupt status flags */
+	writel(int_status & mask, &zynq_i2c->interrupt_status);
+
+	return int_status & mask;
+}
+
+/*
+ * I2C probe called by cmd_i2c when doing 'i2c probe'.
+ * Begin read, nak data byte, end.
+ */
+int i2c_probe(u8 dev)
+{
+	/* Attempt to read a byte */
+	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
+		ZYNQ_I2C_CONTROL_RW);
+	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
+	writel(0xFF, &zynq_i2c->interrupt_status);
+	writel(dev, &zynq_i2c->address);
+	writel(1, &zynq_i2c->transfer_size);
+
+	return (zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP |
+		ZYNQ_I2C_INTERRUPT_NACK) &
+		ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
+}
+
+/*
+ * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
+ * Begin write, send address byte(s), begin read, receive data bytes, end.
+ */
+int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
+{
+	u32 status;
+	u32 i = 0;
+	u8 *cur_data = data;
+
+	/* Check the hardware can handle the requested bytes */
+	if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
+		return -EINVAL;
+
+	/* Write the register address */
+	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
+		ZYNQ_I2C_CONTROL_HOLD);
+	/*
+	 * Temporarily disable restart (by clearing hold)
+	 * It doesn't seem to work.
+	 */
+	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW |
+		ZYNQ_I2C_CONTROL_HOLD);
+	writel(0xFF, &zynq_i2c->interrupt_status);
+	while (alen--)
+		writel(addr >> (8*alen), &zynq_i2c->data);
+	writel(dev, &zynq_i2c->address);
+
+	/* Wait for the address to be sent */
+	if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
+		/* Release the bus */
+		clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
+		return -ETIMEDOUT;
+	}
+	debug("Device acked address\n");
+
+	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
+		ZYNQ_I2C_CONTROL_RW);
+	/* Start reading data */
+	writel(dev, &zynq_i2c->address);
+	writel(length, &zynq_i2c->transfer_size);
+
+	/* Wait for data */
+	do {
+		status = zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP |
+			ZYNQ_I2C_INTERRUPT_DATA);
+		if (!status) {
+			/* Release the bus */
+			clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
+			return -ETIMEDOUT;
+		}
+		debug("Read %d bytes\n",
+		      length - readl(&zynq_i2c->transfer_size));
+		for (; i < length - readl(&zynq_i2c->transfer_size); i++)
+			*(cur_data++) = readl(&zynq_i2c->data);
+	} while (readl(&zynq_i2c->transfer_size) != 0);
+	/* All done... release the bus */
+	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
+
+#ifdef DEBUG
+	zynq_i2c_debug_status();
+#endif
+	return 0;
+}
+
+/*
+ * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
+ * Begin write, send address byte(s), send data bytes, end.
+ */
+int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
+{
+	u8 *cur_data = data;
+
+	/* Write the register address */
+	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
+		ZYNQ_I2C_CONTROL_HOLD);
+	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
+	writel(0xFF, &zynq_i2c->interrupt_status);
+	while (alen--)
+		writel(addr >> (8*alen), &zynq_i2c->data);
+	/* Start the tranfer */
+	writel(dev, &zynq_i2c->address);
+	if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
+		/* Release the bus */
+		clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
+		return -ETIMEDOUT;
+	}
+
+	debug("Device acked address\n");
+	while (length--) {
+		writel(*(cur_data++), &zynq_i2c->data);
+		if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
+			if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
+				/* Release the bus */
+				clrbits_le32(&zynq_i2c->control,
+					     ZYNQ_I2C_CONTROL_HOLD);
+				return -ETIMEDOUT;
+			}
+		}
+	}
+
+	/* All done... release the bus */
+	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
+	/* Wait for the address and data to be sent */
+	if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP))
+		return -ETIMEDOUT;
+	return 0;
+}
+
+int i2c_set_bus_num(unsigned int bus)
+{
+	/* Only support bus 0 */
+	if (bus > 0)
+		return -1;
+	return 0;
+}
+
+unsigned int i2c_get_bus_num(void)
+{
+	/* Only support bus 0 */
+	return 0;
+}
diff --git a/drivers/input/key_matrix.c b/drivers/input/key_matrix.c
index 946a186..c900e45 100644
--- a/drivers/input/key_matrix.c
+++ b/drivers/input/key_matrix.c
@@ -154,54 +154,42 @@
 	return map;
 }
 
-int key_matrix_decode_fdt(struct key_matrix *config, const void *blob,
-			  int node)
+int key_matrix_decode_fdt(struct key_matrix *config, const void *blob, int node)
 {
 	const struct fdt_property *prop;
-	const char prefix[] = "linux,";
-	int plen = sizeof(prefix) - 1;
-	int offset;
+	int proplen;
+	uchar *plain_keycode;
 
-	/* Check each property name for ones that we understand */
-	for (offset = fdt_first_property_offset(blob, node);
-		      offset > 0;
-		      offset = fdt_next_property_offset(blob, offset)) {
-		const char *name;
-		int len;
-
-		prop = fdt_get_property_by_offset(blob, offset, NULL);
-		name = fdt_string(blob, fdt32_to_cpu(prop->nameoff));
-		len = strlen(name);
-
-		/* Name needs to match "1,<type>keymap" */
-		debug("%s: property '%s'\n", __func__, name);
-		if (strncmp(name, prefix, plen) ||
-				len < plen + 6 ||
-				strcmp(name + len - 6, "keymap"))
-			continue;
-
-		len -= plen + 6;
-		if (len == 0) {
-			config->plain_keycode = create_keymap(config,
-				(u32 *)prop->data, fdt32_to_cpu(prop->len),
-				KEY_FN, &config->fn_pos);
-		} else if (0 == strncmp(name + plen, "fn-", len)) {
-			config->fn_keycode = create_keymap(config,
-				(u32 *)prop->data, fdt32_to_cpu(prop->len),
-				-1, NULL);
-		} else {
-			debug("%s: unrecognised property '%s'\n", __func__,
-			      name);
-		}
-	}
-	debug("%s: Decoded key maps %p, %p from fdt\n", __func__,
-	      config->plain_keycode, config->fn_keycode);
-
-	if (!config->plain_keycode) {
+	prop = fdt_get_property(blob, node, "linux,keymap", &proplen);
+	/* Basic keymap is required */
+	if (!prop) {
 		debug("%s: cannot find keycode-plain map\n", __func__);
 		return -1;
 	}
 
+	plain_keycode = create_keymap(config, (u32 *)prop->data,
+		proplen, KEY_FN, &config->fn_pos);
+	config->plain_keycode = plain_keycode;
+	/* Conversion error -> fail */
+	if (!config->plain_keycode)
+		return -1;
+
+	prop = fdt_get_property(blob, node, "linux,fn-keymap", &proplen);
+	/* fn keymap is optional */
+	if (!prop)
+		goto done;
+
+	config->fn_keycode = create_keymap(config, (u32 *)prop->data,
+		proplen, -1, NULL);
+	/* Conversion error -> fail */
+	if (!config->fn_keycode) {
+		free(plain_keycode);
+		return -1;
+	}
+
+done:
+	debug("%s: Decoded key maps %p, %p from fdt\n", __func__,
+	      config->plain_keycode, config->fn_keycode);
 	return 0;
 }
 
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 8cdc3b6..5d869b4 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -28,8 +28,10 @@
 COBJS-$(CONFIG_ALI152X) += ali512x.o
 COBJS-$(CONFIG_DS4510)  += ds4510.o
 COBJS-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
+COBJS-$(CONFIG_FSL_IIM) += fsl_iim.o
 COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
 COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
+COBJS-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
 COBJS-$(CONFIG_NS87308) += ns87308.o
 COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
 COBJS-$(CONFIG_STATUS_LED) += status_led.o
diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c
new file mode 100644
index 0000000..9179fbb
--- /dev/null
+++ b/drivers/misc/fsl_iim.c
@@ -0,0 +1,286 @@
+/*
+ * (C) Copyright 2009-2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on the mpc512x iim code:
+ * Copyright 2008 Silicon Turnkey Express, Inc.
+ * Martha Marx <mmarx@silicontkx.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fuse.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#ifndef CONFIG_MPC512X
+#include <asm/arch/imx-regs.h>
+#endif
+
+/* FSL IIM-specific constants */
+#define STAT_BUSY		0x80
+#define STAT_PRGD		0x02
+#define STAT_SNSD		0x01
+
+#define STATM_PRGD_M		0x02
+#define STATM_SNSD_M		0x01
+
+#define ERR_PRGE		0x80
+#define ERR_WPE			0x40
+#define ERR_OPE			0x20
+#define ERR_RPE			0x10
+#define ERR_WLRE		0x08
+#define ERR_SNSE		0x04
+#define ERR_PARITYE		0x02
+
+#define EMASK_PRGE_M		0x80
+#define EMASK_WPE_M		0x40
+#define EMASK_OPE_M		0x20
+#define EMASK_RPE_M		0x10
+#define EMASK_WLRE_M		0x08
+#define EMASK_SNSE_M		0x04
+#define EMASK_PARITYE_M		0x02
+
+#define FCTL_DPC		0x80
+#define FCTL_PRG_LENGTH_MASK	0x70
+#define FCTL_ESNS_N		0x08
+#define FCTL_ESNS_0		0x04
+#define FCTL_ESNS_1		0x02
+#define FCTL_PRG		0x01
+
+#define UA_A_BANK_MASK		0x38
+#define UA_A_ROWH_MASK		0x07
+
+#define LA_A_ROWL_MASK		0xf8
+#define LA_A_BIT_MASK		0x07
+
+#define PREV_PROD_REV_MASK	0xf8
+#define PREV_PROD_VT_MASK	0x07
+
+/* Select the correct accessors depending on endianness */
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define iim_read32		in_le32
+#define iim_write32		out_le32
+#define iim_clrsetbits32	clrsetbits_le32
+#define iim_clrbits32		clrbits_le32
+#define iim_setbits32		setbits_le32
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#define iim_read32		in_be32
+#define iim_write32		out_be32
+#define iim_clrsetbits32	clrsetbits_be32
+#define iim_clrbits32		clrbits_be32
+#define iim_setbits32		setbits_be32
+#else
+#error Endianess is not defined: please fix to continue
+#endif
+
+/* IIM control registers */
+struct fsl_iim {
+	u32 stat;
+	u32 statm;
+	u32 err;
+	u32 emask;
+	u32 fctl;
+	u32 ua;
+	u32 la;
+	u32 sdat;
+	u32 prev;
+	u32 srev;
+	u32 prg_p;
+	u32 scs[0x1f5];
+	struct {
+		u32 word[0x100];
+	} bank[8];
+};
+
+static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
+				const char *caller)
+{
+	*regs = (struct fsl_iim *)IIM_BASE_ADDR;
+
+	if (bank >= ARRAY_SIZE((*regs)->bank) ||
+			word >= ARRAY_SIZE((*regs)->bank[0].word) ||
+			!assert) {
+		printf("fsl_iim %s(): Invalid argument\n", caller);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void clear_status(struct fsl_iim *regs)
+{
+	iim_setbits32(&regs->stat, 0);
+	iim_setbits32(&regs->err, 0);
+}
+
+static void finish_access(struct fsl_iim *regs, u32 *stat, u32 *err)
+{
+	*stat = iim_read32(&regs->stat);
+	*err = iim_read32(&regs->err);
+	clear_status(regs);
+}
+
+static int prepare_read(struct fsl_iim **regs, u32 bank, u32 word, u32 *val,
+			const char *caller)
+{
+	int ret;
+
+	ret = prepare_access(regs, bank, word, val != NULL, caller);
+	if (ret)
+		return ret;
+
+	clear_status(*regs);
+
+	return 0;
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+	struct fsl_iim *regs;
+	u32 stat, err;
+	int ret;
+
+	ret = prepare_read(&regs, bank, word, val, __func__);
+	if (ret)
+		return ret;
+
+	*val = iim_read32(&regs->bank[bank].word[word]);
+	finish_access(regs, &stat, &err);
+
+	if (err & ERR_RPE) {
+		puts("fsl_iim fuse_read(): Read protect error\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static void direct_access(struct fsl_iim *regs, u32 bank, u32 word, u32 bit,
+				u32 fctl, u32 *stat, u32 *err)
+{
+	iim_write32(&regs->ua, bank << 3 | word >> 5);
+	iim_write32(&regs->la, (word << 3 | bit) & 0xff);
+	if (fctl == FCTL_PRG)
+		iim_write32(&regs->prg_p, 0xaa);
+	iim_setbits32(&regs->fctl, fctl);
+	while (iim_read32(&regs->stat) & STAT_BUSY)
+		udelay(20);
+	finish_access(regs, stat, err);
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+	struct fsl_iim *regs;
+	u32 stat, err;
+	int ret;
+
+	ret = prepare_read(&regs, bank, word, val, __func__);
+	if (ret)
+		return ret;
+
+	direct_access(regs, bank, word, 0, FCTL_ESNS_N, &stat, &err);
+
+	if (err & ERR_SNSE) {
+		puts("fsl_iim fuse_sense(): Explicit sense cycle error\n");
+		return -EIO;
+	}
+
+	if (!(stat & STAT_SNSD)) {
+		puts("fsl_iim fuse_sense(): Explicit sense cycle did not complete\n");
+		return -EIO;
+	}
+
+	*val = iim_read32(&regs->sdat);
+	return 0;
+}
+
+static int prog_bit(struct fsl_iim *regs, u32 bank, u32 word, u32 bit)
+{
+	u32 stat, err;
+
+	clear_status(regs);
+	direct_access(regs, bank, word, bit, FCTL_PRG, &stat, &err);
+	iim_write32(&regs->prg_p, 0x00);
+
+	if (err & ERR_PRGE) {
+		puts("fsl_iim fuse_prog(): Program error\n");
+		return -EIO;
+	}
+
+	if (err & ERR_WPE) {
+		puts("fsl_iim fuse_prog(): Write protect error\n");
+		return -EIO;
+	}
+
+	if (!(stat & STAT_PRGD)) {
+		puts("fsl_iim fuse_prog(): Program did not complete\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int prepare_write(struct fsl_iim **regs, u32 bank, u32 word, u32 val,
+				const char *caller)
+{
+	return prepare_access(regs, bank, word, !(val & ~0xff), caller);
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+	struct fsl_iim *regs;
+	u32 bit;
+	int ret;
+
+	ret = prepare_write(&regs, bank, word, val, __func__);
+	if (ret)
+		return ret;
+
+	for (bit = 0; val; bit++, val >>= 1)
+		if (val & 0x01) {
+			ret = prog_bit(regs, bank, word, bit);
+			if (ret)
+				return ret;
+		}
+
+	return 0;
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+	struct fsl_iim *regs;
+	u32 stat, err;
+	int ret;
+
+	ret = prepare_write(&regs, bank, word, val, __func__);
+	if (ret)
+		return ret;
+
+	clear_status(regs);
+	iim_write32(&regs->bank[bank].word[word], val);
+	finish_access(regs, &stat, &err);
+
+	if (err & ERR_OPE) {
+		puts("fsl_iim fuse_override(): Override protect error\n");
+		return -EIO;
+	}
+
+	return 0;
+}
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
new file mode 100644
index 0000000..0095b47
--- /dev/null
+++ b/drivers/misc/mxc_ocotp.c
@@ -0,0 +1,216 @@
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on Dirk Behme's
+ * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
+ * which is based on Freescale's
+ * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
+ * which is:
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fuse.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+
+#define BO_CTRL_WR_UNLOCK		16
+#define BM_CTRL_WR_UNLOCK		0xffff0000
+#define BV_CTRL_WR_UNLOCK_KEY		0x3e77
+#define BM_CTRL_ERROR			0x00000200
+#define BM_CTRL_BUSY			0x00000100
+#define BO_CTRL_ADDR			0
+#define BM_CTRL_ADDR			0x0000007f
+
+#define BO_TIMING_STROBE_READ		16
+#define BM_TIMING_STROBE_READ		0x003f0000
+#define BV_TIMING_STROBE_READ_NS	37
+#define BO_TIMING_RELAX			12
+#define BM_TIMING_RELAX			0x0000f000
+#define BV_TIMING_RELAX_NS		17
+#define BO_TIMING_STROBE_PROG		0
+#define BM_TIMING_STROBE_PROG		0x00000fff
+#define BV_TIMING_STROBE_PROG_US	10
+
+#define BM_READ_CTRL_READ_FUSE		0x00000001
+
+#define BF(value, field)		(((value) << BO_##field) & BM_##field)
+
+#define WRITE_POSTAMBLE_US		2
+
+static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
+{
+	while (readl(&regs->ctrl) & BM_CTRL_BUSY)
+		udelay(delay_us);
+}
+
+static void clear_error(struct ocotp_regs *regs)
+{
+	writel(BM_CTRL_ERROR, &regs->ctrl_clr);
+}
+
+static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
+				int assert, const char *caller)
+{
+	*regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+
+	if (bank >= ARRAY_SIZE((*regs)->bank) ||
+			word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
+			!assert) {
+		printf("mxc_ocotp %s(): Invalid argument\n", caller);
+		return -EINVAL;
+	}
+
+	enable_ocotp_clk(1);
+
+	wait_busy(*regs, 1);
+	clear_error(*regs);
+
+	return 0;
+}
+
+static int finish_access(struct ocotp_regs *regs, const char *caller)
+{
+	u32 err;
+
+	err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
+	clear_error(regs);
+
+	enable_ocotp_clk(0);
+
+	if (err) {
+		printf("mxc_ocotp %s(): Access protect error\n", caller);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
+			const char *caller)
+{
+	return prepare_access(regs, bank, word, val != NULL, caller);
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+	struct ocotp_regs *regs;
+	int ret;
+
+	ret = prepare_read(&regs, bank, word, val, __func__);
+	if (ret)
+		return ret;
+
+	*val = readl(&regs->bank[bank].fuse_regs[word << 2]);
+
+	return finish_access(regs, __func__);
+}
+
+static void set_timing(struct ocotp_regs *regs)
+{
+	u32 ipg_clk;
+	u32 relax, strobe_read, strobe_prog;
+	u32 timing;
+
+	ipg_clk = mxc_get_clock(MXC_IPG_CLK);
+
+	relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
+	strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
+					1000000000) + 2 * (relax + 1) - 1;
+	strobe_prog = DIV_ROUND(ipg_clk * BV_TIMING_STROBE_PROG_US, 1000000) +
+			2 * (relax + 1) - 1;
+
+	timing = BF(strobe_read, TIMING_STROBE_READ) |
+			BF(relax, TIMING_RELAX) |
+			BF(strobe_prog, TIMING_STROBE_PROG);
+
+	clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
+			BM_TIMING_STROBE_PROG, timing);
+}
+
+static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
+				int write)
+{
+	u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
+	u32 addr = bank << 3 | word;
+
+	set_timing(regs);
+	clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
+			BF(wr_unlock, CTRL_WR_UNLOCK) |
+			BF(addr, CTRL_ADDR));
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+	struct ocotp_regs *regs;
+	int ret;
+
+	ret = prepare_read(&regs, bank, word, val, __func__);
+	if (ret)
+		return ret;
+
+	setup_direct_access(regs, bank, word, false);
+	writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
+	wait_busy(regs, 1);
+	*val = readl(&regs->read_fuse_data);
+
+	return finish_access(regs, __func__);
+}
+
+static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
+				const char *caller)
+{
+	return prepare_access(regs, bank, word, true, caller);
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+	struct ocotp_regs *regs;
+	int ret;
+
+	ret = prepare_write(&regs, bank, word, __func__);
+	if (ret)
+		return ret;
+
+	setup_direct_access(regs, bank, word, true);
+	writel(val, &regs->data);
+	wait_busy(regs, BV_TIMING_STROBE_PROG_US);
+	udelay(WRITE_POSTAMBLE_US);
+
+	return finish_access(regs, __func__);
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+	struct ocotp_regs *regs;
+	int ret;
+
+	ret = prepare_write(&regs, bank, word, __func__);
+	if (ret)
+		return ret;
+
+	writel(val, &regs->bank[bank].fuse_regs[word << 2]);
+
+	return finish_access(regs, __func__);
+}
diff --git a/drivers/misc/twl4030_led.c b/drivers/misc/twl4030_led.c
index 33cea11..e150d8f 100644
--- a/drivers/misc/twl4030_led.c
+++ b/drivers/misc/twl4030_led.c
@@ -42,7 +42,7 @@
 	if (ledon_mask & TWL4030_LED_LEDEN_LEDBON)
 		ledon_mask |= TWL4030_LED_LEDEN_LEDBPWM;
 
-	twl4030_i2c_write_u8(TWL4030_CHIP_LED, ledon_mask,
-			     TWL4030_LED_LEDEN);
+	twl4030_i2c_write_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN,
+			     ledon_mask);
 
 }
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 1d6faa2..24648a2 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -25,14 +25,11 @@
 
 LIB	:= $(obj)libmmc.o
 
-ifdef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
-endif
 
 COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
 COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
-COBJS-$(CONFIG_FTSDC010) += ftsdc010_esdhc.o
+COBJS-$(CONFIG_FTSDC010) += ftsdc010_mci.o
 COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
 COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
 COBJS-$(CONFIG_MMC_SPI) += mmc_spi.o
@@ -46,9 +43,11 @@
 COBJS-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
 COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
 COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o
+COBJS-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
 COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
 COBJS-$(CONFIG_DWMMC) += dw_mmc.o
 COBJS-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
+COBJS-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c
index e2379e3..5aa2184 100644
--- a/drivers/mmc/davinci_mmc.c
+++ b/drivers/mmc/davinci_mmc.c
@@ -285,8 +285,11 @@
 			 */
 			if (bytes_left > fifo_bytes)
 				dmmc_wait_fifo_status(regs, 0x4a);
-			else if (bytes_left == fifo_bytes)
+			else if (bytes_left == fifo_bytes) {
 				dmmc_wait_fifo_status(regs, 0x40);
+				if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD)
+					udelay(600);
+			}
 
 			for (i = 0; bytes_left && (i < fifo_words); i++) {
 				cmddata = get_val(&regs->mmcdrr);
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index e945c0a..861f4b9 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -178,7 +178,7 @@
 	int timeout;
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
-#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 	uint wml_value;
 
 	wml_value = data->blocksize/4;
@@ -601,8 +601,7 @@
 {
 	struct fsl_esdhc_cfg *cfg;
 
-	cfg = malloc(sizeof(struct fsl_esdhc_cfg));
-	memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
+	cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
 	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
 	cfg->sdhc_clk = gd->arch.sdhc_clk;
 	return fsl_esdhc_initialize(bis, cfg);
diff --git a/drivers/mmc/ftsdc010_esdhc.c b/drivers/mmc/ftsdc010_esdhc.c
deleted file mode 100644
index 42f0e0c..0000000
--- a/drivers/mmc/ftsdc010_esdhc.c
+++ /dev/null
@@ -1,687 +0,0 @@
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <mmc.h>
-
-#include <asm/io.h>
-#include <faraday/ftsdc010.h>
-
-/*
- * supported mmc hosts
- * setting the number CONFIG_FTSDC010_NUMBER in your configuration file.
- */
-static struct mmc ftsdc010_dev[CONFIG_FTSDC010_NUMBER];
-static struct mmc_host ftsdc010_host[CONFIG_FTSDC010_NUMBER];
-
-static struct ftsdc010_mmc *ftsdc010_get_base_mmc(int dev_index)
-{
-	return (struct ftsdc010_mmc *)CONFIG_FTSDC010_BASE + dev_index;
-}
-
-#ifdef DEBUG
-static void ftsdc010_dump_reg(struct mmc_host *host)
-{
-	debug("cmd: %08x\n",		readl(&host->reg->cmd));
-	debug("argu: %08x\n",		readl(&host->reg->argu));
-	debug("rsp0: %08x\n",		readl(&host->reg->rsp0));
-	debug("rsp1: %08x\n",		readl(&host->reg->rsp1));
-	debug("rsp2: %08x\n",		readl(&host->reg->rsp2));
-	debug("rsp3: %08x\n",		readl(&host->reg->rsp3));
-	debug("rsp_cmd: %08x\n",	readl(&host->reg->rsp_cmd));
-	debug("dcr: %08x\n",		readl(&host->reg->dcr));
-	debug("dtr: %08x\n",		readl(&host->reg->dtr));
-	debug("dlr: %08x\n",		readl(&host->reg->dlr));
-	debug("status: %08x\n",		readl(&host->reg->status));
-	debug("clr: %08x\n",		readl(&host->reg->clr));
-	debug("int_mask: %08x\n",	readl(&host->reg->int_mask));
-	debug("pcr: %08x\n",		readl(&host->reg->pcr));
-	debug("ccr: %08x\n",		readl(&host->reg->ccr));
-	debug("bwr: %08x\n",		readl(&host->reg->bwr));
-	debug("dwr: %08x\n",		readl(&host->reg->dwr));
-	debug("feature: %08x\n",	readl(&host->reg->feature));
-	debug("rev: %08x\n",		readl(&host->reg->rev));
-}
-#endif
-
-static unsigned int enable_imask(struct ftsdc010_mmc *reg, unsigned int imask)
-{
-	unsigned int newmask;
-
-	newmask = readl(&reg->int_mask);
-	newmask |= imask;
-
-	writel(newmask, &reg->int_mask);
-
-	return newmask;
-}
-
-static void ftsdc010_pio_read(struct mmc_host *host, char *buf, unsigned int size)
-{
-	unsigned int fifo;
-	unsigned int fifo_words;
-	unsigned int *ptr;
-	unsigned int status;
-	unsigned int retry = 0;
-
-	/* get_data_buffer */
-	ptr = (unsigned int *)buf;
-
-	while (size) {
-		status = readl(&host->reg->status);
-		debug("%s: size: %08x\n", __func__, size);
-
-		if (status & FTSDC010_STATUS_FIFO_ORUN) {
-
-			debug("%s: FIFO OVERRUN: sta: %08x\n",
-					__func__, status);
-
-			fifo = host->fifo_len > size ?
-				size : host->fifo_len;
-
-			size -= fifo;
-
-			fifo_words = fifo >> 2;
-
-			while (fifo_words--)
-				*ptr++ = readl(&host->reg->dwr);
-
-			/*
-			 * for adding some delays for SD card to put
-			 * data into FIFO again
-			 */
-			udelay(4*FTSDC010_DELAY_UNIT);
-
-#ifdef CONFIG_FTSDC010_SDIO
-			/* sdio allow non-power-of-2 blksz */
-			if (fifo & 3) {
-				unsigned int n = fifo & 3;
-				unsigned int data = readl(&host->reg->dwr);
-
-				unsigned char *p = (unsigned char *)ptr;
-
-				while (n--) {
-					*p++ = data;
-					data >>= 8;
-				}
-			}
-#endif
-		} else {
-			udelay(1);
-			if (++retry >= FTSDC010_PIO_RETRY) {
-				debug("%s: PIO_RETRY timeout\n", __func__);
-				return;
-			}
-		}
-	}
-}
-
-static void ftsdc010_pio_write(struct mmc_host *host, const char *buf,
-			unsigned int size)
-{
-	unsigned int fifo;
-	unsigned int *ptr;
-	unsigned int status;
-	unsigned int retry = 0;
-
-	/* get data buffer */
-	ptr = (unsigned int *)buf;
-
-	while (size) {
-		status = readl(&host->reg->status);
-
-		if (status & FTSDC010_STATUS_FIFO_URUN) {
-			fifo = host->fifo_len > size ?
-				size : host->fifo_len;
-
-			size -= fifo;
-
-			fifo = (fifo + 3) >> 2;
-
-			while (fifo--) {
-				writel(*ptr, &host->reg->dwr);
-				ptr++;
-			}
-		} else {
-			udelay(1);
-			if (++retry >= FTSDC010_PIO_RETRY) {
-				debug("%s: PIO_RETRY timeout\n", __func__);
-				return;
-			}
-		}
-	}
-}
-
-static int ftsdc010_check_rsp(struct mmc *mmc, struct mmc_cmd *cmd,
-			struct mmc_data *data)
-{
-	struct mmc_host *host = mmc->priv;
-	unsigned int sta, clear;
-
-	sta = readl(&host->reg->status);
-	debug("%s: sta: %08x cmd %d\n", __func__, sta, cmd->cmdidx);
-
-	/* check RSP TIMEOUT or FAIL */
-	if (sta & FTSDC010_STATUS_RSP_TIMEOUT) {
-		/* RSP TIMEOUT */
-		debug("%s: RSP timeout: sta: %08x\n", __func__, sta);
-
-		clear |= FTSDC010_CLR_RSP_TIMEOUT;
-		writel(clear, &host->reg->clr);
-
-		return TIMEOUT;
-	} else if (sta & FTSDC010_STATUS_RSP_CRC_FAIL) {
-		/* clear response fail bit */
-		debug("%s: RSP CRC FAIL: sta: %08x\n", __func__, sta);
-
-		clear |= FTSDC010_CLR_RSP_CRC_FAIL;
-		writel(clear, &host->reg->clr);
-
-		return COMM_ERR;
-	} else if (sta & FTSDC010_STATUS_RSP_CRC_OK) {
-
-		/* clear response CRC OK bit */
-		clear |= FTSDC010_CLR_RSP_CRC_OK;
-	}
-
-	writel(clear, &host->reg->clr);
-	return 0;
-}
-
-static int ftsdc010_check_data(struct mmc *mmc, struct mmc_cmd *cmd,
-			struct mmc_data *data)
-{
-	struct mmc_host *host = mmc->priv;
-	unsigned int sta, clear;
-
-	sta = readl(&host->reg->status);
-	debug("%s: sta: %08x cmd %d\n", __func__, sta, cmd->cmdidx);
-
-	/* check DATA TIMEOUT or FAIL */
-	if (data) {
-
-		/* Transfer Complete */
-		if (sta & FTSDC010_STATUS_DATA_END)
-			clear |= FTSDC010_STATUS_DATA_END;
-
-		/* Data CRC_OK */
-		if (sta & FTSDC010_STATUS_DATA_CRC_OK)
-			clear |= FTSDC010_STATUS_DATA_CRC_OK;
-
-		/* DATA TIMEOUT or DATA CRC FAIL */
-		if (sta & FTSDC010_STATUS_DATA_TIMEOUT) {
-			/* DATA TIMEOUT */
-			debug("%s: DATA TIMEOUT: sta: %08x\n", __func__, sta);
-
-			clear |= FTSDC010_STATUS_DATA_TIMEOUT;
-			writel(clear, &host->reg->clr);
-
-			return TIMEOUT;
-		} else if (sta & FTSDC010_STATUS_DATA_CRC_FAIL) {
-			/* DATA CRC FAIL */
-			debug("%s: DATA CRC FAIL: sta: %08x\n", __func__, sta);
-
-			clear |= FTSDC010_STATUS_DATA_CRC_FAIL;
-			writel(clear, &host->reg->clr);
-
-			return COMM_ERR;
-		}
-		writel(clear, &host->reg->clr);
-	}
-	return 0;
-}
-
-static int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
-			struct mmc_data *data)
-{
-	struct mmc_host *host = mmc->priv;
-
-#ifdef CONFIG_FTSDC010_SDIO
-	unsigned int scon;
-#endif
-	unsigned int ccon;
-	unsigned int mask, tmpmask;
-	unsigned int ret;
-	unsigned int sta, i;
-
-	ret = 0;
-
-	if (data)
-		mask = FTSDC010_INT_MASK_RSP_TIMEOUT;
-	else if (cmd->resp_type & MMC_RSP_PRESENT)
-		mask = FTSDC010_INT_MASK_RSP_TIMEOUT;
-	else
-		mask = FTSDC010_INT_MASK_CMD_SEND;
-
-	/* write argu reg */
-	debug("%s: argu: %08x\n", __func__, host->reg->argu);
-	writel(cmd->cmdarg, &host->reg->argu);
-
-	/* setup commnad */
-	ccon = FTSDC010_CMD_IDX(cmd->cmdidx);
-
-	/* setup command flags */
-	ccon |= FTSDC010_CMD_CMD_EN;
-
-	/*
-	 * This hardware didn't support specific commands for mapping
-	 * MMC_RSP_BUSY and MMC_RSP_OPCODE. Hence we don't deal with it.
-	 */
-	if (cmd->resp_type & MMC_RSP_PRESENT) {
-		ccon |= FTSDC010_CMD_NEED_RSP;
-		mask |= FTSDC010_INT_MASK_RSP_CRC_OK |
-			FTSDC010_INT_MASK_RSP_CRC_FAIL;
-	}
-
-	if (cmd->resp_type & MMC_RSP_136)
-		ccon |= FTSDC010_CMD_LONG_RSP;
-
-	/* In Linux driver, MMC_CMD_APP_CMD is checked in last_opcode */
-	if (host->last_opcode == MMC_CMD_APP_CMD)
-		ccon |= FTSDC010_CMD_APP_CMD;
-
-#ifdef CONFIG_FTSDC010_SDIO
-	scon = readl(&host->reg->sdio_ctrl1);
-	if (host->card_type == MMC_TYPE_SDIO)
-		scon |= FTSDC010_SDIO_CTRL1_SDIO_ENABLE;
-	else
-		scon &= ~FTSDC010_SDIO_CTRL1_SDIO_ENABLE;
-	writel(scon, &host->reg->sdio_ctrl1);
-#endif
-
-	/* record last opcode for specifing the command type to hardware */
-	host->last_opcode = cmd->cmdidx;
-
-	/* write int_mask reg */
-	tmpmask = readl(&host->reg->int_mask);
-	tmpmask |= mask;
-	writel(tmpmask, &host->reg->int_mask);
-
-	/* write cmd reg */
-	debug("%s: ccon: %08x\n", __func__, ccon);
-	writel(ccon, &host->reg->cmd);
-
-	/* check CMD_SEND */
-	for (i = 0; i < FTSDC010_CMD_RETRY; i++) {
-		/*
-		 * If we read status register too fast
-		 * will lead hardware error and the RSP_TIMEOUT
-		 * flag will be raised incorrectly.
-		 */
-		udelay(16*FTSDC010_DELAY_UNIT);
-		sta = readl(&host->reg->status);
-
-		/* Command Complete */
-		/*
-		 * Note:
-		 *	Do not clear FTSDC010_CLR_CMD_SEND flag.
-		 *	(by writing FTSDC010_CLR_CMD_SEND bit to clear register)
-		 *	It will make the driver becomes very slow.
-		 *	If the operation hasn't been finished, hardware will
-		 *	clear this bit automatically.
-		 *	In origin, the driver will clear this flag if there is
-		 *	no data need to be read.
-		 */
-		if (sta & FTSDC010_STATUS_CMD_SEND)
-			break;
-	}
-
-	if (i > FTSDC010_CMD_RETRY) {
-		printf("%s: send command timeout\n", __func__);
-		return TIMEOUT;
-	}
-
-	/* check rsp status */
-	ret = ftsdc010_check_rsp(mmc, cmd, data);
-	if (ret)
-		return ret;
-
-	/* read response if we have RSP_OK */
-	if (ccon & FTSDC010_CMD_LONG_RSP) {
-		cmd->response[0] = readl(&host->reg->rsp3);
-		cmd->response[1] = readl(&host->reg->rsp2);
-		cmd->response[2] = readl(&host->reg->rsp1);
-		cmd->response[3] = readl(&host->reg->rsp0);
-	} else {
-		cmd->response[0] = readl(&host->reg->rsp0);
-	}
-
-	/* read/write data */
-	if (data && (data->flags & MMC_DATA_READ)) {
-		ftsdc010_pio_read(host, data->dest,
-				data->blocksize * data->blocks);
-	} else if (data && (data->flags & MMC_DATA_WRITE)) {
-		ftsdc010_pio_write(host, data->src,
-				data->blocksize * data->blocks);
-	}
-
-	/* check data status */
-	if (data) {
-		ret = ftsdc010_check_data(mmc, cmd, data);
-		if (ret)
-			return ret;
-	}
-
-	udelay(FTSDC010_DELAY_UNIT);
-	return ret;
-}
-
-static unsigned int cal_blksz(unsigned int blksz)
-{
-	unsigned int blksztwo = 0;
-
-	while (blksz >>= 1)
-		blksztwo++;
-
-	return blksztwo;
-}
-
-static int ftsdc010_setup_data(struct mmc *mmc, struct mmc_data *data)
-{
-	struct mmc_host *host = mmc->priv;
-	unsigned int dcon, newmask;
-
-	/* configure data transfer paramter */
-	if (!data)
-		return 0;
-
-	if (((data->blocksize - 1) & data->blocksize) != 0) {
-		printf("%s: can't do non-power-of 2 sized block transfers"
-			" (blksz %d)\n", __func__, data->blocksize);
-		return -1;
-	}
-
-	/*
-	 * We cannot deal with unaligned blocks with more than
-	 * one block being transfered.
-	 */
-	if ((data->blocksize <= 2) && (data->blocks > 1)) {
-			printf("%s: can't do non-word sized block transfers"
-				" (blksz %d)\n", __func__, data->blocksize);
-			return -1;
-	}
-
-	/* data length */
-	dcon = data->blocksize * data->blocks;
-	writel(dcon, &host->reg->dlr);
-
-	/* write data control */
-	dcon = cal_blksz(data->blocksize);
-
-	/* add to IMASK register */
-	newmask = (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT);
-
-	/*
-	 * enable UNDERRUN will trigger interrupt immediatedly
-	 * So setup it when rsp is received successfully
-	 */
-	if (data->flags & MMC_DATA_WRITE) {
-		dcon |= FTSDC010_DCR_DATA_WRITE;
-	} else {
-		dcon &= ~FTSDC010_DCR_DATA_WRITE;
-		newmask |= FTSDC010_STATUS_FIFO_ORUN;
-	}
-	enable_imask(host->reg, newmask);
-
-#ifdef CONFIG_FTSDC010_SDIO
-	/* always reset fifo since last transfer may fail */
-	dcon |= FTSDC010_DCR_FIFO_RST;
-
-	if (data->blocks > 1)
-		dcon |= FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE;
-#endif
-
-	/* enable data transfer which will be pended until cmd is send */
-	dcon |= FTSDC010_DCR_DATA_EN;
-	writel(dcon, &host->reg->dcr);
-
-	return 0;
-}
-
-static int ftsdc010_send_request(struct mmc *mmc, struct mmc_cmd *cmd,
-			struct mmc_data *data)
-{
-	int ret;
-
-	if (data) {
-		ret = ftsdc010_setup_data(mmc, data);
-
-		if (ret) {
-			printf("%s: setup data error\n", __func__);
-			return -1;
-		}
-
-		if ((data->flags & MMC_DATA_BOTH_DIR) == MMC_DATA_BOTH_DIR) {
-			printf("%s: data is both direction\n", __func__);
-			return -1;
-		}
-	}
-
-	/* Send command */
-	ret = ftsdc010_send_cmd(mmc, cmd, data);
-	return ret;
-}
-
-static int ftsdc010_card_detect(struct mmc *mmc)
-{
-	struct mmc_host *host = mmc->priv;
-	unsigned int sta;
-
-	sta = readl(&host->reg->status);
-	debug("%s: card status: %08x\n", __func__, sta);
-
-	return (sta & FTSDC010_STATUS_CARD_DETECT) ? 0 : 1;
-}
-
-static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
-			struct mmc_data *data)
-{
-	int ret;
-
-	if (ftsdc010_card_detect(mmc) == 0) {
-		printf("%s: no medium present\n", __func__);
-		return -1;
-	} else {
-		ret = ftsdc010_send_request(mmc, cmd, data);
-		return ret;
-	}
-}
-
-static void ftsdc010_set_clk(struct mmc *mmc)
-{
-	struct mmc_host *host = mmc->priv;
-	unsigned char clk_div;
-	unsigned int real_rate;
-	unsigned int clock;
-
-	debug("%s: mmc_set_clock: %x\n", __func__, mmc->clock);
-	clock = readl(&host->reg->ccr);
-
-	if (mmc->clock == 0) {
-		real_rate = 0;
-		clock |= FTSDC010_CCR_CLK_DIS;
-	} else {
-		debug("%s, mmc->clock: %08x, origin clock: %08x\n",
-			 __func__, mmc->clock, clock);
-
-		for (clk_div = 0; clk_div <= 127; clk_div++) {
-			real_rate = (CONFIG_SYS_CLK_FREQ / 2) /
-					(2 * (clk_div + 1));
-
-			if (real_rate <= mmc->clock)
-				break;
-		}
-
-		debug("%s: computed real_rate: %x, clk_div: %x\n",
-			 __func__, real_rate, clk_div);
-
-		if (clk_div > 127)
-			debug("%s: no match clock rate, %x\n",
-				__func__, mmc->clock);
-
-		clock = (clock & ~FTSDC010_CCR_CLK_DIV(0x7f)) |
-				FTSDC010_CCR_CLK_DIV(clk_div);
-
-		clock &= ~FTSDC010_CCR_CLK_DIS;
-	}
-
-	debug("%s, set clock: %08x\n", __func__, clock);
-	writel(clock, &host->reg->ccr);
-}
-
-static void ftsdc010_set_ios(struct mmc *mmc)
-{
-	struct mmc_host *host = mmc->priv;
-	unsigned int power;
-	unsigned long val;
-	unsigned int bus_width;
-
-	debug("%s: bus_width: %x, clock: %d\n",
-		__func__, mmc->bus_width, mmc->clock);
-
-	/* set pcr: power on */
-	power = readl(&host->reg->pcr);
-	power |= FTSDC010_PCR_POWER_ON;
-	writel(power, &host->reg->pcr);
-
-	if (mmc->clock)
-		ftsdc010_set_clk(mmc);
-
-	/* set bwr: bus width reg */
-	bus_width = readl(&host->reg->bwr);
-	bus_width &= ~(FTSDC010_BWR_WIDE_8_BUS | FTSDC010_BWR_WIDE_4_BUS |
-			FTSDC010_BWR_SINGLE_BUS);
-
-	if (mmc->bus_width == 8)
-		bus_width |= FTSDC010_BWR_WIDE_8_BUS;
-	else if (mmc->bus_width == 4)
-		bus_width |= FTSDC010_BWR_WIDE_4_BUS;
-	else
-		bus_width |= FTSDC010_BWR_SINGLE_BUS;
-
-	writel(bus_width, &host->reg->bwr);
-
-	/* set fifo depth */
-	val = readl(&host->reg->feature);
-	host->fifo_len = FTSDC010_FEATURE_FIFO_DEPTH(val) * 4; /* 4 bytes */
-
-	/* set data timeout register */
-	val = -1;
-	writel(val, &host->reg->dtr);
-}
-
-static void ftsdc010_reset(struct mmc_host *host)
-{
-	unsigned int timeout;
-	unsigned int sta;
-
-	/* Do SDC_RST: Software reset for all register */
-	writel(FTSDC010_CMD_SDC_RST, &host->reg->cmd);
-
-	host->clock = 0;
-
-	/* this hardware has no reset finish flag to read */
-	/* wait 100ms maximum */
-	timeout = 100;
-
-	/* hw clears the bit when it's done */
-	while (readl(&host->reg->dtr) != 0) {
-		if (timeout == 0) {
-			printf("%s: reset timeout error\n", __func__);
-			return;
-		}
-		timeout--;
-		udelay(10*FTSDC010_DELAY_UNIT);
-	}
-
-	sta = readl(&host->reg->status);
-	if (sta & FTSDC010_STATUS_CARD_CHANGE)
-		writel(FTSDC010_CLR_CARD_CHANGE, &host->reg->clr);
-}
-
-static int ftsdc010_core_init(struct mmc *mmc)
-{
-	struct mmc_host *host = mmc->priv;
-	unsigned int mask;
-	unsigned int major, minor, revision;
-
-	/* get hardware version */
-	host->version = readl(&host->reg->rev);
-
-	major = FTSDC010_REV_MAJOR(host->version);
-	minor = FTSDC010_REV_MINOR(host->version);
-	revision = FTSDC010_REV_REVISION(host->version);
-
-	printf("ftsdc010 hardware ver: %d_%d_r%d\n", major, minor, revision);
-
-	/* Interrupt MASK register init - mask all */
-	writel(0x0, &host->reg->int_mask);
-
-	mask = FTSDC010_INT_MASK_CMD_SEND |
-		FTSDC010_INT_MASK_DATA_END |
-		FTSDC010_INT_MASK_CARD_CHANGE;
-#ifdef CONFIG_FTSDC010_SDIO
-	mask |= FTSDC010_INT_MASK_CP_READY |
-		FTSDC010_INT_MASK_CP_BUF_READY |
-		FTSDC010_INT_MASK_PLAIN_TEXT_READY |
-		FTSDC010_INT_MASK_SDIO_IRPT;
-#endif
-
-	writel(mask, &host->reg->int_mask);
-
-	return 0;
-}
-
-int ftsdc010_mmc_init(int dev_index)
-{
-	struct mmc *mmc;
-	struct mmc_host *host;
-
-	mmc = &ftsdc010_dev[dev_index];
-
-	sprintf(mmc->name, "FTSDC010 SD/MMC");
-	mmc->priv = &ftsdc010_host[dev_index];
-	mmc->send_cmd = ftsdc010_request;
-	mmc->set_ios = ftsdc010_set_ios;
-	mmc->init = ftsdc010_core_init;
-	mmc->getcd = NULL;
-	mmc->getwp = NULL;
-
-	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
-
-	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
-
-	mmc->f_min = CONFIG_SYS_CLK_FREQ / 2 / (2*128);
-	mmc->f_max = CONFIG_SYS_CLK_FREQ / 2 / 2;
-
-	ftsdc010_host[dev_index].clock = 0;
-	ftsdc010_host[dev_index].reg = ftsdc010_get_base_mmc(dev_index);
-	mmc_register(mmc);
-
-	/* reset mmc */
-	host = (struct mmc_host *)mmc->priv;
-	ftsdc010_reset(host);
-
-	return 0;
-}
diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c
new file mode 100644
index 0000000..562b14a
--- /dev/null
+++ b/drivers/mmc/ftsdc010_mci.c
@@ -0,0 +1,377 @@
+/*
+ * Faraday MMC/SD Host Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <part.h>
+#include <mmc.h>
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/byteorder.h>
+#include <faraday/ftsdc010.h>
+
+#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
+#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
+
+struct ftsdc010_chip {
+	void __iomem *regs;
+	uint32_t wprot;   /* write protected (locked) */
+	uint32_t rate;    /* actual SD clock in Hz */
+	uint32_t sclk;    /* FTSDC010 source clock in Hz */
+	uint32_t fifo;    /* fifo depth in bytes */
+	uint32_t acmd;
+};
+
+static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
+{
+	struct ftsdc010_chip *chip = mmc->priv;
+	struct ftsdc010_mmc __iomem *regs = chip->regs;
+	int ret = TIMEOUT;
+	uint32_t ts, st;
+	uint32_t cmd   = FTSDC010_CMD_IDX(mmc_cmd->cmdidx);
+	uint32_t arg   = mmc_cmd->cmdarg;
+	uint32_t flags = mmc_cmd->resp_type;
+
+	cmd |= FTSDC010_CMD_CMD_EN;
+
+	if (chip->acmd) {
+		cmd |= FTSDC010_CMD_APP_CMD;
+		chip->acmd = 0;
+	}
+
+	if (flags & MMC_RSP_PRESENT)
+		cmd |= FTSDC010_CMD_NEED_RSP;
+
+	if (flags & MMC_RSP_136)
+		cmd |= FTSDC010_CMD_LONG_RSP;
+
+	writel(FTSDC010_STATUS_RSP_MASK | FTSDC010_STATUS_CMD_SEND,
+		&regs->clr);
+	writel(arg, &regs->argu);
+	writel(cmd, &regs->cmd);
+
+	if (!(flags & (MMC_RSP_PRESENT | MMC_RSP_136))) {
+		for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+			if (readl(&regs->status) & FTSDC010_STATUS_CMD_SEND) {
+				writel(FTSDC010_STATUS_CMD_SEND, &regs->clr);
+				ret = 0;
+				break;
+			}
+		}
+	} else {
+		st = 0;
+		for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+			st = readl(&regs->status);
+			writel(st & FTSDC010_STATUS_RSP_MASK, &regs->clr);
+			if (st & FTSDC010_STATUS_RSP_MASK)
+				break;
+		}
+		if (st & FTSDC010_STATUS_RSP_CRC_OK) {
+			if (flags & MMC_RSP_136) {
+				mmc_cmd->response[0] = readl(&regs->rsp3);
+				mmc_cmd->response[1] = readl(&regs->rsp2);
+				mmc_cmd->response[2] = readl(&regs->rsp1);
+				mmc_cmd->response[3] = readl(&regs->rsp0);
+			} else {
+				mmc_cmd->response[0] = readl(&regs->rsp0);
+			}
+			ret = 0;
+		} else {
+			debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n",
+				mmc_cmd->cmdidx, st);
+		}
+	}
+
+	if (ret) {
+		debug("ftsdc010: cmd timeout (op code=%d)\n",
+			mmc_cmd->cmdidx);
+	} else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) {
+		chip->acmd = 1;
+	}
+
+	return ret;
+}
+
+static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate)
+{
+	struct ftsdc010_chip *chip = mmc->priv;
+	struct ftsdc010_mmc __iomem *regs = chip->regs;
+	uint32_t div;
+
+	for (div = 0; div < 0x7f; ++div) {
+		if (rate >= chip->sclk / (2 * (div + 1)))
+			break;
+	}
+	chip->rate = chip->sclk / (2 * (div + 1));
+
+	writel(FTSDC010_CCR_CLK_DIV(div), &regs->ccr);
+
+	if (IS_SD(mmc)) {
+		setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_SD);
+
+		if (chip->rate > 25000000)
+			setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
+		else
+			clrbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
+	}
+}
+
+static inline int ftsdc010_is_ro(struct mmc *mmc)
+{
+	struct ftsdc010_chip *chip = mmc->priv;
+	const uint8_t *csd = (const uint8_t *)mmc->csd;
+
+	return chip->wprot || (csd[1] & 0x30);
+}
+
+static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
+{
+	int ret = TIMEOUT;
+	uint32_t st, ts;
+
+	for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+		st = readl(&regs->status);
+		if (!(st & mask))
+			continue;
+		writel(st & mask, &regs->clr);
+		ret = 0;
+		break;
+	}
+
+	if (ret)
+		debug("ftsdc010: wait st(0x%x) timeout\n", mask);
+
+	return ret;
+}
+
+/*
+ * u-boot mmc api
+ */
+
+static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
+	struct mmc_data *data)
+{
+	int ret = UNUSABLE_ERR;
+	uint32_t len = 0;
+	struct ftsdc010_chip *chip = mmc->priv;
+	struct ftsdc010_mmc __iomem *regs = chip->regs;
+
+	if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) {
+		printf("ftsdc010: the card is write protected!\n");
+		return ret;
+	}
+
+	if (data) {
+		uint32_t dcr;
+
+		len = data->blocksize * data->blocks;
+
+		/* 1. data disable + fifo reset */
+		writel(FTSDC010_DCR_FIFO_RST, &regs->dcr);
+
+		/* 2. clear status register */
+		writel(FTSDC010_STATUS_DATA_MASK | FTSDC010_STATUS_FIFO_URUN
+			| FTSDC010_STATUS_FIFO_ORUN, &regs->clr);
+
+		/* 3. data timeout (1 sec) */
+		writel(chip->rate, &regs->dtr);
+
+		/* 4. data length (bytes) */
+		writel(len, &regs->dlr);
+
+		/* 5. data enable */
+		dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN;
+		if (data->flags & MMC_DATA_WRITE)
+			dcr |= FTSDC010_DCR_DATA_WRITE;
+		writel(dcr, &regs->dcr);
+	}
+
+	ret = ftsdc010_send_cmd(mmc, cmd);
+	if (ret) {
+		printf("ftsdc010: CMD%d failed\n", cmd->cmdidx);
+		return ret;
+	}
+
+	if (!data)
+		return ret;
+
+	if (data->flags & MMC_DATA_WRITE) {
+		const uint8_t *buf = (const uint8_t *)data->src;
+
+		while (len > 0) {
+			int wlen;
+
+			/* wait for tx ready */
+			ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_URUN);
+			if (ret)
+				break;
+
+			/* write bytes to ftsdc010 */
+			for (wlen = 0; wlen < len && wlen < chip->fifo; ) {
+				writel(*(uint32_t *)buf, &regs->dwr);
+				buf  += 4;
+				wlen += 4;
+			}
+
+			len -= wlen;
+		}
+
+	} else {
+		uint8_t *buf = (uint8_t *)data->dest;
+
+		while (len > 0) {
+			int rlen;
+
+			/* wait for rx ready */
+			ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_ORUN);
+			if (ret)
+				break;
+
+			/* fetch bytes from ftsdc010 */
+			for (rlen = 0; rlen < len && rlen < chip->fifo; ) {
+				*(uint32_t *)buf = readl(&regs->dwr);
+				buf  += 4;
+				rlen += 4;
+			}
+
+			len -= rlen;
+		}
+
+	}
+
+	if (!ret) {
+		ret = ftsdc010_wait(regs,
+			FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_ERROR);
+	}
+
+	return ret;
+}
+
+static void ftsdc010_set_ios(struct mmc *mmc)
+{
+	struct ftsdc010_chip *chip = mmc->priv;
+	struct ftsdc010_mmc __iomem *regs = chip->regs;
+
+	ftsdc010_clkset(mmc, mmc->clock);
+
+	clrbits_le32(&regs->bwr, FTSDC010_BWR_MODE_MASK);
+	switch (mmc->bus_width) {
+	case 4:
+		setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_4BIT);
+		break;
+	case 8:
+		setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_8BIT);
+		break;
+	default:
+		setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_1BIT);
+		break;
+	}
+}
+
+static int ftsdc010_init(struct mmc *mmc)
+{
+	struct ftsdc010_chip *chip = mmc->priv;
+	struct ftsdc010_mmc __iomem *regs = chip->regs;
+	uint32_t ts;
+
+	if (readl(&regs->status) & FTSDC010_STATUS_CARD_DETECT)
+		return NO_CARD_ERR;
+
+	if (readl(&regs->status) & FTSDC010_STATUS_WRITE_PROT) {
+		printf("ftsdc010: write protected\n");
+		chip->wprot = 1;
+	}
+
+	chip->fifo = (readl(&regs->feature) & 0xff) << 2;
+
+	/* 1. chip reset */
+	writel(FTSDC010_CMD_SDC_RST, &regs->cmd);
+	for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) {
+		if (readl(&regs->cmd) & FTSDC010_CMD_SDC_RST)
+			continue;
+		break;
+	}
+	if (readl(&regs->cmd) & FTSDC010_CMD_SDC_RST) {
+		printf("ftsdc010: reset failed\n");
+		return UNUSABLE_ERR;
+	}
+
+	/* 2. enter low speed mode (400k card detection) */
+	ftsdc010_clkset(mmc, 400000);
+
+	/* 3. interrupt disabled */
+	writel(0, &regs->int_mask);
+
+	return 0;
+}
+
+int ftsdc010_mmc_init(int devid)
+{
+	struct mmc *mmc;
+	struct ftsdc010_chip *chip;
+	struct ftsdc010_mmc __iomem *regs;
+#ifdef CONFIG_FTSDC010_BASE_LIST
+	uint32_t base_list[] = CONFIG_FTSDC010_BASE_LIST;
+
+	if (devid < 0 || devid >= ARRAY_SIZE(base_list))
+		return -1;
+	regs = (void __iomem *)base_list[devid];
+#else
+	regs = (void __iomem *)(CONFIG_FTSDC010_BASE + (devid << 20));
+#endif
+
+	mmc = malloc(sizeof(struct mmc));
+	if (!mmc)
+		return -ENOMEM;
+	memset(mmc, 0, sizeof(struct mmc));
+
+	chip = malloc(sizeof(struct ftsdc010_chip));
+	if (!chip) {
+		free(mmc);
+		return -ENOMEM;
+	}
+	memset(chip, 0, sizeof(struct ftsdc010_chip));
+
+	chip->regs = regs;
+	mmc->priv  = chip;
+
+	sprintf(mmc->name, "ftsdc010");
+	mmc->send_cmd  = ftsdc010_request;
+	mmc->set_ios   = ftsdc010_set_ios;
+	mmc->init      = ftsdc010_init;
+
+	mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
+	switch (readl(&regs->bwr) & FTSDC010_BWR_CAPS_MASK) {
+	case FTSDC010_BWR_CAPS_4BIT:
+		mmc->host_caps |= MMC_MODE_4BIT;
+		break;
+	case FTSDC010_BWR_CAPS_8BIT:
+		mmc->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
+		break;
+	default:
+		break;
+	}
+
+#ifdef CONFIG_SYS_CLK_FREQ
+	chip->sclk = CONFIG_SYS_CLK_FREQ;
+#else
+	chip->sclk = clk_get_rate("SDC");
+#endif
+
+	mmc->voltages  = MMC_VDD_32_33 | MMC_VDD_33_34;
+	mmc->f_max     = chip->sclk / 2;
+	mmc->f_min     = chip->sclk / 0x100;
+	mmc->block_dev.part_type = PART_TYPE_DOS;
+
+	mmc_register(mmc);
+
+	return 0;
+}
diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index 70a9f91..77ebf17 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -50,6 +50,12 @@
 
 static int initialized = 0;
 
+/* Read Atmel MCI IP version */
+static unsigned int atmel_mci_get_version(struct atmel_mci *mci)
+{
+	return readl(&mci->version) & 0x00000fff;
+}
+
 /*
  * Print command and status:
  *
@@ -205,7 +211,10 @@
 	/* Wait for the command to complete */
 	while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY)));
 
-	if (status & error_flags) {
+	if ((status & error_flags) & MMCI_BIT(RTOE)) {
+		dump_cmd(cmdr, cmd->cmdarg, status, "Command Time Out");
+		return TIMEOUT;
+	} else if (status & error_flags) {
 		dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed");
 		return COMM_ERR;
 	}
@@ -297,7 +306,9 @@
 static void mci_set_ios(struct mmc *mmc)
 {
 	atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
-	int busw = (mmc->bus_width == 4) ? 1 : 0;
+	int bus_width = mmc->bus_width;
+	unsigned int version = atmel_mci_get_version(mci);
+	int busw;
 
 	/* Set the clock speed */
 	mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);
@@ -305,9 +316,26 @@
 	/*
 	 * set the bus width and select slot for this interface
 	 * there is no capability for multiple slots on the same interface yet
-	 * Bitfield SCDBUS needs to be expanded to 2 bits for 8-bit buses
 	 */
-	writel(MMCI_BF(SCDBUS, busw) | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
+	if ((version & 0xf00) >= 0x300) {
+		switch (bus_width) {
+		case 8:
+			busw = 3;
+			break;
+		case 4:
+			busw = 2;
+			break;
+		default:
+			busw = 0;
+			break;
+		}
+
+		writel(busw << 6 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
+	} else {
+		busw = (bus_width == 4) ? 1 : 0;
+
+		writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
+	}
 }
 
 /* Entered into mmc structure during driver init */
@@ -340,9 +368,12 @@
 int atmel_mci_init(void *regs)
 {
 	struct mmc *mmc = malloc(sizeof(struct mmc));
+	struct atmel_mci *mci;
+	unsigned int version;
 
 	if (!mmc)
 		return -1;
+
 	strcpy(mmc->name, "mci");
 	mmc->priv = regs;
 	mmc->send_cmd = mci_send_cmd;
@@ -353,7 +384,13 @@
 
 	/* need to be able to pass these in on a board by board basis */
 	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
-	mmc->host_caps = MMC_MODE_4BIT;
+	mci = (struct atmel_mci *)mmc->priv;
+	version = atmel_mci_get_version(mci);
+	if ((version & 0xf00) >= 0x300)
+		mmc->host_caps = MMC_MODE_8BIT;
+
+	mmc->host_caps |= MMC_MODE_4BIT;
+
 	/*
 	 * min and max frequencies determined by
 	 * max and min of clock divider
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 2590f1b..0a2f535 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -524,48 +524,70 @@
 	return 0;
 }
 
-static int mmc_send_op_cond(struct mmc *mmc)
+/* We pass in the cmd since otherwise the init seems to fail */
+static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
+		int use_arg)
 {
-	int timeout = 10000;
-	struct mmc_cmd cmd;
 	int err;
 
+	cmd->cmdidx = MMC_CMD_SEND_OP_COND;
+	cmd->resp_type = MMC_RSP_R3;
+	cmd->cmdarg = 0;
+	if (use_arg && !mmc_host_is_spi(mmc)) {
+		cmd->cmdarg =
+			(mmc->voltages &
+			(mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
+			(mmc->op_cond_response & OCR_ACCESS_MODE);
+
+		if (mmc->host_caps & MMC_MODE_HC)
+			cmd->cmdarg |= OCR_HCS;
+	}
+	err = mmc_send_cmd(mmc, cmd, NULL);
+	if (err)
+		return err;
+	mmc->op_cond_response = cmd->response[0];
+	return 0;
+}
+
+int mmc_send_op_cond(struct mmc *mmc)
+{
+	struct mmc_cmd cmd;
+	int err, i;
+
 	/* Some cards seem to need this */
 	mmc_go_idle(mmc);
 
  	/* Asking to the card its capabilities */
- 	cmd.cmdidx = MMC_CMD_SEND_OP_COND;
- 	cmd.resp_type = MMC_RSP_R3;
- 	cmd.cmdarg = 0;
-
- 	err = mmc_send_cmd(mmc, &cmd, NULL);
-
- 	if (err)
- 		return err;
-
- 	udelay(1000);
-
-	do {
-		cmd.cmdidx = MMC_CMD_SEND_OP_COND;
-		cmd.resp_type = MMC_RSP_R3;
-		cmd.cmdarg = (mmc_host_is_spi(mmc) ? 0 :
-				(mmc->voltages &
-				(cmd.response[0] & OCR_VOLTAGE_MASK)) |
-				(cmd.response[0] & OCR_ACCESS_MODE));
-
-		if (mmc->host_caps & MMC_MODE_HC)
-			cmd.cmdarg |= OCR_HCS;
-
-		err = mmc_send_cmd(mmc, &cmd, NULL);
-
+	mmc->op_cond_pending = 1;
+	for (i = 0; i < 2; i++) {
+		err = mmc_send_op_cond_iter(mmc, &cmd, i != 0);
 		if (err)
 			return err;
 
-		udelay(1000);
-	} while (!(cmd.response[0] & OCR_BUSY) && timeout--);
+		/* exit if not busy (flag seems to be inverted) */
+		if (mmc->op_cond_response & OCR_BUSY)
+			return 0;
+	}
+	return IN_PROGRESS;
+}
 
-	if (timeout <= 0)
-		return UNUSABLE_ERR;
+int mmc_complete_op_cond(struct mmc *mmc)
+{
+	struct mmc_cmd cmd;
+	int timeout = 1000;
+	uint start;
+	int err;
+
+	mmc->op_cond_pending = 0;
+	start = get_timer(0);
+	do {
+		err = mmc_send_op_cond_iter(mmc, &cmd, 1);
+		if (err)
+			return err;
+		if (get_timer(start) > timeout)
+			return UNUSABLE_ERR;
+		udelay(100);
+	} while (!(mmc->op_cond_response & OCR_BUSY));
 
 	if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 		cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
@@ -1274,7 +1296,7 @@
 }
 #endif
 
-int mmc_init(struct mmc *mmc)
+int mmc_start_init(struct mmc *mmc)
 {
 	int err;
 
@@ -1314,17 +1336,48 @@
 	if (err == TIMEOUT) {
 		err = mmc_send_op_cond(mmc);
 
-		if (err) {
+		if (err && err != IN_PROGRESS) {
 			printf("Card did not respond to voltage select!\n");
 			return UNUSABLE_ERR;
 		}
 	}
 
-	err = mmc_startup(mmc);
+	if (err == IN_PROGRESS)
+		mmc->init_in_progress = 1;
+
+	return err;
+}
+
+static int mmc_complete_init(struct mmc *mmc)
+{
+	int err = 0;
+
+	if (mmc->op_cond_pending)
+		err = mmc_complete_op_cond(mmc);
+
+	if (!err)
+		err = mmc_startup(mmc);
 	if (err)
 		mmc->has_init = 0;
 	else
 		mmc->has_init = 1;
+	mmc->init_in_progress = 0;
+	return err;
+}
+
+int mmc_init(struct mmc *mmc)
+{
+	int err = IN_PROGRESS;
+	unsigned start = get_timer(0);
+
+	if (mmc->has_init)
+		return 0;
+	if (!mmc->init_in_progress)
+		err = mmc_start_init(mmc);
+
+	if (!err || err == IN_PROGRESS)
+		err = mmc_complete_init(mmc);
+	debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
 	return err;
 }
 
@@ -1362,6 +1415,25 @@
 	return cur_dev_num;
 }
 
+void mmc_set_preinit(struct mmc *mmc, int preinit)
+{
+	mmc->preinit = preinit;
+}
+
+static void do_preinit(void)
+{
+	struct mmc *m;
+	struct list_head *entry;
+
+	list_for_each(entry, &mmc_devices) {
+		m = list_entry(entry, struct mmc, link);
+
+		if (m->preinit)
+			mmc_start_init(m);
+	}
+}
+
+
 int mmc_initialize(bd_t *bis)
 {
 	INIT_LIST_HEAD (&mmc_devices);
@@ -1372,5 +1444,6 @@
 
 	print_mmc_devices(',');
 
+	do_preinit();
 	return 0;
 }
diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
index 2fe34b6..63e1f90 100644
--- a/drivers/mmc/mv_sdhci.c
+++ b/drivers/mmc/mv_sdhci.c
@@ -51,6 +51,5 @@
 		host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 	else
 		host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
-	add_sdhci(host, max_clk, min_clk);
-	return 0;
+	return add_sdhci(host, max_clk, min_clk);
 }
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index a89660f..fdaf9c7 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -41,7 +41,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
 #include <bouncebuf.h>
 
 struct mxsmmc_priv {
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 166744c..afdfa88 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -29,7 +29,7 @@
 #include <i2c.h>
 #include <twl4030.h>
 #include <twl6030.h>
-#include <twl6035.h>
+#include <palmas.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/mmc_host_def.h>
@@ -107,7 +107,7 @@
 }
 #endif
 
-#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
+#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
 static void omap5_pbias_config(struct mmc *mmc)
 {
 	u32 value = 0;
@@ -117,7 +117,7 @@
 	value |= SDCARD_BIAS_HIZ_MODE;
 	writel(value, (*ctrl)->control_pbias);
 
-	twl6035_mmc1_poweron_ldo();
+	palmas_mmc1_poweron_ldo();
 
 	value = readl((*ctrl)->control_pbias);
 	value &= ~SDCARD_BIAS_HIZ_MODE;
@@ -178,7 +178,7 @@
 	if (mmc->block_dev.dev == 0)
 		omap4_vmmc_pbias_config(mmc);
 #endif
-#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
+#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
 	if (mmc->block_dev.dev == 0)
 		omap5_pbias_config(mmc);
 #endif
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index dc49d37..e50ff92 100644
--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -94,6 +94,5 @@
 
 	host->host_caps = MMC_MODE_HC;
 
-	add_sdhci(host, 52000000, 400000);
-	return 0;
+	return add_sdhci(host, 52000000, 400000);
 }
diff --git a/drivers/mmc/spear_sdhci.c b/drivers/mmc/spear_sdhci.c
new file mode 100644
index 0000000..23f1f4b
--- /dev/null
+++ b/drivers/mmc/spear_sdhci.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+
+int spear_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
+{
+	struct sdhci_host *host = NULL;
+	host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
+	if (!host) {
+		printf("sdhci host malloc fail!\n");
+		return 1;
+	}
+
+	host->name = "sdhci";
+	host->ioaddr = (void *)regbase;
+	host->quirks = quirks;
+
+	if (quirks & SDHCI_QUIRK_REG32_RW)
+		host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
+	else
+		host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+	add_sdhci(host, max_clk, min_clk);
+	return 0;
+}
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
new file mode 100644
index 0000000..9e37af4
--- /dev/null
+++ b/drivers/mmc/zynq_sdhci.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2013 Inc.
+ *
+ * Xilinx Zynq SD Host Controller Interface
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <asm/arch/sys_proto.h>
+
+int zynq_sdhci_init(u32 regbase)
+{
+	struct sdhci_host *host = NULL;
+
+	host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
+	if (!host) {
+		printf("zynq_sdhci_init: sdhci_host malloc fail\n");
+		return 1;
+	}
+
+	host->name = "zynq_sdhci";
+	host->ioaddr = (void *)regbase;
+	host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD;
+	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+	host->host_caps = MMC_MODE_HC;
+
+	add_sdhci(host, 52000000, 52000000 >> 9);
+	return 0;
+}
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 543c845..99f39fc 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -25,7 +25,9 @@
 
 LIB	:= $(obj)libmtd.o
 
-COBJS-$(CONFIG_MTD_DEVICE) += mtdcore.o
+ifneq (,$(findstring y,$(CONFIG_MTD_DEVICE)$(CONFIG_CMD_NAND)$(CONFIG_CMD_ONENAND)))
+COBJS-y += mtdcore.o
+endif
 COBJS-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
 COBJS-$(CONFIG_MTD_CONCAT) += mtdconcat.o
 COBJS-$(CONFIG_HAS_DATAFLASH) += at45.o
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 22d8440..25f8752 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -38,6 +38,7 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/byteorder.h>
+#include <asm/unaligned.h>
 #include <environment.h>
 #include <mtd/cfi_flash.h>
 #include <watchdog.h>
@@ -183,16 +184,16 @@
 flash_info_t *flash_get_info(ulong base)
 {
 	int i;
-	flash_info_t *info = NULL;
+	flash_info_t *info;
 
 	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		info = & flash_info[i];
+		info = &flash_info[i];
 		if (info->size && info->start[0] <= base &&
 		    base <= info->start[0] + info->size - 1)
-			break;
+			return info;
 	}
 
-	return info;
+	return NULL;
 }
 #endif
 
@@ -1640,9 +1641,10 @@
 	u32 tmp;
 
 	for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) {
-		tmp = qry->erase_region_info[i];
-		qry->erase_region_info[i] = qry->erase_region_info[j];
-		qry->erase_region_info[j] = tmp;
+		tmp = get_unaligned(&(qry->erase_region_info[i]));
+		put_unaligned(get_unaligned(&(qry->erase_region_info[j])),
+			      &(qry->erase_region_info[i]));
+		put_unaligned(tmp, &(qry->erase_region_info[j]));
 	}
 }
 
@@ -2073,8 +2075,8 @@
 	info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE);
 
 	if (flash_detect_cfi (info, &qry)) {
-		info->vendor = le16_to_cpu(qry.p_id);
-		info->ext_addr = le16_to_cpu(qry.p_adr);
+		info->vendor = le16_to_cpu(get_unaligned(&(qry.p_id)));
+		info->ext_addr = le16_to_cpu(get_unaligned(&(qry.p_adr)));
 		num_erase_regions = qry.num_erase_regions;
 
 		if (info->ext_addr) {
@@ -2163,7 +2165,8 @@
 				break;
 			}
 
-			tmp = le32_to_cpu(qry.erase_region_info[i]);
+			tmp = le32_to_cpu(get_unaligned(
+						&(qry.erase_region_info[i])));
 			debug("erase region %u: 0x%08lx\n", i, tmp);
 
 			erase_region_count = (tmp & 0xffff) + 1;
diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c
index 8d74fa9..bbb71a1 100644
--- a/drivers/mtd/cfi_mtd.c
+++ b/drivers/mtd/cfi_mtd.c
@@ -244,12 +244,12 @@
 		mtd->size		= fi->size;
 		mtd->writesize		= 1;
 
-		mtd->erase		= cfi_mtd_erase;
-		mtd->read		= cfi_mtd_read;
-		mtd->write		= cfi_mtd_write;
-		mtd->sync		= cfi_mtd_sync;
-		mtd->lock		= cfi_mtd_lock;
-		mtd->unlock		= cfi_mtd_unlock;
+		mtd->_erase		= cfi_mtd_erase;
+		mtd->_read		= cfi_mtd_read;
+		mtd->_write		= cfi_mtd_write;
+		mtd->_sync		= cfi_mtd_sync;
+		mtd->_lock		= cfi_mtd_lock;
+		mtd->_unlock		= cfi_mtd_unlock;
 		mtd->priv		= fi;
 
 		if (add_mtd_device(mtd))
diff --git a/drivers/mtd/mtdconcat.c b/drivers/mtd/mtdconcat.c
index e6d9384..31e4289 100644
--- a/drivers/mtd/mtdconcat.c
+++ b/drivers/mtd/mtdconcat.c
@@ -70,14 +70,14 @@
 			/* Entire transaction goes into this subdev */
 			size = len;
 
-		err = subdev->read(subdev, from, size, &retsize, buf);
+		err = mtd_read(subdev, from, size, &retsize, buf);
 
 		/* Save information about bitflips! */
 		if (unlikely(err)) {
-			if (err == -EBADMSG) {
+			if (mtd_is_eccerr(err)) {
 				mtd->ecc_stats.failed++;
 				ret = err;
-			} else if (err == -EUCLEAN) {
+			} else if (mtd_is_bitflip(err)) {
 				mtd->ecc_stats.corrected++;
 				/* Do not overwrite -EBADMSG !! */
 				if (!ret)
@@ -105,9 +105,6 @@
 	int err = -EINVAL;
 	int i;
 
-	if (!(mtd->flags & MTD_WRITEABLE))
-		return -EROFS;
-
 	*retlen = 0;
 
 	for (i = 0; i < concat->num_subdev; i++) {
@@ -124,11 +121,7 @@
 		else
 			size = len;
 
-		if (!(subdev->flags & MTD_WRITEABLE))
-			err = -EROFS;
-		else
-			err = subdev->write(subdev, to, size, &retsize, buf);
-
+		err = mtd_write(subdev, to, size, &retsize, buf);
 		if (err)
 			break;
 
@@ -165,16 +158,16 @@
 		if (from + devops.len > subdev->size)
 			devops.len = subdev->size - from;
 
-		err = subdev->read_oob(subdev, from, &devops);
+		err = mtd_read_oob(subdev, from, &devops);
 		ops->retlen += devops.retlen;
 		ops->oobretlen += devops.oobretlen;
 
 		/* Save information about bitflips! */
 		if (unlikely(err)) {
-			if (err == -EBADMSG) {
+			if (mtd_is_eccerr(err)) {
 				mtd->ecc_stats.failed++;
 				ret = err;
-			} else if (err == -EUCLEAN) {
+			} else if (mtd_is_bitflip(err)) {
 				mtd->ecc_stats.corrected++;
 				/* Do not overwrite -EBADMSG !! */
 				if (!ret)
@@ -225,7 +218,7 @@
 		if (to + devops.len > subdev->size)
 			devops.len = subdev->size - to;
 
-		err = subdev->write_oob(subdev, to, &devops);
+		err = mtd_write_oob(subdev, to, &devops);
 		ops->retlen += devops.retlen;
 		if (err)
 			return err;
@@ -271,7 +264,7 @@
 	 * FIXME: Allow INTERRUPTIBLE. Which means
 	 * not having the wait_queue head on the stack.
 	 */
-	err = mtd->erase(mtd, erase);
+	err = mtd_erase(mtd, erase);
 	if (!err) {
 		set_current_state(TASK_UNINTERRUPTIBLE);
 		add_wait_queue(&waitq, &wait);
@@ -294,15 +287,6 @@
 	uint64_t length, offset = 0;
 	struct erase_info *erase;
 
-	if (!(mtd->flags & MTD_WRITEABLE))
-		return -EROFS;
-
-	if (instr->addr > concat->mtd.size)
-		return -EINVAL;
-
-	if (instr->len + instr->addr > concat->mtd.size)
-		return -EINVAL;
-
 	/*
 	 * Check for proper erase block alignment of the to-be-erased area.
 	 * It is easier to do this based on the super device's erase
@@ -350,8 +334,6 @@
 			return -EINVAL;
 	}
 
-	instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
-
 	/* make a local copy of instr to avoid modifying the caller's struct */
 	erase = kmalloc(sizeof (struct erase_info), GFP_KERNEL);
 
@@ -390,10 +372,6 @@
 		else
 			erase->len = length;
 
-		if (!(subdev->flags & MTD_WRITEABLE)) {
-			err = -EROFS;
-			break;
-		}
 		length -= erase->len;
 		if ((err = concat_dev_erase(subdev, erase))) {
 			/* sanity check: should never happen since
@@ -429,9 +407,6 @@
 	struct mtd_concat *concat = CONCAT(mtd);
 	int i, err = -EINVAL;
 
-	if ((len + ofs) > mtd->size)
-		return -EINVAL;
-
 	for (i = 0; i < concat->num_subdev; i++) {
 		struct mtd_info *subdev = concat->subdev[i];
 		uint64_t size;
@@ -446,7 +421,7 @@
 		else
 			size = len;
 
-		err = subdev->lock(subdev, ofs, size);
+		err = mtd_lock(subdev, ofs, size);
 
 		if (err)
 			break;
@@ -467,9 +442,6 @@
 	struct mtd_concat *concat = CONCAT(mtd);
 	int i, err = 0;
 
-	if ((len + ofs) > mtd->size)
-		return -EINVAL;
-
 	for (i = 0; i < concat->num_subdev; i++) {
 		struct mtd_info *subdev = concat->subdev[i];
 		uint64_t size;
@@ -484,7 +456,7 @@
 		else
 			size = len;
 
-		err = subdev->unlock(subdev, ofs, size);
+		err = mtd_unlock(subdev, ofs, size);
 
 		if (err)
 			break;
@@ -507,7 +479,7 @@
 
 	for (i = 0; i < concat->num_subdev; i++) {
 		struct mtd_info *subdev = concat->subdev[i];
-		subdev->sync(subdev);
+		mtd_sync(subdev);
 	}
 }
 
@@ -516,12 +488,9 @@
 	struct mtd_concat *concat = CONCAT(mtd);
 	int i, res = 0;
 
-	if (!concat->subdev[0]->block_isbad)
+	if (!mtd_can_have_bb(concat->subdev[0]))
 		return res;
 
-	if (ofs > mtd->size)
-		return -EINVAL;
-
 	for (i = 0; i < concat->num_subdev; i++) {
 		struct mtd_info *subdev = concat->subdev[i];
 
@@ -530,7 +499,7 @@
 			continue;
 		}
 
-		res = subdev->block_isbad(subdev, ofs);
+		res = mtd_block_isbad(subdev, ofs);
 		break;
 	}
 
@@ -542,12 +511,9 @@
 	struct mtd_concat *concat = CONCAT(mtd);
 	int i, err = -EINVAL;
 
-	if (!concat->subdev[0]->block_markbad)
+	if (!mtd_can_have_bb(concat->subdev[0]))
 		return 0;
 
-	if (ofs > mtd->size)
-		return -EINVAL;
-
 	for (i = 0; i < concat->num_subdev; i++) {
 		struct mtd_info *subdev = concat->subdev[i];
 
@@ -556,7 +522,7 @@
 			continue;
 		}
 
-		err = subdev->block_markbad(subdev, ofs);
+		err = mtd_block_markbad(subdev, ofs);
 		if (!err)
 			mtd->ecc_stats.badblocks++;
 		break;
@@ -609,14 +575,14 @@
 	concat->mtd.subpage_sft = subdev[0]->subpage_sft;
 	concat->mtd.oobsize = subdev[0]->oobsize;
 	concat->mtd.oobavail = subdev[0]->oobavail;
-	if (subdev[0]->read_oob)
-		concat->mtd.read_oob = concat_read_oob;
-	if (subdev[0]->write_oob)
-		concat->mtd.write_oob = concat_write_oob;
-	if (subdev[0]->block_isbad)
-		concat->mtd.block_isbad = concat_block_isbad;
-	if (subdev[0]->block_markbad)
-		concat->mtd.block_markbad = concat_block_markbad;
+	if (subdev[0]->_read_oob)
+		concat->mtd._read_oob = concat_read_oob;
+	if (subdev[0]->_write_oob)
+		concat->mtd._write_oob = concat_write_oob;
+	if (subdev[0]->_block_isbad)
+		concat->mtd._block_isbad = concat_block_isbad;
+	if (subdev[0]->_block_markbad)
+		concat->mtd._block_markbad = concat_block_markbad;
 
 	concat->mtd.ecc_stats.badblocks = subdev[0]->ecc_stats.badblocks;
 
@@ -653,8 +619,8 @@
 		if (concat->mtd.writesize   !=  subdev[i]->writesize ||
 		    concat->mtd.subpage_sft != subdev[i]->subpage_sft ||
 		    concat->mtd.oobsize    !=  subdev[i]->oobsize ||
-		    !concat->mtd.read_oob  != !subdev[i]->read_oob ||
-		    !concat->mtd.write_oob != !subdev[i]->write_oob) {
+		    !concat->mtd._read_oob  != !subdev[i]->_read_oob ||
+		    !concat->mtd._write_oob != !subdev[i]->_write_oob) {
 			kfree(concat);
 			printk("Incompatible OOB or ECC data on \"%s\"\n",
 			       subdev[i]->name);
@@ -669,12 +635,12 @@
 	concat->num_subdev = num_devs;
 	concat->mtd.name = name;
 
-	concat->mtd.erase = concat_erase;
-	concat->mtd.read = concat_read;
-	concat->mtd.write = concat_write;
-	concat->mtd.sync = concat_sync;
-	concat->mtd.lock = concat_lock;
-	concat->mtd.unlock = concat_unlock;
+	concat->mtd._erase = concat_erase;
+	concat->mtd._read = concat_read;
+	concat->mtd._write = concat_write;
+	concat->mtd._sync = concat_sync;
+	concat->mtd._lock = concat_lock;
+	concat->mtd._unlock = concat_unlock;
 
 	/*
 	 * Combine the erase block size info of the subdevices:
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index 3a81ada..49c0814 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -25,6 +25,11 @@
 			mtd->index = i;
 			mtd->usecount = 0;
 
+			/* default value if not set by driver */
+			if (mtd->bitflip_threshold == 0)
+				mtd->bitflip_threshold = mtd->ecc_strength;
+
+
 			/* No need to get a refcount on the module containing
 			   the notifier, since we hold the mtd_table_mutex */
 
@@ -186,3 +191,189 @@
 	}
 }
 #endif /* defined(CONFIG_CMD_MTDPARTS_SPREAD) */
+
+ /*
+ * Erase is an asynchronous operation.  Device drivers are supposed
+ * to call instr->callback() whenever the operation completes, even
+ * if it completes with a failure.
+ * Callers are supposed to pass a callback function and wait for it
+ * to be called before writing to the block.
+ */
+int mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+	if (instr->addr > mtd->size || instr->len > mtd->size - instr->addr)
+		return -EINVAL;
+	if (!(mtd->flags & MTD_WRITEABLE))
+		return -EROFS;
+	instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+	if (!instr->len) {
+		instr->state = MTD_ERASE_DONE;
+		mtd_erase_callback(instr);
+		return 0;
+	}
+	return mtd->_erase(mtd, instr);
+}
+
+int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+	     u_char *buf)
+{
+	if (from < 0 || from > mtd->size || len > mtd->size - from)
+		return -EINVAL;
+	if (!len)
+		return 0;
+	return mtd->_read(mtd, from, len, retlen, buf);
+}
+
+int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+	      const u_char *buf)
+{
+	*retlen = 0;
+	if (to < 0 || to > mtd->size || len > mtd->size - to)
+		return -EINVAL;
+	if (!mtd->_write || !(mtd->flags & MTD_WRITEABLE))
+		return -EROFS;
+	if (!len)
+		return 0;
+	return mtd->_write(mtd, to, len, retlen, buf);
+}
+
+/*
+ * In blackbox flight recorder like scenarios we want to make successful writes
+ * in interrupt context. panic_write() is only intended to be called when its
+ * known the kernel is about to panic and we need the write to succeed. Since
+ * the kernel is not going to be running for much longer, this function can
+ * break locks and delay to ensure the write succeeds (but not sleep).
+ */
+int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+		    const u_char *buf)
+{
+	*retlen = 0;
+	if (!mtd->_panic_write)
+		return -EOPNOTSUPP;
+	if (to < 0 || to > mtd->size || len > mtd->size - to)
+		return -EINVAL;
+	if (!(mtd->flags & MTD_WRITEABLE))
+		return -EROFS;
+	if (!len)
+		return 0;
+	return mtd->_panic_write(mtd, to, len, retlen, buf);
+}
+
+int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops)
+{
+	ops->retlen = ops->oobretlen = 0;
+	if (!mtd->_read_oob)
+		return -EOPNOTSUPP;
+	return mtd->_read_oob(mtd, from, ops);
+}
+
+/*
+ * Method to access the protection register area, present in some flash
+ * devices. The user data is one time programmable but the factory data is read
+ * only.
+ */
+int mtd_get_fact_prot_info(struct mtd_info *mtd, struct otp_info *buf,
+			   size_t len)
+{
+	if (!mtd->_get_fact_prot_info)
+		return -EOPNOTSUPP;
+	if (!len)
+		return 0;
+	return mtd->_get_fact_prot_info(mtd, buf, len);
+}
+
+int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+			   size_t *retlen, u_char *buf)
+{
+	*retlen = 0;
+	if (!mtd->_read_fact_prot_reg)
+		return -EOPNOTSUPP;
+	if (!len)
+		return 0;
+	return mtd->_read_fact_prot_reg(mtd, from, len, retlen, buf);
+}
+
+int mtd_get_user_prot_info(struct mtd_info *mtd, struct otp_info *buf,
+			   size_t len)
+{
+	if (!mtd->_get_user_prot_info)
+		return -EOPNOTSUPP;
+	if (!len)
+		return 0;
+	return mtd->_get_user_prot_info(mtd, buf, len);
+}
+
+int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+			   size_t *retlen, u_char *buf)
+{
+	*retlen = 0;
+	if (!mtd->_read_user_prot_reg)
+		return -EOPNOTSUPP;
+	if (!len)
+		return 0;
+	return mtd->_read_user_prot_reg(mtd, from, len, retlen, buf);
+}
+
+int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len,
+			    size_t *retlen, u_char *buf)
+{
+	*retlen = 0;
+	if (!mtd->_write_user_prot_reg)
+		return -EOPNOTSUPP;
+	if (!len)
+		return 0;
+	return mtd->_write_user_prot_reg(mtd, to, len, retlen, buf);
+}
+
+int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len)
+{
+	if (!mtd->_lock_user_prot_reg)
+		return -EOPNOTSUPP;
+	if (!len)
+		return 0;
+	return mtd->_lock_user_prot_reg(mtd, from, len);
+}
+
+/* Chip-supported device locking */
+int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+	if (!mtd->_lock)
+		return -EOPNOTSUPP;
+	if (ofs < 0 || ofs > mtd->size || len > mtd->size - ofs)
+		return -EINVAL;
+	if (!len)
+		return 0;
+	return mtd->_lock(mtd, ofs, len);
+}
+
+int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+	if (!mtd->_unlock)
+		return -EOPNOTSUPP;
+	if (ofs < 0 || ofs > mtd->size || len > mtd->size - ofs)
+		return -EINVAL;
+	if (!len)
+		return 0;
+	return mtd->_unlock(mtd, ofs, len);
+}
+
+int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs)
+{
+	if (!mtd->_block_isbad)
+		return 0;
+	if (ofs < 0 || ofs > mtd->size)
+		return -EINVAL;
+	return mtd->_block_isbad(mtd, ofs);
+}
+
+int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+	if (!mtd->_block_markbad)
+		return -EOPNOTSUPP;
+	if (ofs < 0 || ofs > mtd->size)
+		return -EINVAL;
+	if (!(mtd->flags & MTD_WRITEABLE))
+		return -EROFS;
+	return mtd->_block_markbad(mtd, ofs);
+}
+
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
index cbfc679..9dfe7bb 100644
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
@@ -52,17 +52,11 @@
 	int res;
 
 	stats = part->master->ecc_stats;
-
-	if (from >= mtd->size)
-		len = 0;
-	else if (from + len > mtd->size)
-		len = mtd->size - from;
-	res = part->master->read(part->master, from + part->offset,
-				   len, retlen, buf);
+	res = mtd_read(part->master, from + part->offset, len, retlen, buf);
 	if (unlikely(res)) {
-		if (res == -EUCLEAN)
+		if (mtd_is_bitflip(res))
 			mtd->ecc_stats.corrected += part->master->ecc_stats.corrected - stats.corrected;
-		if (res == -EBADMSG)
+		if (mtd_is_eccerr(res))
 			mtd->ecc_stats.failed += part->master->ecc_stats.failed - stats.failed;
 	}
 	return res;
@@ -78,12 +72,12 @@
 		return -EINVAL;
 	if (ops->datbuf && from + ops->len > mtd->size)
 		return -EINVAL;
-	res = part->master->read_oob(part->master, from + part->offset, ops);
+	res = mtd_read_oob(part->master, from + part->offset, ops);
 
 	if (unlikely(res)) {
-		if (res == -EUCLEAN)
+		if (mtd_is_bitflip(res))
 			mtd->ecc_stats.corrected++;
-		if (res == -EBADMSG)
+		if (mtd_is_eccerr(res))
 			mtd->ecc_stats.failed++;
 	}
 	return res;
@@ -93,58 +87,35 @@
 		size_t len, size_t *retlen, u_char *buf)
 {
 	struct mtd_part *part = PART(mtd);
-	return part->master->read_user_prot_reg(part->master, from,
-					len, retlen, buf);
+	return mtd_read_user_prot_reg(part->master, from, len, retlen, buf);
 }
 
 static int part_get_user_prot_info(struct mtd_info *mtd,
 		struct otp_info *buf, size_t len)
 {
 	struct mtd_part *part = PART(mtd);
-	return part->master->get_user_prot_info(part->master, buf, len);
+	return mtd_get_user_prot_info(part->master, buf, len);
 }
 
 static int part_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
 		size_t len, size_t *retlen, u_char *buf)
 {
 	struct mtd_part *part = PART(mtd);
-	return part->master->read_fact_prot_reg(part->master, from,
-					len, retlen, buf);
+	return mtd_read_fact_prot_reg(part->master, from, len, retlen, buf);
 }
 
 static int part_get_fact_prot_info(struct mtd_info *mtd, struct otp_info *buf,
 		size_t len)
 {
 	struct mtd_part *part = PART(mtd);
-	return part->master->get_fact_prot_info(part->master, buf, len);
+	return mtd_get_fact_prot_info(part->master, buf, len);
 }
 
 static int part_write(struct mtd_info *mtd, loff_t to, size_t len,
 		size_t *retlen, const u_char *buf)
 {
 	struct mtd_part *part = PART(mtd);
-	if (!(mtd->flags & MTD_WRITEABLE))
-		return -EROFS;
-	if (to >= mtd->size)
-		len = 0;
-	else if (to + len > mtd->size)
-		len = mtd->size - to;
-	return part->master->write(part->master, to + part->offset,
-				    len, retlen, buf);
-}
-
-static int part_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
-		size_t *retlen, const u_char *buf)
-{
-	struct mtd_part *part = PART(mtd);
-	if (!(mtd->flags & MTD_WRITEABLE))
-		return -EROFS;
-	if (to >= mtd->size)
-		len = 0;
-	else if (to + len > mtd->size)
-		len = mtd->size - to;
-	return part->master->panic_write(part->master, to + part->offset,
-				    len, retlen, buf);
+	return mtd_write(part->master, to + part->offset, len, retlen, buf);
 }
 
 static int part_write_oob(struct mtd_info *mtd, loff_t to,
@@ -152,41 +123,34 @@
 {
 	struct mtd_part *part = PART(mtd);
 
-	if (!(mtd->flags & MTD_WRITEABLE))
-		return -EROFS;
-
 	if (to >= mtd->size)
 		return -EINVAL;
 	if (ops->datbuf && to + ops->len > mtd->size)
 		return -EINVAL;
-	return part->master->write_oob(part->master, to + part->offset, ops);
+	return mtd_write_oob(part->master, to + part->offset, ops);
 }
 
 static int part_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
 		size_t len, size_t *retlen, u_char *buf)
 {
 	struct mtd_part *part = PART(mtd);
-	return part->master->write_user_prot_reg(part->master, from,
-					len, retlen, buf);
+	return mtd_write_user_prot_reg(part->master, from, len, retlen, buf);
 }
 
 static int part_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
 		size_t len)
 {
 	struct mtd_part *part = PART(mtd);
-	return part->master->lock_user_prot_reg(part->master, from, len);
+	return mtd_lock_user_prot_reg(part->master, from, len);
 }
 
 static int part_erase(struct mtd_info *mtd, struct erase_info *instr)
 {
 	struct mtd_part *part = PART(mtd);
 	int ret;
-	if (!(mtd->flags & MTD_WRITEABLE))
-		return -EROFS;
-	if (instr->addr >= mtd->size)
-		return -EINVAL;
+
 	instr->addr += part->offset;
-	ret = part->master->erase(part->master, instr);
+	ret = mtd_erase(part->master, instr);
 	if (ret) {
 		if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN)
 			instr->fail_addr -= part->offset;
@@ -197,7 +161,7 @@
 
 void mtd_erase_callback(struct erase_info *instr)
 {
-	if (instr->mtd->erase == part_erase) {
+	if (instr->mtd->_erase == part_erase) {
 		struct mtd_part *part = PART(instr->mtd);
 
 		if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN)
@@ -211,32 +175,26 @@
 static int part_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 {
 	struct mtd_part *part = PART(mtd);
-	if ((len + ofs) > mtd->size)
-		return -EINVAL;
-	return part->master->lock(part->master, ofs + part->offset, len);
+	return mtd_lock(part->master, ofs + part->offset, len);
 }
 
 static int part_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 {
 	struct mtd_part *part = PART(mtd);
-	if ((len + ofs) > mtd->size)
-		return -EINVAL;
-	return part->master->unlock(part->master, ofs + part->offset, len);
+	return mtd_unlock(part->master, ofs + part->offset, len);
 }
 
 static void part_sync(struct mtd_info *mtd)
 {
 	struct mtd_part *part = PART(mtd);
-	part->master->sync(part->master);
+	mtd_sync(part->master);
 }
 
 static int part_block_isbad(struct mtd_info *mtd, loff_t ofs)
 {
 	struct mtd_part *part = PART(mtd);
-	if (ofs >= mtd->size)
-		return -EINVAL;
 	ofs += part->offset;
-	return part->master->block_isbad(part->master, ofs);
+	return mtd_block_isbad(part->master, ofs);
 }
 
 static int part_block_markbad(struct mtd_info *mtd, loff_t ofs)
@@ -244,12 +202,8 @@
 	struct mtd_part *part = PART(mtd);
 	int res;
 
-	if (!(mtd->flags & MTD_WRITEABLE))
-		return -EROFS;
-	if (ofs >= mtd->size)
-		return -EINVAL;
 	ofs += part->offset;
-	res = part->master->block_markbad(part->master, ofs);
+	res = mtd_block_markbad(part->master, ofs);
 	if (!res)
 		mtd->ecc_stats.badblocks++;
 	return res;
@@ -303,39 +257,36 @@
 	slave->mtd.name = part->name;
 	slave->mtd.owner = master->owner;
 
-	slave->mtd.read = part_read;
-	slave->mtd.write = part_write;
+	slave->mtd._read = part_read;
+	slave->mtd._write = part_write;
 
-	if (master->panic_write)
-		slave->mtd.panic_write = part_panic_write;
-
-	if (master->read_oob)
-		slave->mtd.read_oob = part_read_oob;
-	if (master->write_oob)
-		slave->mtd.write_oob = part_write_oob;
-	if (master->read_user_prot_reg)
-		slave->mtd.read_user_prot_reg = part_read_user_prot_reg;
-	if (master->read_fact_prot_reg)
-		slave->mtd.read_fact_prot_reg = part_read_fact_prot_reg;
-	if (master->write_user_prot_reg)
-		slave->mtd.write_user_prot_reg = part_write_user_prot_reg;
-	if (master->lock_user_prot_reg)
-		slave->mtd.lock_user_prot_reg = part_lock_user_prot_reg;
-	if (master->get_user_prot_info)
-		slave->mtd.get_user_prot_info = part_get_user_prot_info;
-	if (master->get_fact_prot_info)
-		slave->mtd.get_fact_prot_info = part_get_fact_prot_info;
-	if (master->sync)
-		slave->mtd.sync = part_sync;
-	if (master->lock)
-		slave->mtd.lock = part_lock;
-	if (master->unlock)
-		slave->mtd.unlock = part_unlock;
-	if (master->block_isbad)
-		slave->mtd.block_isbad = part_block_isbad;
-	if (master->block_markbad)
-		slave->mtd.block_markbad = part_block_markbad;
-	slave->mtd.erase = part_erase;
+	if (master->_read_oob)
+		slave->mtd._read_oob = part_read_oob;
+	if (master->_write_oob)
+		slave->mtd._write_oob = part_write_oob;
+	if (master->_read_user_prot_reg)
+		slave->mtd._read_user_prot_reg = part_read_user_prot_reg;
+	if (master->_read_fact_prot_reg)
+		slave->mtd._read_fact_prot_reg = part_read_fact_prot_reg;
+	if (master->_write_user_prot_reg)
+		slave->mtd._write_user_prot_reg = part_write_user_prot_reg;
+	if (master->_lock_user_prot_reg)
+		slave->mtd._lock_user_prot_reg = part_lock_user_prot_reg;
+	if (master->_get_user_prot_info)
+		slave->mtd._get_user_prot_info = part_get_user_prot_info;
+	if (master->_get_fact_prot_info)
+		slave->mtd._get_fact_prot_info = part_get_fact_prot_info;
+	if (master->_sync)
+		slave->mtd._sync = part_sync;
+	if (master->_lock)
+		slave->mtd._lock = part_lock;
+	if (master->_unlock)
+		slave->mtd._unlock = part_unlock;
+	if (master->_block_isbad)
+		slave->mtd._block_isbad = part_block_isbad;
+	if (master->_block_markbad)
+		slave->mtd._block_markbad = part_block_markbad;
+	slave->mtd._erase = part_erase;
 	slave->master = master;
 	slave->offset = part->offset;
 	slave->index = partno;
@@ -416,12 +367,11 @@
 	}
 
 	slave->mtd.ecclayout = master->ecclayout;
-	if (master->block_isbad) {
+	if (master->_block_isbad) {
 		uint64_t offs = 0;
 
 		while (offs < slave->mtd.size) {
-			if (master->block_isbad(master,
-						offs + slave->offset))
+			if (mtd_block_isbad(master, offs + slave->offset))
 				slave->mtd.ecc_stats.badblocks++;
 			offs += slave->mtd.erasesize;
 		}
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 35769c5..8821704 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -34,6 +34,7 @@
 endif
 
 COBJS-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
+COBJS-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o
 COBJS-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
 COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
 COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
@@ -77,6 +78,7 @@
 COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o
 COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
+COBJS-$(CONFIG_NAND_DOCG4) += docg4.o
 
 else  # minimal SPL drivers
 
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 994dd9f..3bfbaf8 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -489,7 +489,7 @@
 }
 
 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
-	struct nand_chip *chip, uint8_t *buf, int page)
+	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 {
 	struct atmel_nand_host *host = chip->priv;
 	int eccsize = chip->ecc.size;
@@ -529,8 +529,9 @@
 	return 0;
 }
 
-static void atmel_nand_pmecc_write_page(struct mtd_info *mtd,
-		struct nand_chip *chip, const uint8_t *buf)
+static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
+		struct nand_chip *chip, const uint8_t *buf,
+		int oob_required)
 {
 	struct atmel_nand_host *host = chip->priv;
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
@@ -557,7 +558,7 @@
 
 	if (!timeout) {
 		printk(KERN_ERR "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
-		return;
+		goto out;
 	}
 
 	for (i = 0; i < host->pmecc_sector_number; i++) {
@@ -570,6 +571,8 @@
 		}
 	}
 	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+out:
+	return 0;
 }
 
 static void atmel_pmecc_core_init(struct mtd_info *mtd)
@@ -706,6 +709,7 @@
 
 	nand->ecc.read_page = atmel_nand_pmecc_read_page;
 	nand->ecc.write_page = atmel_nand_pmecc_write_page;
+	nand->ecc.strength = cap;
 
 	atmel_pmecc_core_init(mtd);
 
@@ -775,9 +779,10 @@
  * mtd:        mtd info structure
  * chip:       nand chip info structure
  * buf:        buffer to store read data
+ * oob_required:    caller expects OOB data read to chip->oob_poi
  */
-static int atmel_nand_read_page(struct mtd_info *mtd,
-		struct nand_chip *chip, uint8_t *buf, int page)
+static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+				uint8_t *buf, int oob_required, int page)
 {
 	int eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
diff --git a/drivers/mtd/nand/bfin_nand.c b/drivers/mtd/nand/bfin_nand.c
index c7ddbb2..7e755e8 100644
--- a/drivers/mtd/nand/bfin_nand.c
+++ b/drivers/mtd/nand/bfin_nand.c
@@ -374,9 +374,11 @@
 		if (!NAND_IS_512()) {
 			chip->ecc.bytes = 3;
 			chip->ecc.size = 256;
+			chip->ecc.strength = 1;
 		} else {
 			chip->ecc.bytes = 6;
 			chip->ecc.size = 512;
+			chip->ecc.strength = 2;
 		}
 		chip->ecc.mode = NAND_ECC_HW;
 		chip->ecc.calculate = bfin_nfc_calculate_ecc;
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index e8506dd..90f5985 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -607,12 +607,13 @@
 {
 	nand->chip_delay  = 0;
 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
-	nand->options	  |= NAND_USE_FLASH_BBT;
+	nand->bbt_options	  |= NAND_BBT_USE_FLASH;
 #endif
 #ifdef CONFIG_SYS_NAND_HW_ECC
 	nand->ecc.mode = NAND_ECC_HW;
 	nand->ecc.size = 512;
 	nand->ecc.bytes = 3;
+	nand->ecc.strength = 1;
 	nand->ecc.calculate = nand_davinci_calculate_ecc;
 	nand->ecc.correct  = nand_davinci_correct_data;
 	nand->ecc.hwctl  = nand_davinci_enable_hwecc;
@@ -623,6 +624,7 @@
 	nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
 	nand->ecc.size = 512;
 	nand->ecc.bytes = 10;
+	nand->ecc.strength = 4;
 	nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
 	nand->ecc.correct = nand_davinci_4bit_correct_data;
 	nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c
index edf3a099..4cd741e 100644
--- a/drivers/mtd/nand/diskonchip.c
+++ b/drivers/mtd/nand/diskonchip.c
@@ -134,7 +134,7 @@
 
 /*
  * The HW decoder in the DoC ASIC's provides us a error syndrome,
- * which we must convert to a standard syndrom usable by the generic
+ * which we must convert to a standard syndrome usable by the generic
  * Reed-Solomon library code.
  *
  * Fabrice Bellard figured this out in the old docecc code. I added
@@ -154,7 +154,7 @@
 	ds[3] = ((ecc[3] & 0xc0) >> 6) | ((ecc[0] & 0xff) << 2);
 	parity = ecc[1];
 
-	/* Initialize the syndrom buffer */
+	/* Initialize the syndrome buffer */
 	for (i = 0; i < NROOTS; i++)
 		s[i] = ds[0];
 	/*
@@ -1033,7 +1033,7 @@
 		WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf);
 	else
 		WriteDOC(DOC_ECC_DIS, docptr, ECCConf);
-	if (no_ecc_failures && (ret == -EBADMSG)) {
+	if (no_ecc_failures && mtd_is_eccerr(ret)) {
 		printk(KERN_ERR "suppressing ECC failure\n");
 		ret = 0;
 	}
@@ -1073,7 +1073,7 @@
 	size_t retlen;
 
 	for (offs = 0; offs < mtd->size; offs += mtd->erasesize) {
-		ret = mtd->read(mtd, offs, mtd->writesize, &retlen, buf);
+		ret = mtd_read(mtd, offs, mtd->writesize, &retlen, buf);
 		if (retlen != mtd->writesize)
 			continue;
 		if (ret) {
@@ -1098,7 +1098,7 @@
 	/* Only one mediaheader was found.  We want buf to contain a
 	   mediaheader on return, so we'll have to re-read the one we found. */
 	offs = doc->mh0_page << this->page_shift;
-	ret = mtd->read(mtd, offs, mtd->writesize, &retlen, buf);
+	ret = mtd_read(mtd, offs, mtd->writesize, &retlen, buf);
 	if (retlen != mtd->writesize) {
 		/* Insanity.  Give up. */
 		printk(KERN_ERR "Read DiskOnChip Media Header once, but can't reread it???\n");
@@ -1658,7 +1658,8 @@
 	nand->ecc.mode		= NAND_ECC_HW_SYNDROME;
 	nand->ecc.size		= 512;
 	nand->ecc.bytes		= 6;
-	nand->options		= NAND_USE_FLASH_BBT;
+	nand->ecc.strength	= 2;
+	nand->bbt_options	= NAND_BBT_USE_FLASH;
 
 	doc->physadr		= physadr;
 	doc->virtadr		= virtadr;
diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c
new file mode 100644
index 0000000..7dd9953
--- /dev/null
+++ b/drivers/mtd/nand/docg4.c
@@ -0,0 +1,1028 @@
+/*
+ * drivers/mtd/nand/docg4.c
+ *
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * mtd nand driver for M-Systems DiskOnChip G4
+ *
+ * Tested on the Palm Treo 680.  The G4 is also present on Toshiba Portege, Asus
+ * P526, some HTC smartphones (Wizard, Prophet, ...), O2 XDA Zinc, maybe others.
+ * Should work on these as well.  Let me know!
+ *
+ * TODO:
+ *
+ *  Mechanism for management of password-protected areas
+ *
+ *  Hamming ecc when reading oob only
+ *
+ *  According to the M-Sys documentation, this device is also available in a
+ *  "dual-die" configuration having a 256MB capacity, but no mechanism for
+ *  detecting this variant is documented.  Currently this driver assumes 128MB
+ *  capacity.
+ *
+ *  Support for multiple cascaded devices ("floors").  Not sure which gadgets
+ *  contain multiple G4s in a cascaded configuration, if any.
+ *
+ */
+
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <asm/errno.h>
+#include <malloc.h>
+#include <nand.h>
+#include <linux/bch.h>
+#include <linux/bitrev.h>
+#include <linux/mtd/docg4.h>
+
+/*
+ * The device has a nop register which M-Sys claims is for the purpose of
+ * inserting precise delays.  But beware; at least some operations fail if the
+ * nop writes are replaced with a generic delay!
+ */
+static inline void write_nop(void __iomem *docptr)
+{
+	writew(0, docptr + DOC_NOP);
+}
+
+
+static int poll_status(void __iomem *docptr)
+{
+	/*
+	 * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
+	 * register.  Operations known to take a long time (e.g., block erase)
+	 * should sleep for a while before calling this.
+	 */
+
+	uint8_t flash_status;
+
+	/* hardware quirk requires reading twice initially */
+	flash_status = readb(docptr + DOC_FLASHCONTROL);
+
+	do {
+		flash_status = readb(docptr + DOC_FLASHCONTROL);
+	} while (!(flash_status & DOC_CTRL_FLASHREADY));
+
+	return 0;
+}
+
+static void write_addr(void __iomem *docptr, uint32_t docg4_addr)
+{
+	/* write the four address bytes packed in docg4_addr to the device */
+
+	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+	docg4_addr >>= 8;
+	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+	docg4_addr >>= 8;
+	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+	docg4_addr >>= 8;
+	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+}
+
+/*
+ * This is a module parameter in the linux kernel version of this driver.  It is
+ * hard-coded to 'off' for u-boot.  This driver uses oob to mark bad blocks.
+ * This can be problematic when dealing with data not intended for the mtd/nand
+ * subsystem.  For example, on boards that boot from the docg4 and use the IPL
+ * to load an spl + u-boot image, the blocks containing the image will be
+ * reported as "bad" because the oob of the first page of each block contains a
+ * magic number that the IPL looks for, which causes the badblock scan to
+ * erroneously add them to the bad block table.  To erase such a block, use
+ * u-boot's 'nand scrub'.  scrub is safe for the docg4.  The device does have a
+ * factory bad block table, but it is read-only, and is used in conjunction with
+ * oob bad block markers that are written by mtd/nand when a block is deemed to
+ * be bad.  To read data from "bad" blocks, use 'read.raw'.  Unfortunately,
+ * read.raw does not use ecc, which would still work fine on such misidentified
+ * bad blocks.  TODO: u-boot nand utilities need the ability to ignore bad
+ * blocks.
+ */
+static const int ignore_badblocks; /* remains false */
+
+struct docg4_priv {
+	int status;
+	struct {
+		unsigned int command;
+		int column;
+		int page;
+	} last_command;
+	uint8_t oob_buf[16];
+	uint8_t ecc_buf[7];
+	int oob_page;
+	struct bch_control *bch;
+};
+/*
+ * Oob bytes 0 - 6 are available to the user.
+ * Byte 7 is hamming ecc for first 7 bytes.  Bytes 8 - 14 are hw-generated ecc.
+ * Byte 15 (the last) is used by the driver as a "page written" flag.
+ */
+static struct nand_ecclayout docg4_oobinfo = {
+	.eccbytes = 9,
+	.eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
+	.oobavail = 7,
+	.oobfree = { {0, 7} }
+};
+
+static void reset(void __iomem *docptr)
+{
+	/* full device reset */
+
+	writew(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN, docptr + DOC_ASICMODE);
+	writew(~(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN),
+	       docptr + DOC_ASICMODECONFIRM);
+	write_nop(docptr);
+
+	writew(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN,
+	       docptr + DOC_ASICMODE);
+	writew(~(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN),
+	       docptr + DOC_ASICMODECONFIRM);
+
+	writew(DOC_ECCCONF1_ECC_ENABLE, docptr + DOC_ECCCONF1);
+
+	poll_status(docptr);
+}
+
+static void docg4_select_chip(struct mtd_info *mtd, int chip)
+{
+	/*
+	 * Select among multiple cascaded chips ("floors").  Multiple floors are
+	 * not yet supported, so the only valid non-negative value is 0.
+	 */
+	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
+
+	if (chip < 0)
+		return;		/* deselected */
+
+	if (chip > 0)
+		printf("multiple floors currently unsupported\n");
+
+	writew(0, docptr + DOC_DEVICESELECT);
+}
+
+static void read_hw_ecc(void __iomem *docptr, uint8_t *ecc_buf)
+{
+	/* read the 7 hw-generated ecc bytes */
+
+	int i;
+	for (i = 0; i < 7; i++) { /* hw quirk; read twice */
+		ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
+		ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
+	}
+}
+
+static int correct_data(struct mtd_info *mtd, uint8_t *buf, int page)
+{
+	/*
+	 * Called after a page read when hardware reports bitflips.
+	 * Up to four bitflips can be corrected.
+	 */
+
+	struct nand_chip *nand = mtd->priv;
+	struct docg4_priv *doc = nand->priv;
+	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
+	int i, numerrs;
+	unsigned int errpos[4];
+	const uint8_t blank_read_hwecc[8] = {
+		0xcf, 0x72, 0xfc, 0x1b, 0xa9, 0xc7, 0xb9, 0 };
+
+	read_hw_ecc(docptr, doc->ecc_buf); /* read 7 hw-generated ecc bytes */
+
+	/* check if read error is due to a blank page */
+	if (!memcmp(doc->ecc_buf, blank_read_hwecc, 7))
+		return 0;	/* yes */
+
+	/* skip additional check of "written flag" if ignore_badblocks */
+	if (!ignore_badblocks) {
+		/*
+		 * If the hw ecc bytes are not those of a blank page, there's
+		 * still a chance that the page is blank, but was read with
+		 * errors.  Check the "written flag" in last oob byte, which
+		 * is set to zero when a page is written.  If more than half
+		 * the bits are set, assume a blank page.  Unfortunately, the
+		 * bit flips(s) are not reported in stats.
+		 */
+
+		if (doc->oob_buf[15]) {
+			int bit, numsetbits = 0;
+			unsigned long written_flag = doc->oob_buf[15];
+
+			for (bit = 0; bit < 8; bit++) {
+				if (written_flag & 0x01)
+					numsetbits++;
+				written_flag >>= 1;
+			}
+			if (numsetbits > 4) { /* assume blank */
+				printf("errors in blank page at offset %08x\n",
+				       page * DOCG4_PAGE_SIZE);
+				return 0;
+			}
+		}
+	}
+
+	/*
+	 * The hardware ecc unit produces oob_ecc ^ calc_ecc.  The kernel's bch
+	 * algorithm is used to decode this.  However the hw operates on page
+	 * data in a bit order that is the reverse of that of the bch alg,
+	 * requiring that the bits be reversed on the result.  Thanks to Ivan
+	 * Djelic for his analysis!
+	 */
+	for (i = 0; i < 7; i++)
+		doc->ecc_buf[i] = bitrev8(doc->ecc_buf[i]);
+
+	numerrs = decode_bch(doc->bch, NULL, DOCG4_USERDATA_LEN, NULL,
+			     doc->ecc_buf, NULL, errpos);
+
+	if (numerrs == -EBADMSG) {
+		printf("uncorrectable errors at offset %08x\n",
+		       page * DOCG4_PAGE_SIZE);
+		return -EBADMSG;
+	}
+
+	BUG_ON(numerrs < 0);	/* -EINVAL, or anything other than -EBADMSG */
+
+	/* undo last step in BCH alg (modulo mirroring not needed) */
+	for (i = 0; i < numerrs; i++)
+		errpos[i] = (errpos[i] & ~7)|(7-(errpos[i] & 7));
+
+	/* fix the errors */
+	for (i = 0; i < numerrs; i++) {
+		/* ignore if error within oob ecc bytes */
+		if (errpos[i] > DOCG4_USERDATA_LEN * 8)
+			continue;
+
+		/* if error within oob area preceeding ecc bytes... */
+		if (errpos[i] > DOCG4_PAGE_SIZE * 8)
+			__change_bit(errpos[i] - DOCG4_PAGE_SIZE * 8,
+				     (unsigned long *)doc->oob_buf);
+
+		else    /* error in page data */
+			__change_bit(errpos[i], (unsigned long *)buf);
+	}
+
+	printf("%d error(s) corrected at offset %08x\n",
+	       numerrs, page * DOCG4_PAGE_SIZE);
+
+	return numerrs;
+}
+
+static int read_progstatus(struct docg4_priv *doc, void __iomem *docptr)
+{
+	/*
+	 * This apparently checks the status of programming.  Done after an
+	 * erasure, and after page data is written.  On error, the status is
+	 * saved, to be later retrieved by the nand infrastructure code.
+	 */
+
+	/* status is read from the I/O reg */
+	uint16_t status1 = readw(docptr + DOC_IOSPACE_DATA);
+	uint16_t status2 = readw(docptr + DOC_IOSPACE_DATA);
+	uint16_t status3 = readw(docptr + DOCG4_MYSTERY_REG);
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "docg4: %s: %02x %02x %02x\n",
+	    __func__, status1, status2, status3);
+
+	if (status1 != DOCG4_PROGSTATUS_GOOD ||
+	    status2 != DOCG4_PROGSTATUS_GOOD_2 ||
+	    status3 != DOCG4_PROGSTATUS_GOOD_2) {
+		doc->status = NAND_STATUS_FAIL;
+		printf("read_progstatus failed: %02x, %02x, %02x\n",
+		       status1, status2, status3);
+		return -EIO;
+	}
+	return 0;
+}
+
+static int pageprog(struct mtd_info *mtd)
+{
+	/*
+	 * Final step in writing a page.  Writes the contents of its
+	 * internal buffer out to the flash array, or some such.
+	 */
+
+	struct nand_chip *nand = mtd->priv;
+	struct docg4_priv *doc = nand->priv;
+	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
+	int retval = 0;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "docg4: %s\n", __func__);
+
+	writew(DOCG4_SEQ_PAGEPROG, docptr + DOC_FLASHSEQUENCE);
+	writew(DOC_CMD_PROG_CYCLE2, docptr + DOC_FLASHCOMMAND);
+	write_nop(docptr);
+	write_nop(docptr);
+
+	/* Just busy-wait; usleep_range() slows things down noticeably. */
+	poll_status(docptr);
+
+	writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
+	writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
+	writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+
+	retval = read_progstatus(doc, docptr);
+	writew(0, docptr + DOC_DATAEND);
+	write_nop(docptr);
+	poll_status(docptr);
+	write_nop(docptr);
+
+	return retval;
+}
+
+static void sequence_reset(void __iomem *docptr)
+{
+	/* common starting sequence for all operations */
+
+	writew(DOC_CTRL_UNKNOWN | DOC_CTRL_CE, docptr + DOC_FLASHCONTROL);
+	writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
+	writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
+	write_nop(docptr);
+	write_nop(docptr);
+	poll_status(docptr);
+	write_nop(docptr);
+}
+
+static void read_page_prologue(void __iomem *docptr, uint32_t docg4_addr)
+{
+	/* first step in reading a page */
+
+	sequence_reset(docptr);
+
+	writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
+	writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
+	write_nop(docptr);
+
+	write_addr(docptr, docg4_addr);
+
+	write_nop(docptr);
+	writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
+	write_nop(docptr);
+	write_nop(docptr);
+
+	poll_status(docptr);
+}
+
+static void write_page_prologue(void __iomem *docptr, uint32_t docg4_addr)
+{
+	/* first step in writing a page */
+
+	sequence_reset(docptr);
+	writew(DOCG4_SEQ_PAGEWRITE, docptr + DOC_FLASHSEQUENCE);
+	writew(DOCG4_CMD_PAGEWRITE, docptr + DOC_FLASHCOMMAND);
+	write_nop(docptr);
+	write_addr(docptr, docg4_addr);
+	write_nop(docptr);
+	write_nop(docptr);
+	poll_status(docptr);
+}
+
+static uint32_t mtd_to_docg4_address(int page, int column)
+{
+	/*
+	 * Convert mtd address to format used by the device, 32 bit packed.
+	 *
+	 * Some notes on G4 addressing... The M-Sys documentation on this device
+	 * claims that pages are 2K in length, and indeed, the format of the
+	 * address used by the device reflects that.  But within each page are
+	 * four 512 byte "sub-pages", each with its own oob data that is
+	 * read/written immediately after the 512 bytes of page data.  This oob
+	 * data contains the ecc bytes for the preceeding 512 bytes.
+	 *
+	 * Rather than tell the mtd nand infrastructure that page size is 2k,
+	 * with four sub-pages each, we engage in a little subterfuge and tell
+	 * the infrastructure code that pages are 512 bytes in size.  This is
+	 * done because during the course of reverse-engineering the device, I
+	 * never observed an instance where an entire 2K "page" was read or
+	 * written as a unit.  Each "sub-page" is always addressed individually,
+	 * its data read/written, and ecc handled before the next "sub-page" is
+	 * addressed.
+	 *
+	 * This requires us to convert addresses passed by the mtd nand
+	 * infrastructure code to those used by the device.
+	 *
+	 * The address that is written to the device consists of four bytes: the
+	 * first two are the 2k page number, and the second is the index into
+	 * the page.  The index is in terms of 16-bit half-words and includes
+	 * the preceeding oob data, so e.g., the index into the second
+	 * "sub-page" is 0x108, and the full device address of the start of mtd
+	 * page 0x201 is 0x00800108.
+	 */
+	int g4_page = page / 4;	                      /* device's 2K page */
+	int g4_index = (page % 4) * 0x108 + column/2; /* offset into page */
+	return (g4_page << 16) | g4_index;	      /* pack */
+}
+
+static void docg4_command(struct mtd_info *mtd, unsigned command, int column,
+			  int page_addr)
+{
+	/* handle standard nand commands */
+
+	struct nand_chip *nand = mtd->priv;
+	struct docg4_priv *doc = nand->priv;
+	uint32_t g4_addr = mtd_to_docg4_address(page_addr, column);
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s %x, page_addr=%x, column=%x\n",
+	    __func__, command, page_addr, column);
+
+	/*
+	 * Save the command and its arguments.  This enables emulation of
+	 * standard flash devices, and also some optimizations.
+	 */
+	doc->last_command.command = command;
+	doc->last_command.column = column;
+	doc->last_command.page = page_addr;
+
+	switch (command) {
+	case NAND_CMD_RESET:
+		reset(CONFIG_SYS_NAND_BASE);
+		break;
+
+	case NAND_CMD_READ0:
+		read_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
+		break;
+
+	case NAND_CMD_STATUS:
+		/* next call to read_byte() will expect a status */
+		break;
+
+	case NAND_CMD_SEQIN:
+		write_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
+
+		/* hack for deferred write of oob bytes */
+		if (doc->oob_page == page_addr)
+			memcpy(nand->oob_poi, doc->oob_buf, 16);
+		break;
+
+	case NAND_CMD_PAGEPROG:
+		pageprog(mtd);
+		break;
+
+	/* we don't expect these, based on review of nand_base.c */
+	case NAND_CMD_READOOB:
+	case NAND_CMD_READID:
+	case NAND_CMD_ERASE1:
+	case NAND_CMD_ERASE2:
+		printf("docg4_command: unexpected nand command 0x%x\n",
+		       command);
+		break;
+	}
+}
+
+static void docg4_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *nand = mtd->priv;
+	uint16_t *p = (uint16_t *)buf;
+	len >>= 1;
+
+	for (i = 0; i < len; i++)
+		p[i] = readw(nand->IO_ADDR_R);
+}
+
+static int docg4_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
+			  int page, int sndcmd)
+{
+	struct docg4_priv *doc = nand->priv;
+	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
+	uint16_t status;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: page %x\n", __func__, page);
+
+	/*
+	 * Oob bytes are read as part of a normal page read.  If the previous
+	 * nand command was a read of the page whose oob is now being read, just
+	 * copy the oob bytes that we saved in a local buffer and avoid a
+	 * separate oob read.
+	 */
+	if (doc->last_command.command == NAND_CMD_READ0 &&
+	    doc->last_command.page == page) {
+		memcpy(nand->oob_poi, doc->oob_buf, 16);
+		return 0;
+	}
+
+	/*
+	 * Separate read of oob data only.
+	 */
+	docg4_command(mtd, NAND_CMD_READ0, nand->ecc.size, page);
+
+	writew(DOC_ECCCONF0_READ_MODE | DOCG4_OOB_SIZE, docptr + DOC_ECCCONF0);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+
+	/* the 1st byte from the I/O reg is a status; the rest is oob data */
+	status = readw(docptr + DOC_IOSPACE_DATA);
+	if (status & DOCG4_READ_ERROR) {
+		printf("docg4_read_oob failed: status = 0x%02x\n", status);
+		return -EIO;
+	}
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: status = 0x%x\n", __func__, status);
+
+	docg4_read_buf(mtd, nand->oob_poi, 16);
+
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+	writew(0, docptr + DOC_DATAEND);
+	write_nop(docptr);
+
+	return 0;
+}
+
+static int docg4_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
+			   int page)
+{
+	/*
+	 * Writing oob-only is not really supported, because MLC nand must write
+	 * oob bytes at the same time as page data.  Nonetheless, we save the
+	 * oob buffer contents here, and then write it along with the page data
+	 * if the same page is subsequently written.  This allows user space
+	 * utilities that write the oob data prior to the page data to work
+	 * (e.g., nandwrite).  The disdvantage is that, if the intention was to
+	 * write oob only, the operation is quietly ignored.  Also, oob can get
+	 * corrupted if two concurrent processes are running nandwrite.
+	 */
+
+	/* note that bytes 7..14 are hw generated hamming/ecc and overwritten */
+	struct docg4_priv *doc = nand->priv;
+	doc->oob_page = page;
+	memcpy(doc->oob_buf, nand->oob_poi, 16);
+	return 0;
+}
+
+static int docg4_block_neverbad(struct mtd_info *mtd, loff_t ofs, int getchip)
+{
+	/* only called when module_param ignore_badblocks is set */
+	return 0;
+}
+
+static void docg4_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *nand = mtd->priv;
+	uint16_t *p = (uint16_t *)buf;
+	len >>= 1;
+
+	for (i = 0; i < len; i++)
+		writew(p[i], nand->IO_ADDR_W);
+}
+
+static void write_page(struct mtd_info *mtd, struct nand_chip *nand,
+		       const uint8_t *buf, int use_ecc)
+{
+	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
+	uint8_t ecc_buf[8];
+
+	writew(DOC_ECCCONF0_ECC_ENABLE |
+	       DOC_ECCCONF0_UNKNOWN |
+	       DOCG4_BCH_SIZE,
+	       docptr + DOC_ECCCONF0);
+	write_nop(docptr);
+
+	/* write the page data */
+	docg4_write_buf16(mtd, buf, DOCG4_PAGE_SIZE);
+
+	/* oob bytes 0 through 5 are written to I/O reg */
+	docg4_write_buf16(mtd, nand->oob_poi, 6);
+
+	/* oob byte 6 written to a separate reg */
+	writew(nand->oob_poi[6], docptr + DOCG4_OOB_6_7);
+
+	write_nop(docptr);
+	write_nop(docptr);
+
+	/* write hw-generated ecc bytes to oob */
+	if (likely(use_ecc)) {
+		/* oob byte 7 is hamming code */
+		uint8_t hamming = readb(docptr + DOC_HAMMINGPARITY);
+		hamming = readb(docptr + DOC_HAMMINGPARITY); /* 2nd read */
+		writew(hamming, docptr + DOCG4_OOB_6_7);
+		write_nop(docptr);
+
+		/* read the 7 bch bytes from ecc regs */
+		read_hw_ecc(docptr, ecc_buf);
+		ecc_buf[7] = 0;         /* clear the "page written" flag */
+	}
+
+	/* write user-supplied bytes to oob */
+	else {
+		writew(nand->oob_poi[7], docptr + DOCG4_OOB_6_7);
+		write_nop(docptr);
+		memcpy(ecc_buf, &nand->oob_poi[8], 8);
+	}
+
+	docg4_write_buf16(mtd, ecc_buf, 8);
+	write_nop(docptr);
+	write_nop(docptr);
+	writew(0, docptr + DOC_DATAEND);
+	write_nop(docptr);
+}
+
+static void docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
+				 const uint8_t *buf)
+{
+	return write_page(mtd, nand, buf, 0);
+}
+
+static void docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand,
+			     const uint8_t *buf)
+{
+	return write_page(mtd, nand, buf, 1);
+}
+
+static int read_page(struct mtd_info *mtd, struct nand_chip *nand,
+		     uint8_t *buf, int page, int use_ecc)
+{
+	struct docg4_priv *doc = nand->priv;
+	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
+	uint16_t status, edc_err, *buf16;
+
+	writew(DOC_ECCCONF0_READ_MODE |
+	       DOC_ECCCONF0_ECC_ENABLE |
+	       DOC_ECCCONF0_UNKNOWN |
+	       DOCG4_BCH_SIZE,
+	       docptr + DOC_ECCCONF0);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+
+	/* the 1st byte from the I/O reg is a status; the rest is page data */
+	status = readw(docptr + DOC_IOSPACE_DATA);
+	if (status & DOCG4_READ_ERROR) {
+		printf("docg4_read_page: bad status: 0x%02x\n", status);
+		writew(0, docptr + DOC_DATAEND);
+		return -EIO;
+	}
+
+	docg4_read_buf(mtd, buf, DOCG4_PAGE_SIZE); /* read the page data */
+
+	/* first 14 oob bytes read from I/O reg */
+	docg4_read_buf(mtd, nand->oob_poi, 14);
+
+	/* last 2 read from another reg */
+	buf16 = (uint16_t *)(nand->oob_poi + 14);
+	*buf16 = readw(docptr + DOCG4_MYSTERY_REG);
+
+	/*
+	 * Diskonchips read oob immediately after a page read.  Mtd
+	 * infrastructure issues a separate command for reading oob after the
+	 * page is read.  So we save the oob bytes in a local buffer and just
+	 * copy it if the next command reads oob from the same page.
+	 */
+	memcpy(doc->oob_buf, nand->oob_poi, 16);
+
+	write_nop(docptr);
+
+	if (likely(use_ecc)) {
+		/* read the register that tells us if bitflip(s) detected  */
+		edc_err = readw(docptr + DOC_ECCCONF1);
+		edc_err = readw(docptr + DOC_ECCCONF1);
+
+		/* If bitflips are reported, attempt to correct with ecc */
+		if (edc_err & DOC_ECCCONF1_BCH_SYNDROM_ERR) {
+			int bits_corrected = correct_data(mtd, buf, page);
+			if (bits_corrected == -EBADMSG)
+				mtd->ecc_stats.failed++;
+			else
+				mtd->ecc_stats.corrected += bits_corrected;
+		}
+	}
+
+	writew(0, docptr + DOC_DATAEND);
+	return 0;
+}
+
+
+static int docg4_read_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
+			       uint8_t *buf, int page)
+{
+	return read_page(mtd, nand, buf, page, 0);
+}
+
+static int docg4_read_page(struct mtd_info *mtd, struct nand_chip *nand,
+			   uint8_t *buf, int page)
+{
+	return read_page(mtd, nand, buf, page, 1);
+}
+
+static void docg4_erase_block(struct mtd_info *mtd, int page)
+{
+	struct nand_chip *nand = mtd->priv;
+	struct docg4_priv *doc = nand->priv;
+	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
+	uint16_t g4_page;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: page %04x\n", __func__, page);
+
+	sequence_reset(docptr);
+
+	writew(DOCG4_SEQ_BLOCKERASE, docptr + DOC_FLASHSEQUENCE);
+	writew(DOC_CMD_PROG_BLOCK_ADDR, docptr + DOC_FLASHCOMMAND);
+	write_nop(docptr);
+
+	/* only 2 bytes of address are written to specify erase block */
+	g4_page = (uint16_t)(page / 4);  /* to g4's 2k page addressing */
+	writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
+	g4_page >>= 8;
+	writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
+	write_nop(docptr);
+
+	/* start the erasure */
+	writew(DOC_CMD_ERASECYCLE2, docptr + DOC_FLASHCOMMAND);
+	write_nop(docptr);
+	write_nop(docptr);
+
+	poll_status(docptr);
+	writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
+	writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
+	writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+
+	read_progstatus(doc, docptr);
+
+	writew(0, docptr + DOC_DATAEND);
+	write_nop(docptr);
+	poll_status(docptr);
+	write_nop(docptr);
+}
+
+static int read_factory_bbt(struct mtd_info *mtd)
+{
+	/*
+	 * The device contains a read-only factory bad block table.  Read it and
+	 * update the memory-based bbt accordingly.
+	 */
+
+	struct nand_chip *nand = mtd->priv;
+	uint32_t g4_addr = mtd_to_docg4_address(DOCG4_FACTORY_BBT_PAGE, 0);
+	uint8_t *buf;
+	int i, block, status;
+
+	buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
+	if (buf == NULL)
+		return -ENOMEM;
+
+	read_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
+	status = docg4_read_page(mtd, nand, buf, DOCG4_FACTORY_BBT_PAGE);
+	if (status)
+		goto exit;
+
+	/*
+	 * If no memory-based bbt was created, exit.  This will happen if module
+	 * parameter ignore_badblocks is set.  Then why even call this function?
+	 * For an unknown reason, block erase always fails if it's the first
+	 * operation after device power-up.  The above read ensures it never is.
+	 * Ugly, I know.
+	 */
+	if (nand->bbt == NULL)  /* no memory-based bbt */
+		goto exit;
+
+	/*
+	 * Parse factory bbt and update memory-based bbt.  Factory bbt format is
+	 * simple: one bit per block, block numbers increase left to right (msb
+	 * to lsb).  Bit clear means bad block.
+	 */
+	for (i = block = 0; block < DOCG4_NUMBLOCKS; block += 8, i++) {
+		int bitnum;
+		uint8_t mask;
+		for (bitnum = 0, mask = 0x80;
+		     bitnum < 8; bitnum++, mask >>= 1) {
+			if (!(buf[i] & mask)) {
+				int badblock = block + bitnum;
+				nand->bbt[badblock / 4] |=
+					0x03 << ((badblock % 4) * 2);
+				mtd->ecc_stats.badblocks++;
+				printf("factory-marked bad block: %d\n",
+				       badblock);
+			}
+		}
+	}
+ exit:
+	kfree(buf);
+	return status;
+}
+
+static int docg4_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+	/*
+	 * Mark a block as bad.  Bad blocks are marked in the oob area of the
+	 * first page of the block.  The default scan_bbt() in the nand
+	 * infrastructure code works fine for building the memory-based bbt
+	 * during initialization, as does the nand infrastructure function that
+	 * checks if a block is bad by reading the bbt.  This function replaces
+	 * the nand default because writes to oob-only are not supported.
+	 */
+
+	int ret, i;
+	uint8_t *buf;
+	struct nand_chip *nand = mtd->priv;
+	struct nand_bbt_descr *bbtd = nand->badblock_pattern;
+	int block = (int)(ofs >> nand->bbt_erase_shift);
+	int page = (int)(ofs >> nand->page_shift);
+	uint32_t g4_addr = mtd_to_docg4_address(page, 0);
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: %08llx\n", __func__, ofs);
+
+	if (unlikely(ofs & (DOCG4_BLOCK_SIZE - 1)))
+		printf("%s: ofs %llx not start of block!\n",
+		       __func__, ofs);
+
+	/* allocate blank buffer for page data */
+	buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
+	if (buf == NULL)
+		return -ENOMEM;
+
+	/* update bbt in memory */
+	nand->bbt[block / 4] |= 0x01 << ((block & 0x03) * 2);
+
+	/* write bit-wise negation of pattern to oob buffer */
+	memset(nand->oob_poi, 0xff, mtd->oobsize);
+	for (i = 0; i < bbtd->len; i++)
+		nand->oob_poi[bbtd->offs + i] = ~bbtd->pattern[i];
+
+	/* write first page of block */
+	write_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
+	docg4_write_page(mtd, nand, buf);
+	ret = pageprog(mtd);
+	if (!ret)
+		mtd->ecc_stats.badblocks++;
+
+	kfree(buf);
+
+	return ret;
+}
+
+static uint8_t docg4_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *nand = mtd->priv;
+	struct docg4_priv *doc = nand->priv;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s\n", __func__);
+
+	if (doc->last_command.command == NAND_CMD_STATUS) {
+		int status;
+
+		/*
+		 * Previous nand command was status request, so nand
+		 * infrastructure code expects to read the status here.  If an
+		 * error occurred in a previous operation, report it.
+		 */
+		doc->last_command.command = 0;
+
+		if (doc->status) {
+			status = doc->status;
+			doc->status = 0;
+		}
+
+		/* why is NAND_STATUS_WP inverse logic?? */
+		else
+			status = NAND_STATUS_WP | NAND_STATUS_READY;
+
+		return status;
+	}
+
+	printf("unexpectd call to read_byte()\n");
+
+	return 0;
+}
+
+static int docg4_wait(struct mtd_info *mtd, struct nand_chip *nand)
+{
+	struct docg4_priv *doc = nand->priv;
+	int status = NAND_STATUS_WP;       /* inverse logic?? */
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s...\n", __func__);
+
+	/* report any previously unreported error */
+	if (doc->status) {
+		status |= doc->status;
+		doc->status = 0;
+		return status;
+	}
+
+	status |= poll_status(CONFIG_SYS_NAND_BASE);
+	return status;
+}
+
+int docg4_nand_init(struct mtd_info *mtd, struct nand_chip *nand, int devnum)
+{
+	uint16_t id1, id2;
+	struct docg4_priv *docg4;
+	int retval;
+
+	docg4 = kzalloc(sizeof(*docg4), GFP_KERNEL);
+	if (!docg4)
+		return -1;
+
+	mtd->priv = nand;
+	nand->priv = docg4;
+
+	/* These must be initialized here because the docg4 is non-standard
+	 * and doesn't produce an id that the nand code can use to look up
+	 * these values (nand_scan_ident() not called).
+	 */
+	mtd->size = DOCG4_CHIP_SIZE;
+	mtd->name = "Msys_Diskonchip_G4";
+	mtd->writesize = DOCG4_PAGE_SIZE;
+	mtd->erasesize = DOCG4_BLOCK_SIZE;
+	mtd->oobsize = DOCG4_OOB_SIZE;
+
+	nand->IO_ADDR_R =
+		(void __iomem *)CONFIG_SYS_NAND_BASE + DOC_IOSPACE_DATA;
+	nand->IO_ADDR_W = nand->IO_ADDR_R;
+	nand->chipsize = DOCG4_CHIP_SIZE;
+	nand->chip_shift = DOCG4_CHIP_SHIFT;
+	nand->bbt_erase_shift = DOCG4_ERASE_SHIFT;
+	nand->phys_erase_shift = DOCG4_ERASE_SHIFT;
+	nand->chip_delay = 20;
+	nand->page_shift = DOCG4_PAGE_SHIFT;
+	nand->pagemask = 0x3ffff;
+	nand->badblockpos = NAND_LARGE_BADBLOCK_POS;
+	nand->badblockbits = 8;
+	nand->ecc.layout = &docg4_oobinfo;
+	nand->ecc.mode = NAND_ECC_HW_SYNDROME;
+	nand->ecc.size = DOCG4_PAGE_SIZE;
+	nand->ecc.prepad = 8;
+	nand->ecc.bytes	= 8;
+	nand->options =
+		NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE | NAND_NO_AUTOINCR;
+	nand->controller = &nand->hwcontrol;
+
+	/* methods */
+	nand->cmdfunc = docg4_command;
+	nand->waitfunc = docg4_wait;
+	nand->select_chip = docg4_select_chip;
+	nand->read_byte = docg4_read_byte;
+	nand->block_markbad = docg4_block_markbad;
+	nand->read_buf = docg4_read_buf;
+	nand->write_buf = docg4_write_buf16;
+	nand->scan_bbt = nand_default_bbt;
+	nand->erase_cmd = docg4_erase_block;
+	nand->ecc.read_page = docg4_read_page;
+	nand->ecc.write_page = docg4_write_page;
+	nand->ecc.read_page_raw = docg4_read_page_raw;
+	nand->ecc.write_page_raw = docg4_write_page_raw;
+	nand->ecc.read_oob = docg4_read_oob;
+	nand->ecc.write_oob = docg4_write_oob;
+
+	/*
+	 * The way the nand infrastructure code is written, a memory-based bbt
+	 * is not created if NAND_SKIP_BBTSCAN is set.  With no memory bbt,
+	 * nand->block_bad() is used.  So when ignoring bad blocks, we skip the
+	 * scan and define a dummy block_bad() which always returns 0.
+	 */
+	if (ignore_badblocks) {
+		nand->options |= NAND_SKIP_BBTSCAN;
+		nand->block_bad	= docg4_block_neverbad;
+	}
+
+	reset(CONFIG_SYS_NAND_BASE);
+
+	/* check for presence of g4 chip by reading id registers */
+	id1 = readw(CONFIG_SYS_NAND_BASE + DOC_CHIPID);
+	id1 = readw(CONFIG_SYS_NAND_BASE + DOCG4_MYSTERY_REG);
+	id2 = readw(CONFIG_SYS_NAND_BASE + DOC_CHIPID_INV);
+	id2 = readw(CONFIG_SYS_NAND_BASE + DOCG4_MYSTERY_REG);
+	if (id1 != DOCG4_IDREG1_VALUE || id2 != DOCG4_IDREG2_VALUE)
+		return -1;
+
+	/* initialize bch algorithm */
+	docg4->bch = init_bch(DOCG4_M, DOCG4_T, DOCG4_PRIMITIVE_POLY);
+	if (docg4->bch == NULL)
+		return -1;
+
+	retval = nand_scan_tail(mtd);
+	if (retval)
+		return -1;
+
+	/*
+	 * Scan for bad blocks and create bbt here, then add the factory-marked
+	 * bad blocks to the bbt.
+	 */
+	nand->scan_bbt(mtd);
+	nand->options |= NAND_BBT_SCANNED;
+	retval = read_factory_bbt(mtd);
+	if (retval)
+		return -1;
+
+	retval = nand_register(devnum);
+	if (retval)
+		return -1;
+
+	return 0;
+}
diff --git a/drivers/mtd/nand/docg4_spl.c b/drivers/mtd/nand/docg4_spl.c
new file mode 100644
index 0000000..95e856c
--- /dev/null
+++ b/drivers/mtd/nand/docg4_spl.c
@@ -0,0 +1,222 @@
+/*
+ * SPL driver for Diskonchip G4 nand flash
+ *
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ *
+ * This driver basically mimics the load functionality of a typical IPL (initial
+ * program loader) resident in the 2k NOR-like region of the docg4 that is
+ * mapped to the reset vector.  It allows the u-boot SPL to continue loading if
+ * the IPL loads a fixed number of flash blocks that is insufficient to contain
+ * the entire u-boot image.  In this case, a concatenated spl + u-boot image is
+ * written at the flash offset from which the IPL loads an image, and when the
+ * IPL jumps to the SPL, the SPL resumes loading where the IPL left off.  See
+ * the palmtreo680 for an example.
+ *
+ * This driver assumes that the data was written to the flash using the device's
+ * "reliable" mode, and also assumes that each 512 byte page is stored
+ * redundantly in the subsequent page.  This storage format is likely to be used
+ * by all boards that boot from the docg4.  The format compensates for the lack
+ * of ecc in the IPL.
+ *
+ * Reliable mode reduces the capacity of a block by half, and the redundant
+ * pages reduce it by half again.  As a result, the normal 256k capacity of a
+ * block is reduced to 64k for the purposes of the IPL/SPL.
+ */
+
+#include <asm/io.h>
+#include <linux/mtd/docg4.h>
+
+/* forward declarations */
+static inline void write_nop(void __iomem *docptr);
+static int poll_status(void __iomem *docptr);
+static void write_addr(void __iomem *docptr, uint32_t docg4_addr);
+static void address_sequence(unsigned int g4_page, unsigned int g4_index,
+			     void __iomem *docptr);
+static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr);
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+	void *load_addr = dst;
+	uint32_t flash_offset = offs;
+	const unsigned int block_count =
+		(size + DOCG4_BLOCK_CAPACITY_SPL - 1)
+		/ DOCG4_BLOCK_CAPACITY_SPL;
+	int i;
+
+	for (i = 0; i < block_count; i++) {
+		int ret = docg4_load_block_reliable(flash_offset, load_addr);
+		if (ret)
+			return ret;
+		load_addr += DOCG4_BLOCK_CAPACITY_SPL;
+		flash_offset += DOCG4_BLOCK_SIZE;
+	}
+	return 0;
+}
+
+static inline void write_nop(void __iomem *docptr)
+{
+	writew(0, docptr + DOC_NOP);
+}
+
+static int poll_status(void __iomem *docptr)
+{
+	/*
+	 * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
+	 * register.  Operations known to take a long time (e.g., block erase)
+	 * should sleep for a while before calling this.
+	 */
+
+	uint8_t flash_status;
+
+	/* hardware quirk requires reading twice initially */
+	flash_status = readb(docptr + DOC_FLASHCONTROL);
+
+	do {
+		flash_status = readb(docptr + DOC_FLASHCONTROL);
+	} while (!(flash_status & DOC_CTRL_FLASHREADY));
+
+	return 0;
+}
+
+static void write_addr(void __iomem *docptr, uint32_t docg4_addr)
+{
+	/* write the four address bytes packed in docg4_addr to the device */
+
+	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+	docg4_addr >>= 8;
+	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+	docg4_addr >>= 8;
+	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+	docg4_addr >>= 8;
+	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+}
+
+static void address_sequence(unsigned int g4_page, unsigned int g4_index,
+			     void __iomem *docptr)
+{
+	writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
+	writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
+	write_nop(docptr);
+	write_addr(docptr, ((uint32_t)g4_page << 16) | g4_index);
+	write_nop(docptr);
+}
+
+static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr)
+{
+	void __iomem *docptr = (void *)CONFIG_SYS_NAND_BASE;
+	unsigned int g4_page = flash_offset >> 11; /* 2k page */
+	const unsigned int last_g4_page = g4_page + 0x80; /* last in block */
+	int g4_index = 0;
+	uint16_t flash_status;
+	uint16_t *buf;
+	uint16_t discard, magic_high, magic_low;
+
+	/* flash_offset must be aligned to the start of a block */
+	if (flash_offset & 0x3ffff)
+		return -1;
+
+	writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
+	writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
+	write_nop(docptr);
+	write_nop(docptr);
+	poll_status(docptr);
+	write_nop(docptr);
+	writew(0x45, docptr + DOC_FLASHSEQUENCE);
+	writew(0xa3, docptr + DOC_FLASHCOMMAND);
+	write_nop(docptr);
+	writew(0x22, docptr + DOC_FLASHCOMMAND);
+	write_nop(docptr);
+
+	/* read 1st 4 oob bytes of first subpage of block */
+	address_sequence(g4_page, 0x0100, docptr); /* index at oob */
+	write_nop(docptr);
+	flash_status = readw(docptr + DOC_FLASHCONTROL);
+	flash_status = readw(docptr + DOC_FLASHCONTROL);
+	if (flash_status & 0x06) /* sequence or protection errors */
+		return -1;
+	writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
+	write_nop(docptr);
+	write_nop(docptr);
+	poll_status(docptr);
+	writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+	write_nop(docptr);
+
+	/*
+	 * Here we read the first four oob bytes of the first page of the block.
+	 * The IPL on the palmtreo680 requires that this contain a 32 bit magic
+	 * number, or the load aborts.  We'll ignore it.
+	 */
+	discard = readw(docptr + 0x103c); /* hw quirk; 1st read discarded */
+	magic_low = readw(docptr + 0x103c);
+	magic_high = readw(docptr + DOCG4_MYSTERY_REG);
+	writew(0, docptr + DOC_DATAEND);
+	write_nop(docptr);
+	write_nop(docptr);
+
+	/* load contents of block to memory */
+	buf = (uint16_t *)dest_addr;
+	do {
+		int i;
+
+		address_sequence(g4_page, g4_index, docptr);
+		writew(DOCG4_CMD_READ2,
+		       docptr + DOC_FLASHCOMMAND);
+		write_nop(docptr);
+		write_nop(docptr);
+		poll_status(docptr);
+		writew(DOC_ECCCONF0_READ_MODE |
+		       DOC_ECCCONF0_ECC_ENABLE |
+		       DOCG4_BCH_SIZE,
+		       docptr + DOC_ECCCONF0);
+		write_nop(docptr);
+		write_nop(docptr);
+		write_nop(docptr);
+		write_nop(docptr);
+		write_nop(docptr);
+
+		/* read the 512 bytes of page data, 2 bytes at a time */
+		discard = readw(docptr + 0x103c);
+		for (i = 0; i < 256; i++)
+			*buf++ = readw(docptr + 0x103c);
+
+		/* read oob, but discard it */
+		for (i = 0; i < 7; i++)
+			discard = readw(docptr + 0x103c);
+		discard = readw(docptr + DOCG4_OOB_6_7);
+		discard = readw(docptr + DOCG4_OOB_6_7);
+
+		writew(0, docptr + DOC_DATAEND);
+		write_nop(docptr);
+		write_nop(docptr);
+
+		if (!(g4_index & 0x100)) {
+			/* not redundant subpage read; check for ecc error */
+			write_nop(docptr);
+			flash_status = readw(docptr + DOC_ECCCONF1);
+			flash_status = readw(docptr + DOC_ECCCONF1);
+			if (flash_status & 0x80) { /* ecc error */
+				g4_index += 0x108; /* read redundant subpage */
+				buf -= 256;        /* back up ram ptr */
+				continue;
+			} else                       /* no ecc error */
+				g4_index += 0x210; /* skip redundant subpage */
+		} else  /* redundant page was just read; skip ecc error check */
+			g4_index += 0x108;
+
+		if (g4_index == 0x420) { /* finished with 2k page */
+			g4_index = 0;
+			g4_page += 2; /* odd-numbered 2k pages skipped */
+		}
+
+	} while (g4_page != last_g4_page); /* while still on same block */
+
+	return 0;
+}
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 834a8a6..0fa776a 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -640,9 +640,8 @@
 	return fsl_elbc_read_byte(mtd);
 }
 
-static int fsl_elbc_read_page(struct mtd_info *mtd,
-			      struct nand_chip *chip,
-			      uint8_t *buf, int page)
+static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+			      uint8_t *buf, int oob_required, int page)
 {
 	fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 	fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -656,12 +655,13 @@
 /* ECC will be calculated automatically, and errors will be detected in
  * waitfunc.
  */
-static void fsl_elbc_write_page(struct mtd_info *mtd,
-				struct nand_chip *chip,
-				const uint8_t *buf)
+static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+				const uint8_t *buf, int oob_required)
 {
 	fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 	fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+	return 0;
 }
 
 static struct fsl_elbc_ctrl *elbc_ctrl;
@@ -747,8 +747,8 @@
 	nand->bbt_md = &bbt_mirror_descr;
 
   	/* set up nand options */
-	nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
-			NAND_USE_FLASH_BBT | NAND_NO_SUBPAGE_WRITE;
+	nand->options = NAND_NO_SUBPAGE_WRITE;
+	nand->bbt_options = NAND_BBT_USE_FLASH;
 
 	nand->controller = &elbc_ctrl->controller;
 	nand->priv = priv;
@@ -756,20 +756,8 @@
 	nand->ecc.read_page = fsl_elbc_read_page;
 	nand->ecc.write_page = fsl_elbc_write_page;
 
-#ifdef CONFIG_FSL_ELBC_FMR
-	priv->fmr = CONFIG_FSL_ELBC_FMR;
-#else
 	priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
 
-	/*
-	 * Hardware expects small page has ECCM0, large page has ECCM1
-	 * when booting from NAND.  Board config can override if not
-	 * booting from NAND.
-	 */
-	if (or & OR_FCM_PGS)
-		priv->fmr |= FMR_ECCM;
-#endif
-
 	/* If CS Base Register selects full hardware ECC then use it */
 	if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 		nand->ecc.mode = NAND_ECC_HW;
@@ -781,16 +769,32 @@
 		nand->ecc.size = 512;
 		nand->ecc.bytes = 3;
 		nand->ecc.steps = 1;
+		nand->ecc.strength = 1;
 	} else {
 		/* otherwise fall back to default software ECC */
 		nand->ecc.mode = NAND_ECC_SOFT;
 	}
 
+	ret = nand_scan_ident(mtd, 1, NULL);
+	if (ret)
+		return ret;
+
 	/* Large-page-specific setup */
-	if (or & OR_FCM_PGS) {
+	if (mtd->writesize == 2048) {
+		setbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
+			     OR_FCM_PGS);
+		in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
+
 		priv->page_size = 1;
 		nand->badblock_pattern = &largepage_memorybased;
 
+		/*
+		 * Hardware expects small page has ECCM0, large page has
+		 * ECCM1 when booting from NAND, and we follow that even
+		 * when not booting from NAND.
+		 */
+		priv->fmr |= FMR_ECCM;
+
 		/* adjust ecc setup if needed */
 		if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 			nand->ecc.steps = 4;
@@ -798,12 +802,14 @@
 					   &fsl_elbc_oob_lp_eccm1 :
 					   &fsl_elbc_oob_lp_eccm0;
 		}
+	} else if (mtd->writesize == 512) {
+		clrbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
+			     OR_FCM_PGS);
+		in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
+	} else {
+		return -ENODEV;
 	}
 
-	ret = nand_scan_ident(mtd, 1, NULL);
-	if (ret)
-		return ret;
-
 	ret = nand_scan_tail(mtd);
 	if (ret)
 		return ret;
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index b13d8a9..439822c 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -21,6 +21,7 @@
 
 #include <common.h>
 #include <malloc.h>
+#include <nand.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -41,7 +42,6 @@
 
 /* mtd information per set */
 struct fsl_ifc_mtd {
-	struct mtd_info mtd;
 	struct nand_chip chip;
 	struct fsl_ifc_ctrl *ctrl;
 
@@ -686,9 +686,8 @@
 	return nand_fsr;
 }
 
-static int fsl_ifc_read_page(struct mtd_info *mtd,
-			      struct nand_chip *chip,
-			      uint8_t *buf, int page)
+static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+			     uint8_t *buf, int oob_required, int page)
 {
 	struct fsl_ifc_mtd *priv = chip->priv;
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
@@ -705,12 +704,13 @@
 /* ECC will be calculated automatically, and errors will be detected in
  * waitfunc.
  */
-static void fsl_ifc_write_page(struct mtd_info *mtd,
-				struct nand_chip *chip,
-				const uint8_t *buf)
+static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+			       const uint8_t *buf, int oob_required)
 {
 	fsl_ifc_write_buf(mtd, buf, mtd->writesize);
 	fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+	return 0;
 }
 
 static void fsl_ifc_ctrl_init(void)
@@ -794,11 +794,14 @@
 	out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
 }
 
-int board_nand_init(struct nand_chip *nand)
+static int fsl_ifc_chip_init(int devnum, u8 *addr)
 {
+	struct mtd_info *mtd = &nand_info[devnum];
+	struct nand_chip *nand;
 	struct fsl_ifc_mtd *priv;
 	struct nand_ecclayout *layout;
 	uint32_t cspr = 0, csor = 0, ver = 0;
+	int ret;
 
 	if (!ifc_ctrl) {
 		fsl_ifc_ctrl_init();
@@ -811,18 +814,18 @@
 		return -ENOMEM;
 
 	priv->ctrl = ifc_ctrl;
-	priv->vbase = nand->IO_ADDR_R;
+	priv->vbase = addr;
 
 	/* Find which chip select it is connected to.
 	 */
 	for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
-		phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R);
+		phys_addr_t phys_addr = virt_to_phys(addr);
 
 		cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
 		csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
 
 		if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
-		    (cspr & CSPR_BA) == CSPR_PHYS_ADDR(base_addr)) {
+		    (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
 			ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
 			break;
 		}
@@ -835,6 +838,9 @@
 		return -ENODEV;
 	}
 
+	nand = &priv->chip;
+	mtd->priv = nand;
+
 	ifc_ctrl->chips[priv->bank] = priv;
 
 	/* fill in nand_chip structure */
@@ -852,8 +858,8 @@
 	nand->bbt_md = &bbt_mirror_descr;
 
 	/* set up nand options */
-	nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
-			NAND_USE_FLASH_BBT | NAND_NO_SUBPAGE_WRITE;
+	nand->options = NAND_NO_SUBPAGE_WRITE;
+	nand->bbt_options = NAND_BBT_USE_FLASH;
 
 	if (cspr & CSPR_PORT_SIZE_16) {
 		nand->read_byte = fsl_ifc_read_byte16;
@@ -884,11 +890,13 @@
 			bbt_mirror_descr.offs = 0;
 		}
 
+		nand->ecc.strength = 4;
 		priv->bufnum_mask = 15;
 		break;
 
 	case CSOR_NAND_PGS_2K:
 		layout = &oob_2048_ecc4;
+		nand->ecc.strength = 4;
 		priv->bufnum_mask = 3;
 		break;
 
@@ -896,8 +904,10 @@
 		if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
 		    CSOR_NAND_ECC_MODE_4) {
 			layout = &oob_4096_ecc4;
+			nand->ecc.strength = 4;
 		} else {
 			layout = &oob_4096_ecc8;
+			nand->ecc.strength = 8;
 			nand->ecc.bytes = 16;
 		}
 
@@ -921,5 +931,31 @@
 	if (ver == FSL_IFC_V1_1_0)
 		fsl_ifc_sram_init();
 
+	ret = nand_scan_ident(mtd, 1, NULL);
+	if (ret)
+		return ret;
+
+	ret = nand_scan_tail(mtd);
+	if (ret)
+		return ret;
+
+	ret = nand_register(devnum);
+	if (ret)
+		return ret;
 	return 0;
 }
+
+#ifndef CONFIG_SYS_NAND_BASE_LIST
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#endif
+
+static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
+	CONFIG_SYS_NAND_BASE_LIST;
+
+void board_nand_init(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		fsl_ifc_chip_init(i, (u8 *)base_address[i]);
+}
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 7a61d88..fab2aeb 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -341,6 +341,7 @@
  * @mtd:	mtd info structure
  * @chip:	nand chip info structure
  * @buf:	buffer to store read data
+ * @oob_required:	caller expects OOB data read to chip->oob_poi
  * @page:	page number to read
  *
  * This routine is needed for fsmc verison 8 as reading from NAND chip has to be
@@ -350,7 +351,7 @@
  * max of 8 bits)
  */
 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
-				 uint8_t *buf, int page)
+				 uint8_t *buf, int oob_required, int page)
 {
 	struct fsmc_eccplace *fsmc_eccpl;
 	int i, j, s, stat, eccsize = chip->ecc.size;
@@ -452,6 +453,7 @@
 	switch (fsmc_version) {
 	case FSMC_VER8:
 		nand->ecc.bytes = 13;
+		nand->ecc.strength = 8;
 		nand->ecc.correct = fsmc_bch8_correct_data;
 		nand->ecc.read_page = fsmc_read_page_hwecc;
 		if (mtd->writesize == 512)
@@ -466,6 +468,7 @@
 		break;
 	default:
 		nand->ecc.bytes = 3;
+		nand->ecc.strength = 1;
 		nand->ecc.layout = &fsmc_ecc1_layout;
 		nand->ecc.correct = nand_correct_data;
 		break;
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index 3ec34f3..a691fbc 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -253,6 +253,7 @@
 	nand->ecc.mode		= NAND_ECC_HW_OOB_FIRST;
 	nand->ecc.size		= CONFIG_SYS_NAND_ECCSIZE;
 	nand->ecc.bytes		= CONFIG_SYS_NAND_ECCBYTES;
+	nand->ecc.strength	= 4;
 	nand->ecc.layout	= &qi_lb60_ecclayout_2gb;
 	nand->chip_delay	= 50;
 	nand->options		= NAND_USE_FLASH_BBT;
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index e6b7a70..e53f341 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -621,7 +621,7 @@
 	chip->write_buf = mpc5121_nfc_write_buf;
 	chip->verify_buf = mpc5121_nfc_verify_buf;
 	chip->select_chip = mpc5121_nfc_select_chip;
-	chip->options = NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT;
+	chip->bbt_options = NAND_BBT_USE_FLASH;
 	chip->ecc.mode = NAND_ECC_SOFT;
 
 	/* Reset NAND Flash controller */
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index eeba521..ac435f2 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -396,7 +396,7 @@
 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
 				      struct nand_chip *chip,
-				      int page, int sndcmd)
+				      int page)
 {
 	struct mxc_nand_host *host = chip->priv;
 	uint8_t *buf = chip->oob_poi;
@@ -450,6 +450,7 @@
 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
 					   struct nand_chip *chip,
 					   uint8_t *buf,
+					   int oob_required,
 					   int page)
 {
 	struct mxc_nand_host *host = chip->priv;
@@ -494,6 +495,7 @@
 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
 				       struct nand_chip *chip,
 				       uint8_t *buf,
+				       int oob_required,
 				       int page)
 {
 	struct mxc_nand_host *host = chip->priv;
@@ -583,9 +585,10 @@
 	return status & NAND_STATUS_FAIL ? -EIO : 0;
 }
 
-static void mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
+static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 					     struct nand_chip *chip,
-					     const uint8_t *buf)
+					     const uint8_t *buf,
+					     int oob_required)
 {
 	struct mxc_nand_host *host = chip->priv;
 	int eccsize = chip->ecc.size;
@@ -619,11 +622,13 @@
 	size = mtd->oobsize - (oob - chip->oob_poi);
 	if (size)
 		chip->write_buf(mtd, oob, size);
+	return 0;
 }
 
-static void mxc_nand_write_page_syndrome(struct mtd_info *mtd,
+static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
 					 struct nand_chip *chip,
-					 const uint8_t *buf)
+					 const uint8_t *buf,
+					 int oob_required)
 {
 	struct mxc_nand_host *host = chip->priv;
 	int i, n, eccsize = chip->ecc.size;
@@ -662,6 +667,7 @@
 	i = mtd->oobsize - (oob - chip->oob_poi);
 	if (i)
 		chip->write_buf(mtd, oob, i);
+	return 0;
 }
 
 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
@@ -1188,7 +1194,7 @@
 #endif
 
 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
-	this->options |= NAND_USE_FLASH_BBT;
+	this->bbt_options |= NAND_BBT_USE_FLASH;
 	this->bbt_td = &bbt_main_descr;
 	this->bbt_md = &bbt_mirror_descr;
 #endif
@@ -1236,6 +1242,13 @@
 		this->ecc.mode = NAND_ECC_HW;
 	}
 
+	if (this->ecc.mode == NAND_ECC_HW) {
+		if (is_mxc_nfc_1())
+			this->ecc.strength = 1;
+		else
+			this->ecc.strength = 4;
+	}
+
 	host->pagesize_2k = 0;
 
 	this->ecc.size = 512;
diff --git a/drivers/mtd/nand/mxc_nand_spl.c b/drivers/mtd/nand/mxc_nand_spl.c
index edc589e..ba725e9 100644
--- a/drivers/mtd/nand/mxc_nand_spl.c
+++ b/drivers/mtd/nand/mxc_nand_spl.c
@@ -290,7 +290,7 @@
 	return 0;
 }
 
-static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
+int nand_spl_load_image(uint32_t from, unsigned int size, void *buf)
 {
 	int i;
 	unsigned int page;
@@ -303,6 +303,7 @@
 	page = from / CONFIG_SYS_NAND_PAGE_SIZE;
 	i = 0;
 
+	size = roundup(size, CONFIG_SYS_NAND_PAGE_SIZE);
 	while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) {
 		if (nfc_read_page(page, buf) < 0)
 			return -1;
@@ -332,6 +333,7 @@
 	return 0;
 }
 
+#ifndef CONFIG_SPL_FRAMEWORK
 /*
  * The main entry for NAND booting. It's necessary that SDRAM is already
  * configured and available since this code loads the main U-Boot image
@@ -345,8 +347,9 @@
 	 * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
 	 * be aligned to full pages
 	 */
-	if (!nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
-		       (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
+	if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+			CONFIG_SYS_NAND_U_BOOT_SIZE,
+			(uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
 		/* Copy from NAND successful, start U-boot */
 		uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 		uboot();
@@ -355,3 +358,7 @@
 		hang();
 	}
 }
+#endif
+
+void nand_init(void) {}
+void nand_deselect(void) {}
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index e38e151..866cabd 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -34,12 +34,19 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/imx-common/regs-bch.h>
+#include <asm/imx-common/regs-gpmi.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
 
 #define	MXS_NAND_DMA_DESCRIPTOR_COUNT		4
 
 #define	MXS_NAND_CHUNK_DATA_CHUNK_SIZE		512
+#if defined(CONFIG_MX6)
+#define	MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT	2
+#else
+#define	MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT	0
+#endif
 #define	MXS_NAND_METADATA_SIZE			10
 
 #define	MXS_NAND_COMMAND_BUFFER_SIZE		32
@@ -546,7 +553,8 @@
  * Read a page from NAND.
  */
 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
-					uint8_t *buf, int page)
+					uint8_t *buf, int oob_required,
+					int page)
 {
 	struct mxs_nand_info *nand_info = nand->priv;
 	struct mxs_dma_desc *d;
@@ -691,8 +699,9 @@
 /*
  * Write a page to NAND.
  */
-static void mxs_nand_ecc_write_page(struct mtd_info *mtd,
-				struct nand_chip *nand, const uint8_t *buf)
+static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
+				struct nand_chip *nand, const uint8_t *buf,
+				int oob_required)
 {
 	struct mxs_nand_info *nand_info = nand->priv;
 	struct mxs_dma_desc *d;
@@ -748,6 +757,7 @@
 
 rtn:
 	mxs_nand_return_dma_descs(nand_info);
+	return 0;
 }
 
 /*
@@ -763,7 +773,7 @@
 	struct mxs_nand_info *nand_info = chip->priv;
 	int ret;
 
-	if (ops->mode == MTD_OOB_RAW)
+	if (ops->mode == MTD_OPS_RAW)
 		nand_info->raw_oob_mode = 1;
 	else
 		nand_info->raw_oob_mode = 0;
@@ -788,7 +798,7 @@
 	struct mxs_nand_info *nand_info = chip->priv;
 	int ret;
 
-	if (ops->mode == MTD_OOB_RAW)
+	if (ops->mode == MTD_OPS_RAW)
 		nand_info->raw_oob_mode = 1;
 	else
 		nand_info->raw_oob_mode = 0;
@@ -866,7 +876,7 @@
  * what to do.
  */
 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
-				int page, int cmd)
+				int page)
 {
 	struct mxs_nand_info *nand_info = nand->priv;
 
@@ -980,14 +990,16 @@
 	tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
 	tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
 		<< BCH_FLASHLAYOUT0_ECC0_OFFSET;
-	tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+	tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
+		>> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
 	writel(tmp, &bch_regs->hw_bch_flash0layout0);
 
 	tmp = (mtd->writesize + mtd->oobsize)
 		<< BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
 	tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
 		<< BCH_FLASHLAYOUT1_ECCN_OFFSET;
-	tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+	tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
+		>> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
 	writel(tmp, &bch_regs->hw_bch_flash0layout1);
 
 	/* Set *all* chip selects to use layout 0 */
@@ -997,19 +1009,19 @@
 	writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
 
 	/* Hook some operations at the MTD level. */
-	if (mtd->read_oob != mxs_nand_hook_read_oob) {
-		nand_info->hooked_read_oob = mtd->read_oob;
-		mtd->read_oob = mxs_nand_hook_read_oob;
+	if (mtd->_read_oob != mxs_nand_hook_read_oob) {
+		nand_info->hooked_read_oob = mtd->_read_oob;
+		mtd->_read_oob = mxs_nand_hook_read_oob;
 	}
 
-	if (mtd->write_oob != mxs_nand_hook_write_oob) {
-		nand_info->hooked_write_oob = mtd->write_oob;
-		mtd->write_oob = mxs_nand_hook_write_oob;
+	if (mtd->_write_oob != mxs_nand_hook_write_oob) {
+		nand_info->hooked_write_oob = mtd->_write_oob;
+		mtd->_write_oob = mxs_nand_hook_write_oob;
 	}
 
-	if (mtd->block_markbad != mxs_nand_hook_block_markbad) {
-		nand_info->hooked_block_markbad = mtd->block_markbad;
-		mtd->block_markbad = mxs_nand_hook_block_markbad;
+	if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
+		nand_info->hooked_block_markbad = mtd->_block_markbad;
+		mtd->_block_markbad = mxs_nand_hook_block_markbad;
 	}
 
 	/* We use the reference implementation for bad block management. */
@@ -1163,6 +1175,7 @@
 	nand->ecc.mode		= NAND_ECC_HW;
 	nand->ecc.bytes		= 9;
 	nand->ecc.size		= 512;
+	nand->ecc.strength	= 8;
 
 	return 0;
 
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index a2d06be..9e05cef 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -21,7 +21,7 @@
  *  TODO:
  *	Enable cached programming for 2k page size chips
  *	Check, if mtd->ecctype should be set to MTD_ECC_HW
- *	if we have HW ecc support.
+ *	if we have HW ECC support.
  *	The AG-AND chips have nice features for speed improvement,
  *	which are not supported yet. Read / program 4 pages in one go.
  *	BBT table is not serialized, has to be fixed
@@ -134,21 +134,14 @@
 		ret = -EINVAL;
 	}
 
-	/* Do not allow past end of device */
-	if (ofs + len > mtd->size) {
-		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
-					__func__);
-		ret = -EINVAL;
-	}
-
 	return ret;
 }
 
 /**
  * nand_release_device - [GENERIC] release chip
- * @mtd:	MTD device structure
+ * @mtd: MTD device structure
  *
- * Deselect, release chip lock and wake up anyone waiting on the device
+ * Deselect, release chip lock and wake up anyone waiting on the device.
  */
 static void nand_release_device(struct mtd_info *mtd)
 {
@@ -160,9 +153,9 @@
 
 /**
  * nand_read_byte - [DEFAULT] read one byte from the chip
- * @mtd:	MTD device structure
+ * @mtd: MTD device structure
  *
- * Default read function for 8bit buswith
+ * Default read function for 8bit buswidth.
  */
 uint8_t nand_read_byte(struct mtd_info *mtd)
 {
@@ -172,10 +165,11 @@
 
 /**
  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
- * @mtd:	MTD device structure
+ * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
+ * @mtd: MTD device structure
  *
- * Default read function for 16bit buswith with
- * endianess conversion
+ * Default read function for 16bit buswidth with endianness conversion.
+ *
  */
 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 {
@@ -185,10 +179,9 @@
 
 /**
  * nand_read_word - [DEFAULT] read one word from the chip
- * @mtd:	MTD device structure
+ * @mtd: MTD device structure
  *
- * Default read function for 16bit buswith without
- * endianess conversion
+ * Default read function for 16bit buswidth without endianness conversion.
  */
 static u16 nand_read_word(struct mtd_info *mtd)
 {
@@ -198,8 +191,8 @@
 
 /**
  * nand_select_chip - [DEFAULT] control CE line
- * @mtd:	MTD device structure
- * @chipnr:	chipnumber to select, -1 for deselect
+ * @mtd: MTD device structure
+ * @chipnr: chipnumber to select, -1 for deselect
  *
  * Default select function for 1 chip devices.
  */
@@ -221,11 +214,11 @@
 
 /**
  * nand_write_buf - [DEFAULT] write buffer to chip
- * @mtd:	MTD device structure
- * @buf:	data buffer
- * @len:	number of bytes to write
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
  *
- * Default write function for 8bit buswith
+ * Default write function for 8bit buswidth.
  */
 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 {
@@ -238,11 +231,11 @@
 
 /**
  * nand_read_buf - [DEFAULT] read chip data into buffer
- * @mtd:	MTD device structure
- * @buf:	buffer to store date
- * @len:	number of bytes to read
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
  *
- * Default read function for 8bit buswith
+ * Default read function for 8bit buswidth.
  */
 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
@@ -255,11 +248,11 @@
 
 /**
  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
- * @mtd:	MTD device structure
- * @buf:	buffer containing the data to compare
- * @len:	number of bytes to compare
+ * @mtd: MTD device structure
+ * @buf: buffer containing the data to compare
+ * @len: number of bytes to compare
  *
- * Default verify function for 8bit buswith
+ * Default verify function for 8bit buswidth.
  */
 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 {
@@ -274,11 +267,11 @@
 
 /**
  * nand_write_buf16 - [DEFAULT] write buffer to chip
- * @mtd:	MTD device structure
- * @buf:	data buffer
- * @len:	number of bytes to write
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
  *
- * Default write function for 16bit buswith
+ * Default write function for 16bit buswidth.
  */
 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 {
@@ -294,11 +287,11 @@
 
 /**
  * nand_read_buf16 - [DEFAULT] read chip data into buffer
- * @mtd:	MTD device structure
- * @buf:	buffer to store date
- * @len:	number of bytes to read
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
  *
- * Default read function for 16bit buswith
+ * Default read function for 16bit buswidth.
  */
 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 {
@@ -313,11 +306,11 @@
 
 /**
  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
- * @mtd:	MTD device structure
- * @buf:	buffer containing the data to compare
- * @len:	number of bytes to compare
+ * @mtd: MTD device structure
+ * @buf: buffer containing the data to compare
+ * @len: number of bytes to compare
  *
- * Default verify function for 16bit buswith
+ * Default verify function for 16bit buswidth.
  */
 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 {
@@ -335,19 +328,19 @@
 
 /**
  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
- * @mtd:	MTD device structure
- * @ofs:	offset from device start
- * @getchip:	0, if the chip is already selected
+ * @mtd: MTD device structure
+ * @ofs: offset from device start
+ * @getchip: 0, if the chip is already selected
  *
  * Check, if the block is bad.
  */
 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 {
-	int page, chipnr, res = 0;
+	int page, chipnr, res = 0, i = 0;
 	struct nand_chip *chip = mtd->priv;
 	u16 bad;
 
-	if (chip->options & NAND_BBT_SCANLASTPAGE)
+	if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 		ofs += mtd->erasesize - mtd->writesize;
 
 	page = (int)(ofs >> chip->page_shift) & chip->pagemask;
@@ -361,23 +354,29 @@
 		chip->select_chip(mtd, chipnr);
 	}
 
-	if (chip->options & NAND_BUSWIDTH_16) {
-		chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
-			      page);
-		bad = cpu_to_le16(chip->read_word(mtd));
-		if (chip->badblockpos & 0x1)
-			bad >>= 8;
-		else
-			bad &= 0xFF;
-	} else {
-		chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
-		bad = chip->read_byte(mtd);
-	}
+	do {
+		if (chip->options & NAND_BUSWIDTH_16) {
+			chip->cmdfunc(mtd, NAND_CMD_READOOB,
+					chip->badblockpos & 0xFE, page);
+			bad = cpu_to_le16(chip->read_word(mtd));
+			if (chip->badblockpos & 0x1)
+				bad >>= 8;
+			else
+				bad &= 0xFF;
+		} else {
+			chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
+					page);
+			bad = chip->read_byte(mtd);
+		}
 
-	if (likely(chip->badblockbits == 8))
-		res = bad != 0xFF;
-	else
-		res = hweight8(bad) < chip->badblockbits;
+		if (likely(chip->badblockbits == 8))
+			res = bad != 0xFF;
+		else
+			res = hweight8(bad) < chip->badblockbits;
+		ofs += mtd->writesize;
+		page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+		i++;
+	} while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
 
 	if (getchip)
 		nand_release_device(mtd);
@@ -387,57 +386,83 @@
 
 /**
  * nand_default_block_markbad - [DEFAULT] mark a block bad
- * @mtd:	MTD device structure
- * @ofs:	offset from device start
+ * @mtd: MTD device structure
+ * @ofs: offset from device start
  *
- * This is the default implementation, which can be overridden by
- * a hardware specific driver.
+ * This is the default implementation, which can be overridden by a hardware
+ * specific driver. We try operations in the following order, according to our
+ * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
+ *  (1) erase the affected block, to allow OOB marker to be written cleanly
+ *  (2) update in-memory BBT
+ *  (3) write bad block marker to OOB area of affected block
+ *  (4) update flash-based BBT
+ * Note that we retain the first error encountered in (3) or (4), finish the
+ * procedures, and dump the error in the end.
 */
 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 {
 	struct nand_chip *chip = mtd->priv;
 	uint8_t buf[2] = { 0, 0 };
-	int block, ret, i = 0;
+	int block, res, ret = 0, i = 0;
+	int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
 
-	if (chip->options & NAND_BBT_SCANLASTPAGE)
-		ofs += mtd->erasesize - mtd->writesize;
+	if (write_oob) {
+		struct erase_info einfo;
+
+		/* Attempt erase before marking OOB */
+		memset(&einfo, 0, sizeof(einfo));
+		einfo.mtd = mtd;
+		einfo.addr = ofs;
+		einfo.len = 1 << chip->phys_erase_shift;
+		nand_erase_nand(mtd, &einfo, 0);
+	}
 
 	/* Get block number */
 	block = (int)(ofs >> chip->bbt_erase_shift);
+	/* Mark block bad in memory-based BBT */
 	if (chip->bbt)
 		chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 
-	/* Do we have a flash based bad block table ? */
-	if (chip->options & NAND_USE_FLASH_BBT)
-		ret = nand_update_bbt(mtd, ofs);
-	else {
+	/* Write bad block marker to OOB */
+	if (write_oob) {
+		struct mtd_oob_ops ops;
+		loff_t wr_ofs = ofs;
+
 		nand_get_device(chip, mtd, FL_WRITING);
 
-		/* Write to first two pages and to byte 1 and 6 if necessary.
-		 * If we write to more than one location, the first error
-		 * encountered quits the procedure. We write two bytes per
-		 * location, so we dont have to mess with 16 bit access.
-		 */
+		ops.datbuf = NULL;
+		ops.oobbuf = buf;
+		ops.ooboffs = chip->badblockpos;
+		if (chip->options & NAND_BUSWIDTH_16) {
+			ops.ooboffs &= ~0x01;
+			ops.len = ops.ooblen = 2;
+		} else {
+			ops.len = ops.ooblen = 1;
+		}
+		ops.mode = MTD_OPS_PLACE_OOB;
+
+		/* Write to first/last page(s) if necessary */
+		if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
+			wr_ofs += mtd->erasesize - mtd->writesize;
 		do {
-			chip->ops.len = chip->ops.ooblen = 2;
-			chip->ops.datbuf = NULL;
-			chip->ops.oobbuf = buf;
-			chip->ops.ooboffs = chip->badblockpos & ~0x01;
+			res = nand_do_write_oob(mtd, wr_ofs, &ops);
+			if (!ret)
+				ret = res;
 
-			ret = nand_do_write_oob(mtd, ofs, &chip->ops);
-
-			if (!ret && (chip->options & NAND_BBT_SCANBYTE1AND6)) {
-				chip->ops.ooboffs = NAND_SMALL_BADBLOCK_POS
-					& ~0x01;
-				ret = nand_do_write_oob(mtd, ofs, &chip->ops);
-			}
 			i++;
-			ofs += mtd->writesize;
-		} while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) &&
-				i < 2);
+			wr_ofs += mtd->writesize;
+		} while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
 
 		nand_release_device(mtd);
 	}
+
+	/* Update flash-based bad block table */
+	if (chip->bbt_options & NAND_BBT_USE_FLASH) {
+		res = nand_update_bbt(mtd, ofs);
+		if (!ret)
+			ret = res;
+	}
+
 	if (!ret)
 		mtd->ecc_stats.badblocks++;
 
@@ -446,16 +471,16 @@
 
 /**
  * nand_check_wp - [GENERIC] check if the chip is write protected
- * @mtd:	MTD device structure
- * Check, if the device is write protected
+ * @mtd: MTD device structure
  *
- * The function expects, that the device is already selected
+ * Check, if the device is write protected. The function expects, that the
+ * device is already selected.
  */
 static int nand_check_wp(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;
 
-	/* broken xD cards report WP despite being writable */
+	/* Broken xD cards report WP despite being writable */
 	if (chip->options & NAND_BROKEN_XD)
 		return 0;
 
@@ -466,10 +491,10 @@
 
 /**
  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
- * @mtd:	MTD device structure
- * @ofs:	offset from device start
- * @getchip:	0, if the chip is already selected
- * @allowbbt:	1, if its allowed to access the bbt area
+ * @mtd: MTD device structure
+ * @ofs: offset from device start
+ * @getchip: 0, if the chip is already selected
+ * @allowbbt: 1, if its allowed to access the bbt area
  *
  * Check, if the block is bad. Either by reading the bad block table or
  * calling of the scan function.
@@ -491,10 +516,7 @@
 	return nand_isbad_bbt(mtd, ofs, allowbbt);
 }
 
-/*
- * Wait for the ready pin, after a command
- * The timeout is catched later.
- */
+/* Wait for the ready pin, after a command. The timeout is caught later. */
 void nand_wait_ready(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;
@@ -503,7 +525,7 @@
 
 	time_start = get_timer(0);
 
-	/* wait until command is processed or timeout occures */
+	/* Wait until command is processed or timeout occurs */
 	while (get_timer(time_start) < timeo) {
 		if (chip->dev_ready)
 			if (chip->dev_ready(mtd))
@@ -513,13 +535,13 @@
 
 /**
  * nand_command - [DEFAULT] Send command to NAND device
- * @mtd:	MTD device structure
- * @command:	the command to be sent
- * @column:	the column address for this command, -1 if none
- * @page_addr:	the page address for this command, -1 if none
+ * @mtd: MTD device structure
+ * @command: the command to be sent
+ * @column: the column address for this command, -1 if none
+ * @page_addr: the page address for this command, -1 if none
  *
- * Send command to NAND device. This function is used for small page
- * devices (256/512 Bytes per page)
+ * Send command to NAND device. This function is used for small page devices
+ * (256/512 Bytes per page).
  */
 static void nand_command(struct mtd_info *mtd, unsigned int command,
 			 int column, int page_addr)
@@ -528,9 +550,7 @@
 	int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 	uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 
-	/*
-	 * Write out the command to the device.
-	 */
+	/* Write out the command to the device */
 	if (command == NAND_CMD_SEQIN) {
 		int readcmd;
 
@@ -550,9 +570,7 @@
 	}
 	chip->cmd_ctrl(mtd, command, ctrl);
 
-	/*
-	 * Address cycle, when necessary
-	 */
+	/* Address cycle, when necessary */
 	ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 	/* Serially input address */
 	if (column != -1) {
@@ -573,8 +591,8 @@
 	chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
 	/*
-	 * program and erase have their own busy handlers
-	 * status and sequential in needs no delay
+	 * Program and erase have their own busy handlers status and sequential
+	 * in needs no delay
 	 */
 	switch (command) {
 
@@ -608,8 +626,10 @@
 			return;
 		}
 	}
-	/* Apply this short delay always to ensure that we do wait tWB in
-	 * any case on any machine. */
+	/*
+	 * Apply this short delay always to ensure that we do wait tWB in
+	 * any case on any machine.
+	 */
 	ndelay(100);
 
 	nand_wait_ready(mtd);
@@ -617,14 +637,14 @@
 
 /**
  * nand_command_lp - [DEFAULT] Send command to NAND large page device
- * @mtd:	MTD device structure
- * @command:	the command to be sent
- * @column:	the column address for this command, -1 if none
- * @page_addr:	the page address for this command, -1 if none
+ * @mtd: MTD device structure
+ * @command: the command to be sent
+ * @column: the column address for this command, -1 if none
+ * @page_addr: the page address for this command, -1 if none
  *
  * Send command to NAND device. This is the version for the new large page
- * devices We dont have the separate regions as we have in the small page
- * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
+ * devices. We don't have the separate regions as we have in the small page
+ * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
  */
 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 			    int column, int page_addr)
@@ -667,8 +687,8 @@
 	chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
 	/*
-	 * program and erase have their own busy handlers
-	 * status, sequential in, and deplete1 need no delay
+	 * Program and erase have their own busy handlers status, sequential
+	 * in, and deplete1 need no delay.
 	 */
 	switch (command) {
 
@@ -682,14 +702,12 @@
 	case NAND_CMD_DEPLETE1:
 		return;
 
-		/*
-		 * read error status commands require only a short delay
-		 */
 	case NAND_CMD_STATUS_ERROR:
 	case NAND_CMD_STATUS_ERROR0:
 	case NAND_CMD_STATUS_ERROR1:
 	case NAND_CMD_STATUS_ERROR2:
 	case NAND_CMD_STATUS_ERROR3:
+		/* Read error status commands require only a short delay */
 		udelay(chip->chip_delay);
 		return;
 
@@ -723,7 +741,7 @@
 	default:
 		/*
 		 * If we don't have access to the busy pin, we apply the given
-		 * command delay
+		 * command delay.
 		 */
 		if (!chip->dev_ready) {
 			udelay(chip->chip_delay);
@@ -731,8 +749,10 @@
 		}
 	}
 
-	/* Apply this short delay always to ensure that we do wait tWB in
-	 * any case on any machine. */
+	/*
+	 * Apply this short delay always to ensure that we do wait tWB in
+	 * any case on any machine.
+	 */
 	ndelay(100);
 
 	nand_wait_ready(mtd);
@@ -740,9 +760,9 @@
 
 /**
  * nand_get_device - [GENERIC] Get chip for selected access
- * @chip:	the nand chip descriptor
- * @mtd:	MTD device structure
- * @new_state:	the state which is requested
+ * @chip: the nand chip descriptor
+ * @mtd: MTD device structure
+ * @new_state: the state which is requested
  *
  * Get the device and lock it for exclusive access
  */
@@ -754,13 +774,13 @@
 }
 
 /**
- * nand_wait - [DEFAULT]  wait until the command is done
- * @mtd:	MTD device structure
- * @chip:	NAND chip structure
+ * nand_wait - [DEFAULT] wait until the command is done
+ * @mtd: MTD device structure
+ * @chip: NAND chip structure
  *
- * Wait for command done. This applies to erase and program only
- * Erase can take up to 400ms and program up to 20ms according to
- * general NAND and SmartMedia specs
+ * Wait for command done. This applies to erase and program only. Erase can
+ * take up to 400ms and program up to 20ms according to general NAND and
+ * SmartMedia specs.
  */
 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
@@ -804,34 +824,37 @@
 }
 
 /**
- * nand_read_page_raw - [Intern] read raw page data without ecc
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @buf:	buffer to store read data
- * @page:	page number to read
+ * nand_read_page_raw - [INTERN] read raw page data without ecc
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
+ * @page: page number to read
  *
- * Not for syndrome calculating ecc controllers, which use a special oob layout
+ * Not for syndrome calculating ECC controllers, which use a special oob layout.
  */
 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-			      uint8_t *buf, int page)
+			      uint8_t *buf, int oob_required, int page)
 {
 	chip->read_buf(mtd, buf, mtd->writesize);
-	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+	if (oob_required)
+		chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 	return 0;
 }
 
 /**
- * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @buf:	buffer to store read data
- * @page:	page number to read
+ * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
+ * @page: page number to read
  *
  * We need a special oob layout and handling even when OOB isn't used.
  */
 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
-					struct nand_chip *chip,
-					uint8_t *buf, int page)
+				       struct nand_chip *chip, uint8_t *buf,
+				       int oob_required, int page)
 {
 	int eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -864,14 +887,15 @@
 }
 
 /**
- * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @buf:	buffer to store read data
- * @page:	page number to read
+ * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
+ * @page: page number to read
  */
 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
-				uint8_t *buf, int page)
+				uint8_t *buf, int oob_required, int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -881,7 +905,7 @@
 	uint8_t *ecc_code = chip->buffers->ecccode;
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
 
-	chip->ecc.read_page_raw(mtd, chip, buf, page);
+	chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
 
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
@@ -905,12 +929,12 @@
 }
 
 /**
- * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @data_offs:	offset of requested data within the page
- * @readlen:	data length
- * @bufpoi:	buffer to store read data
+ * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @data_offs: offset of requested data within the page
+ * @readlen: data length
+ * @bufpoi: buffer to store read data
  */
 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
 			uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
@@ -923,12 +947,12 @@
 	int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
 	int index = 0;
 
-	/* Column address wihin the page aligned to ECC size (256bytes). */
+	/* Column address within the page aligned to ECC size (256bytes) */
 	start_step = data_offs / chip->ecc.size;
 	end_step = (data_offs + readlen - 1) / chip->ecc.size;
 	num_steps = end_step - start_step + 1;
 
-	/* Data size aligned to ECC ecc.size*/
+	/* Data size aligned to ECC ecc.size */
 	datafrag_len = num_steps * chip->ecc.size;
 	eccfrag_len = num_steps * chip->ecc.bytes;
 
@@ -940,13 +964,14 @@
 	p = bufpoi + data_col_addr;
 	chip->read_buf(mtd, p, datafrag_len);
 
-	/* Calculate  ECC */
+	/* Calculate ECC */
 	for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
 		chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
 
-	/* The performance is faster if to position offsets
-	   according to ecc.pos. Let make sure here that
-	   there are no gaps in ecc positions */
+	/*
+	 * The performance is faster if we position offsets according to
+	 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
+	 */
 	for (i = 0; i < eccfrag_len - 1; i++) {
 		if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
 			eccpos[i + start_step * chip->ecc.bytes + 1]) {
@@ -958,8 +983,10 @@
 		chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 		chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 	} else {
-		/* send the command to read the particular ecc bytes */
-		/* take care about buswidth alignment in read_buf */
+		/*
+		 * Send the command to read the particular ECC bytes take care
+		 * about buswidth alignment in read_buf.
+		 */
 		index = start_step * chip->ecc.bytes;
 
 		aligned_pos = eccpos[index] & ~(busw - 1);
@@ -992,16 +1019,17 @@
 }
 
 /**
- * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @buf:	buffer to store read data
- * @page:	page number to read
+ * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
+ * @page: page number to read
  *
- * Not for syndrome calculating ecc controllers which need a special oob layout
+ * Not for syndrome calculating ECC controllers which need a special oob layout.
  */
 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
-				uint8_t *buf, int page)
+				uint8_t *buf, int oob_required, int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1037,21 +1065,21 @@
 }
 
 /**
- * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @buf:	buffer to store read data
- * @page:	page number to read
+ * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
+ * @page: page number to read
  *
- * Hardware ECC for large page chips, require OOB to be read first.
- * For this ECC mode, the write_page method is re-used from ECC_HW.
- * These methods read/write ECC from the OOB area, unlike the
- * ECC_HW_SYNDROME support with multiple ECC steps, follows the
- * "infix ECC" scheme and reads/writes ECC from the data area, by
- * overwriting the NAND manufacturer bad block markings.
+ * Hardware ECC for large page chips, require OOB to be read first. For this
+ * ECC mode, the write_page method is re-used from ECC_HW. These methods
+ * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
+ * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
+ * the data area, by overwriting the NAND manufacturer bad block markings.
  */
 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
-	struct nand_chip *chip, uint8_t *buf, int page)
+	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1086,17 +1114,18 @@
 }
 
 /**
- * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @buf:	buffer to store read data
- * @page:	page number to read
+ * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
+ * @page: page number to read
  *
- * The hw generator calculates the error syndrome automatically. Therefor
- * we need a special oob layout and handling.
+ * The hw generator calculates the error syndrome automatically. Therefore we
+ * need a special oob layout and handling.
  */
 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
-				   uint8_t *buf, int page)
+				   uint8_t *buf, int oob_required, int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1141,29 +1170,29 @@
 }
 
 /**
- * nand_transfer_oob - [Internal] Transfer oob to client buffer
- * @chip:	nand chip structure
- * @oob:	oob destination address
- * @ops:	oob ops structure
- * @len:	size of oob to transfer
+ * nand_transfer_oob - [INTERN] Transfer oob to client buffer
+ * @chip: nand chip structure
+ * @oob: oob destination address
+ * @ops: oob ops structure
+ * @len: size of oob to transfer
  */
 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
 				  struct mtd_oob_ops *ops, size_t len)
 {
 	switch (ops->mode) {
 
-	case MTD_OOB_PLACE:
-	case MTD_OOB_RAW:
+	case MTD_OPS_PLACE_OOB:
+	case MTD_OPS_RAW:
 		memcpy(oob, chip->oob_poi + ops->ooboffs, len);
 		return oob + len;
 
-	case MTD_OOB_AUTO: {
+	case MTD_OPS_AUTO_OOB: {
 		struct nand_oobfree *free = chip->ecc.layout->oobfree;
 		uint32_t boffs = 0, roffs = ops->ooboffs;
 		size_t bytes = 0;
 
 		for (; free->length && len; free++, len -= bytes) {
-			/* Read request not from offset 0 ? */
+			/* Read request not from offset 0? */
 			if (unlikely(roffs)) {
 				if (roffs >= free->length) {
 					roffs -= free->length;
@@ -1189,26 +1218,23 @@
 }
 
 /**
- * nand_do_read_ops - [Internal] Read data with ECC
- *
- * @mtd:	MTD device structure
- * @from:	offset to read from
- * @ops:	oob ops structure
+ * nand_do_read_ops - [INTERN] Read data with ECC
+ * @mtd: MTD device structure
+ * @from: offset to read from
+ * @ops: oob ops structure
  *
  * Internal function. Called with chip held.
  */
 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 			    struct mtd_oob_ops *ops)
 {
-	int chipnr, page, realpage, col, bytes, aligned;
+	int chipnr, page, realpage, col, bytes, aligned, oob_required;
 	struct nand_chip *chip = mtd->priv;
 	struct mtd_ecc_stats stats;
-	int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
-	int sndcmd = 1;
 	int ret = 0;
 	uint32_t readlen = ops->len;
 	uint32_t oobreadlen = ops->ooblen;
-	uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
+	uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
 		mtd->oobavail : mtd->oobsize;
 
 	uint8_t *bufpoi, *oob, *buf;
@@ -1225,6 +1251,7 @@
 
 	buf = ops->datbuf;
 	oob = ops->oobbuf;
+	oob_required = oob ? 1 : 0;
 
 	while (1) {
 		WATCHDOG_RESET();
@@ -1232,41 +1259,46 @@
 		bytes = min(mtd->writesize - col, readlen);
 		aligned = (bytes == mtd->writesize);
 
-		/* Is the current page in the buffer ? */
+		/* Is the current page in the buffer? */
 		if (realpage != chip->pagebuf || oob) {
 			bufpoi = aligned ? buf : chip->buffers->databuf;
 
-			if (likely(sndcmd)) {
-				chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
-				sndcmd = 0;
-			}
+			chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
 
 			/* Now read the page into the buffer */
-			if (unlikely(ops->mode == MTD_OOB_RAW))
-				ret = chip->ecc.read_page_raw(mtd, chip,
-							      bufpoi, page);
+			if (unlikely(ops->mode == MTD_OPS_RAW))
+				ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
+							      oob_required,
+							      page);
 			else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
 			    !oob)
 				ret = chip->ecc.read_subpage(mtd, chip,
 							col, bytes, bufpoi);
 			else
 				ret = chip->ecc.read_page(mtd, chip, bufpoi,
-							  page);
-			if (ret < 0)
+							  oob_required, page);
+			if (ret < 0) {
+				if (!aligned)
+					/* Invalidate page cache */
+					chip->pagebuf = -1;
 				break;
+			}
 
 			/* Transfer not aligned data */
 			if (!aligned) {
 				if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
-				    !(mtd->ecc_stats.failed - stats.failed))
+				    !(mtd->ecc_stats.failed - stats.failed) &&
+				    (ops->mode != MTD_OPS_RAW))
 					chip->pagebuf = realpage;
+				else
+					/* Invalidate page cache */
+					chip->pagebuf = -1;
 				memcpy(buf, chip->buffers->databuf + col, bytes);
 			}
 
 			buf += bytes;
 
 			if (unlikely(oob)) {
-
 				int toread = min(oobreadlen, max_oobsize);
 
 				if (toread) {
@@ -1275,20 +1307,6 @@
 					oobreadlen -= toread;
 				}
 			}
-
-			if (!(chip->options & NAND_NO_READRDY)) {
-				/*
-				 * Apply delay or wait for ready/busy pin. Do
-				 * this before the AUTOINCR check, so no
-				 * problems arise if a chip which does auto
-				 * increment is marked as NOAUTOINCR by the
-				 * board driver.
-				 */
-				if (!chip->dev_ready)
-					udelay(chip->chip_delay);
-				else
-					nand_wait_ready(mtd);
-			}
 		} else {
 			memcpy(buf, chip->buffers->databuf + col, bytes);
 			buf += bytes;
@@ -1299,7 +1317,7 @@
 		if (!readlen)
 			break;
 
-		/* For subsequent reads align to page boundary. */
+		/* For subsequent reads align to page boundary */
 		col = 0;
 		/* Increment page address */
 		realpage++;
@@ -1311,12 +1329,6 @@
 			chip->select_chip(mtd, -1);
 			chip->select_chip(mtd, chipnr);
 		}
-
-		/* Check, if the chip supports auto page increment
-		 * or if we have hit a block boundary.
-		 */
-		if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
-			sndcmd = 1;
 	}
 
 	ops->retlen = ops->len - (size_t) readlen;
@@ -1334,69 +1346,55 @@
 
 /**
  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
- * @mtd:	MTD device structure
- * @from:	offset to read from
- * @len:	number of bytes to read
- * @retlen:	pointer to variable to store the number of read bytes
- * @buf:	the databuffer to put data
+ * @mtd: MTD device structure
+ * @from: offset to read from
+ * @len: number of bytes to read
+ * @retlen: pointer to variable to store the number of read bytes
+ * @buf: the databuffer to put data
  *
- * Get hold of the chip and call nand_do_read
+ * Get hold of the chip and call nand_do_read.
  */
 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
 		     size_t *retlen, uint8_t *buf)
 {
 	struct nand_chip *chip = mtd->priv;
+	struct mtd_oob_ops ops;
 	int ret;
 
-	/* Do not allow reads past end of device */
-	if ((from + len) > mtd->size)
-		return -EINVAL;
-	if (!len)
-		return 0;
-
 	nand_get_device(chip, mtd, FL_READING);
-
-	chip->ops.len = len;
-	chip->ops.datbuf = buf;
-	chip->ops.oobbuf = NULL;
-
-	ret = nand_do_read_ops(mtd, from, &chip->ops);
-
-	*retlen = chip->ops.retlen;
-
+	ops.len = len;
+	ops.datbuf = buf;
+	ops.oobbuf = NULL;
+	ops.mode = MTD_OPS_PLACE_OOB;
+	ret = nand_do_read_ops(mtd, from, &ops);
+	*retlen = ops.retlen;
 	nand_release_device(mtd);
-
 	return ret;
 }
 
 /**
- * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @page:	page number to read
- * @sndcmd:	flag whether to issue read command or not
+ * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @page: page number to read
  */
 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
-			     int page, int sndcmd)
+			     int page)
 {
-	if (sndcmd) {
-		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
-		sndcmd = 0;
-	}
+	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
-	return sndcmd;
+	return 0;
 }
 
 /**
- * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
+ * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
  *			    with syndromes
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @page:	page number to read
- * @sndcmd:	flag whether to issue read command or not
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @page: page number to read
  */
 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
-				  int page, int sndcmd)
+				  int page)
 {
 	uint8_t *buf = chip->oob_poi;
 	int length = mtd->oobsize;
@@ -1423,14 +1421,14 @@
 	if (length > 0)
 		chip->read_buf(mtd, bufpoi, length);
 
-	return 1;
+	return 0;
 }
 
 /**
- * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @page:	page number to write
+ * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @page: page number to write
  */
 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
 			      int page)
@@ -1450,11 +1448,11 @@
 }
 
 /**
- * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
- *			     with syndrome - only for large page flash !
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @page:	page number to write
+ * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
+ *			     with syndrome - only for large page flash
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @page: page number to write
  */
 static int nand_write_oob_syndrome(struct mtd_info *mtd,
 				   struct nand_chip *chip, int page)
@@ -1509,27 +1507,30 @@
 }
 
 /**
- * nand_do_read_oob - [Intern] NAND read out-of-band
- * @mtd:	MTD device structure
- * @from:	offset to read from
- * @ops:	oob operations description structure
+ * nand_do_read_oob - [INTERN] NAND read out-of-band
+ * @mtd: MTD device structure
+ * @from: offset to read from
+ * @ops: oob operations description structure
  *
- * NAND read out-of-band data from the spare area
+ * NAND read out-of-band data from the spare area.
  */
 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
 			    struct mtd_oob_ops *ops)
 {
-	int page, realpage, chipnr, sndcmd = 1;
+	int page, realpage, chipnr;
 	struct nand_chip *chip = mtd->priv;
-	int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
+	struct mtd_ecc_stats stats;
 	int readlen = ops->ooblen;
 	int len;
 	uint8_t *buf = ops->oobbuf;
+	int ret = 0;
 
 	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
 			__func__, (unsigned long long)from, readlen);
 
-	if (ops->mode == MTD_OOB_AUTO)
+	stats = mtd->ecc_stats;
+
+	if (ops->mode == MTD_OPS_AUTO_OOB)
 		len = chip->ecc.layout->oobavail;
 	else
 		len = mtd->oobsize;
@@ -1558,24 +1559,17 @@
 
 	while (1) {
 		WATCHDOG_RESET();
-		sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
+		if (ops->mode == MTD_OPS_RAW)
+			ret = chip->ecc.read_oob_raw(mtd, chip, page);
+		else
+			ret = chip->ecc.read_oob(mtd, chip, page);
+
+		if (ret < 0)
+			break;
 
 		len = min(len, readlen);
 		buf = nand_transfer_oob(chip, buf, ops, len);
 
-		if (!(chip->options & NAND_NO_READRDY)) {
-			/*
-			 * Apply delay or wait for ready/busy pin. Do this
-			 * before the AUTOINCR check, so no problems arise if a
-			 * chip which does auto increment is marked as
-			 * NOAUTOINCR by the board driver.
-			 */
-			if (!chip->dev_ready)
-				udelay(chip->chip_delay);
-			else
-				nand_wait_ready(mtd);
-		}
-
 		readlen -= len;
 		if (!readlen)
 			break;
@@ -1590,25 +1584,26 @@
 			chip->select_chip(mtd, -1);
 			chip->select_chip(mtd, chipnr);
 		}
-
-		/* Check, if the chip supports auto page increment
-		 * or if we have hit a block boundary.
-		 */
-		if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
-			sndcmd = 1;
 	}
 
-	ops->oobretlen = ops->ooblen;
-	return 0;
+	ops->oobretlen = ops->ooblen - readlen;
+
+	if (ret < 0)
+		return ret;
+
+	if (mtd->ecc_stats.failed - stats.failed)
+		return -EBADMSG;
+
+	return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
 }
 
 /**
  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
- * @mtd:	MTD device structure
- * @from:	offset to read from
- * @ops:	oob operation description structure
+ * @mtd: MTD device structure
+ * @from: offset to read from
+ * @ops: oob operation description structure
  *
- * NAND read data and/or out-of-band data
+ * NAND read data and/or out-of-band data.
  */
 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
 			 struct mtd_oob_ops *ops)
@@ -1628,9 +1623,9 @@
 	nand_get_device(chip, mtd, FL_READING);
 
 	switch (ops->mode) {
-	case MTD_OOB_PLACE:
-	case MTD_OOB_AUTO:
-	case MTD_OOB_RAW:
+	case MTD_OPS_PLACE_OOB:
+	case MTD_OPS_AUTO_OOB:
+	case MTD_OPS_RAW:
 		break;
 
 	default:
@@ -1649,31 +1644,36 @@
 
 
 /**
- * nand_write_page_raw - [Intern] raw page write function
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @buf:	data buffer
+ * nand_write_page_raw - [INTERN] raw page write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
  *
- * Not for syndrome calculating ecc controllers, which use a special oob layout
+ * Not for syndrome calculating ECC controllers, which use a special oob layout.
  */
-static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-				const uint8_t *buf)
+static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+				const uint8_t *buf, int oob_required)
 {
 	chip->write_buf(mtd, buf, mtd->writesize);
-	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+	if (oob_required)
+		chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+	return 0;
 }
 
 /**
- * nand_write_page_raw_syndrome - [Intern] raw page write function
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @buf:	data buffer
+ * nand_write_page_raw_syndrome - [INTERN] raw page write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
  *
  * We need a special oob layout and handling even when ECC isn't checked.
  */
-static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
+static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
 					struct nand_chip *chip,
-					const uint8_t *buf)
+					const uint8_t *buf, int oob_required)
 {
 	int eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1701,15 +1701,18 @@
 	size = mtd->oobsize - (oob - chip->oob_poi);
 	if (size)
 		chip->write_buf(mtd, oob, size);
+
+	return 0;
 }
 /**
- * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @buf:	data buffer
+ * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
  */
-static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
-				  const uint8_t *buf)
+static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
+				  const uint8_t *buf, int oob_required)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1718,24 +1721,25 @@
 	const uint8_t *p = buf;
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
 
-	/* Software ecc calculation */
+	/* Software ECC calculation */
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 
 	for (i = 0; i < chip->ecc.total; i++)
 		chip->oob_poi[eccpos[i]] = ecc_calc[i];
 
-	chip->ecc.write_page_raw(mtd, chip, buf);
+	return chip->ecc.write_page_raw(mtd, chip, buf, 1);
 }
 
 /**
- * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @buf:	data buffer
+ * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
  */
-static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
-				  const uint8_t *buf)
+static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
+				  const uint8_t *buf, int oob_required)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1754,19 +1758,23 @@
 		chip->oob_poi[eccpos[i]] = ecc_calc[i];
 
 	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+	return 0;
 }
 
 /**
- * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
- * @mtd:	mtd info structure
- * @chip:	nand chip info structure
- * @buf:	data buffer
+ * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
  *
- * The hw generator calculates the error syndrome automatically. Therefor
- * we need a special oob layout and handling.
+ * The hw generator calculates the error syndrome automatically. Therefore we
+ * need a special oob layout and handling.
  */
-static void nand_write_page_syndrome(struct mtd_info *mtd,
-				    struct nand_chip *chip, const uint8_t *buf)
+static int nand_write_page_syndrome(struct mtd_info *mtd,
+				    struct nand_chip *chip,
+				    const uint8_t *buf, int oob_required)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1798,32 +1806,39 @@
 	i = mtd->oobsize - (oob - chip->oob_poi);
 	if (i)
 		chip->write_buf(mtd, oob, i);
+
+	return 0;
 }
 
 /**
  * nand_write_page - [REPLACEABLE] write one page
- * @mtd:	MTD device structure
- * @chip:	NAND chip descriptor
- * @buf:	the data to write
- * @page:	page number to write
- * @cached:	cached programming
- * @raw:	use _raw version of write_page
+ * @mtd: MTD device structure
+ * @chip: NAND chip descriptor
+ * @buf: the data to write
+ * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
+ * @cached: cached programming
+ * @raw: use _raw version of write_page
  */
 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-			   const uint8_t *buf, int page, int cached, int raw)
+			   const uint8_t *buf, int oob_required, int page,
+			   int cached, int raw)
 {
 	int status;
 
 	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
 
 	if (unlikely(raw))
-		chip->ecc.write_page_raw(mtd, chip, buf);
+		status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
 	else
-		chip->ecc.write_page(mtd, chip, buf);
+		status = chip->ecc.write_page(mtd, chip, buf, oob_required);
+
+	if (status < 0)
+		return status;
 
 	/*
-	 * Cached progamming disabled for now, Not sure if its worth the
-	 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
+	 * Cached progamming disabled for now. Not sure if it's worth the
+	 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
 	 */
 	cached = 0;
 
@@ -1833,7 +1848,7 @@
 		status = chip->waitfunc(mtd, chip);
 		/*
 		 * See if operation failed and additional status checks are
-		 * available
+		 * available.
 		 */
 		if ((status & NAND_STATUS_FAIL) && (chip->errstat))
 			status = chip->errstat(mtd, chip, FL_WRITING, status,
@@ -1852,34 +1867,45 @@
 
 	if (chip->verify_buf(mtd, buf, mtd->writesize))
 		return -EIO;
+
+	/* Make sure the next page prog is preceded by a status read */
+	chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 #endif
 	return 0;
 }
 
 /**
- * nand_fill_oob - [Internal] Transfer client buffer to oob
- * @chip:	nand chip structure
- * @oob:	oob data buffer
- * @len:	oob data write length
- * @ops:	oob ops structure
+ * nand_fill_oob - [INTERN] Transfer client buffer to oob
+ * @mtd: MTD device structure
+ * @oob: oob data buffer
+ * @len: oob data write length
+ * @ops: oob ops structure
  */
-static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
-						struct mtd_oob_ops *ops)
+static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
+			      struct mtd_oob_ops *ops)
 {
+	struct nand_chip *chip = mtd->priv;
+
+	/*
+	 * Initialise to all 0xFF, to avoid the possibility of left over OOB
+	 * data from a previous OOB read.
+	 */
+	memset(chip->oob_poi, 0xff, mtd->oobsize);
+
 	switch (ops->mode) {
 
-	case MTD_OOB_PLACE:
-	case MTD_OOB_RAW:
+	case MTD_OPS_PLACE_OOB:
+	case MTD_OPS_RAW:
 		memcpy(chip->oob_poi + ops->ooboffs, oob, len);
 		return oob + len;
 
-	case MTD_OOB_AUTO: {
+	case MTD_OPS_AUTO_OOB: {
 		struct nand_oobfree *free = chip->ecc.layout->oobfree;
 		uint32_t boffs = 0, woffs = ops->ooboffs;
 		size_t bytes = 0;
 
 		for (; free->length && len; free++, len -= bytes) {
-			/* Write request not from offset 0 ? */
+			/* Write request not from offset 0? */
 			if (unlikely(woffs)) {
 				if (woffs >= free->length) {
 					woffs -= free->length;
@@ -1907,12 +1933,12 @@
 #define NOTALIGNED(x)	((x & (chip->subpagesize - 1)) != 0)
 
 /**
- * nand_do_write_ops - [Internal] NAND write with ECC
- * @mtd:	MTD device structure
- * @to:		offset to write to
- * @ops:	oob operations description structure
+ * nand_do_write_ops - [INTERN] NAND write with ECC
+ * @mtd: MTD device structure
+ * @to: offset to write to
+ * @ops: oob operations description structure
  *
- * NAND write with ECC
+ * NAND write with ECC.
  */
 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
 			     struct mtd_oob_ops *ops)
@@ -1922,12 +1948,13 @@
 	uint32_t writelen = ops->len;
 
 	uint32_t oobwritelen = ops->ooblen;
-	uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
+	uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
 				mtd->oobavail : mtd->oobsize;
 
 	uint8_t *oob = ops->oobbuf;
 	uint8_t *buf = ops->datbuf;
 	int ret, subpage;
+	int oob_required = oob ? 1 : 0;
 
 	ops->retlen = 0;
 	if (!writelen)
@@ -1957,10 +1984,6 @@
 	    (chip->pagebuf << chip->page_shift) < (to + ops->len))
 		chip->pagebuf = -1;
 
-	/* If we're not given explicit OOB data, let it be 0xFF */
-	if (likely(!oob))
-		memset(chip->oob_poi, 0xff, mtd->oobsize);
-
 	/* Don't allow multipage oob writes with offset */
 	if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
 		return -EINVAL;
@@ -1972,8 +1995,8 @@
 		int cached = writelen > bytes && page != blockmask;
 		uint8_t *wbuf = buf;
 
-		/* Partial page write ? */
-		if (unlikely(column || writelen < (mtd->writesize - 1))) {
+		/* Partial page write? */
+		if (unlikely(column || writelen < mtd->writesize)) {
 			cached = 0;
 			bytes = min_t(int, bytes - column, (int) writelen);
 			chip->pagebuf = -1;
@@ -1984,12 +2007,15 @@
 
 		if (unlikely(oob)) {
 			size_t len = min(oobwritelen, oobmaxlen);
-			oob = nand_fill_oob(chip, oob, len, ops);
+			oob = nand_fill_oob(mtd, oob, len, ops);
 			oobwritelen -= len;
+		} else {
+			/* We still need to erase leftover OOB data */
+			memset(chip->oob_poi, 0xff, mtd->oobsize);
 		}
 
-		ret = chip->write_page(mtd, chip, wbuf, page, cached,
-				       (ops->mode == MTD_OOB_RAW));
+		ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
+				       cached, (ops->mode == MTD_OPS_RAW));
 		if (ret)
 			break;
 
@@ -2018,48 +2044,39 @@
 
 /**
  * nand_write - [MTD Interface] NAND write with ECC
- * @mtd:	MTD device structure
- * @to:		offset to write to
- * @len:	number of bytes to write
- * @retlen:	pointer to variable to store the number of written bytes
- * @buf:	the data to write
+ * @mtd: MTD device structure
+ * @to: offset to write to
+ * @len: number of bytes to write
+ * @retlen: pointer to variable to store the number of written bytes
+ * @buf: the data to write
  *
- * NAND write with ECC
+ * NAND write with ECC.
  */
 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
 			  size_t *retlen, const uint8_t *buf)
 {
 	struct nand_chip *chip = mtd->priv;
+	struct mtd_oob_ops ops;
 	int ret;
 
-	/* Do not allow writes past end of device */
-	if ((to + len) > mtd->size)
-		return -EINVAL;
-	if (!len)
-		return 0;
-
 	nand_get_device(chip, mtd, FL_WRITING);
-
-	chip->ops.len = len;
-	chip->ops.datbuf = (uint8_t *)buf;
-	chip->ops.oobbuf = NULL;
-
-	ret = nand_do_write_ops(mtd, to, &chip->ops);
-
-	*retlen = chip->ops.retlen;
-
+	ops.len = len;
+	ops.datbuf = (uint8_t *)buf;
+	ops.oobbuf = NULL;
+	ops.mode = MTD_OPS_PLACE_OOB;
+	ret = nand_do_write_ops(mtd, to, &ops);
+	*retlen = ops.retlen;
 	nand_release_device(mtd);
-
 	return ret;
 }
 
 /**
  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
- * @mtd:	MTD device structure
- * @to:		offset to write to
- * @ops:	oob operation description structure
+ * @mtd: MTD device structure
+ * @to: offset to write to
+ * @ops: oob operation description structure
  *
- * NAND write out-of-band
+ * NAND write out-of-band.
  */
 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 			     struct mtd_oob_ops *ops)
@@ -2070,7 +2087,7 @@
 	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
 			 __func__, (unsigned int)to, (int)ops->ooblen);
 
-	if (ops->mode == MTD_OOB_AUTO)
+	if (ops->mode == MTD_OPS_AUTO_OOB)
 		len = chip->ecc.layout->oobavail;
 	else
 		len = mtd->oobsize;
@@ -2120,10 +2137,12 @@
 	if (page == chip->pagebuf)
 		chip->pagebuf = -1;
 
-	memset(chip->oob_poi, 0xff, mtd->oobsize);
-	nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
-	status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
-	memset(chip->oob_poi, 0xff, mtd->oobsize);
+	nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
+
+	if (ops->mode == MTD_OPS_RAW)
+		status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
+	else
+		status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
 
 	if (status)
 		return status;
@@ -2135,9 +2154,9 @@
 
 /**
  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
- * @mtd:	MTD device structure
- * @to:		offset to write to
- * @ops:	oob operation description structure
+ * @mtd: MTD device structure
+ * @to: offset to write to
+ * @ops: oob operation description structure
  */
 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
 			  struct mtd_oob_ops *ops)
@@ -2157,9 +2176,9 @@
 	nand_get_device(chip, mtd, FL_WRITING);
 
 	switch (ops->mode) {
-	case MTD_OOB_PLACE:
-	case MTD_OOB_AUTO:
-	case MTD_OOB_RAW:
+	case MTD_OPS_PLACE_OOB:
+	case MTD_OPS_AUTO_OOB:
+	case MTD_OPS_RAW:
 		break;
 
 	default:
@@ -2177,11 +2196,11 @@
 }
 
 /**
- * single_erease_cmd - [GENERIC] NAND standard block erase command function
- * @mtd:	MTD device structure
- * @page:	the page address of the block which will be erased
+ * single_erase_cmd - [GENERIC] NAND standard block erase command function
+ * @mtd: MTD device structure
+ * @page: the page address of the block which will be erased
  *
- * Standard erase command for NAND chips
+ * Standard erase command for NAND chips.
  */
 static void single_erase_cmd(struct mtd_info *mtd, int page)
 {
@@ -2192,12 +2211,11 @@
 }
 
 /**
- * multi_erease_cmd - [GENERIC] AND specific block erase command function
- * @mtd:	MTD device structure
- * @page:	the page address of the block which will be erased
+ * multi_erase_cmd - [GENERIC] AND specific block erase command function
+ * @mtd: MTD device structure
+ * @page: the page address of the block which will be erased
  *
- * AND multi block erase command function
- * Erase 4 consecutive blocks
+ * AND multi block erase command function. Erase 4 consecutive blocks.
  */
 static void multi_erase_cmd(struct mtd_info *mtd, int page)
 {
@@ -2212,10 +2230,10 @@
 
 /**
  * nand_erase - [MTD Interface] erase block(s)
- * @mtd:	MTD device structure
- * @instr:	erase instruction
+ * @mtd: MTD device structure
+ * @instr: erase instruction
  *
- * Erase one ore more blocks
+ * Erase one ore more blocks.
  */
 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
 {
@@ -2224,12 +2242,12 @@
 
 #define BBT_PAGE_MASK	0xffffff3f
 /**
- * nand_erase_nand - [Internal] erase block(s)
- * @mtd:	MTD device structure
- * @instr:	erase instruction
- * @allowbbt:	allow erasing the bbt area
+ * nand_erase_nand - [INTERN] erase block(s)
+ * @mtd: MTD device structure
+ * @instr: erase instruction
+ * @allowbbt: allow erasing the bbt area
  *
- * Erase one ore more blocks
+ * Erase one ore more blocks.
  */
 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 		    int allowbbt)
@@ -2247,8 +2265,6 @@
 	if (check_offs_len(mtd, instr->addr, instr->len))
 		return -EINVAL;
 
-	instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
-
 	/* Grab the lock and see if the device is available */
 	nand_get_device(chip, mtd, FL_ERASING);
 
@@ -2274,7 +2290,7 @@
 	 * If BBT requires refresh, set the BBT page mask to see if the BBT
 	 * should be rewritten. Otherwise the mask is set to 0xffffffff which
 	 * can not be matched. This is also done when the bbt is actually
-	 * erased to avoid recusrsive updates
+	 * erased to avoid recursive updates.
 	 */
 	if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
 		bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
@@ -2286,20 +2302,18 @@
 
 	while (len) {
 		WATCHDOG_RESET();
-		/*
-		 * heck if we have a bad block, we do not erase bad blocks !
-		 */
+		/* Check if we have a bad block, we do not erase bad blocks! */
 		if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
 					chip->page_shift, 0, allowbbt)) {
-			printk(KERN_WARNING "%s: attempt to erase a bad block "
-					"at page 0x%08x\n", __func__, page);
+			pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
+				   __func__, page);
 			instr->state = MTD_ERASE_FAILED;
 			goto erase_exit;
 		}
 
 		/*
 		 * Invalidate the page cache, if we erase the block which
-		 * contains the current cached page
+		 * contains the current cached page.
 		 */
 		if (page <= chip->pagebuf && chip->pagebuf <
 		    (page + pages_per_block))
@@ -2329,7 +2343,7 @@
 
 		/*
 		 * If BBT requires refresh, set the BBT rewrite flag to the
-		 * page being erased
+		 * page being erased.
 		 */
 		if (bbt_masked_page != 0xffffffff &&
 		    (page & BBT_PAGE_MASK) == bbt_masked_page)
@@ -2348,7 +2362,7 @@
 
 			/*
 			 * If BBT requires refresh and BBT-PERCHIP, set the BBT
-			 * page mask to see if this BBT should be rewritten
+			 * page mask to see if this BBT should be rewritten.
 			 */
 			if (bbt_masked_page != 0xffffffff &&
 			    (chip->bbt_td->options & NAND_BBT_PERCHIP))
@@ -2371,7 +2385,7 @@
 
 	/*
 	 * If BBT requires refresh and erase was successful, rewrite any
-	 * selected bad block tables
+	 * selected bad block tables.
 	 */
 	if (bbt_masked_page == 0xffffffff || ret)
 		return ret;
@@ -2379,7 +2393,7 @@
 	for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
 		if (!rewrite_bbt[chipnr])
 			continue;
-		/* update the BBT for chip */
+		/* Update the BBT for chip */
 		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
 			"(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
 			rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
@@ -2392,9 +2406,9 @@
 
 /**
  * nand_sync - [MTD Interface] sync
- * @mtd:	MTD device structure
+ * @mtd: MTD device structure
  *
- * Sync is actually a wait for chip ready function
+ * Sync is actually a wait for chip ready function.
  */
 static void nand_sync(struct mtd_info *mtd)
 {
@@ -2410,22 +2424,18 @@
 
 /**
  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
- * @mtd:	MTD device structure
- * @offs:	offset relative to mtd start
+ * @mtd: MTD device structure
+ * @offs: offset relative to mtd start
  */
 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
 {
-	/* Check for invalid offset */
-	if (offs > mtd->size)
-		return -EINVAL;
-
 	return nand_block_checkbad(mtd, offs, 1, 0);
 }
 
 /**
  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
- * @mtd:	MTD device structure
- * @ofs:	offset relative to mtd start
+ * @mtd: MTD device structure
+ * @ofs: offset relative to mtd start
  */
 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
 {
@@ -2434,7 +2444,7 @@
 
 	ret = nand_block_isbad(mtd, ofs);
 	if (ret) {
-		/* If it was bad already, return success and do nothing. */
+		/* If it was bad already, return success and do nothing */
 		if (ret > 0)
 			return 0;
 		return ret;
@@ -2443,9 +2453,51 @@
 	return chip->block_markbad(mtd, ofs);
 }
 
-/*
- * Set default functions
+ /**
+ * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
+ * @mtd: MTD device structure
+ * @chip: nand chip info structure
+ * @addr: feature address.
+ * @subfeature_param: the subfeature parameters, a four bytes array.
  */
+static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
+			int addr, uint8_t *subfeature_param)
+{
+	int status;
+
+	if (!chip->onfi_version)
+		return -EINVAL;
+
+	chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
+	chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
+	status = chip->waitfunc(mtd, chip);
+	if (status & NAND_STATUS_FAIL)
+		return -EIO;
+	return 0;
+}
+
+/**
+ * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
+ * @mtd: MTD device structure
+ * @chip: nand chip info structure
+ * @addr: feature address.
+ * @subfeature_param: the subfeature parameters, a four bytes array.
+ */
+static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
+			int addr, uint8_t *subfeature_param)
+{
+	if (!chip->onfi_version)
+		return -EINVAL;
+
+	/* clear the sub feature parameters */
+	memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
+
+	chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
+	chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
+	return 0;
+}
+
+/* Set default functions */
 static void nand_set_defaults(struct nand_chip *chip, int busw)
 {
 	/* check for proper chip_delay setup, set 20us if not */
@@ -2483,23 +2535,21 @@
 }
 
 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
-/*
- * sanitize ONFI strings so we can safely print them
- */
+/* Sanitize ONFI strings so we can safely print them */
 static void sanitize_string(char *s, size_t len)
 {
 	ssize_t i;
 
-	/* null terminate */
+	/* Null terminate */
 	s[len - 1] = 0;
 
-	/* remove non printable chars */
+	/* Remove non printable chars */
 	for (i = 0; i < len - 1; i++) {
 		if (s[i] < ' ' || s[i] > 127)
 			s[i] = '?';
 	}
 
-	/* remove trailing spaces */
+	/* Remove trailing spaces */
 	strim(s);
 }
 
@@ -2516,7 +2566,7 @@
 }
 
 /*
- * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
+ * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
  */
 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
 					int *busw)
@@ -2525,20 +2575,18 @@
 	int i;
 	int val;
 
-	/* try ONFI for unknow chip or LP */
+	/* Try ONFI for unknown chip or LP */
 	chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
 	if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
 		chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
 		return 0;
 
-	MTDDEBUG(MTD_DEBUG_LEVEL0, "ONFI flash detected\n");
 	chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
 	for (i = 0; i < 3; i++) {
 		chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
 		if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
 				le16_to_cpu(p->crc)) {
-			MTDDEBUG(MTD_DEBUG_LEVEL0,
-				 "ONFI param page %d valid\n", i);
+			pr_info("ONFI param page %d valid\n", i);
 			break;
 		}
 	}
@@ -2546,7 +2594,7 @@
 	if (i == 3)
 		return 0;
 
-	/* check version */
+	/* Check version */
 	val = le16_to_cpu(p->revision);
 	if (val & (1 << 5))
 		chip->onfi_version = 23;
@@ -2562,8 +2610,7 @@
 		chip->onfi_version = 0;
 
 	if (!chip->onfi_version) {
-		printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
-								__func__, val);
+		pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
 		return 0;
 	}
 
@@ -2580,8 +2627,7 @@
 	if (le16_to_cpu(p->features) & 1)
 		*busw = NAND_BUSWIDTH_16;
 
-	chip->options |= NAND_NO_READRDY | NAND_NO_AUTOINCR;
-
+	pr_info("ONFI flash detected\n");
 	return 1;
 }
 #else
@@ -2594,7 +2640,248 @@
 #endif
 
 /*
- * Get the flash and manufacturer id and lookup if the type is supported
+ * nand_id_has_period - Check if an ID string has a given wraparound period
+ * @id_data: the ID string
+ * @arrlen: the length of the @id_data array
+ * @period: the period of repitition
+ *
+ * Check if an ID string is repeated within a given sequence of bytes at
+ * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
+ * period of 2). This is a helper function for nand_id_len(). Returns non-zero
+ * if the repetition has a period of @period; otherwise, returns zero.
+ */
+static int nand_id_has_period(u8 *id_data, int arrlen, int period)
+{
+	int i, j;
+	for (i = 0; i < period; i++)
+		for (j = i + period; j < arrlen; j += period)
+			if (id_data[i] != id_data[j])
+				return 0;
+	return 1;
+}
+
+/*
+ * nand_id_len - Get the length of an ID string returned by CMD_READID
+ * @id_data: the ID string
+ * @arrlen: the length of the @id_data array
+
+ * Returns the length of the ID string, according to known wraparound/trailing
+ * zero patterns. If no pattern exists, returns the length of the array.
+ */
+static int nand_id_len(u8 *id_data, int arrlen)
+{
+	int last_nonzero, period;
+
+	/* Find last non-zero byte */
+	for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
+		if (id_data[last_nonzero])
+			break;
+
+	/* All zeros */
+	if (last_nonzero < 0)
+		return 0;
+
+	/* Calculate wraparound period */
+	for (period = 1; period < arrlen; period++)
+		if (nand_id_has_period(id_data, arrlen, period))
+			break;
+
+	/* There's a repeated pattern */
+	if (period < arrlen)
+		return period;
+
+	/* There are trailing zeros */
+	if (last_nonzero < arrlen - 1)
+		return last_nonzero + 1;
+
+	/* No pattern detected */
+	return arrlen;
+}
+
+/*
+ * Many new NAND share similar device ID codes, which represent the size of the
+ * chip. The rest of the parameters must be decoded according to generic or
+ * manufacturer-specific "extended ID" decoding patterns.
+ */
+static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
+				u8 id_data[8], int *busw)
+{
+	int extid, id_len;
+	/* The 3rd id byte holds MLC / multichip data */
+	chip->cellinfo = id_data[2];
+	/* The 4th id byte is the important one */
+	extid = id_data[3];
+
+	id_len = nand_id_len(id_data, 8);
+
+	/*
+	 * Field definitions are in the following datasheets:
+	 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
+	 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
+	 * Hynix MLC   (6 byte ID): Hynix H27UBG8T2B (p.22)
+	 *
+	 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
+	 * ID to decide what to do.
+	 */
+	if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
+			(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
+			id_data[5] != 0x00) {
+		/* Calc pagesize */
+		mtd->writesize = 2048 << (extid & 0x03);
+		extid >>= 2;
+		/* Calc oobsize */
+		switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
+		case 1:
+			mtd->oobsize = 128;
+			break;
+		case 2:
+			mtd->oobsize = 218;
+			break;
+		case 3:
+			mtd->oobsize = 400;
+			break;
+		case 4:
+			mtd->oobsize = 436;
+			break;
+		case 5:
+			mtd->oobsize = 512;
+			break;
+		case 6:
+		default: /* Other cases are "reserved" (unknown) */
+			mtd->oobsize = 640;
+			break;
+		}
+		extid >>= 2;
+		/* Calc blocksize */
+		mtd->erasesize = (128 * 1024) <<
+			(((extid >> 1) & 0x04) | (extid & 0x03));
+		*busw = 0;
+	} else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
+			(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
+		unsigned int tmp;
+
+		/* Calc pagesize */
+		mtd->writesize = 2048 << (extid & 0x03);
+		extid >>= 2;
+		/* Calc oobsize */
+		switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
+		case 0:
+			mtd->oobsize = 128;
+			break;
+		case 1:
+			mtd->oobsize = 224;
+			break;
+		case 2:
+			mtd->oobsize = 448;
+			break;
+		case 3:
+			mtd->oobsize = 64;
+			break;
+		case 4:
+			mtd->oobsize = 32;
+			break;
+		case 5:
+			mtd->oobsize = 16;
+			break;
+		default:
+			mtd->oobsize = 640;
+			break;
+		}
+		extid >>= 2;
+		/* Calc blocksize */
+		tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
+		if (tmp < 0x03)
+			mtd->erasesize = (128 * 1024) << tmp;
+		else if (tmp == 0x03)
+			mtd->erasesize = 768 * 1024;
+		else
+			mtd->erasesize = (64 * 1024) << tmp;
+		*busw = 0;
+	} else {
+		/* Calc pagesize */
+		mtd->writesize = 1024 << (extid & 0x03);
+		extid >>= 2;
+		/* Calc oobsize */
+		mtd->oobsize = (8 << (extid & 0x01)) *
+			(mtd->writesize >> 9);
+		extid >>= 2;
+		/* Calc blocksize. Blocksize is multiples of 64KiB */
+		mtd->erasesize = (64 * 1024) << (extid & 0x03);
+		extid >>= 2;
+		/* Get buswidth information */
+		*busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
+	}
+}
+
+ /*
+ * Old devices have chip data hardcoded in the device ID table. nand_decode_id
+ * decodes a matching ID table entry and assigns the MTD size parameters for
+ * the chip.
+ */
+static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
+				const struct nand_flash_dev *type, u8 id_data[8],
+				int *busw)
+{
+	int maf_id = id_data[0];
+
+	mtd->erasesize = type->erasesize;
+	mtd->writesize = type->pagesize;
+	mtd->oobsize = mtd->writesize / 32;
+	*busw = type->options & NAND_BUSWIDTH_16;
+
+	/*
+	 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
+	 * some Spansion chips have erasesize that conflicts with size
+	 * listed in nand_ids table.
+	 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
+	 */
+	if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
+			&& id_data[6] == 0x00 && id_data[7] == 0x00
+			&& mtd->writesize == 512) {
+		mtd->erasesize = 128 * 1024;
+		mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
+	}
+}
+
+ /*
+ * Set the bad block marker/indicator (BBM/BBI) patterns according to some
+ * heuristic patterns using various detected parameters (e.g., manufacturer,
+ * page size, cell-type information).
+ */
+static void nand_decode_bbm_options(struct mtd_info *mtd,
+				    struct nand_chip *chip, u8 id_data[8])
+{
+	int maf_id = id_data[0];
+
+	/* Set the bad block position */
+	if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
+		chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
+	else
+		chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
+
+	/*
+	 * Bad block marker is stored in the last page of each block on Samsung
+	 * and Hynix MLC devices; stored in first two pages of each block on
+	 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
+	 * AMD/Spansion, and Macronix.  All others scan only the first page.
+	 */
+	if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
+			(maf_id == NAND_MFR_SAMSUNG ||
+			 maf_id == NAND_MFR_HYNIX))
+		chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
+	else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
+				(maf_id == NAND_MFR_SAMSUNG ||
+				 maf_id == NAND_MFR_HYNIX ||
+				 maf_id == NAND_MFR_TOSHIBA ||
+				 maf_id == NAND_MFR_AMD ||
+				 maf_id == NAND_MFR_MACRONIX)) ||
+			(mtd->writesize == 2048 &&
+			 maf_id == NAND_MFR_MICRON))
+		chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
+}
+
+/*
+ * Get the flash and manufacturer id and lookup if the type is supported.
  */
 static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 						  struct nand_chip *chip,
@@ -2605,14 +2892,13 @@
 	const char *name;
 	int i, maf_idx;
 	u8 id_data[8];
-	int ret;
 
 	/* Select the device */
 	chip->select_chip(mtd, 0);
 
 	/*
 	 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
-	 * after power-up
+	 * after power-up.
 	 */
 	chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
 
@@ -2623,7 +2909,8 @@
 	*maf_id = chip->read_byte(mtd);
 	*dev_id = chip->read_byte(mtd);
 
-	/* Try again to make sure, as some systems the bus-hold or other
+	/*
+	 * Try again to make sure, as some systems the bus-hold or other
 	 * interface concerns can cause random data which looks like a
 	 * possibly credible NAND flash to appear. If the two results do
 	 * not match, ignore the device completely.
@@ -2631,13 +2918,14 @@
 
 	chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
 
-	for (i = 0; i < 2; i++)
+	/* Read entire ID string */
+	for (i = 0; i < 8; i++)
 		id_data[i] = chip->read_byte(mtd);
 
 	if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
-		printk(KERN_INFO "%s: second ID read did not match "
-		       "%02x,%02x against %02x,%02x\n", __func__,
-		       *maf_id, *dev_id, id_data[0], id_data[1]);
+		pr_info("%s: second ID read did not match "
+			"%02x,%02x against %02x,%02x\n", __func__,
+			*maf_id, *dev_id, id_data[0], id_data[1]);
 		return ERR_PTR(-ENODEV);
 	}
 
@@ -2651,18 +2939,10 @@
 	chip->onfi_version = 0;
 	if (!type->name || !type->pagesize) {
 		/* Check is chip is ONFI compliant */
-		ret = nand_flash_detect_onfi(mtd, chip, &busw);
-		if (ret)
+		if (nand_flash_detect_onfi(mtd, chip, &busw))
 			goto ident_done;
 	}
 
-	chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
-
-	/* Read entire ID string */
-
-	for (i = 0; i < 8; i++)
-		id_data[i] = chip->read_byte(mtd);
-
 	if (!type->name)
 		return ERR_PTR(-ENODEV);
 
@@ -2672,101 +2952,25 @@
 	chip->chipsize = (uint64_t)type->chipsize << 20;
 
 	if (!type->pagesize && chip->init_size) {
-		/* set the pagesize, oobsize, erasesize by the driver*/
+		/* Set the pagesize, oobsize, erasesize by the driver */
 		busw = chip->init_size(mtd, chip, id_data);
 	} else if (!type->pagesize) {
-		int extid;
-		/* The 3rd id byte holds MLC / multichip data */
-		chip->cellinfo = id_data[2];
-		/* The 4th id byte is the important one */
-		extid = id_data[3];
-
-		/*
-		 * Field definitions are in the following datasheets:
-		 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
-		 * New style   (6 byte ID): Samsung K9GBG08U0M (p.40)
-		 *
-		 * Check for wraparound + Samsung ID + nonzero 6th byte
-		 * to decide what to do.
-		 */
-		if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
-				id_data[0] == NAND_MFR_SAMSUNG &&
-				(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
-				id_data[5] != 0x00) {
-			/* Calc pagesize */
-			mtd->writesize = 2048 << (extid & 0x03);
-			extid >>= 2;
-			/* Calc oobsize */
-			switch (extid & 0x03) {
-			case 1:
-				mtd->oobsize = 128;
-				break;
-			case 2:
-				mtd->oobsize = 218;
-				break;
-			case 3:
-				mtd->oobsize = 400;
-				break;
-			default:
-				mtd->oobsize = 436;
-				break;
-			}
-			extid >>= 2;
-			/* Calc blocksize */
-			mtd->erasesize = (128 * 1024) <<
-				(((extid >> 1) & 0x04) | (extid & 0x03));
-			busw = 0;
-		} else {
-			/* Calc pagesize */
-			mtd->writesize = 1024 << (extid & 0x03);
-			extid >>= 2;
-			/* Calc oobsize */
-			mtd->oobsize = (8 << (extid & 0x01)) *
-				(mtd->writesize >> 9);
-			extid >>= 2;
-			/* Calc blocksize. Blocksize is multiples of 64KiB */
-			mtd->erasesize = (64 * 1024) << (extid & 0x03);
-			extid >>= 2;
-			/* Get buswidth information */
-			busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
-		}
+		/* Decode parameters from extended ID */
+		nand_decode_ext_id(mtd, chip, id_data, &busw);
 	} else {
-		/*
-		 * Old devices have chip data hardcoded in the device id table
-		 */
-		mtd->erasesize = type->erasesize;
-		mtd->writesize = type->pagesize;
-		mtd->oobsize = mtd->writesize / 32;
-		busw = type->options & NAND_BUSWIDTH_16;
-
-		/*
-		 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
-		 * some Spansion chips have erasesize that conflicts with size
-		 * listed in nand_ids table
-		 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
-		 */
-		if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
-				id_data[5] == 0x00 && id_data[6] == 0x00 &&
-				id_data[7] == 0x00 && mtd->writesize == 512) {
-			mtd->erasesize = 128 * 1024;
-			mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
-		}
+		nand_decode_id(mtd, chip, type, id_data, &busw);
 	}
 	/* Get chip options, preserve non chip based options */
 	chip->options |= type->options;
 
-	/* Check if chip is a not a samsung device. Do not clear the
-	 * options for chips which are not having an extended id.
+	/*
+	 * Check if chip is not a Samsung device. Do not clear the
+	 * options for chips which do not have an extended id.
 	 */
 	if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
 		chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
 ident_done:
 
-	/*
-	 * Set chip as a default. Board drivers can override it, if necessary
-	 */
-	chip->options |= NAND_NO_AUTOINCR;
-
 	/* Try to identify manufacturer */
 	for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
 		if (nand_manuf_ids[maf_idx].id == *maf_id)
@@ -2775,21 +2979,23 @@
 
 	/*
 	 * Check, if buswidth is correct. Hardware drivers should set
-	 * chip correct !
+	 * chip correct!
 	 */
 	if (busw != (chip->options & NAND_BUSWIDTH_16)) {
-		printk(KERN_INFO "NAND device: Manufacturer ID:"
-		       " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
-		       *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
-		printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
-		       (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
-		       busw ? 16 : 8);
+		pr_info("NAND device: Manufacturer ID:"
+			" 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
+			*dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
+		pr_warn("NAND bus width %d instead %d bit\n",
+			   (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
+			   busw ? 16 : 8);
 		return ERR_PTR(-EINVAL);
 	}
 
+	nand_decode_bbm_options(mtd, chip, id_data);
+
 	/* Calculate the address shift from the page size */
 	chip->page_shift = ffs(mtd->writesize) - 1;
-	/* Convert chipsize to number of pages per chip -1. */
+	/* Convert chipsize to number of pages per chip -1 */
 	chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
 
 	chip->bbt_erase_shift = chip->phys_erase_shift =
@@ -2803,73 +3009,38 @@
 
 	chip->badblockbits = 8;
 
-	/* Set the bad block position */
-	if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
-		chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
-	else
-		chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
-
-	/*
-	 * Bad block marker is stored in the last page of each block
-	 * on Samsung and Hynix MLC devices; stored in first two pages
-	 * of each block on Micron devices with 2KiB pages and on
-	 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
-	 * only the first page.
-	 */
-	if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
-			(*maf_id == NAND_MFR_SAMSUNG ||
-			 *maf_id == NAND_MFR_HYNIX))
-		chip->options |= NAND_BBT_SCANLASTPAGE;
-	else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
-				(*maf_id == NAND_MFR_SAMSUNG ||
-				 *maf_id == NAND_MFR_HYNIX ||
-				 *maf_id == NAND_MFR_TOSHIBA ||
-				 *maf_id == NAND_MFR_AMD)) ||
-			(mtd->writesize == 2048 &&
-			 *maf_id == NAND_MFR_MICRON))
-		chip->options |= NAND_BBT_SCAN2NDPAGE;
-
-	/*
-	 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6
-	 */
-	if (!(busw & NAND_BUSWIDTH_16) &&
-			*maf_id == NAND_MFR_STMICRO &&
-			mtd->writesize == 2048) {
-		chip->options |= NAND_BBT_SCANBYTE1AND6;
-		chip->badblockpos = 0;
-	}
-
 	/* Check for AND chips with 4 page planes */
 	if (chip->options & NAND_4PAGE_ARRAY)
 		chip->erase_cmd = multi_erase_cmd;
 	else
 		chip->erase_cmd = single_erase_cmd;
 
-	/* Do not replace user supplied command function ! */
+	/* Do not replace user supplied command function! */
 	if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
 		chip->cmdfunc = nand_command_lp;
 
-	/* TODO onfi flash name */
 	name = type->name;
 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 	if (chip->onfi_version)
 		name = chip->onfi_params.model;
 #endif
-	MTDDEBUG(MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
-		 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
-		 nand_manuf_ids[maf_idx].name, name);
+	pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
+		" page size: %d, OOB size: %d\n",
+		*maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
+		name,
+		mtd->writesize, mtd->oobsize);
 
 	return type;
 }
 
 /**
  * nand_scan_ident - [NAND Interface] Scan for the NAND device
- * @mtd:	     MTD device structure
- * @maxchips:	     Number of chips to scan for
- * @table:	     Alternative NAND ID table
+ * @mtd: MTD device structure
+ * @maxchips: number of chips to scan for
+ * @table: alternative NAND ID table
  *
- * This is the first phase of the normal nand_scan() function. It
- * reads the flash ID and sets up MTD fields accordingly.
+ * This is the first phase of the normal nand_scan() function. It reads the
+ * flash ID and sets up MTD fields accordingly.
  *
  * The mtd->owner field must be set to the module of the caller.
  */
@@ -2891,7 +3062,7 @@
 
 	if (IS_ERR(type)) {
 #ifndef CONFIG_SYS_NAND_QUIET_TEST
-		printk(KERN_WARNING "No NAND device found!!!\n");
+		pr_warn("No NAND device found\n");
 #endif
 		chip->select_chip(mtd, -1);
 		return PTR_ERR(type);
@@ -2911,7 +3082,7 @@
 	}
 #ifdef DEBUG
 	if (i > 1)
-		printk(KERN_INFO "%d NAND chips detected\n", i);
+		pr_info("%d NAND chips detected\n", i);
 #endif
 
 	/* Store the number of chips and calc total size for mtd */
@@ -2924,17 +3095,21 @@
 
 /**
  * nand_scan_tail - [NAND Interface] Scan for the NAND device
- * @mtd:	    MTD device structure
+ * @mtd: MTD device structure
  *
- * This is the second phase of the normal nand_scan() function. It
- * fills out all the uninitialized function pointers with the defaults
- * and scans for a bad block table if appropriate.
+ * This is the second phase of the normal nand_scan() function. It fills out
+ * all the uninitialized function pointers with the defaults and scans for a
+ * bad block table if appropriate.
  */
 int nand_scan_tail(struct mtd_info *mtd)
 {
 	int i;
 	struct nand_chip *chip = mtd->priv;
 
+	/* New bad blocks should be marked in OOB, flash-based BBT, or both */
+	BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
+			!(chip->bbt_options & NAND_BBT_USE_FLASH));
+
 	if (!(chip->options & NAND_OWN_BUFFERS))
 		chip->buffers = memalign(ARCH_DMA_MINALIGN,
 					 sizeof(*chip->buffers));
@@ -2945,7 +3120,7 @@
 	chip->oob_poi = chip->buffers->databuf + mtd->writesize;
 
 	/*
-	 * If no default placement scheme is given, select an appropriate one
+	 * If no default placement scheme is given, select an appropriate one.
 	 */
 	if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
 		switch (mtd->oobsize) {
@@ -2962,16 +3137,22 @@
 			chip->ecc.layout = &nand_oob_128;
 			break;
 		default:
-			printk(KERN_WARNING "No oob scheme defined for "
-			       "oobsize %d\n", mtd->oobsize);
+			pr_warn("No oob scheme defined for oobsize %d\n",
+				   mtd->oobsize);
 		}
 	}
 
 	if (!chip->write_page)
 		chip->write_page = nand_write_page;
 
+	/* set for ONFI nand */
+	if (!chip->onfi_set_features)
+		chip->onfi_set_features = nand_onfi_set_features;
+	if (!chip->onfi_get_features)
+		chip->onfi_get_features = nand_onfi_get_features;
+
 	/*
-	 * check ECC mode, default to software if 3byte/512byte hardware ECC is
+	 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
 	 * selected and we have 256 byte pagesize fallback to software ECC
 	 */
 
@@ -2980,15 +3161,15 @@
 		/* Similar to NAND_ECC_HW, but a separate read_page handle */
 		if (!chip->ecc.calculate || !chip->ecc.correct ||
 		     !chip->ecc.hwctl) {
-			printk(KERN_WARNING "No ECC functions supplied; "
-			       "Hardware ECC not possible\n");
+			pr_warn("No ECC functions supplied; "
+				   "hardware ECC not possible\n");
 			BUG();
 		}
 		if (!chip->ecc.read_page)
 			chip->ecc.read_page = nand_read_page_hwecc_oob_first;
 
 	case NAND_ECC_HW:
-		/* Use standard hwecc read page function ? */
+		/* Use standard hwecc read page function? */
 		if (!chip->ecc.read_page)
 			chip->ecc.read_page = nand_read_page_hwecc;
 		if (!chip->ecc.write_page)
@@ -3009,11 +3190,11 @@
 		     chip->ecc.read_page == nand_read_page_hwecc ||
 		     !chip->ecc.write_page ||
 		     chip->ecc.write_page == nand_write_page_hwecc)) {
-			printk(KERN_WARNING "No ECC functions supplied; "
-			       "Hardware ECC not possible\n");
+			pr_warn("No ECC functions supplied; "
+				   "hardware ECC not possible\n");
 			BUG();
 		}
-		/* Use standard syndrome read/write page function ? */
+		/* Use standard syndrome read/write page function? */
 		if (!chip->ecc.read_page)
 			chip->ecc.read_page = nand_read_page_syndrome;
 		if (!chip->ecc.write_page)
@@ -3027,11 +3208,16 @@
 		if (!chip->ecc.write_oob)
 			chip->ecc.write_oob = nand_write_oob_syndrome;
 
-		if (mtd->writesize >= chip->ecc.size)
+		if (mtd->writesize >= chip->ecc.size) {
+			if (!chip->ecc.strength) {
+				pr_warn("Driver must set ecc.strength when using hardware ECC\n");
+				BUG();
+			}
 			break;
-		printk(KERN_WARNING "%d byte HW ECC not possible on "
-		       "%d byte page size, fallback to SW ECC\n",
-		       chip->ecc.size, mtd->writesize);
+		}
+		pr_warn("%d byte HW ECC not possible on "
+			   "%d byte page size, fallback to SW ECC\n",
+			   chip->ecc.size, mtd->writesize);
 		chip->ecc.mode = NAND_ECC_SOFT;
 
 	case NAND_ECC_SOFT:
@@ -3047,11 +3233,12 @@
 		if (!chip->ecc.size)
 			chip->ecc.size = 256;
 		chip->ecc.bytes = 3;
+		chip->ecc.strength = 1;
 		break;
 
 	case NAND_ECC_SOFT_BCH:
 		if (!mtd_nand_has_bch()) {
-			printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
+			pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
 			return -EINVAL;
 		}
 		chip->ecc.calculate = nand_bch_calculate_ecc;
@@ -3066,8 +3253,8 @@
 		/*
 		 * Board driver should supply ecc.size and ecc.bytes values to
 		 * select how many bits are correctable; see nand_bch_init()
-		 * for details.
-		 * Otherwise, default to 4 bits for large page devices
+		 * for details. Otherwise, default to 4 bits for large page
+		 * devices.
 		 */
 		if (!chip->ecc.size && (mtd->oobsize >= 64)) {
 			chip->ecc.size = 512;
@@ -3078,13 +3265,14 @@
 					       chip->ecc.bytes,
 					       &chip->ecc.layout);
 		if (!chip->ecc.priv)
-			printk(KERN_WARNING "BCH ECC initialization failed!\n");
-
+			pr_warn("BCH ECC initialization failed!\n");
+ 		chip->ecc.strength =
+			chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
 		break;
 
 	case NAND_ECC_NONE:
-		printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
-		       "This is not recommended !!\n");
+		pr_warn("NAND_ECC_NONE selected by board driver. "
+		        "This is not recommended !!\n");
 		chip->ecc.read_page = nand_read_page_raw;
 		chip->ecc.write_page = nand_write_page_raw;
 		chip->ecc.read_oob = nand_read_oob_std;
@@ -3096,14 +3284,19 @@
 		break;
 
 	default:
-		printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
-		       chip->ecc.mode);
+		pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
 		BUG();
 	}
 
+	/* For many systems, the standard OOB write also works for raw */
+	if (!chip->ecc.read_oob_raw)
+		chip->ecc.read_oob_raw = chip->ecc.read_oob;
+	if (!chip->ecc.write_oob_raw)
+		chip->ecc.write_oob_raw = chip->ecc.write_oob;
+
 	/*
 	 * The number of bytes available for a client to place data into
-	 * the out of band area
+	 * the out of band area.
 	 */
 	chip->ecc.layout->oobavail = 0;
 	for (i = 0; chip->ecc.layout->oobfree[i].length
@@ -3114,19 +3307,16 @@
 
 	/*
 	 * Set the number of read / write steps for one page depending on ECC
-	 * mode
+	 * mode.
 	 */
 	chip->ecc.steps = mtd->writesize / chip->ecc.size;
 	if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
-		printk(KERN_WARNING "Invalid ecc parameters\n");
+		pr_warn("Invalid ECC parameters\n");
 		BUG();
 	}
 	chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
 
-	/*
-	 * Allow subpage writes up to ecc.steps. Not possible for MLC
-	 * FLASH.
-	 */
+	/* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
 	if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
 	    !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
 		switch (chip->ecc.steps) {
@@ -3159,21 +3349,29 @@
 	mtd->type = MTD_NANDFLASH;
 	mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
 						MTD_CAP_NANDFLASH;
-	mtd->erase = nand_erase;
-	mtd->point = NULL;
-	mtd->unpoint = NULL;
-	mtd->read = nand_read;
-	mtd->write = nand_write;
-	mtd->read_oob = nand_read_oob;
-	mtd->write_oob = nand_write_oob;
-	mtd->sync = nand_sync;
-	mtd->lock = NULL;
-	mtd->unlock = NULL;
-	mtd->block_isbad = nand_block_isbad;
-	mtd->block_markbad = nand_block_markbad;
+	mtd->_erase = nand_erase;
+	mtd->_point = NULL;
+	mtd->_unpoint = NULL;
+	mtd->_read = nand_read;
+	mtd->_write = nand_write;
+	mtd->_read_oob = nand_read_oob;
+	mtd->_write_oob = nand_write_oob;
+	mtd->_sync = nand_sync;
+	mtd->_lock = NULL;
+	mtd->_unlock = NULL;
+	mtd->_block_isbad = nand_block_isbad;
+	mtd->_block_markbad = nand_block_markbad;
 
-	/* propagate ecc.layout to mtd_info */
+	/* propagate ecc info to mtd_info */
 	mtd->ecclayout = chip->ecc.layout;
+	mtd->ecc_strength = chip->ecc.strength;
+	/*
+	 * Initialize bitflip_threshold to its default prior scan_bbt() call.
+	 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
+	 * properly set.
+	 */
+	if (!mtd->bitflip_threshold)
+		mtd->bitflip_threshold = mtd->ecc_strength;
 
 	/* Check, if we should skip the bad block table scan */
 	if (chip->options & NAND_SKIP_BBTSCAN)
@@ -3184,15 +3382,13 @@
 
 /**
  * nand_scan - [NAND Interface] Scan for the NAND device
- * @mtd:	MTD device structure
- * @maxchips:	Number of chips to scan for
+ * @mtd: MTD device structure
+ * @maxchips: number of chips to scan for
  *
- * This fills out all the uninitialized function pointers
- * with the defaults.
- * The flash ID is read and the mtd/chip structures are
- * filled with the appropriate values.
- * The mtd->owner field must be set to the module of the caller
- *
+ * This fills out all the uninitialized function pointers with the defaults.
+ * The flash ID is read and the mtd/chip structures are filled with the
+ * appropriate values. The mtd->owner field must be set to the module of the
+ * caller.
  */
 int nand_scan(struct mtd_info *mtd, int maxchips)
 {
@@ -3206,8 +3402,8 @@
 
 /**
  * nand_release - [NAND Interface] Free resources held by the NAND device
- * @mtd:	MTD device structure
-*/
+ * @mtd: MTD device structure
+ */
 void nand_release(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 74a7061..8ef5845 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -4,7 +4,7 @@
  *  Overview:
  *   Bad block table support for the NAND driver
  *
- *  Copyright (C) 2004 Thomas Gleixner (tglx@linutronix.de)
+ *  Copyright © 2004 Thomas Gleixner (tglx@linutronix.de)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -14,7 +14,7 @@
  *
  * When nand_scan_bbt is called, then it tries to find the bad block table
  * depending on the options in the BBT descriptor(s). If no flash based BBT
- * (NAND_USE_FLASH_BBT) is specified then the device is scanned for factory
+ * (NAND_BBT_USE_FLASH) is specified then the device is scanned for factory
  * marked good / bad blocks. This information is used to create a memory BBT.
  * Once a new bad block is discovered then the "factory" information is updated
  * on the device.
@@ -22,7 +22,7 @@
  * BBT on flash. If a BBT is found then the contents are read and the memory
  * based BBT is created. If a mirrored BBT is selected then the mirror is
  * searched too and the versions are compared. If the mirror has a greater
- * version number than the mirror BBT is used to build the memory based BBT.
+ * version number, then the mirror BBT is used to build the memory based BBT.
  * If the tables are not versioned, then we "or" the bad block information.
  * If one of the BBTs is out of date or does not exist it is (re)created.
  * If no BBT exists at all then the device is scanned for factory marked
@@ -36,9 +36,9 @@
  * The table is marked in the OOB area with an ident pattern and a version
  * number which indicates which of both tables is more up to date. If the NAND
  * controller needs the complete OOB area for the ECC information then the
- * option NAND_USE_FLASH_BBT_NO_OOB should be used: it moves the ident pattern
- * and the version byte into the data area and the OOB area will remain
- * untouched.
+ * option NAND_BBT_NO_OOB should be used (along with NAND_BBT_USE_FLASH, of
+ * course): it moves the ident pattern and the version byte into the data area
+ * and the OOB area will remain untouched.
  *
  * The table uses 2 bits per block
  * 11b:		block is good
@@ -63,126 +63,81 @@
 #include <malloc.h>
 #include <linux/compat.h>
 #include <linux/mtd/mtd.h>
+#include <linux/mtd/bbm.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/bitops.h>
+#include <linux/string.h>
 
 #include <asm/errno.h>
 
 static int check_pattern_no_oob(uint8_t *buf, struct nand_bbt_descr *td)
 {
-	int ret;
-
-	ret = memcmp(buf, td->pattern, td->len);
-	if (!ret)
-		return ret;
-	return -1;
+	if (memcmp(buf, td->pattern, td->len))
+		return -1;
+	return 0;
 }
 
 /**
  * check_pattern - [GENERIC] check if a pattern is in the buffer
- * @buf:	the buffer to search
- * @len:	the length of buffer to search
- * @paglen:	the pagelength
- * @td:		search pattern descriptor
+ * @buf: the buffer to search
+ * @len: the length of buffer to search
+ * @paglen: the pagelength
+ * @td: search pattern descriptor
  *
- * Check for a pattern at the given place. Used to search bad block
- * tables and good / bad block identifiers.
- * If the SCAN_EMPTY option is set then check, if all bytes except the
- * pattern area contain 0xff
- *
-*/
+ * Check for a pattern at the given place. Used to search bad block tables and
+ * good / bad block identifiers. If the SCAN_EMPTY option is set then check, if
+ * all bytes except the pattern area contain 0xff.
+ */
 static int check_pattern(uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td)
 {
-	int i, end = 0;
+	int end = 0;
 	uint8_t *p = buf;
 
 	if (td->options & NAND_BBT_NO_OOB)
 		return check_pattern_no_oob(buf, td);
 
 	end = paglen + td->offs;
-	if (td->options & NAND_BBT_SCANEMPTY) {
-		for (i = 0; i < end; i++) {
-			if (p[i] != 0xff)
-				return -1;
-		}
-	}
+	if (td->options & NAND_BBT_SCANEMPTY)
+		if (memchr_inv(p, 0xff, end))
+			return -1;
 	p += end;
 
 	/* Compare the pattern */
-	for (i = 0; i < td->len; i++) {
-		if (p[i] != td->pattern[i])
-			return -1;
-	}
-
-	/* Check both positions 1 and 6 for pattern? */
-	if (td->options & NAND_BBT_SCANBYTE1AND6) {
-		if (td->options & NAND_BBT_SCANEMPTY) {
-			p += td->len;
-			end += NAND_SMALL_BADBLOCK_POS - td->offs;
-			/* Check region between positions 1 and 6 */
-			for (i = 0; i < NAND_SMALL_BADBLOCK_POS - td->offs - td->len;
-					i++) {
-				if (*p++ != 0xff)
-					return -1;
-			}
-		}
-		else {
-			p += NAND_SMALL_BADBLOCK_POS - td->offs;
-		}
-		/* Compare the pattern */
-		for (i = 0; i < td->len; i++) {
-			if (p[i] != td->pattern[i])
-				return -1;
-		}
-	}
+	if (memcmp(p, td->pattern, td->len))
+		return -1;
 
 	if (td->options & NAND_BBT_SCANEMPTY) {
 		p += td->len;
 		end += td->len;
-		for (i = end; i < len; i++) {
-			if (*p++ != 0xff)
-				return -1;
-		}
+		if (memchr_inv(p, 0xff, len - end))
+			return -1;
 	}
 	return 0;
 }
 
 /**
  * check_short_pattern - [GENERIC] check if a pattern is in the buffer
- * @buf:	the buffer to search
- * @td:		search pattern descriptor
+ * @buf: the buffer to search
+ * @td:	search pattern descriptor
  *
- * Check for a pattern at the given place. Used to search bad block
- * tables and good / bad block identifiers. Same as check_pattern, but
- * no optional empty check
- *
-*/
+ * Check for a pattern at the given place. Used to search bad block tables and
+ * good / bad block identifiers. Same as check_pattern, but no optional empty
+ * check.
+ */
 static int check_short_pattern(uint8_t *buf, struct nand_bbt_descr *td)
 {
-	int i;
-	uint8_t *p = buf;
-
 	/* Compare the pattern */
-	for (i = 0; i < td->len; i++) {
-		if (p[td->offs + i] != td->pattern[i])
-			return -1;
-	}
-	/* Need to check location 1 AND 6? */
-	if (td->options & NAND_BBT_SCANBYTE1AND6) {
-		for (i = 0; i < td->len; i++) {
-			if (p[NAND_SMALL_BADBLOCK_POS + i] != td->pattern[i])
-				return -1;
-		}
-	}
+	if (memcmp(buf + td->offs, td->pattern, td->len))
+		return -1;
 	return 0;
 }
 
 /**
  * add_marker_len - compute the length of the marker in data area
- * @td:		BBT descriptor used for computation
+ * @td: BBT descriptor used for computation
  *
- * The length will be 0 if the markeris located in OOB area.
+ * The length will be 0 if the marker is located in OOB area.
  */
 static u32 add_marker_len(struct nand_bbt_descr *td)
 {
@@ -199,34 +154,33 @@
 
 /**
  * read_bbt - [GENERIC] Read the bad block table starting from page
- * @mtd:	MTD device structure
- * @buf:	temporary buffer
- * @page:	the starting page
- * @num:	the number of bbt descriptors to read
- * @td:		the bbt describtion table
- * @offs:	offset in the memory table
+ * @mtd: MTD device structure
+ * @buf: temporary buffer
+ * @page: the starting page
+ * @num: the number of bbt descriptors to read
+ * @td: the bbt describtion table
+ * @offs: offset in the memory table
  *
  * Read the bad block table starting from page.
- *
  */
 static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num,
 		struct nand_bbt_descr *td, int offs)
 {
-	int res, i, j, act = 0;
+	int res, ret = 0, i, j, act = 0;
 	struct nand_chip *this = mtd->priv;
 	size_t retlen, len, totlen;
 	loff_t from;
 	int bits = td->options & NAND_BBT_NRBITS_MSK;
-	uint8_t msk = (uint8_t) ((1 << bits) - 1);
+	uint8_t msk = (uint8_t)((1 << bits) - 1);
 	u32 marker_len;
 	int reserved_block_code = td->reserved_block_code;
 
 	totlen = (num * bits) >> 3;
 	marker_len = add_marker_len(td);
-	from = ((loff_t) page) << this->page_shift;
+	from = ((loff_t)page) << this->page_shift;
 
 	while (totlen) {
-		len = min(totlen, (size_t) (1 << this->bbt_erase_shift));
+		len = min(totlen, (size_t)(1 << this->bbt_erase_shift));
 		if (marker_len) {
 			/*
 			 * In case the BBT marker is not in the OOB area it
@@ -236,13 +190,20 @@
 			from += marker_len;
 			marker_len = 0;
 		}
-		res = mtd->read(mtd, from, len, &retlen, buf);
+		res = mtd_read(mtd, from, len, &retlen, buf);
 		if (res < 0) {
-			if (retlen != len) {
-				printk(KERN_INFO "nand_bbt: Error reading bad block table\n");
+			if (mtd_is_eccerr(res)) {
+				pr_info("nand_bbt: ECC error in BBT at "
+					"0x%012llx\n", from & ~mtd->writesize);
+				return res;
+			} else if (mtd_is_bitflip(res)) {
+				pr_info("nand_bbt: corrected error in BBT at "
+					"0x%012llx\n", from & ~mtd->writesize);
+				ret = res;
+			} else {
+				pr_info("nand_bbt: error reading BBT\n");
 				return res;
 			}
-			printk(KERN_WARNING "nand_bbt: ECC error while reading bad block table\n");
 		}
 
 		/* Analyse data */
@@ -253,17 +214,16 @@
 				if (tmp == msk)
 					continue;
 				if (reserved_block_code && (tmp == reserved_block_code)) {
-					printk(KERN_DEBUG "nand_read_bbt: Reserved block at 0x%012llx\n",
-					       (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
+					pr_info("nand_read_bbt: reserved block at 0x%012llx\n",
+						 (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
 					this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06);
 					mtd->ecc_stats.bbtblocks++;
 					continue;
 				}
-				MTDDEBUG(MTD_DEBUG_LEVEL0, "nand_read_bbt: " \
-					"Bad block at 0x%012llx\n",
+				pr_info("nand_read_bbt: Bad block at 0x%012llx\n",
 					(loff_t)((offs << 2) + (act >> 1))
 					<< this->bbt_erase_shift);
-				/* Factory marked bad or worn out ? */
+				/* Factory marked bad or worn out? */
 				if (tmp == 0)
 					this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06);
 				else
@@ -274,20 +234,20 @@
 		totlen -= len;
 		from += len;
 	}
-	return 0;
+	return ret;
 }
 
 /**
  * read_abs_bbt - [GENERIC] Read the bad block table starting at a given page
- * @mtd:	MTD device structure
- * @buf:	temporary buffer
- * @td:		descriptor for the bad block table
- * @chip:	read the table for a specific chip, -1 read all chips.
- *		Applies only if NAND_BBT_PERCHIP option is set
+ * @mtd: MTD device structure
+ * @buf: temporary buffer
+ * @td: descriptor for the bad block table
+ * @chip: read the table for a specific chip, -1 read all chips; applies only if
+ *        NAND_BBT_PERCHIP option is set
  *
- * Read the bad block table for all chips starting at a given page
- * We assume that the bbt bits are in consecutive order.
-*/
+ * Read the bad block table for all chips starting at a given page. We assume
+ * that the bbt bits are in consecutive order.
+ */
 static int read_abs_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, int chip)
 {
 	struct nand_chip *this = mtd->priv;
@@ -313,10 +273,8 @@
 	return 0;
 }
 
-/*
- * BBT marker is in the first page, no OOB.
- */
-static int scan_read_raw_data(struct mtd_info *mtd, uint8_t *buf, loff_t offs,
+/* BBT marker is in the first page, no OOB */
+static int scan_read_data(struct mtd_info *mtd, uint8_t *buf, loff_t offs,
 			 struct nand_bbt_descr *td)
 {
 	size_t retlen;
@@ -326,70 +284,73 @@
 	if (td->options & NAND_BBT_VERSION)
 		len++;
 
-	return mtd->read(mtd, offs, len, &retlen, buf);
+	return mtd_read(mtd, offs, len, &retlen, buf);
 }
 
-/*
- * Scan read raw data from flash
+/**
+ * scan_read_oob - [GENERIC] Scan data+OOB region to buffer
+ * @mtd: MTD device structure
+ * @buf: temporary buffer
+ * @offs: offset at which to scan
+ * @len: length of data region to read
+ *
+ * Scan read data from data+OOB. May traverse multiple pages, interleaving
+ * page,OOB,page,OOB,... in buf. Completes transfer and returns the "strongest"
+ * ECC condition (error or bitflip). May quit on the first (non-ECC) error.
  */
-static int scan_read_raw_oob(struct mtd_info *mtd, uint8_t *buf, loff_t offs,
+static int scan_read_oob(struct mtd_info *mtd, uint8_t *buf, loff_t offs,
 			 size_t len)
 {
 	struct mtd_oob_ops ops;
-	int res;
+	int res, ret = 0;
 
-	ops.mode = MTD_OOB_RAW;
+	ops.mode = MTD_OPS_PLACE_OOB;
 	ops.ooboffs = 0;
 	ops.ooblen = mtd->oobsize;
 
-
 	while (len > 0) {
-		if (len <= mtd->writesize) {
-			ops.oobbuf = buf + len;
-			ops.datbuf = buf;
-			ops.len = len;
-			return mtd->read_oob(mtd, offs, &ops);
-		} else {
-			ops.oobbuf = buf + mtd->writesize;
-			ops.datbuf = buf;
-			ops.len = mtd->writesize;
-			res = mtd->read_oob(mtd, offs, &ops);
+		ops.datbuf = buf;
+		ops.len = min(len, (size_t)mtd->writesize);
+		ops.oobbuf = buf + ops.len;
 
-			if (res)
+		res = mtd_read_oob(mtd, offs, &ops);
+		if (res) {
+			if (!mtd_is_bitflip_or_eccerr(res))
 				return res;
+			else if (mtd_is_eccerr(res) || !ret)
+				ret = res;
 		}
 
 		buf += mtd->oobsize + mtd->writesize;
 		len -= mtd->writesize;
+		offs += mtd->writesize;
 	}
-	return 0;
+	return ret;
 }
 
-static int scan_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t offs,
+static int scan_read(struct mtd_info *mtd, uint8_t *buf, loff_t offs,
 			 size_t len, struct nand_bbt_descr *td)
 {
 	if (td->options & NAND_BBT_NO_OOB)
-		return scan_read_raw_data(mtd, buf, offs, td);
+		return scan_read_data(mtd, buf, offs, td);
 	else
-		return scan_read_raw_oob(mtd, buf, offs, len);
+		return scan_read_oob(mtd, buf, offs, len);
 }
 
-/*
- * Scan write data with oob to flash
- */
+/* Scan write data with oob to flash */
 static int scan_write_bbt(struct mtd_info *mtd, loff_t offs, size_t len,
 			  uint8_t *buf, uint8_t *oob)
 {
 	struct mtd_oob_ops ops;
 
-	ops.mode = MTD_OOB_PLACE;
+	ops.mode = MTD_OPS_PLACE_OOB;
 	ops.ooboffs = 0;
 	ops.ooblen = mtd->oobsize;
 	ops.datbuf = buf;
 	ops.oobbuf = oob;
 	ops.len = len;
 
-	return mtd->write_oob(mtd, offs, &ops);
+	return mtd_write_oob(mtd, offs, &ops);
 }
 
 static u32 bbt_get_ver_offs(struct mtd_info *mtd, struct nand_bbt_descr *td)
@@ -403,65 +364,60 @@
 
 /**
  * read_abs_bbts - [GENERIC] Read the bad block table(s) for all chips starting at a given page
- * @mtd:	MTD device structure
- * @buf:	temporary buffer
- * @td:		descriptor for the bad block table
- * @md:		descriptor for the bad block table mirror
+ * @mtd: MTD device structure
+ * @buf: temporary buffer
+ * @td: descriptor for the bad block table
+ * @md:	descriptor for the bad block table mirror
  *
- * Read the bad block table(s) for all chips starting at a given page
- * We assume that the bbt bits are in consecutive order.
- *
-*/
-static int read_abs_bbts(struct mtd_info *mtd, uint8_t *buf,
-			 struct nand_bbt_descr *td, struct nand_bbt_descr *md)
+ * Read the bad block table(s) for all chips starting at a given page. We
+ * assume that the bbt bits are in consecutive order.
+ */
+static void read_abs_bbts(struct mtd_info *mtd, uint8_t *buf,
+			  struct nand_bbt_descr *td, struct nand_bbt_descr *md)
 {
 	struct nand_chip *this = mtd->priv;
 
 	/* Read the primary version, if available */
 	if (td->options & NAND_BBT_VERSION) {
-		scan_read_raw(mtd, buf, (loff_t)td->pages[0] << this->page_shift,
+		scan_read(mtd, buf, (loff_t)td->pages[0] << this->page_shift,
 			      mtd->writesize, td);
 		td->version[0] = buf[bbt_get_ver_offs(mtd, td)];
-		printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n",
-		       td->pages[0], td->version[0]);
+		pr_info("Bad block table at page %d, version 0x%02X\n",
+			 td->pages[0], td->version[0]);
 	}
 
 	/* Read the mirror version, if available */
 	if (md && (md->options & NAND_BBT_VERSION)) {
-		scan_read_raw(mtd, buf, (loff_t)md->pages[0] << this->page_shift,
-			      mtd->writesize, td);
+		scan_read(mtd, buf, (loff_t)md->pages[0] << this->page_shift,
+			      mtd->writesize, md);
 		md->version[0] = buf[bbt_get_ver_offs(mtd, md)];
-		printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n",
-		       md->pages[0], md->version[0]);
+		pr_info("Bad block table at page %d, version 0x%02X\n",
+			 md->pages[0], md->version[0]);
 	}
-	return 1;
 }
 
-/*
- * Scan a given block full
- */
+/* Scan a given block full */
 static int scan_block_full(struct mtd_info *mtd, struct nand_bbt_descr *bd,
 			   loff_t offs, uint8_t *buf, size_t readlen,
-			   int scanlen, int len)
+			   int scanlen, int numpages)
 {
 	int ret, j;
 
-	ret = scan_read_raw_oob(mtd, buf, offs, readlen);
-	if (ret)
+	ret = scan_read_oob(mtd, buf, offs, readlen);
+	/* Ignore ECC errors when checking for BBM */
+	if (ret && !mtd_is_bitflip_or_eccerr(ret))
 		return ret;
 
-	for (j = 0; j < len; j++, buf += scanlen) {
+	for (j = 0; j < numpages; j++, buf += scanlen) {
 		if (check_pattern(buf, scanlen, mtd->writesize, bd))
 			return 1;
 	}
 	return 0;
 }
 
-/*
- * Scan a given block partially
- */
+/* Scan a given block partially */
 static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd,
-			   loff_t offs, uint8_t *buf, int len)
+			   loff_t offs, uint8_t *buf, int numpages)
 {
 	struct mtd_oob_ops ops;
 	int j, ret;
@@ -470,16 +426,16 @@
 	ops.oobbuf = buf;
 	ops.ooboffs = 0;
 	ops.datbuf = NULL;
-	ops.mode = MTD_OOB_PLACE;
+	ops.mode = MTD_OPS_PLACE_OOB;
 
-	for (j = 0; j < len; j++) {
+	for (j = 0; j < numpages; j++) {
 		/*
-		 * Read the full oob until read_oob is fixed to
-		 * handle single byte reads for 16 bit
-		 * buswidth
+		 * Read the full oob until read_oob is fixed to handle single
+		 * byte reads for 16 bit buswidth.
 		 */
-		ret = mtd->read_oob(mtd, offs, &ops);
-		if (ret)
+		ret = mtd_read_oob(mtd, offs, &ops);
+		/* Ignore ECC errors when checking for BBM */
+		if (ret && !mtd_is_bitflip_or_eccerr(ret))
 			return ret;
 
 		if (check_short_pattern(buf, bd))
@@ -492,32 +448,32 @@
 
 /**
  * create_bbt - [GENERIC] Create a bad block table by scanning the device
- * @mtd:	MTD device structure
- * @buf:	temporary buffer
- * @bd:		descriptor for the good/bad block search pattern
- * @chip:	create the table for a specific chip, -1 read all chips.
- *		Applies only if NAND_BBT_PERCHIP option is set
+ * @mtd: MTD device structure
+ * @buf: temporary buffer
+ * @bd: descriptor for the good/bad block search pattern
+ * @chip: create the table for a specific chip, -1 read all chips; applies only
+ *        if NAND_BBT_PERCHIP option is set
  *
- * Create a bad block table by scanning the device
- * for the given good/bad block identify pattern
+ * Create a bad block table by scanning the device for the given good/bad block
+ * identify pattern.
  */
 static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
 	struct nand_bbt_descr *bd, int chip)
 {
 	struct nand_chip *this = mtd->priv;
-	int i, numblocks, len, scanlen;
+	int i, numblocks, numpages, scanlen;
 	int startblock;
 	loff_t from;
 	size_t readlen;
 
-	MTDDEBUG(MTD_DEBUG_LEVEL0, "Scanning device for bad blocks\n");
+	pr_info("Scanning device for bad blocks\n");
 
 	if (bd->options & NAND_BBT_SCANALLPAGES)
-		len = 1 << (this->bbt_erase_shift - this->page_shift);
+		numpages = 1 << (this->bbt_erase_shift - this->page_shift);
 	else if (bd->options & NAND_BBT_SCAN2NDPAGE)
-		len = 2;
+		numpages = 2;
 	else
-		len = 1;
+		numpages = 1;
 
 	if (!(bd->options & NAND_BBT_SCANEMPTY)) {
 		/* We need only read few bytes from the OOB area */
@@ -526,18 +482,20 @@
 	} else {
 		/* Full page content should be read */
 		scanlen = mtd->writesize + mtd->oobsize;
-		readlen = len * mtd->writesize;
+		readlen = numpages * mtd->writesize;
 	}
 
 	if (chip == -1) {
-		/* Note that numblocks is 2 * (real numblocks) here, see i+=2
-		 * below as it makes shifting and masking less painful */
+		/*
+		 * Note that numblocks is 2 * (real numblocks) here, see i+=2
+		 * below as it makes shifting and masking less painful
+		 */
 		numblocks = mtd->size >> (this->bbt_erase_shift - 1);
 		startblock = 0;
 		from = 0;
 	} else {
 		if (chip >= this->numchips) {
-			printk(KERN_WARNING "create_bbt(): chipnr (%d) > available chips (%d)\n",
+			pr_warn("create_bbt(): chipnr (%d) > available chips (%d)\n",
 			       chip + 1, this->numchips);
 			return -EINVAL;
 		}
@@ -547,8 +505,8 @@
 		from = (loff_t)startblock << (this->bbt_erase_shift - 1);
 	}
 
-	if (this->options & NAND_BBT_SCANLASTPAGE)
-		from += mtd->erasesize - (mtd->writesize * len);
+	if (this->bbt_options & NAND_BBT_SCANLASTPAGE)
+		from += mtd->erasesize - (mtd->writesize * numpages);
 
 	for (i = startblock; i < numblocks;) {
 		int ret;
@@ -557,17 +515,16 @@
 
 		if (bd->options & NAND_BBT_SCANALLPAGES)
 			ret = scan_block_full(mtd, bd, from, buf, readlen,
-					      scanlen, len);
+					      scanlen, numpages);
 		else
-			ret = scan_block_fast(mtd, bd, from, buf, len);
+			ret = scan_block_fast(mtd, bd, from, buf, numpages);
 
 		if (ret < 0)
 			return ret;
 
 		if (ret) {
 			this->bbt[i >> 3] |= 0x03 << (i & 0x6);
-			MTDDEBUG(MTD_DEBUG_LEVEL0,
-				  "Bad eraseblock %d at 0x%012llx\n",
+			pr_warn("Bad eraseblock %d at 0x%012llx\n",
 				  i >> 1, (unsigned long long)from);
 			mtd->ecc_stats.badblocks++;
 		}
@@ -580,20 +537,18 @@
 
 /**
  * search_bbt - [GENERIC] scan the device for a specific bad block table
- * @mtd:	MTD device structure
- * @buf:	temporary buffer
- * @td:		descriptor for the bad block table
+ * @mtd: MTD device structure
+ * @buf: temporary buffer
+ * @td: descriptor for the bad block table
  *
- * Read the bad block table by searching for a given ident pattern.
- * Search is preformed either from the beginning up or from the end of
- * the device downwards. The search starts always at the start of a
- * block.
- * If the option NAND_BBT_PERCHIP is given, each chip is searched
- * for a bbt, which contains the bad block information of this chip.
- * This is necessary to provide support for certain DOC devices.
+ * Read the bad block table by searching for a given ident pattern. Search is
+ * preformed either from the beginning up or from the end of the device
+ * downwards. The search starts always at the start of a block. If the option
+ * NAND_BBT_PERCHIP is given, each chip is searched for a bbt, which contains
+ * the bad block information of this chip. This is necessary to provide support
+ * for certain DOC devices.
  *
- * The bbt ident pattern resides in the oob area of the first page
- * in a block.
+ * The bbt ident pattern resides in the oob area of the first page in a block.
  */
 static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td)
 {
@@ -604,7 +559,7 @@
 	int bbtblocks;
 	int blocktopage = this->bbt_erase_shift - this->page_shift;
 
-	/* Search direction top -> down ? */
+	/* Search direction top -> down? */
 	if (td->options & NAND_BBT_LASTBLOCK) {
 		startblock = (mtd->size >> this->bbt_erase_shift) - 1;
 		dir = -1;
@@ -613,7 +568,7 @@
 		dir = 1;
 	}
 
-	/* Do we have a bbt per chip ? */
+	/* Do we have a bbt per chip? */
 	if (td->options & NAND_BBT_PERCHIP) {
 		chips = this->numchips;
 		bbtblocks = this->chipsize >> this->bbt_erase_shift;
@@ -634,7 +589,7 @@
 			loff_t offs = (loff_t)actblock << this->bbt_erase_shift;
 
 			/* Read first page */
-			scan_read_raw(mtd, buf, offs, mtd->writesize, td);
+			scan_read(mtd, buf, offs, mtd->writesize, td);
 			if (!check_pattern(buf, scanlen, mtd->writesize, td)) {
 				td->pages[i] = actblock << blocktopage;
 				if (td->options & NAND_BBT_VERSION) {
@@ -649,10 +604,9 @@
 	/* Check, if we found a bbt for each requested chip */
 	for (i = 0; i < chips; i++) {
 		if (td->pages[i] == -1)
-			printk(KERN_WARNING "Bad block table not found for chip %d\n", i);
+			pr_warn("Bad block table not found for chip %d\n", i);
 		else
-			MTDDEBUG(MTD_DEBUG_LEVEL0, "Bad block table found " \
-				"at page %d, version 0x%02X\n", td->pages[i],
+			pr_info("Bad block table found at page %d, version 0x%02X\n", td->pages[i],
 				td->version[i]);
 	}
 	return 0;
@@ -660,14 +614,16 @@
 
 /**
  * search_read_bbts - [GENERIC] scan the device for bad block table(s)
- * @mtd:	MTD device structure
- * @buf:	temporary buffer
- * @td:		descriptor for the bad block table
- * @md:		descriptor for the bad block table mirror
+ * @mtd: MTD device structure
+ * @buf: temporary buffer
+ * @td: descriptor for the bad block table
+ * @md: descriptor for the bad block table mirror
  *
- * Search and read the bad block table(s)
-*/
-static int search_read_bbts(struct mtd_info *mtd, uint8_t * buf, struct nand_bbt_descr *td, struct nand_bbt_descr *md)
+ * Search and read the bad block table(s).
+ */
+static void search_read_bbts(struct mtd_info *mtd, uint8_t *buf,
+			     struct nand_bbt_descr *td,
+			     struct nand_bbt_descr *md)
 {
 	/* Search the primary table */
 	search_bbt(mtd, buf, td);
@@ -675,23 +631,18 @@
 	/* Search the mirror table */
 	if (md)
 		search_bbt(mtd, buf, md);
-
-	/* Force result check */
-	return 1;
 }
 
 /**
  * write_bbt - [GENERIC] (Re)write the bad block table
+ * @mtd: MTD device structure
+ * @buf: temporary buffer
+ * @td: descriptor for the bad block table
+ * @md: descriptor for the bad block table mirror
+ * @chipsel: selector for a specific chip, -1 for all
  *
- * @mtd:	MTD device structure
- * @buf:	temporary buffer
- * @td:		descriptor for the bad block table
- * @md:		descriptor for the bad block table mirror
- * @chipsel:	selector for a specific chip, -1 for all
- *
- * (Re)write the bad block table
- *
-*/
+ * (Re)write the bad block table.
+ */
 static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 		     struct nand_bbt_descr *td, struct nand_bbt_descr *md,
 		     int chipsel)
@@ -710,14 +661,14 @@
 	ops.ooblen = mtd->oobsize;
 	ops.ooboffs = 0;
 	ops.datbuf = NULL;
-	ops.mode = MTD_OOB_PLACE;
+	ops.mode = MTD_OPS_PLACE_OOB;
 
 	if (!rcode)
 		rcode = 0xff;
-	/* Write bad block table per chip rather than per device ? */
+	/* Write bad block table per chip rather than per device? */
 	if (td->options & NAND_BBT_PERCHIP) {
 		numblocks = (int)(this->chipsize >> this->bbt_erase_shift);
-		/* Full device write or specific chip ? */
+		/* Full device write or specific chip? */
 		if (chipsel == -1) {
 			nrchips = this->numchips;
 		} else {
@@ -731,8 +682,8 @@
 
 	/* Loop through the chips */
 	for (; chip < nrchips; chip++) {
-
-		/* There was already a version of the table, reuse the page
+		/*
+		 * There was already a version of the table, reuse the page
 		 * This applies for absolute placement too, as we have the
 		 * page nr. in td->pages.
 		 */
@@ -741,8 +692,10 @@
 			goto write;
 		}
 
-		/* Automatic placement of the bad block table */
-		/* Search direction top -> down ? */
+		/*
+		 * Automatic placement of the bad block table. Search direction
+		 * top -> down?
+		 */
 		if (td->options & NAND_BBT_LASTBLOCK) {
 			startblock = numblocks * (chip + 1) - 1;
 			dir = -1;
@@ -766,7 +719,7 @@
 			if (!md || md->pages[chip] != page)
 				goto write;
 		}
-		printk(KERN_ERR "No space left to write bad block table\n");
+		pr_err("No space left to write bad block table\n");
 		return -ENOSPC;
 	write:
 
@@ -791,29 +744,27 @@
 
 		bbtoffs = chip * (numblocks >> 2);
 
-		to = ((loff_t) page) << this->page_shift;
+		to = ((loff_t)page) << this->page_shift;
 
-		/* Must we save the block contents ? */
+		/* Must we save the block contents? */
 		if (td->options & NAND_BBT_SAVECONTENT) {
 			/* Make it block aligned */
-			to &= ~((loff_t) ((1 << this->bbt_erase_shift) - 1));
+			to &= ~((loff_t)((1 << this->bbt_erase_shift) - 1));
 			len = 1 << this->bbt_erase_shift;
-			res = mtd->read(mtd, to, len, &retlen, buf);
+			res = mtd_read(mtd, to, len, &retlen, buf);
 			if (res < 0) {
 				if (retlen != len) {
-					printk(KERN_INFO "nand_bbt: Error "
-					       "reading block for writing "
-					       "the bad block table\n");
+					pr_info("nand_bbt: error reading block "
+						"for writing the bad block table\n");
 					return res;
 				}
-				printk(KERN_WARNING "nand_bbt: ECC error "
-				       "while reading block for writing "
-				       "bad block table\n");
+				pr_warn("nand_bbt: ECC error while reading "
+					"block for writing bad block table\n");
 			}
 			/* Read oob data */
 			ops.ooblen = (len >> this->page_shift) * mtd->oobsize;
 			ops.oobbuf = &buf[len];
-			res = mtd->read_oob(mtd, to + mtd->writesize, &ops);
+			res = mtd_read_oob(mtd, to + mtd->writesize, &ops);
 			if (res < 0 || ops.oobretlen != ops.ooblen)
 				goto outerr;
 
@@ -821,19 +772,19 @@
 			pageoffs = page - (int)(to >> this->page_shift);
 			offs = pageoffs << this->page_shift;
 			/* Preset the bbt area with 0xff */
-			memset(&buf[offs], 0xff, (size_t) (numblocks >> sft));
+			memset(&buf[offs], 0xff, (size_t)(numblocks >> sft));
 			ooboffs = len + (pageoffs * mtd->oobsize);
 
 		} else if (td->options & NAND_BBT_NO_OOB) {
 			ooboffs = 0;
 			offs = td->len;
-			/* the version byte */
+			/* The version byte */
 			if (td->options & NAND_BBT_VERSION)
 				offs++;
 			/* Calc length */
-			len = (size_t) (numblocks >> sft);
+			len = (size_t)(numblocks >> sft);
 			len += offs;
-			/* Make it page aligned ! */
+			/* Make it page aligned! */
 			len = ALIGN(len, mtd->writesize);
 			/* Preset the buffer with 0xff */
 			memset(buf, 0xff, len);
@@ -841,8 +792,8 @@
 			memcpy(buf, td->pattern, td->len);
 		} else {
 			/* Calc length */
-			len = (size_t) (numblocks >> sft);
-			/* Make it page aligned ! */
+			len = (size_t)(numblocks >> sft);
+			/* Make it page aligned! */
 			len = ALIGN(len, mtd->writesize);
 			/* Preset the buffer with 0xff */
 			memset(buf, 0xff, len +
@@ -856,13 +807,13 @@
 		if (td->options & NAND_BBT_VERSION)
 			buf[ooboffs + td->veroffs] = td->version[chip];
 
-		/* walk through the memory table */
+		/* Walk through the memory table */
 		for (i = 0; i < numblocks;) {
 			uint8_t dat;
 			dat = this->bbt[bbtoffs + (i >> 2)];
 			for (j = 0; j < 4; j++, i++) {
 				int sftcnt = (i << (3 - sft)) & sftmsk;
-				/* Do not store the reserved bbt blocks ! */
+				/* Do not store the reserved bbt blocks! */
 				buf[offs + (i >> sft)] &=
 					~(msk[dat & 0x03] << sftcnt);
 				dat >>= 2;
@@ -883,8 +834,8 @@
 		if (res < 0)
 			goto outerr;
 
-		printk(KERN_DEBUG "Bad block table written to 0x%012llx, version "
-		       "0x%02X\n", (unsigned long long)to, td->version[chip]);
+		pr_info("Bad block table written to 0x%012llx, version 0x%02X\n",
+			 (unsigned long long)to, td->version[chip]);
 
 		/* Mark it as used */
 		td->pages[chip] = page;
@@ -892,19 +843,18 @@
 	return 0;
 
  outerr:
-	printk(KERN_WARNING
-	       "nand_bbt: Error while writing bad block table %d\n", res);
+	pr_warn("nand_bbt: error while writing bad block table %d\n", res);
 	return res;
 }
 
 /**
  * nand_memory_bbt - [GENERIC] create a memory based bad block table
- * @mtd:	MTD device structure
- * @bd:		descriptor for the good/bad block search pattern
+ * @mtd: MTD device structure
+ * @bd: descriptor for the good/bad block search pattern
  *
- * The function creates a memory based bbt by scanning the device
- * for manufacturer / software marked good / bad blocks
-*/
+ * The function creates a memory based bbt by scanning the device for
+ * manufacturer / software marked good / bad blocks.
+ */
 static inline int nand_memory_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 {
 	struct nand_chip *this = mtd->priv;
@@ -915,25 +865,24 @@
 
 /**
  * check_create - [GENERIC] create and write bbt(s) if necessary
- * @mtd:	MTD device structure
- * @buf:	temporary buffer
- * @bd:		descriptor for the good/bad block search pattern
+ * @mtd: MTD device structure
+ * @buf: temporary buffer
+ * @bd: descriptor for the good/bad block search pattern
  *
- * The function checks the results of the previous call to read_bbt
- * and creates / updates the bbt(s) if necessary
- * Creation is necessary if no bbt was found for the chip/device
- * Update is necessary if one of the tables is missing or the
- * version nr. of one table is less than the other
-*/
+ * The function checks the results of the previous call to read_bbt and creates
+ * / updates the bbt(s) if necessary. Creation is necessary if no bbt was found
+ * for the chip/device. Update is necessary if one of the tables is missing or
+ * the version nr. of one table is less than the other.
+ */
 static int check_create(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd)
 {
-	int i, chips, writeops, chipsel, res;
+	int i, chips, writeops, create, chipsel, res, res2;
 	struct nand_chip *this = mtd->priv;
 	struct nand_bbt_descr *td = this->bbt_td;
 	struct nand_bbt_descr *md = this->bbt_md;
 	struct nand_bbt_descr *rd, *rd2;
 
-	/* Do we have a bbt per chip ? */
+	/* Do we have a bbt per chip? */
 	if (td->options & NAND_BBT_PERCHIP)
 		chips = this->numchips;
 	else
@@ -941,86 +890,98 @@
 
 	for (i = 0; i < chips; i++) {
 		writeops = 0;
+		create = 0;
 		rd = NULL;
 		rd2 = NULL;
-		/* Per chip or per device ? */
+		res = res2 = 0;
+		/* Per chip or per device? */
 		chipsel = (td->options & NAND_BBT_PERCHIP) ? i : -1;
-		/* Mirrored table available ? */
+		/* Mirrored table available? */
 		if (md) {
 			if (td->pages[i] == -1 && md->pages[i] == -1) {
+				create = 1;
 				writeops = 0x03;
-				goto create;
-			}
-
-			if (td->pages[i] == -1) {
+			} else if (td->pages[i] == -1) {
 				rd = md;
-				td->version[i] = md->version[i];
-				writeops = 1;
-				goto writecheck;
-			}
-
-			if (md->pages[i] == -1) {
+				writeops = 0x01;
+			} else if (md->pages[i] == -1) {
 				rd = td;
-				md->version[i] = td->version[i];
-				writeops = 2;
-				goto writecheck;
-			}
-
-			if (td->version[i] == md->version[i]) {
+				writeops = 0x02;
+			} else if (td->version[i] == md->version[i]) {
 				rd = td;
 				if (!(td->options & NAND_BBT_VERSION))
 					rd2 = md;
-				goto writecheck;
-			}
-
-			if (((int8_t) (td->version[i] - md->version[i])) > 0) {
+			} else if (((int8_t)(td->version[i] - md->version[i])) > 0) {
 				rd = td;
-				md->version[i] = td->version[i];
-				writeops = 2;
+				writeops = 0x02;
 			} else {
 				rd = md;
-				td->version[i] = md->version[i];
-				writeops = 1;
+				writeops = 0x01;
 			}
-
-			goto writecheck;
-
 		} else {
 			if (td->pages[i] == -1) {
+				create = 1;
 				writeops = 0x01;
-				goto create;
+			} else {
+				rd = td;
 			}
-			rd = td;
-			goto writecheck;
 		}
-	create:
-		/* Create the bad block table by scanning the device ? */
-		if (!(td->options & NAND_BBT_CREATE))
-			continue;
 
-		/* Create the table in memory by scanning the chip(s) */
-		if (!(this->options & NAND_CREATE_EMPTY_BBT))
-			create_bbt(mtd, buf, bd, chipsel);
+		if (create) {
+			/* Create the bad block table by scanning the device? */
+			if (!(td->options & NAND_BBT_CREATE))
+				continue;
 
-		td->version[i] = 1;
-		if (md)
-			md->version[i] = 1;
-	writecheck:
-		/* read back first ? */
-		if (rd)
-			read_abs_bbt(mtd, buf, rd, chipsel);
-		/* If they weren't versioned, read both. */
-		if (rd2)
-			read_abs_bbt(mtd, buf, rd2, chipsel);
+			/* Create the table in memory by scanning the chip(s) */
+			if (!(this->bbt_options & NAND_BBT_CREATE_EMPTY))
+				create_bbt(mtd, buf, bd, chipsel);
 
-		/* Write the bad block table to the device ? */
+			td->version[i] = 1;
+			if (md)
+				md->version[i] = 1;
+		}
+
+		/* Read back first? */
+		if (rd) {
+			res = read_abs_bbt(mtd, buf, rd, chipsel);
+			if (mtd_is_eccerr(res)) {
+				/* Mark table as invalid */
+				rd->pages[i] = -1;
+				rd->version[i] = 0;
+				i--;
+				continue;
+			}
+		}
+		/* If they weren't versioned, read both */
+		if (rd2) {
+			res2 = read_abs_bbt(mtd, buf, rd2, chipsel);
+			if (mtd_is_eccerr(res2)) {
+				/* Mark table as invalid */
+				rd2->pages[i] = -1;
+				rd2->version[i] = 0;
+				i--;
+				continue;
+			}
+		}
+
+		/* Scrub the flash table(s)? */
+		if (mtd_is_bitflip(res) || mtd_is_bitflip(res2))
+			writeops = 0x03;
+
+		/* Update version numbers before writing */
+		if (md) {
+			td->version[i] = max(td->version[i], md->version[i]);
+			md->version[i] = td->version[i];
+		}
+
+		/* Write the bad block table to the device? */
 		if ((writeops & 0x01) && (td->options & NAND_BBT_WRITE)) {
 			res = write_bbt(mtd, buf, td, md, chipsel);
 			if (res < 0)
 				return res;
 		}
 
-		/* Write the mirror bad block table to the device ? */
+		/* Write the mirror bad block table to the device? */
 		if ((writeops & 0x02) && md && (md->options & NAND_BBT_WRITE)) {
 			res = write_bbt(mtd, buf, md, td, chipsel);
 			if (res < 0)
@@ -1032,20 +993,19 @@
 
 /**
  * mark_bbt_regions - [GENERIC] mark the bad block table regions
- * @mtd:	MTD device structure
- * @td:		bad block table descriptor
+ * @mtd: MTD device structure
+ * @td: bad block table descriptor
  *
- * The bad block table regions are marked as "bad" to prevent
- * accidental erasures / writes. The regions are identified by
- * the mark 0x02.
-*/
+ * The bad block table regions are marked as "bad" to prevent accidental
+ * erasures / writes. The regions are identified by the mark 0x02.
+ */
 static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td)
 {
 	struct nand_chip *this = mtd->priv;
 	int i, j, chips, block, nrblocks, update;
 	uint8_t oldval, newval;
 
-	/* Do we have a bbt per chip ? */
+	/* Do we have a bbt per chip? */
 	if (td->options & NAND_BBT_PERCHIP) {
 		chips = this->numchips;
 		nrblocks = (int)(this->chipsize >> this->bbt_erase_shift);
@@ -1082,9 +1042,11 @@
 				update = 1;
 			block += 2;
 		}
-		/* If we want reserved blocks to be recorded to flash, and some
-		   new ones have been marked, then we need to update the stored
-		   bbts.  This should only happen once. */
+		/*
+		 * If we want reserved blocks to be recorded to flash, and some
+		 * new ones have been marked, then we need to update the stored
+		 * bbts.  This should only happen once.
+		 */
 		if (update && td->reserved_block_code)
 			nand_update_bbt(mtd, (loff_t)(block - 2) << (this->bbt_erase_shift - 1));
 	}
@@ -1092,8 +1054,8 @@
 
 /**
  * verify_bbt_descr - verify the bad block description
- * @mtd:	MTD device structure
- * @bd:		the table to verify
+ * @mtd: MTD device structure
+ * @bd: the table to verify
  *
  * This functions performs a few sanity checks on the bad block description
  * table.
@@ -1111,16 +1073,16 @@
 	pattern_len = bd->len;
 	bits = bd->options & NAND_BBT_NRBITS_MSK;
 
-	BUG_ON((this->options & NAND_USE_FLASH_BBT_NO_OOB) &&
-			!(this->options & NAND_USE_FLASH_BBT));
+	BUG_ON((this->bbt_options & NAND_BBT_NO_OOB) &&
+			!(this->bbt_options & NAND_BBT_USE_FLASH));
 	BUG_ON(!bits);
 
 	if (bd->options & NAND_BBT_VERSION)
 		pattern_len++;
 
 	if (bd->options & NAND_BBT_NO_OOB) {
-		BUG_ON(!(this->options & NAND_USE_FLASH_BBT));
-		BUG_ON(!(this->options & NAND_USE_FLASH_BBT_NO_OOB));
+		BUG_ON(!(this->bbt_options & NAND_BBT_USE_FLASH));
+		BUG_ON(!(this->bbt_options & NAND_BBT_NO_OOB));
 		BUG_ON(bd->offs);
 		if (bd->options & NAND_BBT_VERSION)
 			BUG_ON(bd->veroffs != bd->len);
@@ -1140,18 +1102,16 @@
 
 /**
  * nand_scan_bbt - [NAND Interface] scan, find, read and maybe create bad block table(s)
- * @mtd:	MTD device structure
- * @bd:		descriptor for the good/bad block search pattern
+ * @mtd: MTD device structure
+ * @bd: descriptor for the good/bad block search pattern
  *
- * The function checks, if a bad block table(s) is/are already
- * available. If not it scans the device for manufacturer
- * marked good / bad blocks and writes the bad block table(s) to
- * the selected place.
+ * The function checks, if a bad block table(s) is/are already available. If
+ * not it scans the device for manufacturer marked good / bad blocks and writes
+ * the bad block table(s) to the selected place.
  *
- * The bad block table memory is allocated here. It must be freed
- * by calling the nand_free_bbt function.
- *
-*/
+ * The bad block table memory is allocated here. It must be freed by calling
+ * the nand_free_bbt function.
+ */
 int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 {
 	struct nand_chip *this = mtd->priv;
@@ -1161,19 +1121,21 @@
 	struct nand_bbt_descr *md = this->bbt_md;
 
 	len = mtd->size >> (this->bbt_erase_shift + 2);
-	/* Allocate memory (2bit per block) and clear the memory bad block table */
+	/*
+	 * Allocate memory (2bit per block) and clear the memory bad block
+	 * table.
+	 */
 	this->bbt = kzalloc(len, GFP_KERNEL);
-	if (!this->bbt) {
-		printk(KERN_ERR "nand_scan_bbt: Out of memory\n");
+	if (!this->bbt)
 		return -ENOMEM;
-	}
 
-	/* If no primary table decriptor is given, scan the device
-	 * to build a memory based bad block table
+	/*
+	 * If no primary table decriptor is given, scan the device to build a
+	 * memory based bad block table.
 	 */
 	if (!td) {
 		if ((res = nand_memory_bbt(mtd, bd))) {
-			printk(KERN_ERR "nand_bbt: Can't scan flash and build the RAM-based BBT\n");
+			pr_err("nand_bbt: can't scan flash and build the RAM-based BBT\n");
 			kfree(this->bbt);
 			this->bbt = NULL;
 		}
@@ -1187,22 +1149,20 @@
 	len += (len >> this->page_shift) * mtd->oobsize;
 	buf = vmalloc(len);
 	if (!buf) {
-		printk(KERN_ERR "nand_bbt: Out of memory\n");
 		kfree(this->bbt);
 		this->bbt = NULL;
 		return -ENOMEM;
 	}
 
-	/* Is the bbt at a given page ? */
+	/* Is the bbt at a given page? */
 	if (td->options & NAND_BBT_ABSPAGE) {
-		res = read_abs_bbts(mtd, buf, td, md);
+		read_abs_bbts(mtd, buf, td, md);
 	} else {
 		/* Search the bad block table using a pattern in oob */
-		res = search_read_bbts(mtd, buf, td, md);
+		search_read_bbts(mtd, buf, td, md);
 	}
 
-	if (res)
-		res = check_create(mtd, buf, bd);
+	res = check_create(mtd, buf, bd);
 
 	/* Prevent the bbt regions from erasing / writing */
 	mark_bbt_region(mtd, td);
@@ -1215,15 +1175,15 @@
 
 /**
  * nand_update_bbt - [NAND Interface] update bad block table(s)
- * @mtd:	MTD device structure
- * @offs:	the offset of the newly marked block
+ * @mtd: MTD device structure
+ * @offs: the offset of the newly marked block
  *
- * The function updates the bad block table(s)
-*/
+ * The function updates the bad block table(s).
+ */
 int nand_update_bbt(struct mtd_info *mtd, loff_t offs)
 {
 	struct nand_chip *this = mtd->priv;
-	int len, res = 0, writeops = 0;
+	int len, res = 0;
 	int chip, chipsel;
 	uint8_t *buf;
 	struct nand_bbt_descr *td = this->bbt_td;
@@ -1236,14 +1196,10 @@
 	len = (1 << this->bbt_erase_shift);
 	len += (len >> this->page_shift) * mtd->oobsize;
 	buf = kmalloc(len, GFP_KERNEL);
-	if (!buf) {
-		printk(KERN_ERR "nand_update_bbt: Out of memory\n");
+	if (!buf)
 		return -ENOMEM;
-	}
 
-	writeops = md != NULL ? 0x03 : 0x01;
-
-	/* Do we have a bbt per chip ? */
+	/* Do we have a bbt per chip? */
 	if (td->options & NAND_BBT_PERCHIP) {
 		chip = (int)(offs >> this->chip_shift);
 		chipsel = chip;
@@ -1256,14 +1212,14 @@
 	if (md)
 		md->version[chip]++;
 
-	/* Write the bad block table to the device ? */
-	if ((writeops & 0x01) && (td->options & NAND_BBT_WRITE)) {
+	/* Write the bad block table to the device? */
+	if (td->options & NAND_BBT_WRITE) {
 		res = write_bbt(mtd, buf, td, md, chipsel);
 		if (res < 0)
 			goto out;
 	}
-	/* Write the mirror bad block table to the device ? */
-	if ((writeops & 0x02) && md && (md->options & NAND_BBT_WRITE)) {
+	/* Write the mirror bad block table to the device? */
+	if (md && (md->options & NAND_BBT_WRITE)) {
 		res = write_bbt(mtd, buf, md, td, chipsel);
 	}
 
@@ -1272,8 +1228,10 @@
 	return res;
 }
 
-/* Define some generic bad / good block scan pattern which are used
- * while scanning a device for factory marked good / bad blocks. */
+/*
+ * Define some generic bad / good block scan pattern which are used
+ * while scanning a device for factory marked good / bad blocks.
+ */
 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
 
 static uint8_t scan_agand_pattern[] = { 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7 };
@@ -1285,8 +1243,7 @@
 	.pattern = scan_agand_pattern
 };
 
-/* Generic flash bbt decriptors
-*/
+/* Generic flash bbt descriptors */
 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
 
@@ -1296,7 +1253,7 @@
 	.offs =	8,
 	.len = 4,
 	.veroffs = 12,
-	.maxblocks = 4,
+	.maxblocks = NAND_BBT_SCAN_MAXBLOCKS,
 	.pattern = bbt_pattern
 };
 
@@ -1306,55 +1263,51 @@
 	.offs =	8,
 	.len = 4,
 	.veroffs = 12,
-	.maxblocks = 4,
+	.maxblocks = NAND_BBT_SCAN_MAXBLOCKS,
 	.pattern = mirror_pattern
 };
 
-static struct nand_bbt_descr bbt_main_no_bbt_descr = {
+static struct nand_bbt_descr bbt_main_no_oob_descr = {
 	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP
 		| NAND_BBT_NO_OOB,
 	.len = 4,
 	.veroffs = 4,
-	.maxblocks = 4,
+	.maxblocks = NAND_BBT_SCAN_MAXBLOCKS,
 	.pattern = bbt_pattern
 };
 
-static struct nand_bbt_descr bbt_mirror_no_bbt_descr = {
+static struct nand_bbt_descr bbt_mirror_no_oob_descr = {
 	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP
 		| NAND_BBT_NO_OOB,
 	.len = 4,
 	.veroffs = 4,
-	.maxblocks = 4,
+	.maxblocks = NAND_BBT_SCAN_MAXBLOCKS,
 	.pattern = mirror_pattern
 };
 
-#define BBT_SCAN_OPTIONS (NAND_BBT_SCANLASTPAGE | NAND_BBT_SCAN2NDPAGE | \
-		NAND_BBT_SCANBYTE1AND6)
+#define BADBLOCK_SCAN_MASK (~NAND_BBT_NO_OOB)
 /**
- * nand_create_default_bbt_descr - [Internal] Creates a BBT descriptor structure
- * @this:	NAND chip to create descriptor for
+ * nand_create_badblock_pattern - [INTERN] Creates a BBT descriptor structure
+ * @this: NAND chip to create descriptor for
  *
  * This function allocates and initializes a nand_bbt_descr for BBM detection
- * based on the properties of "this". The new descriptor is stored in
+ * based on the properties of @this. The new descriptor is stored in
  * this->badblock_pattern. Thus, this->badblock_pattern should be NULL when
  * passed to this function.
- *
  */
-static int nand_create_default_bbt_descr(struct nand_chip *this)
+static int nand_create_badblock_pattern(struct nand_chip *this)
 {
 	struct nand_bbt_descr *bd;
 	if (this->badblock_pattern) {
-		printk(KERN_WARNING "BBT descr already allocated; not replacing.\n");
+		pr_warn("Bad block pattern already allocated; not replacing\n");
 		return -EINVAL;
 	}
 	bd = kzalloc(sizeof(*bd), GFP_KERNEL);
-	if (!bd) {
-		printk(KERN_ERR "nand_create_default_bbt_descr: Out of memory\n");
+	if (!bd)
 		return -ENOMEM;
-	}
-	bd->options = this->options & BBT_SCAN_OPTIONS;
+	bd->options = this->bbt_options & BADBLOCK_SCAN_MASK;
 	bd->offs = this->badblockpos;
 	bd->len = (this->options & NAND_BUSWIDTH_16) ? 2 : 1;
 	bd->pattern = scan_ff_pattern;
@@ -1365,22 +1318,20 @@
 
 /**
  * nand_default_bbt - [NAND Interface] Select a default bad block table for the device
- * @mtd:	MTD device structure
+ * @mtd: MTD device structure
  *
- * This function selects the default bad block table
- * support for the device and calls the nand_scan_bbt function
- *
-*/
+ * This function selects the default bad block table support for the device and
+ * calls the nand_scan_bbt function.
+ */
 int nand_default_bbt(struct mtd_info *mtd)
 {
 	struct nand_chip *this = mtd->priv;
 
-	/* Default for AG-AND. We must use a flash based
-	 * bad block table as the devices have factory marked
-	 * _good_ blocks. Erasing those blocks leads to loss
-	 * of the good / bad information, so we _must_ store
-	 * this information in a good / bad table during
-	 * startup
+	/*
+	 * Default for AG-AND. We must use a flash based bad block table as the
+	 * devices have factory marked _good_ blocks. Erasing those blocks
+	 * leads to loss of the good / bad information, so we _must_ store this
+	 * information in a good / bad table during startup.
 	 */
 	if (this->options & NAND_IS_AND) {
 		/* Use the default pattern descriptors */
@@ -1388,17 +1339,17 @@
 			this->bbt_td = &bbt_main_descr;
 			this->bbt_md = &bbt_mirror_descr;
 		}
-		this->options |= NAND_USE_FLASH_BBT;
+		this->bbt_options |= NAND_BBT_USE_FLASH;
 		return nand_scan_bbt(mtd, &agand_flashbased);
 	}
 
-	/* Is a flash based bad block table requested ? */
-	if (this->options & NAND_USE_FLASH_BBT) {
+	/* Is a flash based bad block table requested? */
+	if (this->bbt_options & NAND_BBT_USE_FLASH) {
 		/* Use the default pattern descriptors */
 		if (!this->bbt_td) {
-			if (this->options & NAND_USE_FLASH_BBT_NO_OOB) {
-				this->bbt_td = &bbt_main_no_bbt_descr;
-				this->bbt_md = &bbt_mirror_no_bbt_descr;
+			if (this->bbt_options & NAND_BBT_NO_OOB) {
+				this->bbt_td = &bbt_main_no_oob_descr;
+				this->bbt_md = &bbt_mirror_no_oob_descr;
 			} else {
 				this->bbt_td = &bbt_main_descr;
 				this->bbt_md = &bbt_mirror_descr;
@@ -1410,18 +1361,17 @@
 	}
 
 	if (!this->badblock_pattern)
-		nand_create_default_bbt_descr(this);
+		nand_create_badblock_pattern(this);
 
 	return nand_scan_bbt(mtd, this->badblock_pattern);
 }
 
 /**
  * nand_isbad_bbt - [NAND Interface] Check if a block is bad
- * @mtd:	MTD device structure
- * @offs:	offset in the device
- * @allowbbt:	allow access to bad block table region
- *
-*/
+ * @mtd: MTD device structure
+ * @offs: offset in the device
+ * @allowbbt: allow access to bad block table region
+ */
 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
 {
 	struct nand_chip *this = mtd->priv;
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 3953549..f856778 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -71,14 +71,15 @@
 	 * These are the new chips with large page size. The pagesize and the
 	 * erasesize is determined from the extended id bytes
 	 */
-#define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR)
+#define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS
 #define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
 
-	/*512 Megabit */
+	/* 512 Megabit */
 	{"NAND 64MiB 1,8V 8-bit",	0xA2, 0,  64, 0, LP_OPTIONS},
 	{"NAND 64MiB 1,8V 8-bit",	0xA0, 0,  64, 0, LP_OPTIONS},
 	{"NAND 64MiB 3,3V 8-bit",	0xF2, 0,  64, 0, LP_OPTIONS},
 	{"NAND 64MiB 3,3V 8-bit",	0xD0, 0,  64, 0, LP_OPTIONS},
+	{"NAND 64MiB 3,3V 8-bit",	0xF0, 0,  64, 0, LP_OPTIONS},
 	{"NAND 64MiB 1,8V 16-bit",	0xB2, 0,  64, 0, LP_OPTIONS16},
 	{"NAND 64MiB 1,8V 16-bit",	0xB0, 0,  64, 0, LP_OPTIONS16},
 	{"NAND 64MiB 3,3V 16-bit",	0xC2, 0,  64, 0, LP_OPTIONS16},
@@ -157,9 +158,7 @@
 	 * writes possible, but not implemented now
 	 */
 	{"AND 128MiB 3,3V 8-bit",	0x01, 2048, 128, 0x4000,
-	 NAND_IS_AND | NAND_NO_AUTOINCR |NAND_NO_READRDY | NAND_4PAGE_ARRAY |
-	 BBT_AUTO_REFRESH
-	},
+	 NAND_IS_AND | NAND_4PAGE_ARRAY | BBT_AUTO_REFRESH},
 
 	{NULL,}
 };
@@ -176,6 +175,9 @@
 	{NAND_MFR_STMICRO, "ST Micro"},
 	{NAND_MFR_HYNIX, "Hynix"},
 	{NAND_MFR_MICRON, "Micron"},
-	{NAND_MFR_AMD, "AMD"},
+	{NAND_MFR_AMD, "AMD/Spansion"},
+	{NAND_MFR_MACRONIX, "Macronix"},
+	{NAND_MFR_EON, "Eon"},
 	{0x0, "Unknown"}
 };
+
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 4727f9c..d81972c 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -121,7 +121,7 @@
 		WATCHDOG_RESET();
 
 		if (!opts->scrub && bbtest) {
-			int ret = meminfo->block_isbad(meminfo, erase.addr);
+			int ret = mtd_block_isbad(meminfo, erase.addr);
 			if (ret > 0) {
 				if (!opts->quiet)
 					printf("\rSkipping bad block at  "
@@ -144,7 +144,7 @@
 
 		erased_length++;
 
-		result = meminfo->erase(meminfo, &erase);
+		result = mtd_erase(meminfo, &erase);
 		if (result != 0) {
 			printf("\n%s: MTD Erase failure: %d\n",
 			       mtd_device, result);
@@ -153,15 +153,16 @@
 
 		/* format for JFFS2 ? */
 		if (opts->jffs2 && chip->ecc.layout->oobavail >= 8) {
-			chip->ops.ooblen = 8;
-			chip->ops.datbuf = NULL;
-			chip->ops.oobbuf = (uint8_t *)&cleanmarker;
-			chip->ops.ooboffs = 0;
-			chip->ops.mode = MTD_OOB_AUTO;
+			struct mtd_oob_ops ops;
+			ops.ooblen = 8;
+			ops.datbuf = NULL;
+			ops.oobbuf = (uint8_t *)&cleanmarker;
+			ops.ooboffs = 0;
+			ops.mode = MTD_OPS_AUTO_OOB;
 
-			result = meminfo->write_oob(meminfo,
+			result = mtd_write_oob(meminfo,
 			                            erase.addr,
-			                            &chip->ops);
+			                            &ops);
 			if (result != 0) {
 				printf("\n%s: MTD writeoob failure: %d\n",
 				       mtd_device, result);
@@ -458,7 +459,8 @@
 static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
 			const size_t *len)
 {
-	size_t i, l = *len;
+	size_t l = *len;
+	ssize_t i;
 
 	for (i = l - 1; i >= 0; i--)
 		if (buf[i] != 0xFF)
@@ -604,7 +606,7 @@
 
 			ops.len = pagesize;
 			ops.ooblen = nand->oobsize;
-			ops.mode = MTD_OOB_AUTO;
+			ops.mode = MTD_OPS_AUTO_OOB;
 			ops.ooboffs = 0;
 
 			pages = write_size / pagesize_oob;
@@ -614,7 +616,7 @@
 				ops.datbuf = p_buffer;
 				ops.oobbuf = ops.datbuf + pagesize;
 
-				rval = nand->write_oob(nand, offset, &ops);
+				rval = mtd_write_oob(nand, offset, &ops);
 				if (rval != 0)
 					break;
 
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 213d2c9..94b9033 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -216,6 +216,7 @@
 	nand->ecc.mode = NAND_ECC_HW;
 	nand->ecc.size = 256;
 	nand->ecc.bytes = 3;
+	nand->ecc.strength = 1;
 	nand->select_chip = ndfc_select_chip;
 
 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
diff --git a/drivers/mtd/nand/nomadik.c b/drivers/mtd/nand/nomadik.c
index b76f4cb..dc8e513 100644
--- a/drivers/mtd/nand/nomadik.c
+++ b/drivers/mtd/nand/nomadik.c
@@ -212,6 +212,7 @@
 	chip->ecc.mode = NAND_ECC_HW;
 	chip->ecc.bytes = 3;
 	chip->ecc.size = 512;
+	chip->ecc.strength = 1;
 	chip->ecc.layout = &nomadik_ecc_layout;
 	chip->ecc.calculate = nomadik_ecc_calculate;
 	chip->ecc.hwctl = nomadik_ecc_hwctl;
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index bc1bcad..5d08822 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -590,11 +590,12 @@
  * @mtd:	mtd info structure
  * @chip:	nand chip info structure
  * @buf:	buffer to store read data
+ * @oob_required: caller expects OOB data read to chip->oob_poi
  * @page:	page number to read
  *
  */
 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
-				uint8_t *buf, int page)
+				uint8_t *buf, int oob_required, int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -804,6 +805,7 @@
 	nand->ecc.hwctl = NULL;
 	nand->ecc.correct = NULL;
 	nand->ecc.calculate = NULL;
+	nand->ecc.strength = eccstrength;
 
 	/* Setup the ecc configurations again */
 	if (hardware) {
@@ -901,7 +903,7 @@
 	nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
 
 	nand->cmd_ctrl = omap_nand_hwcontrol;
-	nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
+	nand->options = NAND_NO_PADDING | NAND_CACHEPRG;
 	/* If we are 16 bit dev, our gpmc config tells us that */
 	if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
 		nand->options |= NAND_BUSWIDTH_16;
@@ -934,6 +936,7 @@
 	nand->ecc.layout = &hw_bch8_nand_oob;
 	nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
 	nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
+	nand->ecc.strength = 8;
 	nand->ecc.hwctl = omap_enable_ecc_bch;
 	nand->ecc.correct = omap_correct_data_bch;
 	nand->ecc.calculate = omap_calculate_ecc_bch;
@@ -952,6 +955,7 @@
 	nand->ecc.hwctl = omap_enable_hwecc;
 	nand->ecc.correct = omap_correct_data;
 	nand->ecc.calculate = omap_calculate_ecc;
+	nand->ecc.strength = 1;
 	omap_hwecc_init(nand);
 #endif
 #endif
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index e1a459b..43d8213 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -173,6 +173,7 @@
 	nand->ecc.mode = NAND_ECC_HW;
 	nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
 	nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
+	nand->ecc.strength = 1;
 #else
 	nand->ecc.mode = NAND_ECC_SOFT;
 #endif
diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index 4d94cc6..6afbec6 100644
--- a/drivers/mtd/nand/tegra_nand.c
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -707,7 +707,7 @@
  *		-EIO when command timeout
  */
 static int nand_read_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, uint8_t *buf, int page)
+	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 {
 	return nand_rw_page(mtd, chip, buf, page, 1, 0);
 }
@@ -719,8 +719,8 @@
  * @param chip	nand chip info structure
  * @param buf	data buffer
  */
-static void nand_write_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf)
+static int nand_write_page_hwecc(struct mtd_info *mtd,
+	struct nand_chip *chip, const uint8_t *buf, int oob_required)
 {
 	int page;
 	struct nand_drv *info;
@@ -731,6 +731,7 @@
 		(readl(&info->reg->addr_reg2) << 16);
 
 	nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
+	return 0;
 }
 
 
@@ -746,7 +747,7 @@
  *		-EIO when command timeout
  */
 static int nand_read_page_raw(struct mtd_info *mtd,
-	struct nand_chip *chip, uint8_t *buf, int page)
+	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 {
 	return nand_rw_page(mtd, chip, buf, page, 0, 0);
 }
@@ -758,8 +759,8 @@
  * @param chip	nand chip info structure
  * @param buf	data buffer
  */
-static void nand_write_page_raw(struct mtd_info *mtd,
-		struct nand_chip *chip,	const uint8_t *buf)
+static int nand_write_page_raw(struct mtd_info *mtd,
+		struct nand_chip *chip,	const uint8_t *buf, int oob_required)
 {
 	int page;
 	struct nand_drv *info;
@@ -769,6 +770,7 @@
 		(readl(&info->reg->addr_reg2) << 16);
 
 	nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
+	return 0;
 }
 
 /**
@@ -873,19 +875,13 @@
  * @param mtd		mtd info structure
  * @param chip		nand chip info structure
  * @param page		page number to read
- * @param sndcmd	flag whether to issue read command or not
- * @return	1 - issue read command next time
- *		0 - not to issue
  */
 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
-	int page, int sndcmd)
+	int page)
 {
-	if (sndcmd) {
-		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
-		sndcmd = 0;
-	}
+	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 	nand_rw_oob(mtd, chip, page, 0, 0);
-	return sndcmd;
+	return 0;
 }
 
 /**
@@ -1018,6 +1014,7 @@
 	nand->ecc.write_page_raw = nand_write_page_raw;
 	nand->ecc.read_oob = nand_read_oob;
 	nand->ecc.write_oob = nand_write_oob;
+	nand->ecc.strength = 1;
 	nand->select_chip = nand_select_chip;
 	nand->dev_ready  = nand_dev_ready;
 	nand->priv = &nand_ctrl;
diff --git a/drivers/mtd/nand/tegra_nand.h b/drivers/mtd/nand/tegra_nand.h
index 7e74be7..622b869 100644
--- a/drivers/mtd/nand/tegra_nand.h
+++ b/drivers/mtd/nand/tegra_nand.h
@@ -224,7 +224,7 @@
 #define BCH_DEC_STATUS_MAX_CORR_CNT_MASK	(0x1f << 8)
 #define BCH_DEC_STATUS_PAGE_NUMBER_MASK		0xFF
 
-#define LP_OPTIONS (NAND_NO_READRDY | NAND_NO_AUTOINCR)
+#define LP_OPTIONS	0
 
 struct nand_ctlr {
 	u32	command;	/* offset 00h */
diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index 858e322..ddfe7e7 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -743,7 +743,7 @@
 }
 
 /**
- * onenand_transfer_auto_oob - [Internal] oob auto-placement transfer
+ * onenand_transfer_auto_oob - [INTERN] oob auto-placement transfer
  * @param mtd		MTD device structure
  * @param buf		destination address
  * @param column	oob offset to read from
@@ -807,7 +807,7 @@
 		return status;
 
 	/* check if we failed due to uncorrectable error */
-	if (status != -EBADMSG && status != ONENAND_BBT_READ_ECC_ERROR)
+	if (!mtd_is_eccerr(status) && status != ONENAND_BBT_READ_ECC_ERROR)
 		return status;
 
 	/* check if address lies in MLC region */
@@ -847,7 +847,7 @@
 
 	MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ops_nolock: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
 
-	if (ops->mode == MTD_OOB_AUTO)
+	if (ops->mode == MTD_OPS_AUTO_OOB)
 		oobsize = this->ecclayout->oobavail;
 	else
 		oobsize = mtd->oobsize;
@@ -914,7 +914,7 @@
 			thisooblen = oobsize - oobcolumn;
 			thisooblen = min_t(int, thisooblen, ooblen - oobread);
 
-			if (ops->mode == MTD_OOB_AUTO)
+			if (ops->mode == MTD_OPS_AUTO_OOB)
 				onenand_transfer_auto_oob(mtd, oobbuf, oobcolumn, thisooblen);
 			else
 				this->read_bufferram(mtd, 0, ONENAND_SPARERAM, oobbuf, oobcolumn, thisooblen);
@@ -929,7 +929,7 @@
 			if (unlikely(ret))
 				ret = onenand_recover_lsb(mtd, from, ret);
 			onenand_update_bufferram(mtd, from, !ret);
-			if (ret == -EBADMSG)
+			if (mtd_is_eccerr(ret))
 				ret = 0;
 		}
 
@@ -950,7 +950,7 @@
 			/* Now wait for load */
 			ret = this->wait(mtd, FL_READING);
 			onenand_update_bufferram(mtd, from, !ret);
-			if (ret == -EBADMSG)
+			if (mtd_is_eccerr(ret))
 				ret = 0;
 		}
 	}
@@ -987,7 +987,7 @@
 	struct mtd_ecc_stats stats;
 	int read = 0, thislen, column, oobsize;
 	size_t len = ops->ooblen;
-	mtd_oob_mode_t mode = ops->mode;
+	unsigned int mode = ops->mode;
 	u_char *buf = ops->oobbuf;
 	int ret = 0, readcmd;
 
@@ -998,7 +998,7 @@
 	/* Initialize return length value */
 	ops->oobretlen = 0;
 
-	if (mode == MTD_OOB_AUTO)
+	if (mode == MTD_OPS_AUTO_OOB)
 		oobsize = this->ecclayout->oobavail;
 	else
 		oobsize = mtd->oobsize;
@@ -1041,7 +1041,7 @@
 			break;
 		}
 
-		if (mode == MTD_OOB_AUTO)
+		if (mode == MTD_OPS_AUTO_OOB)
 			onenand_transfer_auto_oob(mtd, buf, column, thislen);
 		else
 			this->read_bufferram(mtd, 0, ONENAND_SPARERAM, buf, column, thislen);
@@ -1115,10 +1115,10 @@
 	int ret;
 
 	switch (ops->mode) {
-	case MTD_OOB_PLACE:
-	case MTD_OOB_AUTO:
+	case MTD_OPS_PLACE_OOB:
+	case MTD_OPS_AUTO_OOB:
 		break;
-	case MTD_OOB_RAW:
+	case MTD_OPS_RAW:
 		/* Not implemented yet */
 	default:
 		return -EINVAL;
@@ -1337,7 +1337,7 @@
 #define NOTALIGNED(x)	((x & (this->subpagesize - 1)) != 0)
 
 /**
- * onenand_fill_auto_oob - [Internal] oob auto-placement transfer
+ * onenand_fill_auto_oob - [INTERN] oob auto-placement transfer
  * @param mtd           MTD device structure
  * @param oob_buf       oob buffer
  * @param buf           source address
@@ -1404,19 +1404,13 @@
 	ops->retlen = 0;
 	ops->oobretlen = 0;
 
-	/* Do not allow writes past end of device */
-	if (unlikely((to + len) > mtd->size)) {
-		printk(KERN_ERR "onenand_write_ops_nolock: Attempt write to past end of device\n");
-		return -EINVAL;
-	}
-
 	/* Reject writes, which are not page aligned */
 	if (unlikely(NOTALIGNED(to) || NOTALIGNED(len))) {
 		printk(KERN_ERR "onenand_write_ops_nolock: Attempt to write not page aligned data\n");
 		return -EINVAL;
 	}
 
-	if (ops->mode == MTD_OOB_AUTO)
+	if (ops->mode == MTD_OPS_AUTO_OOB)
 		oobsize = this->ecclayout->oobavail;
 	else
 		oobsize = mtd->oobsize;
@@ -1450,7 +1444,7 @@
 			/* We send data to spare ram with oobsize
 			 *                          * to prevent byte access */
 			memset(oobbuf, 0xff, mtd->oobsize);
-			if (ops->mode == MTD_OOB_AUTO)
+			if (ops->mode == MTD_OPS_AUTO_OOB)
 				onenand_fill_auto_oob(mtd, oobbuf, oob, oobcolumn, thisooblen);
 			else
 				memcpy(oobbuf + oobcolumn, oob, thisooblen);
@@ -1502,7 +1496,7 @@
 }
 
 /**
- * onenand_write_oob_nolock - [Internal] OneNAND write out-of-band
+ * onenand_write_oob_nolock - [INTERN] OneNAND write out-of-band
  * @param mtd           MTD device structure
  * @param to            offset to write to
  * @param len           number of bytes to write
@@ -1521,7 +1515,7 @@
 	u_char *oobbuf;
 	size_t len = ops->ooblen;
 	const u_char *buf = ops->oobbuf;
-	mtd_oob_mode_t mode = ops->mode;
+	unsigned int mode = ops->mode;
 
 	to += ops->ooboffs;
 
@@ -1530,7 +1524,7 @@
 	/* Initialize retlen, in case of early exit */
 	ops->oobretlen = 0;
 
-	if (mode == MTD_OOB_AUTO)
+	if (mode == MTD_OPS_AUTO_OOB)
 		oobsize = this->ecclayout->oobavail;
 	else
 		oobsize = mtd->oobsize;
@@ -1571,7 +1565,7 @@
 		/* We send data to spare ram with oobsize
 		 * to prevent byte access */
 		memset(oobbuf, 0xff, mtd->oobsize);
-		if (mode == MTD_OOB_AUTO)
+		if (mode == MTD_OPS_AUTO_OOB)
 			onenand_fill_auto_oob(mtd, oobbuf, buf, column, thislen);
 		else
 			memcpy(oobbuf + column, buf, thislen);
@@ -1661,10 +1655,10 @@
 	int ret;
 
 	switch (ops->mode) {
-	case MTD_OOB_PLACE:
-	case MTD_OOB_AUTO:
+	case MTD_OPS_PLACE_OOB:
+	case MTD_OPS_AUTO_OOB:
 		break;
-	case MTD_OOB_RAW:
+	case MTD_OPS_RAW:
 		/* Not implemented yet */
 	default:
 		return -EINVAL;
@@ -1720,13 +1714,6 @@
 	MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n",
 			(unsigned int) addr, len);
 
-	/* Do not allow erase past end of device */
-	if (unlikely((len + addr) > mtd->size)) {
-		MTDDEBUG(MTD_DEBUG_LEVEL0, "onenand_erase:"
-					"Erase past end of device\n");
-		return -EINVAL;
-	}
-
 	if (FLEXONENAND(this)) {
 		/* Find the eraseregion of this address */
 		i = flexonenand_region(mtd, addr);
@@ -1762,8 +1749,6 @@
 		return -EINVAL;
 	}
 
-	instr->fail_addr = 0xffffffff;
-
 	/* Grab the lock and see if the device is available */
 	onenand_get_device(mtd, FL_ERASING);
 
@@ -1889,7 +1874,7 @@
 	struct bbm_info *bbm = this->bbm;
 	u_char buf[2] = {0, 0};
 	struct mtd_oob_ops ops = {
-		.mode = MTD_OOB_PLACE,
+		.mode = MTD_OPS_PLACE_OOB,
 		.ooblen = 2,
 		.oobbuf = buf,
 		.ooboffs = 0,
@@ -1915,7 +1900,6 @@
  */
 int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
 {
-	struct onenand_chip *this = mtd->priv;
 	int ret;
 
 	ret = onenand_block_isbad(mtd, ofs);
@@ -1926,7 +1910,7 @@
 		return ret;
 	}
 
-	ret = this->block_markbad(mtd, ofs);
+	ret = mtd_block_markbad(mtd, ofs);
 	return ret;
 }
 
@@ -2386,7 +2370,7 @@
 	int i, ret;
 	int block;
 	struct mtd_oob_ops ops = {
-		.mode = MTD_OOB_PLACE,
+		.mode = MTD_OPS_PLACE_OOB,
 		.ooboffs = 0,
 		.ooblen	= mtd->oobsize,
 		.datbuf	= NULL,
@@ -2645,14 +2629,14 @@
 		mtd->size = this->chipsize;
 
 	mtd->flags = MTD_CAP_NANDFLASH;
-	mtd->erase = onenand_erase;
-	mtd->read = onenand_read;
-	mtd->write = onenand_write;
-	mtd->read_oob = onenand_read_oob;
-	mtd->write_oob = onenand_write_oob;
-	mtd->sync = onenand_sync;
-	mtd->block_isbad = onenand_block_isbad;
-	mtd->block_markbad = onenand_block_markbad;
+	mtd->_erase = onenand_erase;
+	mtd->_read = onenand_read;
+	mtd->_write = onenand_write;
+	mtd->_read_oob = onenand_read_oob;
+	mtd->_write_oob = onenand_write_oob;
+	mtd->_sync = onenand_sync;
+	mtd->_block_isbad = onenand_block_isbad;
+	mtd->_block_markbad = onenand_block_markbad;
 
 	return 0;
 }
diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c
index 9d5da54..0267c2c 100644
--- a/drivers/mtd/onenand/onenand_bbt.c
+++ b/drivers/mtd/onenand/onenand_bbt.c
@@ -87,7 +87,7 @@
 	startblock = 0;
 	from = 0;
 
-	ops.mode = MTD_OOB_PLACE;
+	ops.mode = MTD_OPS_PLACE_OOB;
 	ops.ooblen = readlen;
 	ops.oobbuf = buf;
 	ops.len = ops.ooboffs = ops.retlen = ops.oobretlen = 0;
@@ -200,10 +200,8 @@
 	len = this->chipsize >> (this->erase_shift + 2);
 	/* Allocate memory (2bit per block) */
 	bbm->bbt = malloc(len);
-	if (!bbm->bbt) {
-		printk(KERN_ERR "onenand_scan_bbt: Out of memory\n");
+	if (!bbm->bbt)
 		return -ENOMEM;
-	}
 	/* Clear the memory bad block table */
 	memset(bbm->bbt, 0x00, len);
 
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index bc558c4..dad30b5 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -94,7 +94,7 @@
 		.idcode2 = 0x4d01,
 		.pages_per_sector = 256,
 		.nr_sectors = 256,
-		.name = "S25FL129P_64K",
+		.name = "S25FL129P_64K/S25FL128S",
 	},
 	{
 		.idcode1 = 0x0219,
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index a708162..2588822 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -539,7 +539,7 @@
 	ubi->peb_count  = mtd_div_by_eb(ubi->mtd->size, ubi->mtd);
 	ubi->flash_size = ubi->mtd->size;
 
-	if (ubi->mtd->block_isbad && ubi->mtd->block_markbad)
+	if (mtd_can_have_bb(ubi->mtd))
 		ubi->bad_allowed = 1;
 
 	ubi->min_io_size = ubi->mtd->writesize;
diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c
index d523c94..d2d3c9c 100644
--- a/drivers/mtd/ubi/eba.c
+++ b/drivers/mtd/ubi/eba.c
@@ -460,7 +460,7 @@
 		if (err == UBI_IO_BITFLIPS) {
 			scrub = 1;
 			err = 0;
-		} else if (err == -EBADMSG) {
+		} else if (mtd_is_eccerr(err)) {
 			if (vol->vol_type == UBI_DYNAMIC_VOLUME)
 				goto out_unlock;
 			scrub = 1;
diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c
index 8423894..05de9ae 100644
--- a/drivers/mtd/ubi/io.c
+++ b/drivers/mtd/ubi/io.c
@@ -154,7 +154,7 @@
 
 	addr = (loff_t)pnum * ubi->peb_size + offset;
 retry:
-	err = ubi->mtd->read(ubi->mtd, addr, len, &read, buf);
+	err = mtd_read(ubi->mtd, addr, len, &read, buf);
 	if (err) {
 		if (err == -EUCLEAN) {
 			/*
@@ -268,7 +268,7 @@
 	}
 
 	addr = (loff_t)pnum * ubi->peb_size + offset;
-	err = ubi->mtd->write(ubi->mtd, addr, len, &written, buf);
+	err = mtd_write(ubi->mtd, addr, len, &written, buf);
 	if (err) {
 		ubi_err("error %d while writing %d bytes to PEB %d:%d, written"
 			" %zd bytes", err, len, pnum, offset, written);
@@ -318,7 +318,7 @@
 	ei.callback = erase_callback;
 	ei.priv     = (unsigned long)&wq;
 
-	err = ubi->mtd->erase(ubi->mtd, &ei);
+	err = mtd_erase(ubi->mtd, &ei);
 	if (err) {
 		if (retries++ < UBI_IO_RETRIES) {
 			dbg_io("error %d while erasing PEB %d, retry",
@@ -516,7 +516,7 @@
 	if (ubi->bad_allowed) {
 		int ret;
 
-		ret = mtd->block_isbad(mtd, (loff_t)pnum * ubi->peb_size);
+		ret = mtd_block_isbad(mtd, (loff_t)pnum * ubi->peb_size);
 		if (ret < 0)
 			ubi_err("error %d while checking if PEB %d is bad",
 				ret, pnum);
@@ -551,7 +551,7 @@
 	if (!ubi->bad_allowed)
 		return 0;
 
-	err = mtd->block_markbad(mtd, (loff_t)pnum * ubi->peb_size);
+	err = mtd_block_markbad(mtd, (loff_t)pnum * ubi->peb_size);
 	if (err)
 		ubi_err("cannot mark PEB %d bad, error %d", pnum, err);
 	return err;
@@ -1242,7 +1242,7 @@
 	loff_t addr = (loff_t)pnum * ubi->peb_size + offset;
 
 	mutex_lock(&ubi->dbg_buf_mutex);
-	err = ubi->mtd->read(ubi->mtd, addr, len, &read, ubi->dbg_peb_buf);
+	err = mtd_read(ubi->mtd, addr, len, &read, ubi->dbg_peb_buf);
 	if (err && err != -EUCLEAN) {
 		ubi_err("error %d while reading %d bytes from PEB %d:%d, "
 			"read %zd bytes", err, len, pnum, offset, read);
diff --git a/drivers/mtd/ubi/kapi.c b/drivers/mtd/ubi/kapi.c
index 423d479..e553188 100644
--- a/drivers/mtd/ubi/kapi.c
+++ b/drivers/mtd/ubi/kapi.c
@@ -349,7 +349,7 @@
 		return 0;
 
 	err = ubi_eba_read_leb(ubi, vol, lnum, buf, offset, len, check);
-	if (err && err == -EBADMSG && vol->vol_type == UBI_STATIC_VOLUME) {
+	if (err && mtd_is_eccerr(err) && vol->vol_type == UBI_STATIC_VOLUME) {
 		ubi_warn("mark volume %d as corrupted", vol_id);
 		vol->corrupted = 1;
 	}
diff --git a/drivers/mtd/ubi/misc.c b/drivers/mtd/ubi/misc.c
index a6410bf..e8660d9 100644
--- a/drivers/mtd/ubi/misc.c
+++ b/drivers/mtd/ubi/misc.c
@@ -82,7 +82,7 @@
 
 		err = ubi_eba_read_leb(ubi, vol, i, buf, 0, size, 1);
 		if (err) {
-			if (err == -EBADMSG)
+			if (mtd_is_eccerr(err))
 				err = 1;
 			break;
 		}
diff --git a/drivers/mtd/ubi/vtbl.c b/drivers/mtd/ubi/vtbl.c
index f679f06..29d2320 100644
--- a/drivers/mtd/ubi/vtbl.c
+++ b/drivers/mtd/ubi/vtbl.c
@@ -388,7 +388,7 @@
 
 		err = ubi_io_read_data(ubi, leb[seb->lnum], seb->pnum, 0,
 				       ubi->vtbl_size);
-		if (err == UBI_IO_BITFLIPS || err == -EBADMSG)
+		if (err == UBI_IO_BITFLIPS || mtd_is_eccerr(err))
 			/*
 			 * Scrub the PEB later. Note, -EBADMSG indicates an
 			 * uncorrectable ECC error, but we have our own CRC and
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index c63398e..0ffd59d 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -122,8 +122,6 @@
 {
 	int i;
 	int result = 0;
-	unsigned int *buf;
-	buf = (unsigned int *)packet;
 
 	if (length <= 0) {
 		printf("Ethernet: bad packet size: %d\n", length);
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 7a36850..379b679 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -109,7 +109,13 @@
 	u32	flow_thresh;
 	u32	port_vlan;
 	u32	tx_pri_map;
+#ifdef CONFIG_AM33XX
 	u32	gap_thresh;
+#elif defined(CONFIG_TI814X)
+	u32	ts_ctl;
+	u32	ts_seq_ltype;
+	u32	ts_vlan;
+#endif
 	u32	sa_lo;
 	u32	sa_hi;
 };
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index f191c79..9aaa828 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -46,6 +46,7 @@
 COBJS-$(CONFIG_PPC_P5020) += p5020.o
 COBJS-$(CONFIG_PPC_P5040) += p5040.o
 COBJS-$(CONFIG_PPC_T4240) += t4240.o
+COBJS-$(CONFIG_PPC_T4160) += t4240.o
 COBJS-$(CONFIG_PPC_B4420) += b4860.o
 COBJS-$(CONFIG_PPC_B4860) += b4860.o
 endif
diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c
index 8cde7af..3b5defe 100644
--- a/drivers/net/fm/b4860.c
+++ b/drivers/net/fm/b4860.c
@@ -55,8 +55,10 @@
 	if (is_device_disabled(port))
 		return PHY_INTERFACE_MODE_NONE;
 
-	if ((port == FM1_10GEC1 || port == FM1_10GEC2)
-			&& (is_serdes_configured(XAUI_FM1)))
+	/*B4860 has two 10Gig Mac*/
+	if ((port == FM1_10GEC1 || port == FM1_10GEC2)	&&
+	    ((is_serdes_configured(XAUI_FM1_MAC9))	||
+	    (is_serdes_configured(XAUI_FM1_MAC10))))
 		return PHY_INTERFACE_MODE_XGMII;
 
 	/* Fix me need to handle RGMII here first */
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 54b142f..9b139ee 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -568,6 +568,8 @@
 	num = fm_eth->num;
 
 #ifdef CONFIG_SYS_FMAN_V3
+	if (fm_eth->type == FM_ETH_10G_E)
+		num += 8;
 	base = &reg->memac[num].fm_memac;
 	phyregs = &reg->memac[num].fm_memac_mdio;
 #else
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 228df33..ba581e9 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -152,4 +152,6 @@
 #define MAX_RXBUF_LOG2		11
 #define MAX_RXBUF_LEN		(1 << MAX_RXBUF_LOG2)
 
+#define PORT_IS_ENABLED(port)	fm_info[fm_port_to_index(port)].enabled
+
 #endif /* __FM_H__ */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index ae389b8..5908c32 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -74,9 +74,15 @@
 #if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
 	FM_TGEC_INFO_INITIALIZER(1, 1),
 #endif
+#if (CONFIG_SYS_NUM_FM1_10GEC >= 2)
+	FM_TGEC_INFO_INITIALIZER(1, 2),
+#endif
 #if (CONFIG_SYS_NUM_FM2_10GEC >= 1)
 	FM_TGEC_INFO_INITIALIZER(2, 1),
 #endif
+#if (CONFIG_SYS_NUM_FM2_10GEC >= 2)
+	FM_TGEC_INFO_INITIALIZER(2, 2),
+#endif
 };
 
 int fm_standard_init(bd_t *bis)
@@ -232,6 +238,26 @@
 		return ;
 	}
 
+#ifdef CONFIG_SYS_FMAN_V3
+	/*
+	 * Physically FM1_DTSEC9 and FM1_10GEC1 use the same dual-role MAC, when
+	 * FM1_10GEC1 is enabled and  FM1_DTSEC9 is disabled, ensure that the
+	 * dual-role MAC is not disabled, ditto for other dual-role MACs.
+	 */
+	if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1)))	||
+	    ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2)))	||
+	    ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9)))	||
+	    ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10)))
+#if (CONFIG_SYS_NUM_FMAN == 2)
+										||
+	    ((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1)))	||
+	    ((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2)))	||
+	    ((info->port == FM2_10GEC1) && (PORT_IS_ENABLED(FM2_DTSEC9)))	||
+	    ((info->port == FM2_10GEC2) && (PORT_IS_ENABLED(FM2_DTSEC10)))
+#endif
+	)
+		return;
+#endif
 	/* board code might have caused offset to change */
 	off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
 
@@ -249,10 +275,15 @@
 {
 	int i;
 
+#ifdef CONFIG_SYS_FMAN_V3
+	for (i = 0; i < ARRAY_SIZE(fm_info); i++)
+		ft_fixup_port(blob, &fm_info[i], "fsl,fman-memac");
+#else
 	for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
 		if (fm_info[i].type == FM_ETH_1G_E)
 			ft_fixup_port(blob, &fm_info[i], "fsl,fman-1g-mac");
 		else
 			ft_fixup_port(blob, &fm_info[i], "fsl,fman-10g-mac");
 	}
+#endif
 }
diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c
index 48c530c..275395f 100644
--- a/drivers/net/fm/t4240.c
+++ b/drivers/net/fm/t4240.c
@@ -70,12 +70,18 @@
 	if (is_device_disabled(port))
 		return PHY_INTERFACE_MODE_NONE;
 
-	if ((port == FM1_10GEC1 || port == FM1_10GEC2)
-			&& (is_serdes_configured(XAUI_FM1)))
+	if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
+	    ((is_serdes_configured(XAUI_FM1_MAC9))	||
+	     (is_serdes_configured(XAUI_FM1_MAC10))	||
+	     (is_serdes_configured(XFI_FM1_MAC9))	||
+	     (is_serdes_configured(XFI_FM1_MAC10))))
 		return PHY_INTERFACE_MODE_XGMII;
 
-	if ((port == FM2_10GEC1 || port == FM2_10GEC2)
-			&& (is_serdes_configured(XAUI_FM2)))
+	if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
+	    ((is_serdes_configured(XAUI_FM2_MAC9))	||
+	     (is_serdes_configured(XAUI_FM2_MAC10))	||
+	     (is_serdes_configured(XFI_FM2_MAC9))	||
+	     (is_serdes_configured(XFI_FM2_MAC10))))
 		return PHY_INTERFACE_MODE_XGMII;
 
 #define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 5e90d70..af5f4b8 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -34,6 +34,7 @@
 COBJS-$(CONFIG_PHY_ATHEROS) += atheros.o
 COBJS-$(CONFIG_PHY_BROADCOM) += broadcom.o
 COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o
+COBJS-$(CONFIG_PHY_ET1011C) += et1011c.o
 COBJS-$(CONFIG_PHY_LXT) += lxt.o
 COBJS-$(CONFIG_PHY_MARVELL) += marvell.o
 COBJS-$(CONFIG_PHY_MICREL) += micrel.o
diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c
new file mode 100644
index 0000000..5e22399
--- /dev/null
+++ b/drivers/net/phy/et1011c.c
@@ -0,0 +1,110 @@
+/*
+ * ET1011C PHY driver
+ *
+ * Derived from Linux kernel driver by Chaithrika U S
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <config.h>
+#include <phy.h>
+
+#define ET1011C_CONFIG_REG		(0x16)
+#define ET1011C_TX_FIFO_MASK		(0x3 << 12)
+#define ET1011C_TX_FIFO_DEPTH_8		(0x0 << 12)
+#define ET1011C_TX_FIFO_DEPTH_16	(0x1 << 12)
+#define ET1011C_INTERFACE_MASK		(0x7 << 0)
+#define ET1011C_GMII_INTERFACE		(0x2 << 0)
+#define ET1011C_SYS_CLK_EN		(0x1 << 4)
+#define ET1011C_TX_CLK_EN		(0x1 << 5)
+
+#define ET1011C_STATUS_REG		(0x1A)
+#define ET1011C_DUPLEX_STATUS		(0x1 << 7)
+#define ET1011C_SPEED_MASK		(0x3 << 8)
+#define ET1011C_SPEED_1000		(0x2 << 8)
+#define ET1011C_SPEED_100		(0x1 << 8)
+#define ET1011C_SPEED_10		(0x0 << 8)
+
+static int et1011c_config(struct phy_device *phydev)
+{
+	int ctl = 0;
+	ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+	if (ctl < 0)
+		return ctl;
+	ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 |
+		 BMCR_ANENABLE);
+	/* First clear the PHY */
+	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET);
+
+	return genphy_config_aneg(phydev);
+}
+
+static int et1011c_parse_status(struct phy_device *phydev)
+{
+	int mii_reg;
+	int speed;
+
+	mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG);
+
+	if (mii_reg & ET1011C_DUPLEX_STATUS)
+		phydev->duplex = DUPLEX_FULL;
+	else
+		phydev->duplex = DUPLEX_HALF;
+
+	speed = mii_reg & ET1011C_SPEED_MASK;
+	switch (speed) {
+	case ET1011C_SPEED_1000:
+		phydev->speed = SPEED_1000;
+		mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG);
+		mii_reg &= ~ET1011C_TX_FIFO_MASK;
+		phy_write(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG,
+			  mii_reg |
+			  ET1011C_GMII_INTERFACE |
+			  ET1011C_SYS_CLK_EN |
+#ifdef CONFIG_PHY_ET1011C_TX_CLK_FIX
+			  ET1011C_TX_CLK_EN |
+#endif
+			  ET1011C_TX_FIFO_DEPTH_16);
+		break;
+	case ET1011C_SPEED_100:
+		phydev->speed = SPEED_100;
+		break;
+	case ET1011C_SPEED_10:
+		phydev->speed = SPEED_10;
+		break;
+	}
+
+	return 0;
+}
+
+static int et1011c_startup(struct phy_device *phydev)
+{
+	genphy_update_link(phydev);
+	et1011c_parse_status(phydev);
+	return 0;
+}
+
+static struct phy_driver et1011c_driver = {
+	.name		= "ET1011C",
+	.uid		= 0x0282f014,
+	.mask		= 0xfffffff0,
+	.features	= PHY_GBIT_FEATURES,
+	.config		= &et1011c_config,
+	.startup	= &et1011c_startup,
+};
+
+int phy_et1011c_init(void)
+{
+	phy_register(&et1011c_driver);
+
+	return 0;
+}
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 4b27198..46801c7 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -465,6 +465,16 @@
 	.shutdown = &genphy_shutdown,
 };
 
+static struct phy_driver M88E1518_driver = {
+	.name = "Marvell 88E1518",
+	.uid = 0x1410dd1,
+	.mask = 0xffffff0,
+	.features = PHY_GBIT_FEATURES,
+	.config = &m88e1111s_config,
+	.startup = &m88e1011s_startup,
+	.shutdown = &genphy_shutdown,
+};
+
 int phy_marvell_init(void)
 {
 	phy_register(&M88E1149S_driver);
@@ -474,6 +484,7 @@
 	phy_register(&M88E1118R_driver);
 	phy_register(&M88E1111S_driver);
 	phy_register(&M88E1011S_driver);
+	phy_register(&M88E1518_driver);
 
 	return 0;
 }
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index d0ed766..f8c5481 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -430,6 +430,9 @@
 #ifdef CONFIG_PHY_DAVICOM
 	phy_davicom_init();
 #endif
+#ifdef CONFIG_PHY_ET1011C
+	phy_et1011c_init();
+#endif
 #ifdef CONFIG_PHY_LXT
 	phy_lxt_init();
 #endif
diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c
index 78447b7..84ce736 100644
--- a/drivers/net/phy/teranetics.c
+++ b/drivers/net/phy/teranetics.c
@@ -34,9 +34,21 @@
 		unsigned short restart_an = (MDIO_AN_CTRL1_RESTART |
 						MDIO_AN_CTRL1_ENABLE |
 						MDIO_AN_CTRL1_XNP);
+		u8 phy_hwversion;
 
-		phy_write(phydev, 30, 93, 2);
-		phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an);
+		/*
+		 * bit 15:12 of register 30.32 indicates PHY hardware
+		 * version. It can be used to distinguish TN80xx from
+		 * TN2020. TN2020 needs write 0x2 to 30.93, but TN80xx
+		 * needs 0x1.
+		 */
+		phy_hwversion = (phy_read(phydev, 30, 32) >> 12) & 0xf;
+		if (phy_hwversion <= 3) {
+			phy_write(phydev, 30, 93, 2);
+			phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an);
+		} else {
+			phy_write(phydev, 30, 93, 1);
+		}
 	}
 
 	return 0;
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 6c5cb99..c283d82 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -48,6 +48,19 @@
 #define MIIM_VSC8601_SKEW_CTRL		0x1c
 
 #define PHY_EXT_PAGE_ACCESS    0x1f
+#define PHY_EXT_PAGE_ACCESS_GENERAL	0x10
+#define PHY_EXT_PAGE_ACCESS_EXTENDED3	0x3
+
+/* Vitesse VSC8574 control register */
+#define MIIM_VSC8574_MAC_SERDES_CON	0x10
+#define MIIM_VSC8574_MAC_SERDES_ANEG	0x80
+#define MIIM_VSC8574_GENERAL18		0x12
+#define MIIM_VSC8574_GENERAL19		0x13
+
+/* Vitesse VSC8574 gerenal purpose register 18 */
+#define MIIM_VSC8574_18G_SGMII		0x80f0
+#define MIIM_VSC8574_18G_QSGMII		0x80e0
+#define MIIM_VSC8574_18G_CMDSTAT	0x8000
 
 /* CIS8201 */
 static int vitesse_config(struct phy_device *phydev)
@@ -145,6 +158,49 @@
 	return 0;
 }
 
+static int vsc8574_config(struct phy_device *phydev)
+{
+	u32 val;
+	/* configure regiser 19G for MAC */
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+		  PHY_EXT_PAGE_ACCESS_GENERAL);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19);
+	if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
+		/* set bit 15:14 to '01' for QSGMII mode */
+		val = (val & 0x3fff) | (1 << 14);
+		phy_write(phydev, MDIO_DEVAD_NONE,
+			  MIIM_VSC8574_GENERAL19, val);
+		/* Enable 4 ports MAC QSGMII */
+		phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
+			  MIIM_VSC8574_18G_QSGMII);
+	} else {
+		/* set bit 15:14 to '00' for SGMII mode */
+		val = val & 0x3fff;
+		phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19, val);
+		/* Enable 4 ports MAC SGMII */
+		phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
+			  MIIM_VSC8574_18G_SGMII);
+	}
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18);
+	/* When bit 15 is cleared the command has completed */
+	while (val & MIIM_VSC8574_18G_CMDSTAT)
+		val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18);
+
+	/* Enable Serdes Auto-negotiation */
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+		  PHY_EXT_PAGE_ACCESS_EXTENDED3);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON);
+	val = val | MIIM_VSC8574_MAC_SERDES_ANEG;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON, val);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+
+	genphy_config_aneg(phydev);
+
+	return 0;
+}
+
 static struct phy_driver VSC8211_driver = {
 	.name	= "Vitesse VSC8211",
 	.uid	= 0xfc4b0,
@@ -185,6 +241,16 @@
 	.shutdown = &genphy_shutdown,
 };
 
+static struct phy_driver VSC8574_driver = {
+	.name = "Vitesse VSC8574",
+	.uid = 0x704a0,
+	.mask = 0xffff0,
+	.features = PHY_GBIT_FEATURES,
+	.config = &vsc8574_config,
+	.startup = &vitesse_startup,
+	.shutdown = &genphy_shutdown,
+};
+
 static struct phy_driver VSC8601_driver = {
 	.name = "Vitesse VSC8601",
 	.uid = 0x70420,
@@ -244,6 +310,7 @@
 	phy_register(&VSC8244_driver);
 	phy_register(&VSC8211_driver);
 	phy_register(&VSC8221_driver);
+	phy_register(&VSC8574_driver);
 	phy_register(&VSC8662_driver);
 	phy_register(&cis8201_driver);
 	phy_register(&cis8204_driver);
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index a290073..f63a069 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -484,7 +484,7 @@
 		while (timeout-- &&
 			!(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
 			udelay(10);
-		if (!timeout) {
+		if (timeout < 0) {
 			printf(DRIVERNAME
 				": timeout waiting for PM restore\n");
 			return;
@@ -500,7 +500,7 @@
 	while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
 		udelay(10);
 
-	if (!timeout) {
+	if (timeout < 0) {
 		printf(DRIVERNAME ": reset timeout\n");
 		return;
 	}
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 3596065..eac9b6f 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -33,6 +33,8 @@
 #include <phy.h>
 #include <miiphy.h>
 #include <watchdog.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
 
 #if !defined(CONFIG_PHYLIB)
 # error XILINX_GEM_ETHERNET requires PHYLIB
@@ -67,13 +69,14 @@
 #define ZYNQ_GEM_NWCTRL_MDEN_MASK	0x00000010 /* Enable MDIO port */
 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK	0x00000200 /* Start tx (tx_go) */
 
-#define ZYNQ_GEM_NWCFG_SPEED		0x00000001 /* 100 Mbps operation */
-#define ZYNQ_GEM_NWCFG_FDEN		0x00000002 /* Full Duplex mode */
-#define ZYNQ_GEM_NWCFG_FSREM		0x00020000 /* FCS removal */
+#define ZYNQ_GEM_NWCFG_SPEED100		0x000000001 /* 100 Mbps operation */
+#define ZYNQ_GEM_NWCFG_SPEED1000	0x000000400 /* 1Gbps operation */
+#define ZYNQ_GEM_NWCFG_FDEN		0x000000002 /* Full Duplex mode */
+#define ZYNQ_GEM_NWCFG_FSREM		0x000020000 /* FCS removal */
 #define ZYNQ_GEM_NWCFG_MDCCLKDIV	0x000080000 /* Div pclk by 32, 80MHz */
+#define ZYNQ_GEM_NWCFG_MDCCLKDIV2	0x0000c0000 /* Div pclk by 48, 120MHz */
 
-#define ZYNQ_GEM_NWCFG_INIT		(ZYNQ_GEM_NWCFG_SPEED | \
-					ZYNQ_GEM_NWCFG_FDEN | \
+#define ZYNQ_GEM_NWCFG_INIT		(ZYNQ_GEM_NWCFG_FDEN | \
 					ZYNQ_GEM_NWCFG_FSREM | \
 					ZYNQ_GEM_NWCFG_MDCCLKDIV)
 
@@ -92,6 +95,17 @@
 					ZYNQ_GEM_DMACR_TXSIZE | \
 					ZYNQ_GEM_DMACR_RXBUF)
 
+/* Use MII register 1 (MII status register) to detect PHY */
+#define PHY_DETECT_REG  1
+
+/* Mask used to verify certain PHY features (or register contents)
+ * in the register above:
+ *  0x1000: 10Mbps full duplex support
+ *  0x0800: 10Mbps half duplex support
+ *  0x0008: Auto-negotiation support
+ */
+#define PHY_DETECT_MASK 0x1808
+
 /* Device registers */
 struct zynq_gem_regs {
 	u32 nwctrl; /* Network Control reg */
@@ -134,6 +148,8 @@
 	u32 rxbd_current;
 	u32 rx_first_buf;
 	int phyaddr;
+	u32 emio;
+	int init;
 	struct phy_device *phydev;
 	struct mii_dev *bus;
 };
@@ -196,6 +212,44 @@
 				ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
 }
 
+static void phy_detection(struct eth_device *dev)
+{
+	int i;
+	u16 phyreg;
+	struct zynq_gem_priv *priv = dev->priv;
+
+	if (priv->phyaddr != -1) {
+		phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
+		if ((phyreg != 0xFFFF) &&
+		    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
+			/* Found a valid PHY address */
+			debug("Default phy address %d is valid\n",
+			      priv->phyaddr);
+			return;
+		} else {
+			debug("PHY address is not setup correctly %d\n",
+			      priv->phyaddr);
+			priv->phyaddr = -1;
+		}
+	}
+
+	debug("detecting phy address\n");
+	if (priv->phyaddr == -1) {
+		/* detect the PHY address */
+		for (i = 31; i >= 0; i--) {
+			phyread(dev, i, PHY_DETECT_REG, &phyreg);
+			if ((phyreg != 0xFFFF) &&
+			    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
+				/* Found a valid PHY address */
+				priv->phyaddr = i;
+				debug("Found valid phy address, %d\n", i);
+				return;
+			}
+		}
+	}
+	printf("PHY is not detected\n");
+}
+
 static int zynq_gem_setup_mac(struct eth_device *dev)
 {
 	u32 i, macaddrlow, macaddrhigh;
@@ -226,7 +280,7 @@
 
 static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
 {
-	u32 i;
+	u32 i, rclk, clk = 0;
 	struct phy_device *phydev;
 	const u32 stat_size = (sizeof(struct zynq_gem_regs) -
 				offsetof(struct zynq_gem_regs, stat)) / 4;
@@ -239,59 +293,92 @@
 			SUPPORTED_1000baseT_Half |
 			SUPPORTED_1000baseT_Full;
 
-	/* Disable all interrupts */
-	writel(0xFFFFFFFF, &regs->idr);
+	if (!priv->init) {
+		/* Disable all interrupts */
+		writel(0xFFFFFFFF, &regs->idr);
 
-	/* Disable the receiver & transmitter */
-	writel(0, &regs->nwctrl);
-	writel(0, &regs->txsr);
-	writel(0, &regs->rxsr);
-	writel(0, &regs->phymntnc);
+		/* Disable the receiver & transmitter */
+		writel(0, &regs->nwctrl);
+		writel(0, &regs->txsr);
+		writel(0, &regs->rxsr);
+		writel(0, &regs->phymntnc);
 
-	/* Clear the Hash registers for the mac address pointed by AddressPtr */
-	writel(0x0, &regs->hashl);
-	/* Write bits [63:32] in TOP */
-	writel(0x0, &regs->hashh);
+		/* Clear the Hash registers for the mac address
+		 * pointed by AddressPtr
+		 */
+		writel(0x0, &regs->hashl);
+		/* Write bits [63:32] in TOP */
+		writel(0x0, &regs->hashh);
 
-	/* Clear all counters */
-	for (i = 0; i <= stat_size; i++)
-		readl(&regs->stat[i]);
+		/* Clear all counters */
+		for (i = 0; i <= stat_size; i++)
+			readl(&regs->stat[i]);
 
-	/* Setup RxBD space */
-	memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd));
-	/* Create the RxBD ring */
-	memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers));
+		/* Setup RxBD space */
+		memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd));
+		/* Create the RxBD ring */
+		memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers));
 
-	for (i = 0; i < RX_BUF; i++) {
-		priv->rx_bd[i].status = 0xF0000000;
-		priv->rx_bd[i].addr = (u32)((char *) &(priv->rxbuffers) +
+		for (i = 0; i < RX_BUF; i++) {
+			priv->rx_bd[i].status = 0xF0000000;
+			priv->rx_bd[i].addr =
+					(u32)((char *)&(priv->rxbuffers) +
 							(i * PKTSIZE_ALIGN));
+		}
+		/* WRAP bit to last BD */
+		priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
+		/* Write RxBDs to IP */
+		writel((u32)&(priv->rx_bd), &regs->rxqbase);
+
+		/* Setup for DMA Configuration register */
+		writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
+
+		/* Setup for Network Control register, MDIO, Rx and Tx enable */
+		setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
+
+		priv->init++;
 	}
-	/* WRAP bit to last BD */
-	priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
-	/* Write RxBDs to IP */
-	writel((u32) &(priv->rx_bd), &regs->rxqbase);
 
-	/* MAC Setup */
-	/* Setup Network Configuration register */
-	writel(ZYNQ_GEM_NWCFG_INIT, &regs->nwcfg);
-
-	/* Setup for DMA Configuration register */
-	writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
-
-	/* Setup for Network Control register, MDIO, Rx and Tx enable */
-	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK |
-			ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK);
+	phy_detection(dev);
 
 	/* interface - look at tsec */
 	phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
 
-	phydev->supported &= supported;
+	phydev->supported = supported | ADVERTISED_Pause |
+			    ADVERTISED_Asym_Pause;
 	phydev->advertising = phydev->supported;
 	priv->phydev = phydev;
 	phy_config(phydev);
 	phy_startup(phydev);
 
+	switch (phydev->speed) {
+	case SPEED_1000:
+		writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
+		       &regs->nwcfg);
+		rclk = (0 << 4) | (1 << 0);
+		clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+		break;
+	case SPEED_100:
+		clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
+				ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
+		rclk = 1 << 0;
+		clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+		break;
+	case SPEED_10:
+		rclk = 1 << 0;
+		/* FIXME untested */
+		clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+		break;
+	}
+
+	/* Change the rclk and clk only not using EMIO interface */
+	if (!priv->emio)
+		zynq_slcr_gem_clk_setup(dev->iobase !=
+					ZYNQ_GEM_BASEADDR0, rclk, clk);
+
+	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
+					ZYNQ_GEM_NWCTRL_TXEN_MASK);
+
 	return 0;
 }
 
@@ -307,11 +394,10 @@
 	writel((u32)&(priv->tx_bd), &regs->txqbase);
 
 	/* Setup Tx BD */
-	memset((void *) &(priv->tx_bd), 0, sizeof(struct emac_bd));
+	memset((void *)&(priv->tx_bd), 0, sizeof(struct emac_bd));
 
 	priv->tx_bd.addr = (u32)ptr;
-	priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK |
-						ZYNQ_GEM_TXBUF_WRAP_MASK;
+	priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK;
 
 	/* Start transmit */
 	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
@@ -364,19 +450,17 @@
 
 		if ((++priv->rxbd_current) >= RX_BUF)
 			priv->rxbd_current = 0;
-
-		return frame_len;
 	}
 
-	return 0;
+	return frame_len;
 }
 
 static void zynq_gem_halt(struct eth_device *dev)
 {
 	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 
-	/* Disable the receiver & transmitter */
-	writel(0, &regs->nwctrl);
+	clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
+						ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
 }
 
 static int zynq_gem_miiphyread(const char *devname, uchar addr,
@@ -399,7 +483,7 @@
 	return phywrite(dev, addr, reg, val);
 }
 
-int zynq_gem_initialize(bd_t *bis, int base_addr)
+int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
 {
 	struct eth_device *dev;
 	struct zynq_gem_priv *priv;
@@ -415,11 +499,8 @@
 	}
 	priv = dev->priv;
 
-#ifdef CONFIG_PHY_ADDR
-	priv->phyaddr = CONFIG_PHY_ADDR;
-#else
-	priv->phyaddr = -1;
-#endif
+	priv->phyaddr = phy_addr;
+	priv->emio = emio;
 
 	sprintf(dev->name, "Gem.%x", base_addr);
 
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 1dac16a..a9c4237 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -30,7 +30,7 @@
 COBJS-$(CONFIG_TPS6586X_POWER)	+= tps6586x.o
 COBJS-$(CONFIG_TWL4030_POWER)	+= twl4030.o
 COBJS-$(CONFIG_TWL6030_POWER)	+= twl6030.o
-COBJS-$(CONFIG_TWL6035_POWER)	+= twl6035.o
+COBJS-$(CONFIG_PALMAS_POWER)	+= palmas.o
 
 COBJS-$(CONFIG_POWER) += power_core.o
 COBJS-$(CONFIG_DIALOG_POWER) += power_dialog.o
diff --git a/drivers/power/twl6035.c b/drivers/power/palmas.c
similarity index 61%
rename from drivers/power/twl6035.c
rename to drivers/power/palmas.c
index d3de698..09c832d 100644
--- a/drivers/power/twl6035.c
+++ b/drivers/power/palmas.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2012
+ * (C) Copyright 2012-2013
  * Texas Instruments, <www.ti.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -21,43 +21,21 @@
  * MA 02111-1307 USA
  */
 #include <config.h>
-#include <twl6035.h>
+#include <palmas.h>
 
-/* Functions to read and write from TWL6030 */
-int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg)
-{
-	return i2c_write(chip_no, reg, 1, &val, 1);
-}
-
-int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg)
-{
-	return i2c_read(chip_no, reg, 1, val, 1);
-}
-
-/* To align with i2c mw/mr address, reg, val command syntax */
-static inline int palmas_write_u8(u8 chip_no, u8 reg, u8 val)
-{
-	return i2c_write(chip_no, reg, 1, &val, 1);
-}
-
-static inline int palmas_read_u8(u8 chip_no, u8 reg, u8 *val)
-{
-	return i2c_read(chip_no, reg, 1, val, 1);
-}
-
-void twl6035_init_settings(void)
+void palmas_init_settings(void)
 {
 	return;
 }
 
-int twl6035_mmc1_poweron_ldo(void)
+int palmas_mmc1_poweron_ldo(void)
 {
 	u8 val = 0;
 
 	/* set LDO9 TWL6035 to 3V */
 	val = 0x2b; /* (3 -.9)*28 +1 */
 
-	if (palmas_write_u8(0x48, LDO9_VOLTAGE, val)) {
+	if (palmas_i2c_write_u8(0x48, LDO9_VOLTAGE, val)) {
 		printf("twl6035: could not set LDO9 voltage.\n");
 		return 1;
 	}
@@ -65,7 +43,7 @@
 	/* TURN ON LDO9 */
 	val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
 
-	if (palmas_write_u8(0x48, LDO9_CTRL, val)) {
+	if (palmas_i2c_write_u8(0x48, LDO9_CTRL, val)) {
 		printf("twl6035: could not turn on LDO9.\n");
 		return 1;
 	}
diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c
index e7d5f13..6610f78 100644
--- a/drivers/power/twl4030.c
+++ b/drivers/power/twl4030.c
@@ -45,14 +45,14 @@
 void twl4030_power_reset_init(void)
 {
 	u8 val = 0;
-	if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val,
-				TWL4030_PM_MASTER_P1_SW_EVENTS)) {
+	if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+				TWL4030_PM_MASTER_P1_SW_EVENTS, &val)) {
 		printf("Error:TWL4030: failed to read the power register\n");
 		printf("Could not initialize hardware reset\n");
 	} else {
 		val |= TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON;
-		if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, val,
-					 TWL4030_PM_MASTER_P1_SW_EVENTS)) {
+		if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+					 TWL4030_PM_MASTER_P1_SW_EVENTS, val)) {
 			printf("Error:TWL4030: failed to write the power register\n");
 			printf("Could not initialize hardware reset\n");
 		}
@@ -68,8 +68,8 @@
 	int ret;
 
 	/* Select the Voltage */
-	ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val,
-				vsel_reg);
+	ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_reg,
+				   vsel_val);
 	if (ret != 0) {
 		printf("Could not write vsel to reg %02x (%d)\n",
 			vsel_reg, ret);
@@ -77,8 +77,8 @@
 	}
 
 	/* Select the Device Group (enable the supply if dev_grp_sel != 0) */
-	ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel,
-				dev_grp);
+	ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp,
+				   dev_grp_sel);
 	if (ret != 0)
 		printf("Could not write grp_sel to reg %02x (%d)\n",
 			dev_grp, ret);
diff --git a/drivers/power/twl6030.c b/drivers/power/twl6030.c
index c5a0038..d421e60 100644
--- a/drivers/power/twl6030.c
+++ b/drivers/power/twl6030.c
@@ -25,30 +25,19 @@
 
 #include <twl6030.h>
 
-/* Functions to read and write from TWL6030 */
-static inline int twl6030_i2c_write_u8(u8 chip_no, u8 val, u8 reg)
-{
-	return i2c_write(chip_no, reg, 1, &val, 1);
-}
-
-static inline int twl6030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg)
-{
-	return i2c_read(chip_no, reg, 1, val, 1);
-}
-
 static int twl6030_gpadc_read_channel(u8 channel_no)
 {
 	u8 lsb = 0;
 	u8 msb = 0;
 	int ret = 0;
 
-	ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &lsb,
-				GPCH0_LSB + channel_no * 2);
+	ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
+				  GPCH0_LSB + channel_no * 2, &lsb);
 	if (ret)
 		return ret;
 
-	ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &msb,
-				GPCH0_MSB + channel_no * 2);
+	ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
+				  GPCH0_MSB + channel_no * 2, &msb);
 	if (ret)
 		return ret;
 
@@ -60,7 +49,7 @@
 	u8 val;
 	int ret = 0;
 
-	ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, CTRL_P2_SP2, CTRL_P2);
+	ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, CTRL_P2, CTRL_P2_SP2);
 	if (ret)
 		return ret;
 
@@ -68,7 +57,7 @@
 	val =  CTRL_P2_BUSY;
 
 	while (!((val & CTRL_P2_EOCP2) && (!(val & CTRL_P2_BUSY)))) {
-		ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &val, CTRL_P2);
+		ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, CTRL_P2, &val);
 		if (ret)
 			return ret;
 		udelay(1000);
@@ -79,29 +68,29 @@
 
 void twl6030_stop_usb_charging(void)
 {
-	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, 0, CONTROLLER_CTRL1);
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CONTROLLER_CTRL1, 0);
 
 	return;
 }
 
 void twl6030_start_usb_charging(void)
 {
-	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VICHRG_1500,
-							CHARGERUSB_VICHRG);
-	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CIN_LIMIT_NONE,
-							CHARGERUSB_CINLIMIT);
-	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, MBAT_TEMP,
-							CONTROLLER_INT_MASK);
-	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, MASK_MCHARGERUSB_THMREG,
-							CHARGERUSB_INT_MASK);
-	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VOREG_4P0,
-							CHARGERUSB_VOREG);
-	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CTRL2_VITERM_400,
-							CHARGERUSB_CTRL2);
-	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TERM, CHARGERUSB_CTRL1);
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
+			     CHARGERUSB_VICHRG, CHARGERUSB_VICHRG_1500);
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
+			     CHARGERUSB_CINLIMIT, CHARGERUSB_CIN_LIMIT_NONE);
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
+			     CONTROLLER_INT_MASK, MBAT_TEMP);
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
+			     CHARGERUSB_INT_MASK, MASK_MCHARGERUSB_THMREG);
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
+			     CHARGERUSB_VOREG, CHARGERUSB_VOREG_4P0);
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
+			     CHARGERUSB_CTRL2, CHARGERUSB_CTRL2_VITERM_400);
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CTRL1, TERM);
 	/* Enable USB charging */
-	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CONTROLLER_CTRL1_EN_CHARGER,
-							CONTROLLER_CTRL1);
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
+			     CONTROLLER_CTRL1, CONTROLLER_CTRL1_EN_CHARGER);
 	return;
 }
 
@@ -111,8 +100,8 @@
 	u8 msb = 0;
 	u8 lsb = 0;
 
-	twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &msb, FG_REG_11);
-	twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &lsb, FG_REG_10);
+	twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, FG_REG_11, &msb);
+	twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, FG_REG_10, &lsb);
 	battery_current = ((msb << 8) | lsb);
 
 	/* convert 10 bit signed number to 16 bit signed number */
@@ -156,10 +145,10 @@
 	int ret = 0;
 
 	/* Enable VBAT measurement */
-	twl6030_i2c_write_u8(TWL6030_CHIP_PM, VBAT_MEAS, MISC1);
+	twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS);
 
 	/* Enable GPADC module */
-	ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, FGS | GPADCS, TOGGLE1);
+	ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TOGGLE1, FGS | GPADCS);
 	if (ret) {
 		printf("Failed to enable GPADC\n");
 		return;
@@ -173,7 +162,7 @@
 		printf("Main battery voltage too low!\n");
 
 	/* Check for the presence of USB charger */
-	twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &stat1, CONTROLLER_STAT1);
+	twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, CONTROLLER_STAT1, &stat1);
 
 	/* check for battery presence indirectly via Fuel gauge */
 	if ((stat1 & VBUS_DET) && (battery_volt < 3300))
@@ -185,8 +174,8 @@
 void twl6030_power_mmc_init()
 {
 	/* set voltage to 3.0 and turnon for APP */
-	twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x15, VMMC_CFG_VOLTATE);
-	twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x21, VMMC_CFG_STATE);
+	twl6030_i2c_write_u8(TWL6030_CHIP_PM, VMMC_CFG_VOLTATE, 0x15);
+	twl6030_i2c_write_u8(TWL6030_CHIP_PM, VMMC_CFG_STATE, 0x21);
 }
 
 void twl6030_usb_device_settings()
@@ -194,12 +183,12 @@
 	u8 data = 0;
 
 	/* Select APP Group and set state to ON */
-	twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x21, VUSB_CFG_STATE);
+	twl6030_i2c_write_u8(TWL6030_CHIP_PM, VUSB_CFG_STATE, 0x21);
 
-	twl6030_i2c_read_u8(TWL6030_CHIP_PM, &data, MISC2);
+	twl6030_i2c_read_u8(TWL6030_CHIP_PM, MISC2, &data);
 	data |= 0x10;
 
 	/* Select the input supply for VBUS regulator */
-	twl6030_i2c_write_u8(TWL6030_CHIP_PM, data, MISC2);
+	twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC2, data);
 }
 #endif
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index fbc4e97..442b7ea 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -52,6 +52,7 @@
 COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
 COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
 COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
+COBJS-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
 
 ifndef CONFIG_SPL_BUILD
 COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 9f04643..daa8003 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -143,7 +143,6 @@
 serial_initfunc(asc_serial_initialize);
 serial_initfunc(jz_serial_initialize);
 serial_initfunc(mpc5xx_serial_initialize);
-serial_initfunc(mpc8220_serial_initialize);
 serial_initfunc(mpc8260_scc_serial_initialize);
 serial_initfunc(mpc8260_smc_serial_initialize);
 serial_initfunc(mpc85xx_serial_initialize);
@@ -236,7 +235,6 @@
 	asc_serial_initialize();
 	jz_serial_initialize();
 	mpc5xx_serial_initialize();
-	mpc8220_serial_initialize();
 	mpc8260_scc_serial_initialize();
 	mpc8260_smc_serial_initialize();
 	mpc85xx_serial_initialize();
diff --git a/arch/blackfin/cpu/serial.c b/drivers/serial/serial_bfin.c
similarity index 78%
rename from arch/blackfin/cpu/serial.c
rename to drivers/serial/serial_bfin.c
index 9847e9f..0443b84 100644
--- a/arch/blackfin/cpu/serial.c
+++ b/drivers/serial/serial_bfin.c
@@ -43,13 +43,12 @@
 #include <serial.h>
 #include <linux/compiler.h>
 #include <asm/blackfin.h>
+#include <asm/serial.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_UART_CONSOLE
 
-#include "serial.h"
-
 #ifdef CONFIG_DEBUG_SERIAL
 static uart_lsr_t cached_lsr[256];
 static uart_lsr_t cached_rbr[256];
@@ -195,7 +194,18 @@
 
 #endif
 
-#ifdef CONFIG_SYS_BFIN_UART
+static inline void __serial_set_baud(uint32_t uart_base, uint32_t baud)
+{
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+	serial_early_set_baud(uart_base, baud);
+#else
+	uint16_t divisor = (get_uart_clk() + (baud * 8)) / (baud * 16)
+			- ANOMALY_05000230;
+
+	/* Program the divisor to get the baud rate we want */
+	serial_set_divisor(uart_base, divisor);
+#endif
+}
 
 static void uart_puts(uint32_t uart_base, const char *s)
 {
@@ -209,7 +219,7 @@
 	const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \
 	peripheral_request_list(pins, "bfin-uart"); \
 	uart_init(MMR_UART(n)); \
-	serial_early_set_baud(MMR_UART(n), gd->baudrate); \
+	__serial_set_baud(MMR_UART(n), gd->baudrate); \
 	uart_lsr_clear(MMR_UART(n)); \
 	return 0; \
 } \
@@ -221,7 +231,7 @@
 \
 static void uart##n##_setbrg(void) \
 { \
-	serial_early_set_baud(MMR_UART(n), gd->baudrate); \
+	__serial_set_baud(MMR_UART(n), gd->baudrate); \
 } \
 \
 static int uart##n##_getc(void) \
@@ -305,65 +315,97 @@
 #endif
 }
 
-#else
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+inline void uart_early_putc(uint32_t uart_base, const char c)
+{
+	/* send a \r for compatibility */
+	if (c == '\n')
+		uart_early_putc(uart_base, '\r');
+
+	/* wait for the hardware fifo to clear up */
+	while (!(_lsr_read(pUART) & THRE))
+		continue;
+
+	/* queue the character for transmission */
+	bfin_write(&pUART->thr, c);
+	SSYNC();
+}
+
+void uart_early_puts(const char *s)
+{
+	while (*s)
+		uart_early_putc(UART_BASE, *s++);
+}
 
 /* Symbol for our assembly to call. */
-void serial_set_baud(uint32_t baud)
+void _serial_early_set_baud(uint32_t baud)
 {
 	serial_early_set_baud(UART_BASE, baud);
 }
 
-/* Symbol for common u-boot code to call.
- * Setup the baudrate (brg: baudrate generator).
- */
-void serial_setbrg(void)
-{
-	serial_set_baud(gd->baudrate);
-}
-
 /* Symbol for our assembly to call. */
-void serial_initialize(void)
+void _serial_early_init(void)
 {
 	serial_early_init(UART_BASE);
 }
+#endif
 
-/* Symbol for common u-boot code to call. */
-int serial_init(void)
+#elif defined(CONFIG_UART_MEM)
+
+char serial_logbuf[CONFIG_UART_MEM];
+char *serial_logbuf_head = serial_logbuf;
+
+int serial_mem_init(void)
 {
-	serial_initialize();
-	serial_setbrg();
-	uart_lsr_clear(UART_BASE);
+	serial_logbuf_head = serial_logbuf;
 	return 0;
 }
 
-int serial_tstc(void)
+void serial_mem_setbrg(void)
 {
-	return uart_tstc(UART_BASE);
 }
 
-int serial_getc(void)
+int serial_mem_tstc(void)
 {
-	return uart_getc(UART_BASE);
+	return 0;
 }
 
-void serial_putc(const char c)
+int serial_mem_getc(void)
 {
-	uart_putc(UART_BASE, c);
+	return 0;
 }
 
-void serial_puts(const char *s)
+void serial_mem_putc(const char c)
+{
+	*serial_logbuf_head = c;
+	if (++serial_logbuf_head == serial_logbuf + CONFIG_UART_MEM)
+		serial_logbuf_head = serial_logbuf;
+}
+
+void serial_mem_puts(const char *s)
 {
 	while (*s)
 		serial_putc(*s++);
 }
 
-LOOP(
-void serial_loop(int state)
+struct serial_device bfin_serial_mem_device = {
+	.name   = "bfin_uart_mem",
+	.start  = serial_mem_init,
+	.setbrg = serial_mem_setbrg,
+	.getc   = serial_mem_getc,
+	.tstc   = serial_mem_tstc,
+	.putc   = serial_mem_putc,
+	.puts   = serial_mem_puts,
+};
+
+
+__weak struct serial_device *default_serial_console(void)
 {
-	uart_loop(UART_BASE, state);
+	return &bfin_serial_mem_device;
 }
-)
 
-#endif
-
-#endif
+void bfin_serial_initialize(void)
+{
+	serial_register(&bfin_serial_mem_device);
+}
+#endif /* CONFIG_UART_MEM */
diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index f4b1bad..52594e3 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -30,6 +30,15 @@
 
 #include "atmel_spi.h"
 
+static int spi_has_wdrbt(struct atmel_spi_slave *slave)
+{
+	unsigned int ver;
+
+	ver = spi_readl(slave, VERSION);
+
+	return (ATMEL_SPI_VERSION_REV(ver) >= 0x210);
+}
+
 void spi_init()
 {
 
@@ -90,10 +99,10 @@
 
 	as->regs = regs;
 	as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS
-#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9M10G45)
-			| ATMEL_SPI_MR_WDRBT
-#endif
 			| ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf);
+	if (spi_has_wdrbt(as))
+		as->mr |= ATMEL_SPI_MR_WDRBT;
+
 	spi_writel(as, CSR(cs), csrx);
 
 	return &as->slave;
diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h
index 057de9a..d240945 100644
--- a/drivers/spi/atmel_spi.h
+++ b/drivers/spi/atmel_spi.h
@@ -64,7 +64,7 @@
 #define ATMEL_SPI_CSRx_DLYBCT(x)	((x) << 24)
 
 /* Bits in VERSION */
-#define ATMEL_SPI_VERSION_REV(x)	((x) << 0)
+#define ATMEL_SPI_VERSION_REV(x)	((x) & 0xfff)
 #define ATMEL_SPI_VERSION_MFN(x)	((x) << 16)
 
 /* Constants for CSRx:BITS */
diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c
index ab2e8b9..a9a4d92 100644
--- a/drivers/spi/bfin_spi.c
+++ b/drivers/spi/bfin_spi.c
@@ -13,7 +13,6 @@
 #include <spi.h>
 
 #include <asm/blackfin.h>
-#include <asm/dma.h>
 #include <asm/gpio.h>
 #include <asm/portmux.h>
 #include <asm/mach-common/bits/spi.h>
@@ -242,109 +241,15 @@
 	SSYNC();
 }
 
-#ifdef __ADSPBF54x__
-# define SPI_DMA_BASE DMA4_NEXT_DESC_PTR
-#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \
-      defined(__ADSPBF538__) || defined(__ADSPBF539__)
-# define SPI_DMA_BASE DMA5_NEXT_DESC_PTR
-#elif defined(__ADSPBF561__)
-# define SPI_DMA_BASE DMA2_4_NEXT_DESC_PTR
-#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \
-      defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
-# define SPI_DMA_BASE DMA7_NEXT_DESC_PTR
-# elif defined(__ADSPBF50x__)
-# define SPI_DMA_BASE DMA6_NEXT_DESC_PTR
-#else
-# error "Please provide SPI DMA channel defines"
-#endif
-static volatile struct dma_register *dma = (void *)SPI_DMA_BASE;
-
 #ifndef CONFIG_BFIN_SPI_IDLE_VAL
 # define CONFIG_BFIN_SPI_IDLE_VAL 0xff
 #endif
 
-#ifdef CONFIG_BFIN_SPI_NO_DMA
-# define SPI_DMA 0
-#else
-# define SPI_DMA 1
-#endif
-
-static int spi_dma_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
-			uint bytes)
-{
-	int ret = -1;
-	u16 ndsize, spi_config, dma_config;
-	struct dmasg dmasg[2];
-	const u8 *buf;
-
-	if (tx) {
-		debug("%s: doing half duplex TX\n", __func__);
-		buf = tx;
-		spi_config = TDBR_DMA;
-		dma_config = 0;
-	} else {
-		debug("%s: doing half duplex RX\n", __func__);
-		buf = rx;
-		spi_config = RDBR_DMA;
-		dma_config = WNR;
-	}
-
-	dmasg[0].start_addr = (unsigned long)buf;
-	dmasg[0].x_modify = 1;
-	dma_config |= WDSIZE_8 | DMAEN;
-	if (bytes <= 65536) {
-		blackfin_dcache_flush_invalidate_range(buf, buf + bytes);
-		ndsize = NDSIZE_5;
-		dmasg[0].cfg = NDSIZE_0 | dma_config | FLOW_STOP | DI_EN;
-		dmasg[0].x_count = bytes;
-	} else {
-		blackfin_dcache_flush_invalidate_range(buf, buf + 65536 - 1);
-		ndsize = NDSIZE_7;
-		dmasg[0].cfg = NDSIZE_5 | dma_config | FLOW_ARRAY | DMA2D;
-		dmasg[0].x_count = 0;	/* 2^16 */
-		dmasg[0].y_count = bytes >> 16;	/* count / 2^16 */
-		dmasg[0].y_modify = 1;
-		dmasg[1].start_addr = (unsigned long)(buf + (bytes & ~0xFFFF));
-		dmasg[1].cfg = NDSIZE_0 | dma_config | FLOW_STOP | DI_EN;
-		dmasg[1].x_count = bytes & 0xFFFF; /* count % 2^16 */
-		dmasg[1].x_modify = 1;
-	}
-
-	dma->cfg = 0;
-	dma->irq_status = DMA_DONE | DMA_ERR;
-	dma->curr_desc_ptr = dmasg;
-	write_SPI_CTL(bss, (bss->ctl & ~TDBR_CORE));
-	write_SPI_STAT(bss, -1);
-	SSYNC();
-
-	write_SPI_TDBR(bss, CONFIG_BFIN_SPI_IDLE_VAL);
-	dma->cfg = ndsize | FLOW_ARRAY | DMAEN;
-	write_SPI_CTL(bss, (bss->ctl & ~TDBR_CORE) | spi_config);
-	SSYNC();
-
-	/*
-	 * We already invalidated the first 64k,
-	 * now while we just wait invalidate the remaining part.
-	 * Its not likely that the DMA is going to overtake
-	 */
-	if (bytes > 65536)
-		blackfin_dcache_flush_invalidate_range(buf + 65536, buf + bytes);
-
-	while (!(dma->irq_status & DMA_DONE))
-		if (ctrlc())
-			goto done;
-
-	dma->cfg = 0;
-
-	ret = 0;
- done:
-	write_SPI_CTL(bss, bss->ctl);
-	return ret;
-}
-
 static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
 			uint bytes)
 {
+	/* discard invalid data and clear RXS */
+	read_SPI_RDBR(bss);
 	/* todo: take advantage of hardware fifos  */
 	while (bytes--) {
 		u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
@@ -393,11 +298,7 @@
 	if (flags & SPI_XFER_BEGIN)
 		spi_cs_activate(slave);
 
-	/* TX DMA doesn't work quite right */
-	if (SPI_DMA && bytes > 6 && (!tx /*|| !rx*/))
-		ret = spi_dma_xfer(bss, tx, rx, bytes);
-	else
-		ret = spi_pio_xfer(bss, tx, rx, bytes);
+	ret = spi_pio_xfer(bss, tx, rx, bytes);
 
  done:
 	if (flags & SPI_XFER_END)
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index aa999f9..db98a13 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -31,7 +31,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
 
 #define	MXS_SPI_MAX_TIMEOUT	1000000
 #define	MXS_SPI_PORT_OFFSET	0x2000
diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile
index e8c159c..913dd9c 100644
--- a/drivers/tpm/Makefile
+++ b/drivers/tpm/Makefile
@@ -25,9 +25,10 @@
 
 $(shell mkdir -p $(obj)slb9635_i2c)
 
-COBJS-$(CONFIG_GENERIC_LPC_TPM) = generic_lpc_tpm.o
-COBJS-$(CONFIG_INFINEON_TPM_I2C) += tis_i2c.o slb9635_i2c/tpm.o
-COBJS-$(CONFIG_INFINEON_TPM_I2C) += slb9635_i2c/tpm_tis_i2c.o
+# TODO: Merge tpm_tis_lpc.c with tpm.c
+COBJS-$(CONFIG_TPM_TIS_I2C) += tpm.o
+COBJS-$(CONFIG_TPM_TIS_I2C) += tpm_tis_i2c.o
+COBJS-$(CONFIG_TPM_TIS_LPC) += tpm_tis_lpc.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/tpm/slb9635_i2c/compatibility.h b/drivers/tpm/slb9635_i2c/compatibility.h
deleted file mode 100644
index 62dc9fa..0000000
--- a/drivers/tpm/slb9635_i2c/compatibility.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2011 Infineon Technologies
- *
- * Authors:
- * Peter Huewe <huewe.external@infineon.com>
- *
- * Version: 2.1.1
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _COMPATIBILITY_H_
-#define _COMPATIBILITY_H_
-
-/* all includes from U-Boot */
-#include <linux/types.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <asm-generic/errno.h>
-#include <compiler.h>
-#include <common.h>
-
-/* extended error numbers from linux (see errno.h) */
-#define	ECANCELED	125	/* Operation Canceled */
-
-#define msleep(t) udelay((t)*1000)
-
-/* Timer frequency. Corresponds to msec timer resolution*/
-#define HZ             1000
-
-#define dev_dbg(dev, format, arg...) debug(format, ##arg)
-#define dev_err(dev, format, arg...) printf(format, ##arg)
-#define dev_info(dev, format, arg...) debug(format, ##arg)
-#define dbg_printf debug
-
-#endif
diff --git a/drivers/tpm/slb9635_i2c/tpm_tis_i2c.c b/drivers/tpm/slb9635_i2c/tpm_tis_i2c.c
deleted file mode 100644
index 82a41bf..0000000
--- a/drivers/tpm/slb9635_i2c/tpm_tis_i2c.c
+++ /dev/null
@@ -1,561 +0,0 @@
-/*
- * Copyright (C) 2011 Infineon Technologies
- *
- * Authors:
- * Peter Huewe <huewe.external@infineon.com>
- *
- * Description:
- * Device driver for TCG/TCPA TPM (trusted platform module).
- * Specifications at www.trustedcomputinggroup.org
- *
- * This device driver implements the TPM interface as defined in
- * the TCG TPM Interface Spec version 1.2, revision 1.0 and the
- * Infineon I2C Protocol Stack Specification v0.20.
- *
- * It is based on the Linux kernel driver tpm.c from Leendert van
- * Dorn, Dave Safford, Reiner Sailer, and Kyleen Hall.
- *
- * Version: 2.1.1
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation, version 2 of the
- * License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <linux/types.h>
-
-#include "compatibility.h"
-#include "tpm.h"
-
-/* max. buffer size supported by our tpm */
-#ifdef TPM_BUFSIZE
-#undef TPM_BUFSIZE
-#endif
-#define TPM_BUFSIZE 1260
-/* Address of the TPM on the I2C bus */
-#define TPM_I2C_ADDR 0x20
-/* max. number of iterations after i2c NAK */
-#define MAX_COUNT 3
-
-#define SLEEP_DURATION 60 /*in usec*/
-
-/* max. number of iterations after i2c NAK for 'long' commands
- * we need this especially for sending TPM_READY, since the cleanup after the
- * transtion to the ready state may take some time, but it is unpredictable
- * how long it will take.
- */
-#define MAX_COUNT_LONG 50
-
-#define SLEEP_DURATION_LONG 210 /* in usec */
-
-/* expected value for DIDVID register */
-#define TPM_TIS_I2C_DID_VID 0x000b15d1L
-
-/* Structure to store I2C TPM specific stuff */
-struct tpm_inf_dev {
-	uint addr;
-	u8 buf[TPM_BUFSIZE + sizeof(u8)];	/* max. buffer size + addr */
-};
-
-static struct tpm_inf_dev tpm_dev = {
-	.addr = TPM_I2C_ADDR
-};
-
-/*
- * iic_tpm_read() - read from TPM register
- * @addr: register address to read from
- * @buffer: provided by caller
- * @len: number of bytes to read
- *
- * Read len bytes from TPM register and put them into
- * buffer (little-endian format, i.e. first byte is put into buffer[0]).
- *
- * NOTE: TPM is big-endian for multi-byte values. Multi-byte
- * values have to be swapped.
- *
- * Return -EIO on error, 0 on success.
- */
-int iic_tpm_read(u8 addr, u8 *buffer, size_t len)
-{
-	int rc;
-	int count;
-	uint myaddr = addr;
-	/* we have to use uint here, uchar hangs the board */
-
-	for (count = 0; count < MAX_COUNT; count++) {
-		rc = i2c_write(tpm_dev.addr, 0, 0, (uchar *)&myaddr, 1);
-		if (rc == 0)
-			break; /*success, break to skip sleep*/
-
-		udelay(SLEEP_DURATION);
-	}
-
-	if (rc)
-		return -rc;
-
-	/* After the TPM has successfully received the register address it needs
-	 * some time, thus we're sleeping here again, before retrieving the data
-	 */
-	for (count = 0; count < MAX_COUNT; count++) {
-		udelay(SLEEP_DURATION);
-		rc = i2c_read(tpm_dev.addr, 0, 0, buffer, len);
-		if (rc == 0)
-			break; /*success, break to skip sleep*/
-	}
-
-	if (rc)
-		return -rc;
-
-	return 0;
-}
-
-static int iic_tpm_write_generic(u8 addr, u8 *buffer, size_t len,
-				unsigned int sleep_time,
-				u8 max_count)
-{
-	int rc = 0;
-	int count;
-
-	/* prepare send buffer */
-	tpm_dev.buf[0] = addr;
-	memcpy(&(tpm_dev.buf[1]), buffer, len);
-
-	for (count = 0; count < max_count; count++) {
-		rc = i2c_write(tpm_dev.addr, 0, 0, tpm_dev.buf, len + 1);
-		if (rc == 0)
-			break; /*success, break to skip sleep*/
-
-		udelay(sleep_time);
-	}
-
-	if (rc)
-		return -rc;
-
-	return 0;
-}
-
-/*
- * iic_tpm_write() - write to TPM register
- * @addr: register address to write to
- * @buffer: containing data to be written
- * @len: number of bytes to write
- *
- * Write len bytes from provided buffer to TPM register (little
- * endian format, i.e. buffer[0] is written as first byte).
- *
- * NOTE: TPM is big-endian for multi-byte values. Multi-byte
- * values have to be swapped.
- *
- * NOTE: use this function instead of the iic_tpm_write_generic function.
- *
- * Return -EIO on error, 0 on success
- */
-static int iic_tpm_write(u8 addr, u8 *buffer, size_t len)
-{
-	return iic_tpm_write_generic(addr, buffer, len, SLEEP_DURATION,
-			MAX_COUNT);
-}
-
-/*
- * This function is needed especially for the cleanup situation after
- * sending TPM_READY
- * */
-static int iic_tpm_write_long(u8 addr, u8 *buffer, size_t len)
-{
-	return iic_tpm_write_generic(addr, buffer, len, SLEEP_DURATION_LONG,
-			MAX_COUNT_LONG);
-}
-
-#define TPM_HEADER_SIZE 10
-
-enum tis_access {
-	TPM_ACCESS_VALID = 0x80,
-	TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
-	TPM_ACCESS_REQUEST_PENDING = 0x04,
-	TPM_ACCESS_REQUEST_USE = 0x02,
-};
-
-enum tis_status {
-	TPM_STS_VALID = 0x80,
-	TPM_STS_COMMAND_READY = 0x40,
-	TPM_STS_GO = 0x20,
-	TPM_STS_DATA_AVAIL = 0x10,
-	TPM_STS_DATA_EXPECT = 0x08,
-};
-
-enum tis_defaults {
-	TIS_SHORT_TIMEOUT = 750,	/* ms */
-	TIS_LONG_TIMEOUT = 2000,	/* 2 sec */
-};
-
-#define	TPM_ACCESS(l)			(0x0000 | ((l) << 4))
-#define	TPM_STS(l)			(0x0001 | ((l) << 4))
-#define	TPM_DATA_FIFO(l)		(0x0005 | ((l) << 4))
-#define	TPM_DID_VID(l)			(0x0006 | ((l) << 4))
-
-static int check_locality(struct tpm_chip *chip, int loc)
-{
-	u8 buf;
-	int rc;
-
-	rc = iic_tpm_read(TPM_ACCESS(loc), &buf, 1);
-	if (rc < 0)
-		return rc;
-
-	if ((buf & (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
-		(TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) {
-		chip->vendor.locality = loc;
-		return loc;
-	}
-
-	return -1;
-}
-
-static void release_locality(struct tpm_chip *chip, int loc, int force)
-{
-	u8 buf;
-	if (iic_tpm_read(TPM_ACCESS(loc), &buf, 1) < 0)
-		return;
-
-	if (force || (buf & (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) ==
-			(TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) {
-		buf = TPM_ACCESS_ACTIVE_LOCALITY;
-		iic_tpm_write(TPM_ACCESS(loc), &buf, 1);
-	}
-}
-
-static int request_locality(struct tpm_chip *chip, int loc)
-{
-	unsigned long start, stop;
-	u8 buf = TPM_ACCESS_REQUEST_USE;
-
-	if (check_locality(chip, loc) >= 0)
-		return loc; /* we already have the locality */
-
-	iic_tpm_write(TPM_ACCESS(loc), &buf, 1);
-
-	/* wait for burstcount */
-	start = get_timer(0);
-	stop = chip->vendor.timeout_a;
-	do {
-		if (check_locality(chip, loc) >= 0)
-			return loc;
-		msleep(TPM_TIMEOUT);
-	} while (get_timer(start) < stop);
-
-	return -1;
-}
-
-static u8 tpm_tis_i2c_status(struct tpm_chip *chip)
-{
-	/* NOTE: since i2c read may fail, return 0 in this case --> time-out */
-	u8 buf;
-	if (iic_tpm_read(TPM_STS(chip->vendor.locality), &buf, 1) < 0)
-		return 0;
-	else
-		return buf;
-}
-
-static void tpm_tis_i2c_ready(struct tpm_chip *chip)
-{
-	/* this causes the current command to be aborted */
-	u8 buf = TPM_STS_COMMAND_READY;
-	iic_tpm_write_long(TPM_STS(chip->vendor.locality), &buf, 1);
-}
-
-static ssize_t get_burstcount(struct tpm_chip *chip)
-{
-	unsigned long start, stop;
-	ssize_t burstcnt;
-	u8 buf[3];
-
-	/* wait for burstcount */
-	/* which timeout value, spec has 2 answers (c & d) */
-	start = get_timer(0);
-	stop = chip->vendor.timeout_d;
-	do {
-		/* Note: STS is little endian */
-		if (iic_tpm_read(TPM_STS(chip->vendor.locality) + 1, buf, 3)
-				< 0)
-			burstcnt = 0;
-		else
-			burstcnt = (buf[2] << 16) + (buf[1] << 8) + buf[0];
-
-		if (burstcnt)
-			return burstcnt;
-		msleep(TPM_TIMEOUT);
-	} while (get_timer(start) < stop);
-
-	return -EBUSY;
-}
-
-static int wait_for_stat(struct tpm_chip *chip, u8 mask, unsigned long timeout,
-			int *status)
-{
-	unsigned long start, stop;
-
-	/* check current status */
-	*status = tpm_tis_i2c_status(chip);
-	if ((*status & mask) == mask)
-		return 0;
-
-	start = get_timer(0);
-	stop = timeout;
-	do {
-		msleep(TPM_TIMEOUT);
-		*status = tpm_tis_i2c_status(chip);
-		if ((*status & mask) == mask)
-			return 0;
-
-	} while (get_timer(start) < stop);
-
-	return -ETIME;
-}
-
-static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
-{
-	size_t size = 0;
-	ssize_t burstcnt;
-	int rc;
-
-	while (size < count) {
-		burstcnt = get_burstcount(chip);
-
-		/* burstcount < 0 = tpm is busy */
-		if (burstcnt < 0)
-			return burstcnt;
-
-		/* limit received data to max. left */
-		if (burstcnt > (count - size))
-			burstcnt = count - size;
-
-		rc = iic_tpm_read(TPM_DATA_FIFO(chip->vendor.locality),
-				  &(buf[size]),
-				  burstcnt);
-		if (rc == 0)
-			size += burstcnt;
-	}
-
-	return size;
-}
-
-static int tpm_tis_i2c_recv(struct tpm_chip *chip, u8 *buf, size_t count)
-{
-	int size = 0;
-	int expected, status;
-
-	if (count < TPM_HEADER_SIZE) {
-		size = -EIO;
-		goto out;
-	}
-
-	/* read first 10 bytes, including tag, paramsize, and result */
-	size = recv_data(chip, buf, TPM_HEADER_SIZE);
-	if (size < TPM_HEADER_SIZE) {
-		dev_err(chip->dev, "Unable to read header\n");
-		goto out;
-	}
-
-	expected = get_unaligned_be32(buf + TPM_RSP_SIZE_BYTE);
-	if ((size_t)expected > count) {
-		size = -EIO;
-		goto out;
-	}
-
-	size += recv_data(chip, &buf[TPM_HEADER_SIZE],
-				expected - TPM_HEADER_SIZE);
-	if (size < expected) {
-		dev_err(chip->dev, "Unable to read remainder of result\n");
-		size = -ETIME;
-		goto out;
-	}
-
-	wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, &status);
-	if (status & TPM_STS_DATA_AVAIL) {	/* retry? */
-		dev_err(chip->dev, "Error left over data\n");
-		size = -EIO;
-		goto out;
-	}
-
-out:
-	tpm_tis_i2c_ready(chip);
-	/* The TPM needs some time to clean up here,
-	 * so we sleep rather than keeping the bus busy
-	 */
-	udelay(2000);
-	release_locality(chip, chip->vendor.locality, 0);
-
-	return size;
-}
-
-static int tpm_tis_i2c_send(struct tpm_chip *chip, u8 *buf, size_t len)
-{
-	int rc, status;
-	ssize_t burstcnt;
-	size_t count = 0;
-	u8 sts = TPM_STS_GO;
-
-	if (len > TPM_BUFSIZE)
-		return -E2BIG; /* command is too long for our tpm, sorry */
-
-	if (request_locality(chip, 0) < 0)
-		return -EBUSY;
-
-	status = tpm_tis_i2c_status(chip);
-	if ((status & TPM_STS_COMMAND_READY) == 0) {
-		tpm_tis_i2c_ready(chip);
-		if (wait_for_stat
-		    (chip, TPM_STS_COMMAND_READY,
-		     chip->vendor.timeout_b, &status) < 0) {
-			rc = -ETIME;
-			goto out_err;
-		}
-	}
-
-	while (count < len - 1) {
-		burstcnt = get_burstcount(chip);
-
-		/* burstcount < 0 = tpm is busy */
-		if (burstcnt < 0)
-			return burstcnt;
-
-		if (burstcnt > (len-1-count))
-			burstcnt = len-1-count;
-
-#ifdef CONFIG_TPM_I2C_BURST_LIMITATION
-		if (burstcnt > CONFIG_TPM_I2C_BURST_LIMITATION)
-			burstcnt = CONFIG_TPM_I2C_BURST_LIMITATION;
-#endif /* CONFIG_TPM_I2C_BURST_LIMITATION */
-
-		rc = iic_tpm_write(TPM_DATA_FIFO(chip->vendor.locality),
-				   &(buf[count]), burstcnt);
-		if (rc == 0)
-			count += burstcnt;
-
-		wait_for_stat(chip, TPM_STS_VALID,
-			      chip->vendor.timeout_c, &status);
-
-		if ((status & TPM_STS_DATA_EXPECT) == 0) {
-			rc = -EIO;
-			goto out_err;
-		}
-	}
-
-	/* write last byte */
-	iic_tpm_write(TPM_DATA_FIFO(chip->vendor.locality), &(buf[count]), 1);
-	wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, &status);
-	if ((status & TPM_STS_DATA_EXPECT) != 0) {
-		rc = -EIO;
-		goto out_err;
-	}
-
-	/* go and do it */
-	iic_tpm_write(TPM_STS(chip->vendor.locality), &sts, 1);
-
-	return len;
-out_err:
-	tpm_tis_i2c_ready(chip);
-	/* The TPM needs some time to clean up here,
-	 * so we sleep rather than keeping the bus busy
-	 */
-	udelay(2000);
-	release_locality(chip, chip->vendor.locality, 0);
-
-	return rc;
-}
-
-static struct tpm_vendor_specific tpm_tis_i2c = {
-	.status = tpm_tis_i2c_status,
-	.recv = tpm_tis_i2c_recv,
-	.send = tpm_tis_i2c_send,
-	.cancel = tpm_tis_i2c_ready,
-	.req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
-	.req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
-	.req_canceled = TPM_STS_COMMAND_READY,
-};
-
-/* initialisation of i2c tpm */
-
-
-int tpm_vendor_init(uint32_t dev_addr)
-{
-	u32 vendor;
-	uint old_addr;
-	int rc = 0;
-	struct tpm_chip *chip;
-
-	old_addr = tpm_dev.addr;
-	if (dev_addr != 0)
-		tpm_dev.addr = dev_addr;
-
-	chip = tpm_register_hardware(&tpm_tis_i2c);
-	if (chip < 0) {
-		rc = -ENODEV;
-		goto out_err;
-	}
-
-	/* Disable interrupts (not supported) */
-	chip->vendor.irq = 0;
-
-	/* Default timeouts */
-	chip->vendor.timeout_a = TIS_SHORT_TIMEOUT;
-	chip->vendor.timeout_b = TIS_LONG_TIMEOUT;
-	chip->vendor.timeout_c = TIS_SHORT_TIMEOUT;
-	chip->vendor.timeout_d = TIS_SHORT_TIMEOUT;
-
-	if (request_locality(chip, 0) != 0) {
-		rc = -ENODEV;
-		goto out_err;
-	}
-
-	/* read four bytes from DID_VID register */
-	if (iic_tpm_read(TPM_DID_VID(0), (uchar *)&vendor, 4) < 0) {
-		rc = -EIO;
-		goto out_release;
-	}
-
-	/* create DID_VID register value, after swapping to little-endian */
-	vendor = be32_to_cpu(vendor);
-
-	if (vendor != TPM_TIS_I2C_DID_VID) {
-		rc = -ENODEV;
-		goto out_release;
-	}
-
-	dev_info(dev, "1.2 TPM (device-id 0x%X)\n", vendor >> 16);
-
-	/*
-	 * A timeout query to TPM can be placed here.
-	 * Standard timeout values are used so far
-	 */
-
-	return 0;
-
-out_release:
-	release_locality(chip, 0, 1);
-
-out_err:
-	tpm_dev.addr = old_addr;
-	return rc;
-}
-
-void tpm_vendor_cleanup(struct tpm_chip *chip)
-{
-	release_locality(chip, chip->vendor.locality, 1);
-}
diff --git a/drivers/tpm/tis_i2c.c b/drivers/tpm/tis_i2c.c
index e818fba..22554e1 100644
--- a/drivers/tpm/tis_i2c.c
+++ b/drivers/tpm/tis_i2c.c
@@ -68,6 +68,10 @@
 
 	node = fdtdec_next_compatible(blob, 0, COMPAT_INFINEON_SLB9635_TPM);
 	if (node < 0) {
+		node = fdtdec_next_compatible(blob, 0,
+					      COMPAT_INFINEON_SLB9645_TPM);
+	}
+	if (node < 0) {
 		debug("%s: Node not found\n", __func__);
 		return -1;
 	}
diff --git a/drivers/tpm/slb9635_i2c/tpm.c b/drivers/tpm/tpm.c
similarity index 63%
rename from drivers/tpm/slb9635_i2c/tpm.c
rename to drivers/tpm/tpm.c
index 496c48e..b657334 100644
--- a/drivers/tpm/slb9635_i2c/tpm.c
+++ b/drivers/tpm/tpm.c
@@ -32,11 +32,30 @@
  * MA 02111-1307 USA
  */
 
-#include <malloc.h>
-#include "tpm.h"
+#include <config.h>
+#include <common.h>
+#include <compiler.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <tpm.h>
+#include <asm-generic/errno.h>
+#include <linux/types.h>
+#include <linux/unaligned/be_byteshift.h>
 
-/* global structure for tpm chip data */
-struct tpm_chip g_chip;
+#include "tpm_private.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* TPM configuration */
+struct tpm {
+	int i2c_bus;
+	int slave_addr;
+	char inited;
+	int old_bus;
+} tpm;
+
+/* Global structure for tpm chip data */
+static struct tpm_chip g_chip;
 
 enum tpm_duration {
 	TPM_SHORT = 0,
@@ -45,9 +64,18 @@
 	TPM_UNDEFINED,
 };
 
-#define TPM_MAX_ORDINAL 243
-#define TPM_MAX_PROTECTED_ORDINAL 12
-#define TPM_PROTECTED_ORDINAL_MASK 0xFF
+/* Extended error numbers from linux (see errno.h) */
+#define ECANCELED	125	/* Operation Canceled */
+
+/* Timer frequency. Corresponds to msec timer resolution*/
+#define HZ		1000
+
+#define TPM_MAX_ORDINAL			243
+#define TPM_MAX_PROTECTED_ORDINAL	12
+#define TPM_PROTECTED_ORDINAL_MASK	0xFF
+
+#define TPM_CMD_COUNT_BYTE	2
+#define TPM_CMD_ORDINAL_BYTE	6
 
 /*
  * Array with one entry per ordinal defining the maximum amount
@@ -318,34 +346,31 @@
 	TPM_MEDIUM,
 };
 
-/*
- * Returns max number of milliseconds to wait
- */
-unsigned long tpm_calc_ordinal_duration(struct tpm_chip *chip, u32 ordinal)
+/* Returns max number of milliseconds to wait */
+static unsigned long tpm_calc_ordinal_duration(struct tpm_chip *chip,
+		u32 ordinal)
 {
 	int duration_idx = TPM_UNDEFINED;
 	int duration = 0;
 
-	if (ordinal < TPM_MAX_ORDINAL)
+	if (ordinal < TPM_MAX_ORDINAL) {
 		duration_idx = tpm_ordinal_duration[ordinal];
-	else if ((ordinal & TPM_PROTECTED_ORDINAL_MASK) <
-		 TPM_MAX_PROTECTED_ORDINAL)
-		duration_idx =
-		    tpm_protected_ordinal_duration[ordinal &
-						   TPM_PROTECTED_ORDINAL_MASK];
+	} else if ((ordinal & TPM_PROTECTED_ORDINAL_MASK) <
+			TPM_MAX_PROTECTED_ORDINAL) {
+		duration_idx = tpm_protected_ordinal_duration[
+				ordinal & TPM_PROTECTED_ORDINAL_MASK];
+	}
 
 	if (duration_idx != TPM_UNDEFINED)
 		duration = chip->vendor.duration[duration_idx];
+
 	if (duration <= 0)
-		return 2 * 60 * HZ; /*two minutes timeout*/
+		return 2 * 60 * HZ; /* Two minutes timeout */
 	else
 		return duration;
 }
 
-#define TPM_CMD_COUNT_BYTE 2
-#define TPM_CMD_ORDINAL_BYTE 6
-
-ssize_t tpm_transmit(const unsigned char *buf, size_t bufsiz)
+static ssize_t tpm_transmit(const unsigned char *buf, size_t bufsiz)
 {
 	ssize_t rc;
 	u32 count, ordinal;
@@ -358,18 +383,17 @@
 	ordinal = get_unaligned_be32(buf + TPM_CMD_ORDINAL_BYTE);
 
 	if (count == 0) {
-		dev_err(chip->dev, "no data\n");
+		error("no data\n");
 		return -ENODATA;
 	}
 	if (count > bufsiz) {
-		dev_err(chip->dev,
-			"invalid count value %x %zx\n", count, bufsiz);
+		error("invalid count value %x %zx\n", count, bufsiz);
 		return -E2BIG;
 	}
 
 	rc = chip->vendor.send(chip, (u8 *)buf, count);
 	if (rc < 0) {
-		dev_err(chip->dev, "tpm_transmit: tpm_send: error %zd\n", rc);
+		error("tpm_transmit: tpm_send: error %zd\n", rc);
 		goto out;
 	}
 
@@ -379,47 +403,126 @@
 	start = get_timer(0);
 	stop = tpm_calc_ordinal_duration(chip, ordinal);
 	do {
-		dbg_printf("waiting for status...\n");
+		debug("waiting for status...\n");
 		u8 status = chip->vendor.status(chip);
 		if ((status & chip->vendor.req_complete_mask) ==
 		    chip->vendor.req_complete_val) {
-			dbg_printf("...got it;\n");
+			debug("...got it;\n");
 			goto out_recv;
 		}
 
 		if ((status == chip->vendor.req_canceled)) {
-			dev_err(chip->dev, "Operation Canceled\n");
+			error("Operation Canceled\n");
 			rc = -ECANCELED;
 			goto out;
 		}
-		msleep(TPM_TIMEOUT);
+		udelay(TPM_TIMEOUT * 1000);
 	} while (get_timer(start) < stop);
 
 	chip->vendor.cancel(chip);
-	dev_err(chip->dev, "Operation Timed out\n");
+	error("Operation Timed out\n");
 	rc = -ETIME;
 	goto out;
 
 out_recv:
-
-	dbg_printf("out_recv: reading response...\n");
+	debug("out_recv: reading response...\n");
 	rc = chip->vendor.recv(chip, (u8 *)buf, TPM_BUFSIZE);
 	if (rc < 0)
-		dev_err(chip->dev, "tpm_transmit: tpm_recv: error %zd\n", rc);
+		error("tpm_transmit: tpm_recv: error %zd\n", rc);
+
 out:
 	return rc;
 }
 
-#define TPM_ERROR_SIZE 10
+static int tpm_open(uint32_t dev_addr)
+{
+	int rc;
+	if (g_chip.is_open)
+		return -EBUSY;
+	rc = tpm_vendor_init(dev_addr);
+	if (rc < 0)
+		g_chip.is_open = 0;
+	return rc;
+}
 
-enum tpm_capabilities {
-	TPM_CAP_PROP = cpu_to_be32(5),
-};
+static void tpm_close(void)
+{
+	if (g_chip.is_open) {
+		tpm_vendor_cleanup(&g_chip);
+		g_chip.is_open = 0;
+	}
+}
 
-enum tpm_sub_capabilities {
-	TPM_CAP_PROP_TIS_TIMEOUT = cpu_to_be32(0x115),
-	TPM_CAP_PROP_TIS_DURATION = cpu_to_be32(0x120),
-};
+static int tpm_select(void)
+{
+	int ret;
+
+	tpm.old_bus = i2c_get_bus_num();
+	if (tpm.old_bus != tpm.i2c_bus) {
+		ret = i2c_set_bus_num(tpm.i2c_bus);
+		if (ret) {
+			debug("%s: Fail to set i2c bus %d\n", __func__,
+			      tpm.i2c_bus);
+			return -1;
+		}
+	}
+	return 0;
+}
+
+static int tpm_deselect(void)
+{
+	int ret;
+
+	if (tpm.old_bus != i2c_get_bus_num()) {
+		ret = i2c_set_bus_num(tpm.old_bus);
+		if (ret) {
+			debug("%s: Fail to restore i2c bus %d\n",
+			      __func__, tpm.old_bus);
+			return -1;
+		}
+	}
+	tpm.old_bus = -1;
+	return 0;
+}
+
+/**
+ * Decode TPM configuration.
+ *
+ * @param dev	Returns a configuration of TPM device
+ * @return 0 if ok, -1 on error
+ */
+static int tpm_decode_config(struct tpm *dev)
+{
+#ifdef CONFIG_OF_CONTROL
+	const void *blob = gd->fdt_blob;
+	int node, parent;
+	int i2c_bus;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_INFINEON_SLB9635_TPM);
+	if (node < 0) {
+		node = fdtdec_next_compatible(blob, 0,
+				COMPAT_INFINEON_SLB9645_TPM);
+	}
+	if (node < 0) {
+		debug("%s: Node not found\n", __func__);
+		return -1;
+	}
+	parent = fdt_parent_offset(blob, node);
+	if (parent < 0) {
+		debug("%s: Cannot find node parent\n", __func__);
+		return -1;
+	}
+	i2c_bus = i2c_get_bus_num_fdt(parent);
+	if (i2c_bus < 0)
+		return -1;
+	dev->i2c_bus = i2c_bus;
+	dev->slave_addr = fdtdec_get_addr(blob, node, "reg");
+#else
+	dev->i2c_bus = CONFIG_TPM_TIS_I2C_BUS_NUMBER;
+	dev->slave_addr = CONFIG_TPM_TIS_I2C_SLAVE_ADDRESS;
+#endif
+	return 0;
+}
 
 struct tpm_chip *tpm_register_hardware(const struct tpm_vendor_specific *entry)
 {
@@ -433,21 +536,94 @@
 	return chip;
 }
 
-int tpm_open(uint32_t dev_addr)
+int tis_init(void)
+{
+	if (tpm.inited)
+		return 0;
+
+	if (tpm_decode_config(&tpm))
+		return -1;
+
+	if (tpm_select())
+		return -1;
+
+	/*
+	 * Probe TPM twice; the first probing might fail because TPM is asleep,
+	 * and the probing can wake up TPM.
+	 */
+	if (i2c_probe(tpm.slave_addr) && i2c_probe(tpm.slave_addr)) {
+		debug("%s: fail to probe i2c addr 0x%x\n", __func__,
+		      tpm.slave_addr);
+		return -1;
+	}
+
+	tpm_deselect();
+
+	tpm.inited = 1;
+
+	return 0;
+}
+
+int tis_open(void)
 {
 	int rc;
-	if (g_chip.is_open)
-		return -EBUSY;
-	rc = tpm_vendor_init(dev_addr);
-	if (rc < 0)
-		g_chip.is_open = 0;
+
+	if (!tpm.inited)
+		return -1;
+
+	if (tpm_select())
+		return -1;
+
+	rc = tpm_open(tpm.slave_addr);
+
+	tpm_deselect();
+
 	return rc;
 }
 
-void tpm_close(void)
+int tis_close(void)
 {
-	if (g_chip.is_open) {
-		tpm_vendor_cleanup(&g_chip);
-		g_chip.is_open = 0;
+	if (!tpm.inited)
+		return -1;
+
+	if (tpm_select())
+		return -1;
+
+	tpm_close();
+
+	tpm_deselect();
+
+	return 0;
+}
+
+int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size,
+		uint8_t *recvbuf, size_t *rbuf_len)
+{
+	int len;
+	uint8_t buf[4096];
+
+	if (!tpm.inited)
+		return -1;
+
+	if (sizeof(buf) < sbuf_size)
+		return -1;
+
+	memcpy(buf, sendbuf, sbuf_size);
+
+	if (tpm_select())
+		return -1;
+
+	len = tpm_transmit(buf, sbuf_size);
+
+	tpm_deselect();
+
+	if (len < 10) {
+		*rbuf_len = 0;
+		return -1;
 	}
+
+	memcpy(recvbuf, buf, len);
+	*rbuf_len = len;
+
+	return 0;
 }
diff --git a/drivers/tpm/slb9635_i2c/tpm.h b/drivers/tpm/tpm_private.h
similarity index 71%
rename from drivers/tpm/slb9635_i2c/tpm.h
rename to drivers/tpm/tpm_private.h
index 9ddee86..888a074 100644
--- a/drivers/tpm/slb9635_i2c/tpm.h
+++ b/drivers/tpm/tpm_private.h
@@ -33,12 +33,11 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _TPM_H_
-#define _TPM_H_
+#ifndef _TPM_PRIVATE_H_
+#define _TPM_PRIVATE_H_
 
 #include <linux/compiler.h>
-
-#include "compatibility.h"
+#include <linux/types.h>
 
 enum tpm_timeout {
 	TPM_TIMEOUT = 5,	/* msecs */
@@ -47,13 +46,9 @@
 /* Size of external transmit buffer (used in tpm_transmit)*/
 #define TPM_BUFSIZE 4096
 
-/* Index of fields in TPM command buffer */
-#define TPM_CMD_SIZE_BYTE 2
-#define TPM_CMD_ORDINAL_BYTE 6
-
 /* Index of Count field in TPM response buffer */
-#define TPM_RSP_SIZE_BYTE 2
-#define TPM_RSP_RC_BYTE 6
+#define TPM_RSP_SIZE_BYTE	2
+#define TPM_RSP_RC_BYTE		6
 
 struct tpm_chip;
 
@@ -65,10 +60,10 @@
 	int (*recv) (struct tpm_chip *, u8 *, size_t);
 	int (*send) (struct tpm_chip *, u8 *, size_t);
 	void (*cancel) (struct tpm_chip *);
-	 u8(*status) (struct tpm_chip *);
+	u8(*status) (struct tpm_chip *);
 	int locality;
-	unsigned long timeout_a, timeout_b, timeout_c, timeout_d; /* msec */
-	unsigned long duration[3];	/* msec */
+	unsigned long timeout_a, timeout_b, timeout_c, timeout_d;  /* msec */
+	unsigned long duration[3];  /* msec */
 };
 
 struct tpm_chip {
@@ -132,30 +127,11 @@
 	union tpm_cmd_params params;
 } __packed;
 
+struct tpm_chip *tpm_register_hardware(const struct tpm_vendor_specific *);
 
-/* ---------- Interface for TPM vendor ------------ */
+int tpm_vendor_init(uint32_t dev_addr);
 
-extern struct tpm_chip *tpm_register_hardware(
-	const struct tpm_vendor_specific *);
+void tpm_vendor_cleanup(struct tpm_chip *chip);
 
-extern int tpm_vendor_init(uint32_t dev_addr);
-
-extern void tpm_vendor_cleanup(struct tpm_chip *chip);
-
-/* ---------- Interface for TDDL ------------------- */
-
-/*
- * if dev_addr != 0 - redefines TPM device address
- * Returns < 0 on error, 0 on success.
- */
-extern int tpm_open(uint32_t dev_addr);
-
-extern void tpm_close(void);
-
-/*
- * Transmit bufsiz bytes out of buf to TPM and get results back in buf, too.
- * Returns < 0 on error, 0 on success.
- */
-extern ssize_t tpm_transmit(const unsigned char *buf, size_t bufsiz);
 
 #endif
diff --git a/drivers/tpm/tpm_tis_i2c.c b/drivers/tpm/tpm_tis_i2c.c
new file mode 100644
index 0000000..2dd8501
--- /dev/null
+++ b/drivers/tpm/tpm_tis_i2c.c
@@ -0,0 +1,637 @@
+/*
+ * Copyright (C) 2011 Infineon Technologies
+ *
+ * Authors:
+ * Peter Huewe <huewe.external@infineon.com>
+ *
+ * Description:
+ * Device driver for TCG/TCPA TPM (trusted platform module).
+ * Specifications at www.trustedcomputinggroup.org
+ *
+ * This device driver implements the TPM interface as defined in
+ * the TCG TPM Interface Spec version 1.2, revision 1.0 and the
+ * Infineon I2C Protocol Stack Specification v0.20.
+ *
+ * It is based on the Linux kernel driver tpm.c from Leendert van
+ * Dorn, Dave Safford, Reiner Sailer, and Kyleen Hall.
+ *
+ * Version: 2.1.1
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation, version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <compiler.h>
+#include <i2c.h>
+#include <tpm.h>
+#include <asm-generic/errno.h>
+#include <linux/types.h>
+#include <linux/unaligned/be_byteshift.h>
+
+#include "tpm_private.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Address of the TPM on the I2C bus */
+#define TPM_I2C_ADDR		0x20
+
+/* Max buffer size supported by our tpm */
+#define TPM_DEV_BUFSIZE		1260
+
+/* Max number of iterations after i2c NAK */
+#define MAX_COUNT		3
+
+/*
+ * Max number of iterations after i2c NAK for 'long' commands
+ *
+ * We need this especially for sending TPM_READY, since the cleanup after the
+ * transtion to the ready state may take some time, but it is unpredictable
+ * how long it will take.
+ */
+#define MAX_COUNT_LONG		50
+
+#define SLEEP_DURATION		60	/* in usec */
+#define SLEEP_DURATION_LONG	210	/* in usec */
+
+#define TPM_HEADER_SIZE		10
+
+/*
+ * Expected value for DIDVID register
+ *
+ * The only device the system knows about at this moment is Infineon slb9635.
+ */
+#define TPM_TIS_I2C_DID_VID	0x000b15d1L
+
+enum tis_access {
+	TPM_ACCESS_VALID		= 0x80,
+	TPM_ACCESS_ACTIVE_LOCALITY	= 0x20,
+	TPM_ACCESS_REQUEST_PENDING	= 0x04,
+	TPM_ACCESS_REQUEST_USE		= 0x02,
+};
+
+enum tis_status {
+	TPM_STS_VALID			= 0x80,
+	TPM_STS_COMMAND_READY		= 0x40,
+	TPM_STS_GO			= 0x20,
+	TPM_STS_DATA_AVAIL		= 0x10,
+	TPM_STS_DATA_EXPECT		= 0x08,
+};
+
+enum tis_defaults {
+	TIS_SHORT_TIMEOUT		= 750,	/* ms */
+	TIS_LONG_TIMEOUT		= 2000,	/* ms */
+};
+
+/* expected value for DIDVID register */
+#define TPM_TIS_I2C_DID_VID_9635 0x000b15d1L
+#define TPM_TIS_I2C_DID_VID_9645 0x001a15d1L
+
+enum i2c_chip_type {
+	SLB9635,
+	SLB9645,
+	UNKNOWN,
+};
+
+static const char * const chip_name[] = {
+	[SLB9635] = "slb9635tt",
+	[SLB9645] = "slb9645tt",
+	[UNKNOWN] = "unknown/fallback to slb9635",
+};
+
+#define	TPM_ACCESS(l)			(0x0000 | ((l) << 4))
+#define	TPM_STS(l)			(0x0001 | ((l) << 4))
+#define	TPM_DATA_FIFO(l)		(0x0005 | ((l) << 4))
+#define	TPM_DID_VID(l)			(0x0006 | ((l) << 4))
+
+/* Structure to store I2C TPM specific stuff */
+struct tpm_dev {
+	uint addr;
+	u8 buf[TPM_DEV_BUFSIZE + sizeof(u8)];  /* Max buffer size + addr */
+	enum i2c_chip_type chip_type;
+};
+
+static struct tpm_dev tpm_dev = {
+	.addr = TPM_I2C_ADDR
+};
+
+static struct tpm_dev tpm_dev;
+
+/*
+ * iic_tpm_read() - read from TPM register
+ * @addr: register address to read from
+ * @buffer: provided by caller
+ * @len: number of bytes to read
+ *
+ * Read len bytes from TPM register and put them into
+ * buffer (little-endian format, i.e. first byte is put into buffer[0]).
+ *
+ * NOTE: TPM is big-endian for multi-byte values. Multi-byte
+ * values have to be swapped.
+ *
+ * Return -EIO on error, 0 on success.
+ */
+static int iic_tpm_read(u8 addr, u8 *buffer, size_t len)
+{
+	int rc;
+	int count;
+	uint32_t addrbuf = addr;
+
+	if ((tpm_dev.chip_type == SLB9635) || (tpm_dev.chip_type == UNKNOWN)) {
+		/* slb9635 protocol should work in both cases */
+		for (count = 0; count < MAX_COUNT; count++) {
+			rc = i2c_write(tpm_dev.addr, 0, 0,
+				       (uchar *)&addrbuf, 1);
+			if (rc == 0)
+				break;  /* Success, break to skip sleep */
+			udelay(SLEEP_DURATION);
+		}
+		if (rc)
+			return -rc;
+
+		/* After the TPM has successfully received the register address
+		 * it needs some time, thus we're sleeping here again, before
+		 * retrieving the data
+		 */
+		for (count = 0; count < MAX_COUNT; count++) {
+			udelay(SLEEP_DURATION);
+			rc = i2c_read(tpm_dev.addr, 0, 0, buffer, len);
+			if (rc == 0)
+				break;  /* success, break to skip sleep */
+		}
+	} else {
+		/*
+		 * Use a combined read for newer chips.
+		 * Unfortunately the smbus functions are not suitable due to
+		 * the 32 byte limit of the smbus.
+		 * Retries should usually not be needed, but are kept just to
+		 * be safe on the safe side.
+		 */
+		for (count = 0; count < MAX_COUNT; count++) {
+			rc = i2c_read(tpm_dev.addr, addr, 1, buffer, len);
+			if (rc == 0)
+				break;  /* break here to skip sleep */
+			udelay(SLEEP_DURATION);
+		}
+	}
+
+	/* Take care of 'guard time' */
+	udelay(SLEEP_DURATION);
+	if (rc)
+		return -rc;
+
+	return 0;
+}
+
+static int iic_tpm_write_generic(u8 addr, u8 *buffer, size_t len,
+		unsigned int sleep_time, u8 max_count)
+{
+	int rc = 0;
+	int count;
+
+	/* Prepare send buffer */
+	tpm_dev.buf[0] = addr;
+	memcpy(&(tpm_dev.buf[1]), buffer, len);
+
+	for (count = 0; count < max_count; count++) {
+		rc = i2c_write(tpm_dev.addr, 0, 0, tpm_dev.buf, len + 1);
+		if (rc == 0)
+			break;  /* Success, break to skip sleep */
+		udelay(sleep_time);
+	}
+
+	/* take care of 'guard time' */
+	udelay(SLEEP_DURATION);
+	if (rc)
+		return -rc;
+
+	return 0;
+}
+
+/*
+ * iic_tpm_write() - write to TPM register
+ * @addr: register address to write to
+ * @buffer: containing data to be written
+ * @len: number of bytes to write
+ *
+ * Write len bytes from provided buffer to TPM register (little
+ * endian format, i.e. buffer[0] is written as first byte).
+ *
+ * NOTE: TPM is big-endian for multi-byte values. Multi-byte
+ * values have to be swapped.
+ *
+ * NOTE: use this function instead of the iic_tpm_write_generic function.
+ *
+ * Return -EIO on error, 0 on success
+ */
+static int iic_tpm_write(u8 addr, u8 *buffer, size_t len)
+{
+	return iic_tpm_write_generic(addr, buffer, len, SLEEP_DURATION,
+			MAX_COUNT);
+}
+
+/*
+ * This function is needed especially for the cleanup situation after
+ * sending TPM_READY
+ */
+static int iic_tpm_write_long(u8 addr, u8 *buffer, size_t len)
+{
+	return iic_tpm_write_generic(addr, buffer, len, SLEEP_DURATION_LONG,
+			MAX_COUNT_LONG);
+}
+
+static int check_locality(struct tpm_chip *chip, int loc)
+{
+	const u8 mask = TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID;
+	u8 buf;
+	int rc;
+
+	rc = iic_tpm_read(TPM_ACCESS(loc), &buf, 1);
+	if (rc < 0)
+		return rc;
+
+	if ((buf & mask) == mask) {
+		chip->vendor.locality = loc;
+		return loc;
+	}
+
+	return -1;
+}
+
+static void release_locality(struct tpm_chip *chip, int loc, int force)
+{
+	const u8 mask = TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID;
+	u8 buf;
+
+	if (iic_tpm_read(TPM_ACCESS(loc), &buf, 1) < 0)
+		return;
+
+	if (force || (buf & mask) == mask) {
+		buf = TPM_ACCESS_ACTIVE_LOCALITY;
+		iic_tpm_write(TPM_ACCESS(loc), &buf, 1);
+	}
+}
+
+static int request_locality(struct tpm_chip *chip, int loc)
+{
+	unsigned long start, stop;
+	u8 buf = TPM_ACCESS_REQUEST_USE;
+
+	if (check_locality(chip, loc) >= 0)
+		return loc;  /* We already have the locality */
+
+	iic_tpm_write(TPM_ACCESS(loc), &buf, 1);
+
+	/* Wait for burstcount */
+	start = get_timer(0);
+	stop = chip->vendor.timeout_a;
+	do {
+		if (check_locality(chip, loc) >= 0)
+			return loc;
+		udelay(TPM_TIMEOUT * 1000);
+	} while (get_timer(start) < stop);
+
+	return -1;
+}
+
+static u8 tpm_tis_i2c_status(struct tpm_chip *chip)
+{
+	/* NOTE: Since i2c read may fail, return 0 in this case --> time-out */
+	u8 buf;
+
+	if (iic_tpm_read(TPM_STS(chip->vendor.locality), &buf, 1) < 0)
+		return 0;
+	else
+		return buf;
+}
+
+static void tpm_tis_i2c_ready(struct tpm_chip *chip)
+{
+	/* This causes the current command to be aborted */
+	u8 buf = TPM_STS_COMMAND_READY;
+
+	iic_tpm_write_long(TPM_STS(chip->vendor.locality), &buf, 1);
+}
+
+static ssize_t get_burstcount(struct tpm_chip *chip)
+{
+	unsigned long start, stop;
+	ssize_t burstcnt;
+	u8 addr, buf[3];
+
+	/* Wait for burstcount */
+	/* XXX: Which timeout value? Spec has 2 answers (c & d) */
+	start = get_timer(0);
+	stop = chip->vendor.timeout_d;
+	do {
+		/* Note: STS is little endian */
+		addr = TPM_STS(chip->vendor.locality) + 1;
+		if (iic_tpm_read(addr, buf, 3) < 0)
+			burstcnt = 0;
+		else
+			burstcnt = (buf[2] << 16) + (buf[1] << 8) + buf[0];
+
+		if (burstcnt)
+			return burstcnt;
+		udelay(TPM_TIMEOUT * 1000);
+	} while (get_timer(start) < stop);
+
+	return -EBUSY;
+}
+
+static int wait_for_stat(struct tpm_chip *chip, u8 mask, unsigned long timeout,
+		int *status)
+{
+	unsigned long start, stop;
+
+	/* Check current status */
+	*status = tpm_tis_i2c_status(chip);
+	if ((*status & mask) == mask)
+		return 0;
+
+	start = get_timer(0);
+	stop = timeout;
+	do {
+		udelay(TPM_TIMEOUT * 1000);
+		*status = tpm_tis_i2c_status(chip);
+		if ((*status & mask) == mask)
+			return 0;
+	} while (get_timer(start) < stop);
+
+	return -ETIME;
+}
+
+static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
+{
+	size_t size = 0;
+	ssize_t burstcnt;
+	int rc;
+
+	while (size < count) {
+		burstcnt = get_burstcount(chip);
+
+		/* burstcount < 0 -> tpm is busy */
+		if (burstcnt < 0)
+			return burstcnt;
+
+		/* Limit received data to max left */
+		if (burstcnt > (count - size))
+			burstcnt = count - size;
+
+		rc = iic_tpm_read(TPM_DATA_FIFO(chip->vendor.locality),
+				&(buf[size]), burstcnt);
+		if (rc == 0)
+			size += burstcnt;
+	}
+
+	return size;
+}
+
+static int tpm_tis_i2c_recv(struct tpm_chip *chip, u8 *buf, size_t count)
+{
+	int size = 0;
+	int expected, status;
+
+	if (count < TPM_HEADER_SIZE) {
+		size = -EIO;
+		goto out;
+	}
+
+	/* Read first 10 bytes, including tag, paramsize, and result */
+	size = recv_data(chip, buf, TPM_HEADER_SIZE);
+	if (size < TPM_HEADER_SIZE) {
+		error("Unable to read header\n");
+		goto out;
+	}
+
+	expected = get_unaligned_be32(buf + TPM_RSP_SIZE_BYTE);
+	if ((size_t)expected > count) {
+		size = -EIO;
+		goto out;
+	}
+
+	size += recv_data(chip, &buf[TPM_HEADER_SIZE],
+			expected - TPM_HEADER_SIZE);
+	if (size < expected) {
+		error("Unable to read remainder of result\n");
+		size = -ETIME;
+		goto out;
+	}
+
+	wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, &status);
+	if (status & TPM_STS_DATA_AVAIL) {  /* Retry? */
+		error("Error left over data\n");
+		size = -EIO;
+		goto out;
+	}
+
+out:
+	tpm_tis_i2c_ready(chip);
+	/*
+	 * The TPM needs some time to clean up here,
+	 * so we sleep rather than keeping the bus busy
+	 */
+	udelay(2000);
+	release_locality(chip, chip->vendor.locality, 0);
+
+	return size;
+}
+
+static int tpm_tis_i2c_send(struct tpm_chip *chip, u8 *buf, size_t len)
+{
+	int rc, status;
+	ssize_t burstcnt;
+	size_t count = 0;
+	int retry = 0;
+	u8 sts = TPM_STS_GO;
+
+	if (len > TPM_DEV_BUFSIZE)
+		return -E2BIG;  /* Command is too long for our tpm, sorry */
+
+	if (request_locality(chip, 0) < 0)
+		return -EBUSY;
+
+	status = tpm_tis_i2c_status(chip);
+	if ((status & TPM_STS_COMMAND_READY) == 0) {
+		tpm_tis_i2c_ready(chip);
+		if (wait_for_stat(chip, TPM_STS_COMMAND_READY,
+				  chip->vendor.timeout_b, &status) < 0) {
+			rc = -ETIME;
+			goto out_err;
+		}
+	}
+
+	burstcnt = get_burstcount(chip);
+
+	/* burstcount < 0 -> tpm is busy */
+	if (burstcnt < 0)
+		return burstcnt;
+
+	while (count < len - 1) {
+		if (burstcnt > len - 1 - count)
+			burstcnt = len - 1 - count;
+
+#ifdef CONFIG_TPM_TIS_I2C_BURST_LIMITATION
+		if (retry && burstcnt > CONFIG_TPM_TIS_I2C_BURST_LIMITATION)
+			burstcnt = CONFIG_TPM_TIS_I2C_BURST_LIMITATION;
+#endif /* CONFIG_TPM_TIS_I2C_BURST_LIMITATION */
+
+		rc = iic_tpm_write(TPM_DATA_FIFO(chip->vendor.locality),
+				&(buf[count]), burstcnt);
+		if (rc == 0)
+			count += burstcnt;
+		else {
+			retry++;
+			wait_for_stat(chip, TPM_STS_VALID,
+				      chip->vendor.timeout_c, &status);
+
+			if ((status & TPM_STS_DATA_EXPECT) == 0) {
+				rc = -EIO;
+				goto out_err;
+			}
+		}
+	}
+
+	/* Write last byte */
+	iic_tpm_write(TPM_DATA_FIFO(chip->vendor.locality), &(buf[count]), 1);
+	wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, &status);
+	if ((status & TPM_STS_DATA_EXPECT) != 0) {
+		rc = -EIO;
+		goto out_err;
+	}
+
+	/* Go and do it */
+	iic_tpm_write(TPM_STS(chip->vendor.locality), &sts, 1);
+
+	return len;
+
+out_err:
+	tpm_tis_i2c_ready(chip);
+	/*
+	 * The TPM needs some time to clean up here,
+	 * so we sleep rather than keeping the bus busy
+	 */
+	udelay(2000);
+	release_locality(chip, chip->vendor.locality, 0);
+
+	return rc;
+}
+
+static struct tpm_vendor_specific tpm_tis_i2c = {
+	.status = tpm_tis_i2c_status,
+	.recv = tpm_tis_i2c_recv,
+	.send = tpm_tis_i2c_send,
+	.cancel = tpm_tis_i2c_ready,
+	.req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
+	.req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
+	.req_canceled = TPM_STS_COMMAND_READY,
+};
+
+
+static enum i2c_chip_type tpm_vendor_chip_type(void)
+{
+#ifdef CONFIG_OF_CONTROL
+	const void *blob = gd->fdt_blob;
+
+	if (fdtdec_next_compatible(blob, 0, COMPAT_INFINEON_SLB9645_TPM) >= 0)
+		return SLB9645;
+
+	if (fdtdec_next_compatible(blob, 0, COMPAT_INFINEON_SLB9635_TPM) >= 0)
+		return SLB9635;
+#endif
+	return UNKNOWN;
+}
+
+/* Initialisation of i2c tpm */
+int tpm_vendor_init(uint32_t dev_addr)
+{
+	u32 vendor;
+	u32 expected_did_vid;
+	uint old_addr;
+	int rc = 0;
+	struct tpm_chip *chip;
+
+	old_addr = tpm_dev.addr;
+	if (dev_addr != 0)
+		tpm_dev.addr = dev_addr;
+
+	tpm_dev.chip_type = tpm_vendor_chip_type();
+
+	chip = tpm_register_hardware(&tpm_tis_i2c);
+	if (chip < 0) {
+		rc = -ENODEV;
+		goto out_err;
+	}
+
+	/* Disable interrupts (not supported) */
+	chip->vendor.irq = 0;
+
+	/* Default timeouts */
+	chip->vendor.timeout_a = TIS_SHORT_TIMEOUT;
+	chip->vendor.timeout_b = TIS_LONG_TIMEOUT;
+	chip->vendor.timeout_c = TIS_SHORT_TIMEOUT;
+	chip->vendor.timeout_d = TIS_SHORT_TIMEOUT;
+
+	if (request_locality(chip, 0) < 0) {
+		rc = -ENODEV;
+		goto out_err;
+	}
+
+	/* Read four bytes from DID_VID register */
+	if (iic_tpm_read(TPM_DID_VID(0), (uchar *)&vendor, 4) < 0) {
+		rc = -EIO;
+		goto out_release;
+	}
+
+	if (tpm_dev.chip_type == SLB9635) {
+		vendor = be32_to_cpu(vendor);
+		expected_did_vid = TPM_TIS_I2C_DID_VID_9635;
+	} else {
+		/* device id and byte order has changed for newer i2c tpms */
+		expected_did_vid = TPM_TIS_I2C_DID_VID_9645;
+	}
+
+	if (tpm_dev.chip_type != UNKNOWN && vendor != expected_did_vid) {
+		error("Vendor id did not match! ID was %08x\n", vendor);
+		rc = -ENODEV;
+		goto out_release;
+	}
+
+	debug("1.2 TPM (chip type %s device-id 0x%X)\n",
+	      chip_name[tpm_dev.chip_type], vendor >> 16);
+
+	/*
+	 * A timeout query to TPM can be placed here.
+	 * Standard timeout values are used so far
+	 */
+
+	return 0;
+
+out_release:
+	release_locality(chip, 0, 1);
+
+out_err:
+	tpm_dev.addr = old_addr;
+	return rc;
+}
+
+void tpm_vendor_cleanup(struct tpm_chip *chip)
+{
+	release_locality(chip, chip->vendor.locality, 1);
+}
diff --git a/drivers/tpm/generic_lpc_tpm.c b/drivers/tpm/tpm_tis_lpc.c
similarity index 100%
rename from drivers/tpm/generic_lpc_tpm.c
rename to drivers/tpm/tpm_tis_lpc.c
diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
index fd8f8a7..685702e 100644
--- a/drivers/usb/eth/smsc95xx.c
+++ b/drivers/usb/eth/smsc95xx.c
@@ -798,6 +798,7 @@
 static const struct smsc95xx_dongle smsc95xx_dongles[] = {
 	{ 0x0424, 0xec00 },	/* LAN9512/LAN9514 Ethernet */
 	{ 0x0424, 0x9500 },	/* LAN9500 Ethernet */
+	{ 0x0424, 0x9730 },	/* LAN9730 Ethernet (HSIC) */
 	{ 0x0000, 0x0000 }	/* END - Do not remove */
 };
 
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 4c00081..71cc0f2 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -610,7 +610,9 @@
 
 #ifdef CONFIG_USB_DEV_PULLUP_GPIO
 	/* Turn on the USB connection by enabling the pullup resistor */
-	set_GPIO_mode(CONFIG_USB_DEV_PULLUP_GPIO | GPIO_OUT);
+	writel(readl(GPDR(CONFIG_USB_DEV_PULLUP_GPIO))
+		     | GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
+	       GPDR(CONFIG_USB_DEV_PULLUP_GPIO));
 	writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), GPSR(CONFIG_USB_DEV_PULLUP_GPIO));
 #else
 	/* Host port 2 transceiver D+ pull up enable */
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index c816878..e0f3e4b 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -122,6 +122,31 @@
 #define ehci_is_TDI()	(0)
 #endif
 
+int __ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
+{
+	return PORTSC_PSPD(reg);
+}
+
+int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
+	__attribute__((weak, alias("__ehci_get_port_speed")));
+
+void __ehci_set_usbmode(int index)
+{
+	uint32_t tmp;
+	uint32_t *reg_ptr;
+
+	reg_ptr = (uint32_t *)((u8 *)&ehcic[index].hcor->or_usbcmd + USBMODE);
+	tmp = ehci_readl(reg_ptr);
+	tmp |= USBMODE_CM_HC;
+#if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
+	tmp |= USBMODE_BE;
+#endif
+	ehci_writel(reg_ptr, tmp);
+}
+
+void ehci_set_usbmode(int index)
+	__attribute__((weak, alias("__ehci_set_usbmode")));
+
 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
 {
 	mdelay(50);
@@ -149,8 +174,6 @@
 static int ehci_reset(int index)
 {
 	uint32_t cmd;
-	uint32_t tmp;
-	uint32_t *reg_ptr;
 	int ret = 0;
 
 	cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
@@ -163,15 +186,8 @@
 		goto out;
 	}
 
-	if (ehci_is_TDI()) {
-		reg_ptr = (uint32_t *)((u8 *)ehcic[index].hcor + USBMODE);
-		tmp = ehci_readl(reg_ptr);
-		tmp |= USBMODE_CM_HC;
-#if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
-		tmp |= USBMODE_BE;
-#endif
-		ehci_writel(reg_ptr, tmp);
-	}
+	if (ehci_is_TDI())
+		ehci_set_usbmode(index);
 
 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
 	cmd = ehci_readl(&ehcic[index].hcor->or_txfilltuning);
@@ -587,16 +603,6 @@
 	return -1;
 }
 
-static inline int min3(int a, int b, int c)
-{
-
-	if (b < a)
-		a = b;
-	if (c < a)
-		a = c;
-	return a;
-}
-
 int
 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 		 int length, struct devrequest *req)
@@ -607,15 +613,14 @@
 	int len, srclen;
 	uint32_t reg;
 	uint32_t *status_reg;
+	int port = le16_to_cpu(req->index) & 0xff;
 	struct ehci_ctrl *ctrl = dev->controller;
 
-	if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
-		printf("The request port(%d) is not configured\n",
-			le16_to_cpu(req->index) - 1);
+	if (port > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
+		printf("The request port(%d) is not configured\n", port - 1);
 		return -1;
 	}
-	status_reg = (uint32_t *)&ctrl->hcor->or_portsc[
-						le16_to_cpu(req->index) - 1];
+	status_reg = (uint32_t *)&ctrl->hcor->or_portsc[port - 1];
 	srclen = 0;
 
 	debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
@@ -711,7 +716,7 @@
 			tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
 
 		if (ehci_is_TDI()) {
-			switch (PORTSC_PSPD(reg)) {
+			switch (ehci_get_port_speed(ctrl->hcor, reg)) {
 			case PORTSC_PSPD_FS:
 				break;
 			case PORTSC_PSPD_LS:
@@ -732,7 +737,7 @@
 			tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
 		if (reg & EHCI_PS_OCC)
 			tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
-		if (ctrl->portreset & (1 << le16_to_cpu(req->index)))
+		if (ctrl->portreset & (1 << port))
 			tmpbuf[2] |= USB_PORT_STAT_C_RESET;
 
 		srcptr = tmpbuf;
@@ -758,7 +763,7 @@
 			    EHCI_PS_IS_LOWSPEED(reg)) {
 				/* Low speed device, give up ownership. */
 				debug("port %d low speed --> companion\n",
-				      req->index - 1);
+				      port - 1);
 				reg |= EHCI_PS_PO;
 				ehci_writel(status_reg, reg);
 				break;
@@ -784,13 +789,17 @@
 				ret = handshake(status_reg, EHCI_PS_PR, 0,
 						2 * 1000);
 				if (!ret)
-					ctrl->portreset |=
-						1 << le16_to_cpu(req->index);
+					ctrl->portreset |= 1 << port;
 				else
 					printf("port(%d) reset error\n",
-					le16_to_cpu(req->index) - 1);
+					       port - 1);
 			}
 			break;
+		case USB_PORT_FEAT_TEST:
+			reg &= ~(0xf << 16);
+			reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
+			ehci_writel(status_reg, reg);
+			break;
 		default:
 			debug("unknown feature %x\n", le16_to_cpu(req->value));
 			goto unknown;
@@ -817,7 +826,7 @@
 			reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
 			break;
 		case USB_PORT_FEAT_C_RESET:
-			ctrl->portreset &= ~(1 << le16_to_cpu(req->index));
+			ctrl->portreset &= ~(1 << port);
 			break;
 		default:
 			debug("unknown feature %x\n", le16_to_cpu(req->value));
diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
index adbed5c..f43c38d 100644
--- a/drivers/usb/host/ehci-mx5.c
+++ b/drivers/usb/host/ehci-mx5.c
@@ -21,8 +21,6 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
 
 #include "ehci.h"
 
@@ -87,77 +85,6 @@
 /* USB_CTRL_1 */
 #define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)
 
-/* USB pin configuration */
-#define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
-			PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
-
-#ifdef CONFIG_MX51
-/*
- * Configure the MX51 USB H1 IOMUX
- */
-void setup_iomux_usb_h1(void)
-{
-	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG);
-
-	mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG);
-}
-
-/*
- * Configure the MX51 USB H2 IOMUX
- */
-void setup_iomux_usb_h2(void)
-{
-	mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG);
-
-	mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG);
-}
-#endif
-
 int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index efd711d..2060a3e 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -42,7 +42,7 @@
 	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
 		;
 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
-	defined(CONFIG_AT91SAM9X5)
+	defined(CONFIG_AT91SAM9X5) || defined(CONFIG_SAMA5D3)
 	/* Enable UPLL */
 	writel(readl(&pmc->uckr) | AT91_PMC_UPLLEN | AT91_PMC_BIASEN,
 		&pmc->uckr);
@@ -54,8 +54,13 @@
 #endif
 
 	/* Enable USB host clock. */
+#ifdef CONFIG_SAMA5D3
+	writel(1 << (ATMEL_ID_UHP - 32), &pmc->pcer1);
+#else
 	writel(1 << ATMEL_ID_UHP, &pmc->pcer);
-#ifdef CONFIG_AT91SAM9261
+#endif
+
+#if defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
 	writel(ATMEL_PMC_UHP | AT91_PMC_HCK0, &pmc->scer);
 #else
 	writel(ATMEL_PMC_UHP, &pmc->scer);
@@ -69,8 +74,13 @@
 	at91_pmc_t *pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
 
 	/* Disable USB host clock. */
+#ifdef CONFIG_SAMA5D3
+	writel(1 << (ATMEL_ID_UHP - 32), &pmc->pcdr1);
+#else
 	writel(1 << ATMEL_ID_UHP, &pmc->pcdr);
-#ifdef CONFIG_AT91SAM9261
+#endif
+
+#if defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
 	writel(ATMEL_PMC_UHP | AT91_PMC_HCK0, &pmc->scdr);
 #else
 	writel(ATMEL_PMC_UHP, &pmc->scdr);
@@ -83,7 +93,7 @@
 	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0)
 		;
 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
-	defined(CONFIG_AT91SAM9X5)
+	defined(CONFIG_AT91SAM9X5) || defined(CONFIG_SAMA5D3)
 	/* Disable UPLL */
 	writel(readl(&pmc->uckr) & (~AT91_PMC_UPLLEN), &pmc->uckr);
 	while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU)
diff --git a/drivers/usb/phy/twl4030.c b/drivers/usb/phy/twl4030.c
index 54d2e61..74f1dcc 100644
--- a/drivers/usb/phy/twl4030.c
+++ b/drivers/usb/phy/twl4030.c
@@ -54,7 +54,7 @@
 {
 	int ret;
 
-	ret = twl4030_i2c_write_u8(TWL4030_CHIP_USB, data, address);
+	ret = twl4030_i2c_write_u8(TWL4030_CHIP_USB, address, data);
 	if (ret != 0)
 		printf("TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
 
@@ -66,7 +66,7 @@
 	u8 data;
 	int ret;
 
-	ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, &data, address);
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, address, &data);
 	if (ret == 0)
 		ret = data;
 	else
@@ -78,40 +78,40 @@
 static void twl4030_usb_ldo_init(void)
 {
 	/* Enable writing to power configuration registers */
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0xC0,
-			     TWL4030_PM_MASTER_PROTECT_KEY);
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x0C,
-			     TWL4030_PM_MASTER_PROTECT_KEY);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PROTECT_KEY, 0xC0);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PROTECT_KEY, 0x0C);
 
 	/* put VUSB3V1 LDO in active state */
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
-			     TWL4030_PM_RECEIVER_VUSB_DEDICATED2);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+			     TWL4030_PM_RECEIVER_VUSB_DEDICATED2, 0x00);
 
 	/* input to VUSB3V1 LDO is from VBAT, not VBUS */
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x14,
-			     TWL4030_PM_RECEIVER_VUSB_DEDICATED1);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+			     TWL4030_PM_RECEIVER_VUSB_DEDICATED1, 0x14);
 
 	/* turn on 3.1V regulator */
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20,
-			     TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP);
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
-			     TWL4030_PM_RECEIVER_VUSB3V1_TYPE);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+			     TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP, 0x20);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+			     TWL4030_PM_RECEIVER_VUSB3V1_TYPE, 0x00);
 
 	/* turn on 1.5V regulator */
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20,
-			     TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP);
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
-			     TWL4030_PM_RECEIVER_VUSB1V5_TYPE);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+			     TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP, 0x20);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+			     TWL4030_PM_RECEIVER_VUSB1V5_TYPE, 0x00);
 
 	/* turn on 1.8V regulator */
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20,
-			     TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP);
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
-			     TWL4030_PM_RECEIVER_VUSB1V8_TYPE);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+			     TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP, 0x20);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+			     TWL4030_PM_RECEIVER_VUSB1V8_TYPE, 0x00);
 
 	/* disable access to power configuration registers */
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x00,
-			     TWL4030_PM_MASTER_PROTECT_KEY);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PROTECT_KEY, 0x00);
 }
 
 static void twl4030_phy_power(void)
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 53952ab..68ff34b 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -49,6 +49,7 @@
 COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
 COBJS-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+COBJS-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
 COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index b769222..b10f159 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -151,6 +151,10 @@
 #endif
 #endif
 
+#ifdef CONFIG_VIDEO_MXS
+#define VIDEO_FB_16BPP_WORD_SWAP
+#endif
+
 /*
  * Defines for the MB862xx driver
  */
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
new file mode 100644
index 0000000..461ff6e
--- /dev/null
+++ b/drivers/video/mxsfb.c
@@ -0,0 +1,189 @@
+/*
+ * Freescale i.MX23/i.MX28 LCDIF driver
+ *
+ * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <malloc.h>
+#include <video_fb.h>
+
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+
+#include "videomodes.h"
+
+#define	PS2KHZ(ps)	(1000000000UL / (ps))
+
+static GraphicDevice panel;
+
+/*
+ * DENX M28EVK:
+ * setenv videomode
+ * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
+ *       le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
+ */
+
+static void mxs_lcd_init(GraphicDevice *panel,
+			struct ctfb_res_modes *mode, int bpp)
+{
+	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+	uint32_t word_len = 0, bus_width = 0;
+	uint8_t valid_data = 0;
+
+	/* Kick in the LCDIF clock */
+	mxs_set_lcdclk(PS2KHZ(mode->pixclock));
+
+	/* Restart the LCDIF block */
+	mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
+
+	switch (bpp) {
+	case 24:
+		word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
+		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
+		valid_data = 0x7;
+		break;
+	case 18:
+		word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
+		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
+		valid_data = 0x7;
+		break;
+	case 16:
+		word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
+		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
+		valid_data = 0xf;
+		break;
+	case 8:
+		word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
+		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
+		valid_data = 0xf;
+		break;
+	}
+
+	writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
+		LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
+		&regs->hw_lcdif_ctrl);
+
+	writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
+		&regs->hw_lcdif_ctrl1);
+	writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
+		&regs->hw_lcdif_transfer_count);
+
+	writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
+		LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
+		LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
+		mode->vsync_len, &regs->hw_lcdif_vdctrl0);
+	writel(mode->upper_margin + mode->lower_margin +
+		mode->vsync_len + mode->yres,
+		&regs->hw_lcdif_vdctrl1);
+	writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
+		(mode->left_margin + mode->right_margin +
+		mode->hsync_len + mode->xres),
+		&regs->hw_lcdif_vdctrl2);
+	writel(((mode->left_margin + mode->hsync_len) <<
+		LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
+		(mode->upper_margin + mode->vsync_len),
+		&regs->hw_lcdif_vdctrl3);
+	writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
+		&regs->hw_lcdif_vdctrl4);
+
+	writel(panel->frameAdrs, &regs->hw_lcdif_cur_buf);
+	writel(panel->frameAdrs, &regs->hw_lcdif_next_buf);
+
+	/* Flush FIFO first */
+	writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
+
+	/* Sync signals ON */
+	setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
+
+	/* FIFO cleared */
+	writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
+
+	/* RUN! */
+	writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
+}
+
+void *video_hw_init(void)
+{
+	int bpp = -1;
+	char *penv;
+	void *fb;
+	struct ctfb_res_modes mode;
+
+	puts("Video: ");
+
+	/* Suck display configuration from "videomode" variable */
+	penv = getenv("videomode");
+	if (!penv) {
+		printf("MXSFB: 'videomode' variable not set!");
+		return NULL;
+	}
+
+	bpp = video_get_params(&mode, penv);
+
+	/* fill in Graphic device struct */
+	sprintf(panel.modeIdent, "%dx%dx%d",
+			mode.xres, mode.yres, bpp);
+
+	panel.winSizeX = mode.xres;
+	panel.winSizeY = mode.yres;
+	panel.plnSizeX = mode.xres;
+	panel.plnSizeY = mode.yres;
+
+	switch (bpp) {
+	case 24:
+	case 18:
+		panel.gdfBytesPP = 4;
+		panel.gdfIndex = GDF_32BIT_X888RGB;
+		break;
+	case 16:
+		panel.gdfBytesPP = 2;
+		panel.gdfIndex = GDF_16BIT_565RGB;
+		break;
+	case 8:
+		panel.gdfBytesPP = 1;
+		panel.gdfIndex = GDF__8BIT_INDEX;
+		break;
+	default:
+		printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
+		return NULL;
+	}
+
+	panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
+
+	/* Allocate framebuffer */
+	fb = malloc(panel.memSize);
+	if (!fb) {
+		printf("MXSFB: Error allocating framebuffer!\n");
+		return NULL;
+	}
+
+	/* Wipe framebuffer */
+	memset(fb, 0, panel.memSize);
+
+	panel.frameAdrs = (u32)fb;
+
+	printf("%s\n", panel.modeIdent);
+
+	/* Start framebuffer */
+	mxs_lcd_init(&panel, &mode, bpp);
+
+	return (void *)&panel;
+}
diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c
index b40ec36..5e4c685 100644
--- a/drivers/video/pxa_lcd.c
+++ b/drivers/video/pxa_lcd.c
@@ -248,6 +248,38 @@
 };
 #endif /* CONFIG_ACX517AKN */
 
+#ifdef CONFIG_ACX544AKN
+
+# define LCD_BPP	LCD_COLOR16
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0	0x003008f9
+# define REG_LCCR3	0x04700007 /* 16bpp */
+
+vidinfo_t panel_info = {
+	.vl_col		= 320,
+	.vl_row		= 320,
+	.vl_width	= 320,
+	.vl_height	= 320,
+	.vl_clkp	= CONFIG_SYS_LOW,
+	.vl_oep		= CONFIG_SYS_LOW,
+	.vl_hsp		= CONFIG_SYS_LOW,
+	.vl_vsp		= CONFIG_SYS_LOW,
+	.vl_dp		= CONFIG_SYS_LOW,
+	.vl_bpix	= LCD_BPP,
+	.vl_lbw		= 0,
+	.vl_splt	= 0,
+	.vl_clor	= 1,
+	.vl_tft		= 1,
+	.vl_hpw		= 0x05,
+	.vl_blw		= 0x13,
+	.vl_elw		= 0x08,
+	.vl_vpw		= 0x02,
+	.vl_bfw		= 0x07,
+	.vl_efw		= 0x05,
+};
+#endif /* CONFIG_ACX544AKN */
+
 /*----------------------------------------------------------------------*/
 
 #ifdef CONFIG_LQ038J7DH53
@@ -378,7 +410,7 @@
 #endif /* LCD_MONOCHROME */
 
 /*----------------------------------------------------------------------*/
-void lcd_enable (void)
+__weak void lcd_enable(void)
 {
 }
 
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 13e7c37..d57578d 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -33,6 +33,7 @@
 COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
 COBJS-$(CONFIG_S5P)               += s5p_wdt.o
 COBJS-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
+COBJS-$(CONFIG_BFIN_WATCHDOG)  += bfin_wdt.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/arch/blackfin/cpu/watchdog.c b/drivers/watchdog/bfin_wdt.c
similarity index 64%
rename from arch/blackfin/cpu/watchdog.c
rename to drivers/watchdog/bfin_wdt.c
index 1886bda..7a6756b 100644
--- a/arch/blackfin/cpu/watchdog.c
+++ b/drivers/watchdog/bfin_wdt.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <watchdog.h>
 #include <asm/blackfin.h>
+#include <asm/mach-common/bits/watchdog.h>
 
 void hw_watchdog_reset(void)
 {
@@ -17,7 +18,9 @@
 
 void hw_watchdog_init(void)
 {
-	bfin_write_WDOG_CNT(5 * get_sclk());	/* 5 second timeout */
+	bfin_write_WDOG_CTL(WDDIS);
+	SSYNC();
+	bfin_write_WDOG_CNT(CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000 * get_sclk());
 	hw_watchdog_reset();
-	bfin_write_WDOG_CTL(0x0);
+	bfin_write_WDOG_CTL(WDEN);
 }
diff --git a/fs/ext4/dev.c b/fs/ext4/dev.c
index 464a67d..81b7633 100644
--- a/fs/ext4/dev.c
+++ b/fs/ext4/dev.c
@@ -40,6 +40,7 @@
 #include <config.h>
 #include <ext4fs.h>
 #include <ext_common.h>
+#include "ext4_common.h"
 
 unsigned long part_offset;
 
@@ -48,37 +49,41 @@
 
 void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info)
 {
+	assert(rbdd->blksz == (1 << rbdd->log2blksz));
 	ext4fs_block_dev_desc = rbdd;
+	get_fs()->dev_desc = rbdd;
 	part_info = info;
 	part_offset = info->start;
-	get_fs()->total_sect = (info->size * info->blksz) / SECTOR_SIZE;
-	get_fs()->dev_desc = rbdd;
+	get_fs()->total_sect = (info->size * info->blksz) >>
+		get_fs()->dev_desc->log2blksz;
 }
 
 int ext4fs_devread(int sector, int byte_offset, int byte_len, char *buf)
 {
-	ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, SECTOR_SIZE);
 	unsigned block_len;
+	int log2blksz = ext4fs_block_dev_desc->log2blksz;
+	ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, (ext4fs_block_dev_desc ?
+						 ext4fs_block_dev_desc->blksz :
+						 0));
+	if (ext4fs_block_dev_desc == NULL) {
+		printf("** Invalid Block Device Descriptor (NULL)\n");
+		return 0;
+	}
 
 	/* Check partition boundaries */
-	if ((sector < 0)
-	    || ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) >=
-		part_info->size)) {
+	if ((sector < 0) ||
+	    ((sector + ((byte_offset + byte_len - 1) >> log2blksz))
+	     >= part_info->size)) {
 		printf("%s read outside partition %d\n", __func__, sector);
 		return 0;
 	}
 
 	/* Get the read to the beginning of a partition */
-	sector += byte_offset >> SECTOR_BITS;
-	byte_offset &= SECTOR_SIZE - 1;
+	sector += byte_offset >> log2blksz;
+	byte_offset &= ext4fs_block_dev_desc->blksz - 1;
 
 	debug(" <%d, %d, %d>\n", sector, byte_offset, byte_len);
 
-	if (ext4fs_block_dev_desc == NULL) {
-		printf("** Invalid Block Device Descriptor (NULL)\n");
-		return 0;
-	}
-
 	if (byte_offset != 0) {
 		/* read first part which isn't aligned with start of sector */
 		if (ext4fs_block_dev_desc->
@@ -89,9 +94,12 @@
 			return 0;
 		}
 		memcpy(buf, sec_buf + byte_offset,
-			min(SECTOR_SIZE - byte_offset, byte_len));
-		buf += min(SECTOR_SIZE - byte_offset, byte_len);
-		byte_len -= min(SECTOR_SIZE - byte_offset, byte_len);
+			min(ext4fs_block_dev_desc->blksz
+			    - byte_offset, byte_len));
+		buf += min(ext4fs_block_dev_desc->blksz
+			   - byte_offset, byte_len);
+		byte_len -= min(ext4fs_block_dev_desc->blksz
+				- byte_offset, byte_len);
 		sector++;
 	}
 
@@ -99,12 +107,12 @@
 		return 1;
 
 	/* read sector aligned part */
-	block_len = byte_len & ~(SECTOR_SIZE - 1);
+	block_len = byte_len & ~(ext4fs_block_dev_desc->blksz - 1);
 
 	if (block_len == 0) {
-		ALLOC_CACHE_ALIGN_BUFFER(u8, p, SECTOR_SIZE);
+		ALLOC_CACHE_ALIGN_BUFFER(u8, p, ext4fs_block_dev_desc->blksz);
 
-		block_len = SECTOR_SIZE;
+		block_len = ext4fs_block_dev_desc->blksz;
 		ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc->dev,
 						  part_info->start + sector,
 						  1, (unsigned long *)p);
@@ -114,16 +122,16 @@
 
 	if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc->dev,
 					       part_info->start + sector,
-					       block_len / SECTOR_SIZE,
+					       block_len >> log2blksz,
 					       (unsigned long *) buf) !=
-					       block_len / SECTOR_SIZE) {
+					       block_len >> log2blksz) {
 		printf(" ** %s read error - block\n", __func__);
 		return 0;
 	}
-	block_len = byte_len & ~(SECTOR_SIZE - 1);
+	block_len = byte_len & ~(ext4fs_block_dev_desc->blksz - 1);
 	buf += block_len;
 	byte_len -= block_len;
-	sector += block_len / SECTOR_SIZE;
+	sector += block_len / ext4fs_block_dev_desc->blksz;
 
 	if (byte_len != 0) {
 		/* read rest of data which are not in whole sector */
@@ -138,3 +146,13 @@
 	}
 	return 1;
 }
+
+int ext4_read_superblock(char *buffer)
+{
+	struct ext_filesystem *fs = get_fs();
+	int sect = SUPERBLOCK_START >> fs->dev_desc->log2blksz;
+	int off = SUPERBLOCK_START % fs->dev_desc->blksz;
+
+	return ext4fs_devread(sect, off, SUPERBLOCK_SIZE,
+				buffer);
+}
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index f12b805..58880b4 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -71,18 +71,18 @@
 	uint64_t startblock;
 	uint64_t remainder;
 	unsigned char *temp_ptr = NULL;
-	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, sec_buf, SECTOR_SIZE);
 	struct ext_filesystem *fs = get_fs();
+	int log2blksz = fs->dev_desc->log2blksz;
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, sec_buf, fs->dev_desc->blksz);
 
-	startblock = off / (uint64_t)SECTOR_SIZE;
+	startblock = off >> log2blksz;
 	startblock += part_offset;
-	remainder = off % (uint64_t)SECTOR_SIZE;
-	remainder &= SECTOR_SIZE - 1;
+	remainder = off & (uint64_t)(fs->dev_desc->blksz - 1);
 
 	if (fs->dev_desc == NULL)
 		return;
 
-	if ((startblock + (size / SECTOR_SIZE)) >
+	if ((startblock + (size >> log2blksz)) >
 	    (part_offset + fs->total_sect)) {
 		printf("part_offset is %lu\n", part_offset);
 		printf("total_sector is %llu\n", fs->total_sect);
@@ -101,10 +101,10 @@
 						  startblock, 1, sec_buf);
 		}
 	} else {
-		if (size / SECTOR_SIZE != 0) {
+		if (size >> log2blksz != 0) {
 			fs->dev_desc->block_write(fs->dev_desc->dev,
 						  startblock,
-						  size / SECTOR_SIZE,
+						  size >> log2blksz,
 						  (unsigned long *)buf);
 		} else {
 			fs->dev_desc->block_read(fs->dev_desc->dev,
@@ -1459,6 +1459,7 @@
 {
 	long int blkno;
 	unsigned int blkoff, desc_per_blk;
+	int log2blksz = get_fs()->dev_desc->log2blksz;
 
 	desc_per_blk = EXT2_BLOCK_SIZE(data) / sizeof(struct ext2_block_group);
 
@@ -1469,7 +1470,7 @@
 	debug("ext4fs read %d group descriptor (blkno %ld blkoff %u)\n",
 	      group, blkno, blkoff);
 
-	return ext4fs_devread(blkno << LOG2_EXT2_BLOCK_SIZE(data),
+	return ext4fs_devread(blkno << (LOG2_BLOCK_SIZE(data) - log2blksz),
 			      blkoff, sizeof(struct ext2_block_group),
 			      (char *)blkgrp);
 }
@@ -1479,6 +1480,7 @@
 	struct ext2_block_group blkgrp;
 	struct ext2_sblock *sblock = &data->sblock;
 	struct ext_filesystem *fs = get_fs();
+	int log2blksz = get_fs()->dev_desc->log2blksz;
 	int inodes_per_block, status;
 	long int blkno;
 	unsigned int blkoff;
@@ -1495,7 +1497,8 @@
 	    (ino % __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
 	blkoff = (ino % inodes_per_block) * fs->inodesz;
 	/* Read the inode. */
-	status = ext4fs_devread(blkno << LOG2_EXT2_BLOCK_SIZE(data), blkoff,
+	status = ext4fs_devread(blkno << (LOG2_BLOCK_SIZE(data) - log2blksz),
+				blkoff,
 				sizeof(struct ext2_inode), (char *)inode);
 	if (status == 0)
 		return 0;
@@ -1515,7 +1518,9 @@
 	unsigned long long start;
 	/* get the blocksize of the filesystem */
 	blksz = EXT2_BLOCK_SIZE(ext4fs_root);
-	log2_blksz = LOG2_EXT2_BLOCK_SIZE(ext4fs_root);
+	log2_blksz = LOG2_BLOCK_SIZE(ext4fs_root)
+		- get_fs()->dev_desc->log2blksz;
+
 	if (le32_to_cpu(inode->flags) & EXT4_EXTENTS_FL) {
 		char *buf = zalloc(blksz);
 		if (!buf)
@@ -1523,11 +1528,11 @@
 		struct ext4_extent_header *ext_block;
 		struct ext4_extent *extent;
 		int i = -1;
-		ext_block = ext4fs_get_extent_block(ext4fs_root, buf,
-						    (struct ext4_extent_header
-						     *)inode->b.
-						    blocks.dir_blocks,
-						    fileblock, log2_blksz);
+		ext_block =
+			ext4fs_get_extent_block(ext4fs_root, buf,
+						(struct ext4_extent_header *)
+						inode->b.blocks.dir_blocks,
+						fileblock, log2_blksz);
 		if (!ext_block) {
 			printf("invalid extent block\n");
 			free(buf);
@@ -1839,7 +1844,7 @@
 		blknr = __le32_to_cpu(ext4fs_indir3_block
 				      [rblock % perblock_child]);
 	}
-	debug("ext4fs_read_block %ld\n", blknr);
+	debug("read_allocated_block %ld\n", blknr);
 
 	return blknr;
 }
@@ -2193,13 +2198,12 @@
 	struct ext2_data *data;
 	int status;
 	struct ext_filesystem *fs = get_fs();
-	data = zalloc(sizeof(struct ext2_data));
+	data = zalloc(SUPERBLOCK_SIZE);
 	if (!data)
 		return 0;
 
 	/* Read the superblock. */
-	status = ext4fs_devread(1 * 2, 0, sizeof(struct ext2_sblock),
-				(char *)&data->sblock);
+	status = ext4_read_superblock((char *)&data->sblock);
 
 	if (status == 0)
 		goto fail;
diff --git a/fs/ext4/ext4_common.h b/fs/ext4/ext4_common.h
index 72cd020..6571df6 100644
--- a/fs/ext4/ext4_common.h
+++ b/fs/ext4/ext4_common.h
@@ -49,7 +49,7 @@
 
 #define S_IFLNK		0120000		/* symbolic link */
 #define BLOCK_NO_ONE		1
-#define SUPERBLOCK_SECTOR	2
+#define SUPERBLOCK_START	(2 * 512)
 #define SUPERBLOCK_SIZE	1024
 #define F_FILE			1
 
diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c
index ba4a7bb..81aa5fc 100644
--- a/fs/ext4/ext4_journal.c
+++ b/fs/ext4/ext4_journal.c
@@ -534,16 +534,14 @@
 		jsb->s_start = cpu_to_be32(1);
 		jsb->s_sequence = cpu_to_be32(be32_to_cpu(jsb->s_sequence) + 1);
 		/* get the superblock */
-		ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE,
-			       (char *)fs->sb);
+		ext4_read_superblock((char *)fs->sb);
 		fs->sb->feature_incompat |= EXT3_FEATURE_INCOMPAT_RECOVER;
 
 		/* Update the super block */
 		put_ext4((uint64_t) (SUPERBLOCK_SIZE),
 			 (struct ext2_sblock *)fs->sb,
 			 (uint32_t) SUPERBLOCK_SIZE);
-		ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE,
-			       (char *)fs->sb);
+		ext4_read_superblock((char *)fs->sb);
 
 		blknr = read_allocated_block(&inode_journal,
 					 EXT2_JOURNAL_SUPERBLOCK);
diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c
index c4e399c..0c1f62b 100644
--- a/fs/ext4/ext4_write.c
+++ b/fs/ext4/ext4_write.c
@@ -614,14 +614,13 @@
 	/* populate fs */
 	fs->blksz = EXT2_BLOCK_SIZE(ext4fs_root);
 	fs->inodesz = INODE_SIZE_FILESYSTEM(ext4fs_root);
-	fs->sect_perblk = fs->blksz / SECTOR_SIZE;
+	fs->sect_perblk = fs->blksz >> fs->dev_desc->log2blksz;
 
 	/* get the superblock */
 	fs->sb = zalloc(SUPERBLOCK_SIZE);
 	if (!fs->sb)
 		return -ENOMEM;
-	if (!ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE,
-			(char *)fs->sb))
+	if (!ext4_read_superblock((char *)fs->sb))
 		goto fail;
 
 	/* init journal */
@@ -722,7 +721,7 @@
 	ext4fs_free_journal();
 
 	/* get the superblock */
-	ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE, (char *)fs->sb);
+	ext4_read_superblock((char *)fs->sb);
 	fs->sb->feature_incompat &= ~EXT3_FEATURE_INCOMPAT_RECOVER;
 	put_ext4((uint64_t)(SUPERBLOCK_SIZE),
 		 (struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE);
@@ -766,9 +765,10 @@
 {
 	int i;
 	int blockcnt;
-	int log2blocksize = LOG2_EXT2_BLOCK_SIZE(ext4fs_root);
 	unsigned int filesize = __le32_to_cpu(file_inode->size);
 	struct ext_filesystem *fs = get_fs();
+	int log2blksz = fs->dev_desc->log2blksz;
+	int log2_fs_blocksize = LOG2_BLOCK_SIZE(ext4fs_root) - log2blksz;
 	int previous_block_number = -1;
 	int delayed_start = 0;
 	int delayed_extent = 0;
@@ -789,16 +789,16 @@
 		if (blknr < 0)
 			return -1;
 
-		blknr = blknr << log2blocksize;
+		blknr = blknr << log2_fs_blocksize;
 
 		if (blknr) {
 			if (previous_block_number != -1) {
 				if (delayed_next == blknr) {
 					delayed_extent += blockend;
-					delayed_next += blockend >> SECTOR_BITS;
+					delayed_next += blockend >> log2blksz;
 				} else {	/* spill */
-					put_ext4((uint64_t) (delayed_start *
-							     SECTOR_SIZE),
+					put_ext4((uint64_t)
+						 (delayed_start << log2blksz),
 						 delayed_buf,
 						 (uint32_t) delayed_extent);
 					previous_block_number = blknr;
@@ -806,7 +806,7 @@
 					delayed_extent = blockend;
 					delayed_buf = buf;
 					delayed_next = blknr +
-					    (blockend >> SECTOR_BITS);
+					    (blockend >> log2blksz);
 				}
 			} else {
 				previous_block_number = blknr;
@@ -814,13 +814,14 @@
 				delayed_extent = blockend;
 				delayed_buf = buf;
 				delayed_next = blknr +
-				    (blockend >> SECTOR_BITS);
+				    (blockend >> log2blksz);
 			}
 		} else {
 			if (previous_block_number != -1) {
 				/* spill */
-				put_ext4((uint64_t) (delayed_start *
-						     SECTOR_SIZE), delayed_buf,
+				put_ext4((uint64_t) (delayed_start <<
+						     log2blksz),
+					 delayed_buf,
 					 (uint32_t) delayed_extent);
 				previous_block_number = -1;
 			}
@@ -830,7 +831,7 @@
 	}
 	if (previous_block_number != -1) {
 		/* spill */
-		put_ext4((uint64_t) (delayed_start * SECTOR_SIZE),
+		put_ext4((uint64_t) (delayed_start << log2blksz),
 			 delayed_buf, (uint32_t) delayed_extent);
 		previous_block_number = -1;
 	}
@@ -921,7 +922,8 @@
 	/* Allocate data blocks */
 	ext4fs_allocate_blocks(file_inode, blocks_remaining,
 			       &blks_reqd_for_file);
-	file_inode->blockcnt = (blks_reqd_for_file * fs->blksz) / SECTOR_SIZE;
+	file_inode->blockcnt = (blks_reqd_for_file * fs->blksz) >>
+		fs->dev_desc->log2blksz;
 
 	temp_ptr = zalloc(fs->blksz);
 	if (!temp_ptr)
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index 4dddde2..1954afb 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -60,10 +60,12 @@
 int ext4fs_read_file(struct ext2fs_node *node, int pos,
 		unsigned int len, char *buf)
 {
+	struct ext_filesystem *fs = get_fs();
 	int i;
 	int blockcnt;
-	int log2blocksize = LOG2_EXT2_BLOCK_SIZE(node->data);
-	int blocksize = 1 << (log2blocksize + DISK_SECTOR_BITS);
+	int log2blksz = fs->dev_desc->log2blksz;
+	int log2_fs_blocksize = LOG2_BLOCK_SIZE(node->data) - log2blksz;
+	int blocksize = (1 << (log2_fs_blocksize + log2blksz));
 	unsigned int filesize = __le32_to_cpu(node->inode.size);
 	int previous_block_number = -1;
 	int delayed_start = 0;
@@ -88,7 +90,7 @@
 		if (blknr < 0)
 			return -1;
 
-		blknr = blknr << log2blocksize;
+		blknr = blknr << log2_fs_blocksize;
 
 		/* Last block.  */
 		if (i == blockcnt - 1) {
@@ -110,7 +112,7 @@
 			if (previous_block_number != -1) {
 				if (delayed_next == blknr) {
 					delayed_extent += blockend;
-					delayed_next += blockend >> SECTOR_BITS;
+					delayed_next += blockend >> log2blksz;
 				} else {	/* spill */
 					status = ext4fs_devread(delayed_start,
 							delayed_skipfirst,
@@ -124,7 +126,7 @@
 					delayed_skipfirst = skipfirst;
 					delayed_buf = buf;
 					delayed_next = blknr +
-						(blockend >> SECTOR_BITS);
+						(blockend >> log2blksz);
 				}
 			} else {
 				previous_block_number = blknr;
@@ -133,7 +135,7 @@
 				delayed_skipfirst = skipfirst;
 				delayed_buf = buf;
 				delayed_next = blknr +
-					(blockend >> SECTOR_BITS);
+					(blockend >> log2blksz);
 			}
 		} else {
 			if (previous_block_number != -1) {
diff --git a/fs/yaffs2/yaffs_mtdif.c b/fs/yaffs2/yaffs_mtdif.c
index db49052..6fcba04 100644
--- a/fs/yaffs2/yaffs_mtdif.c
+++ b/fs/yaffs2/yaffs_mtdif.c
@@ -70,22 +70,22 @@
 	u8 spareAsBytes[8]; /* OOB */
 
 	if (data && !spare)
-		retval = mtd->write(mtd, addr, dev->data_bytes_per_chunk,
+		retval = mtd_write(mtd, addr, dev->data_bytes_per_chunk,
 				&dummy, data);
 	else if (spare) {
 		if (dev->param.use_nand_ecc) {
 			translate_spare2oob(spare, spareAsBytes);
-			ops.mode = MTD_OOB_AUTO;
+			ops.mode = MTD_OPS_AUTO_OOB;
 			ops.ooblen = 8; /* temp hack */
 		} else {
-			ops.mode = MTD_OOB_RAW;
+			ops.mode = MTD_OPS_RAW;
 			ops.ooblen = YAFFS_BYTES_PER_SPARE;
 		}
 		ops.len = data ? dev->data_bytes_per_chunk : ops.ooblen;
 		ops.datbuf = (u8 *)data;
 		ops.ooboffs = 0;
 		ops.oobbuf = spareAsBytes;
-		retval = mtd->write_oob(mtd, addr, &ops);
+		retval = mtd_write_oob(mtd, addr, &ops);
 	}
 
 	if (retval == 0)
@@ -106,21 +106,21 @@
 	u8 spareAsBytes[8]; /* OOB */
 
 	if (data && !spare)
-		retval = mtd->read(mtd, addr, dev->data_bytes_per_chunk,
+		retval = mtd_read(mtd, addr, dev->data_bytes_per_chunk,
 				&dummy, data);
 	else if (spare) {
 		if (dev->param.use_nand_ecc) {
-			ops.mode = MTD_OOB_AUTO;
+			ops.mode = MTD_OPS_AUTO_OOB;
 			ops.ooblen = 8; /* temp hack */
 		} else {
-			ops.mode = MTD_OOB_RAW;
+			ops.mode = MTD_OPS_RAW;
 			ops.ooblen = YAFFS_BYTES_PER_SPARE;
 		}
 		ops.len = data ? dev->data_bytes_per_chunk : ops.ooblen;
 		ops.datbuf = data;
 		ops.ooboffs = 0;
 		ops.oobbuf = spareAsBytes;
-		retval = mtd->read_oob(mtd, addr, &ops);
+		retval = mtd_read_oob(mtd, addr, &ops);
 		if (dev->param.use_nand_ecc)
 			translate_oob2spare(spare, spareAsBytes);
 	}
@@ -151,7 +151,7 @@
 	/* Todo finish off the ei if required */
 
 
-	retval = mtd->erase(mtd, &ei);
+	retval = mtd_erase(mtd, &ei);
 
 	if (retval == 0)
 		return YAFFS_OK;
diff --git a/fs/yaffs2/yaffs_mtdif2.c b/fs/yaffs2/yaffs_mtdif2.c
index 8135bcc..234cb70 100644
--- a/fs/yaffs2/yaffs_mtdif2.c
+++ b/fs/yaffs2/yaffs_mtdif2.c
@@ -77,13 +77,13 @@
 		yaffs_pack_tags2(&pt, tags, !dev->param.no_tags_ecc);
 	}
 
-	ops.mode = MTD_OOB_AUTO;
+	ops.mode = MTD_OPS_AUTO_OOB;
 	ops.ooblen = (dev->param.inband_tags) ? 0 : packed_tags_size;
 	ops.len = dev->param.total_bytes_per_chunk;
 	ops.ooboffs = 0;
 	ops.datbuf = (u8 *) data;
 	ops.oobbuf = (dev->param.inband_tags) ? NULL : packed_tags_ptr;
-	retval = mtd->write_oob(mtd, addr, &ops);
+	retval = mtd_write_oob(mtd, addr, &ops);
 
 	if (retval == 0)
 		return YAFFS_OK;
@@ -121,16 +121,16 @@
 	}
 
 	if (dev->param.inband_tags || (data && !tags))
-		retval = mtd->read(mtd, addr, dev->param.total_bytes_per_chunk,
+		retval = mtd_read(mtd, addr, dev->param.total_bytes_per_chunk,
 				   &dummy, data);
 	else if (tags) {
-		ops.mode = MTD_OOB_AUTO;
+		ops.mode = MTD_OPS_AUTO_OOB;
 		ops.ooblen = packed_tags_size;
 		ops.len = data ? dev->data_bytes_per_chunk : packed_tags_size;
 		ops.ooboffs = 0;
 		ops.datbuf = data;
 		ops.oobbuf = local_spare;
-		retval = mtd->read_oob(mtd, addr, &ops);
+		retval = mtd_read_oob(mtd, addr, &ops);
 	}
 
 	if (dev->param.inband_tags) {
@@ -179,7 +179,7 @@
 		"nandmtd2_MarkNANDBlockBad %d", blockNo);
 
 	retval =
-	    mtd->block_markbad(mtd,
+	    mtd_block_markbad(mtd,
 			       blockNo * dev->param.chunks_per_block *
 			       dev->data_bytes_per_chunk);
 
@@ -198,7 +198,7 @@
 
 	yaffs_trace(YAFFS_TRACE_MTD, "nandmtd2_QueryNANDBlock %d", blockNo);
 	retval =
-	    mtd->block_isbad(mtd,
+	    mtd_block_isbad(mtd,
 			     blockNo * dev->param.chunks_per_block *
 			     dev->data_bytes_per_chunk);
 
diff --git a/include/altera.h b/include/altera.h
index 7a2bece..6aad5ee 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -27,23 +27,6 @@
 #ifndef _ALTERA_H_
 #define _ALTERA_H_
 
-/* Altera Model definitions
- *********************************************************************/
-#define CONFIG_SYS_ACEX1K		CONFIG_SYS_FPGA_DEV( 0x1 )
-#define CONFIG_SYS_CYCLON2		CONFIG_SYS_FPGA_DEV( 0x2 )
-#define CONFIG_SYS_STRATIX_II		CONFIG_SYS_FPGA_DEV( 0x4 )
-
-#define CONFIG_SYS_ALTERA_ACEX1K	(CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_ACEX1K)
-#define CONFIG_SYS_ALTERA_CYCLON2	(CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_CYCLON2)
-#define CONFIG_SYS_ALTERA_STRATIX_II	(CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_STRATIX_II)
-/* Add new models here */
-
-/* Altera Interface definitions
- *********************************************************************/
-#define CONFIG_SYS_ALTERA_IF_PS	CONFIG_SYS_FPGA_IF( 0x1 )	/* passive serial */
-#define CONFIG_SYS_ALTERA_IF_FPP	CONFIG_SYS_FPGA_IF( 0x2 )	/* fast passive parallel */
-/* Add new interfaces here */
-
 typedef enum {				/* typedef Altera_iface */
 	min_altera_iface_type,		/* insert all new types after this */
 	passive_serial,			/* serial data and external clock */
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index a9aa8ba..a4bfdac 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -61,14 +61,6 @@
 #if defined(CONFIG_MPC83xx)
 	unsigned long	bi_immrbar;
 #endif
-#if defined(CONFIG_MPC8220)
-	unsigned long	bi_mbar_base;	/* base of internal registers */
-	unsigned long   bi_inpfreq;     /* Input Freq, In MHz */
-	unsigned long   bi_pcifreq;     /* PCI Freq, in MHz */
-	unsigned long   bi_pevfreq;     /* PEV Freq, in MHz */
-	unsigned long   bi_flbfreq;     /* Flexbus Freq, in MHz */
-	unsigned long   bi_vcofreq;     /* VCO Freq, in MHz */
-#endif
 	unsigned long	bi_bootflags;	/* boot / reboot flag (Unused) */
 	unsigned long	bi_ip_addr;	/* IP Address */
 	unsigned char	bi_enetaddr[6];	/* OLD: see README.enetaddr */
diff --git a/include/atmel_mci.h b/include/atmel_mci.h
index c711881..31c4569 100644
--- a/include/atmel_mci.h
+++ b/include/atmel_mci.h
@@ -52,6 +52,8 @@
 	u32	ier;	/* 0x44 */
 	u32	idr;	/* 0x48 */
 	u32	imr;	/* 0x4c */
+	u32	reserved[43];
+	u32	version;
 } atmel_mci_t;
 
 #endif /* __ASSEMBLY__ */
diff --git a/include/bootstage.h b/include/bootstage.h
index 3b2216b..ef07a87 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -37,6 +37,24 @@
 	BOOTSTAGEF_ALLOC	= 1 << 1,	/* Allocate an id */
 };
 
+/* bootstate sub-IDs used for kernel and ramdisk ranges */
+enum {
+	BOOTSTAGE_SUB_FORMAT,
+	BOOTSTAGE_SUB_FORMAT_OK,
+	BOOTSTAGE_SUB_NO_UNIT_NAME,
+	BOOTSTAGE_SUB_UNIT_NAME,
+	BOOTSTAGE_SUB_SUBNODE,
+
+	BOOTSTAGE_SUB_CHECK,
+	BOOTSTAGE_SUB_HASH = 5,
+	BOOTSTAGE_SUB_CHECK_ARCH = 5,
+	BOOTSTAGE_SUB_CHECK_ALL,
+	BOOTSTAGE_SUB_GET_DATA,
+	BOOTSTAGE_SUB_CHECK_ALL_OK = 7,
+	BOOTSTAGE_SUB_GET_DATA_OK,
+	BOOTSTAGE_SUB_LOAD,
+};
+
 /*
  * A list of boot stages that we know about. Each of these indicates the
  * state that we are at, and the action that we are about to perform. For
@@ -137,43 +155,24 @@
 	BOOTSTAGE_ID_NET_DONE_ERR,
 	BOOTSTAGE_ID_NET_DONE,
 
+	BOOTSTAGE_ID_FIT_FDT_START = 90,
 	/*
 	 * Boot stages related to loading a FIT image. Some of these are a
 	 * bit wonky.
 	 */
-	BOOTSTAGE_ID_FIT_FORMAT = 100,
-	BOOTSTAGE_ID_FIT_NO_UNIT_NAME,
-	BOOTSTAGE_ID_FIT_UNIT_NAME,
-	BOOTSTAGE_ID_FIT_CONFIG,
-	BOOTSTAGE_ID_FIT_CHECK_SUBIMAGE,
-	BOOTSTAGE_ID_FIT_CHECK_HASH = 104,
+	BOOTSTAGE_ID_FIT_KERNEL_START = 100,
 
-	BOOTSTAGE_ID_FIT_CHECK_ARCH,
-	BOOTSTAGE_ID_FIT_CHECK_KERNEL,
-	BOOTSTAGE_ID_FIT_CHECKED,
-
-	BOOTSTAGE_ID_FIT_KERNEL_INFO_ERR = 107,
-	BOOTSTAGE_ID_FIT_KERNEL_INFO,
+	BOOTSTAGE_ID_FIT_CONFIG = 110,
 	BOOTSTAGE_ID_FIT_TYPE,
+	BOOTSTAGE_ID_FIT_KERNEL_INFO,
 
 	BOOTSTAGE_ID_FIT_COMPRESSION,
 	BOOTSTAGE_ID_FIT_OS,
 	BOOTSTAGE_ID_FIT_LOADADDR,
 	BOOTSTAGE_ID_OVERWRITTEN,
 
-	BOOTSTAGE_ID_FIT_RD_FORMAT = 120,
-	BOOTSTAGE_ID_FIT_RD_FORMAT_OK,
-	BOOTSTAGE_ID_FIT_RD_NO_UNIT_NAME,
-	BOOTSTAGE_ID_FIT_RD_UNIT_NAME,
-	BOOTSTAGE_ID_FIT_RD_SUBNODE,
-
-	BOOTSTAGE_ID_FIT_RD_CHECK,
-	BOOTSTAGE_ID_FIT_RD_HASH = 125,
-	BOOTSTAGE_ID_FIT_RD_CHECK_ALL,
-	BOOTSTAGE_ID_FIT_RD_GET_DATA,
-	BOOTSTAGE_ID_FIT_RD_CHECK_ALL_OK = 127,
-	BOOTSTAGE_ID_FIT_RD_GET_DATA_OK,
-	BOOTSTAGE_ID_FIT_RD_LOAD,
+	/* Next 10 IDs used by BOOTSTAGE_SUB_... */
+	BOOTSTAGE_ID_FIT_RD_START = 120,	/* Ramdisk stages */
 
 	BOOTSTAGE_ID_IDE_FIT_READ = 140,
 	BOOTSTAGE_ID_IDE_FIT_READ_OK,
@@ -221,7 +220,7 @@
  */
 ulong timer_get_boot_us(void);
 
-#ifndef CONFIG_SPL_BUILD
+#if !defined(CONFIG_SPL_BUILD) && !defined(USE_HOSTCC)
 /*
  * Board code can implement show_boot_progress() if needed.
  *
@@ -233,10 +232,21 @@
 #define show_boot_progress(val) do {} while (0)
 #endif
 
-#if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD) && \
+	!defined(USE_HOSTCC)
 /* This is the full bootstage implementation */
 
 /**
+ * Relocate existing bootstage records
+ *
+ * Call this after relocation has happened and after malloc has been initted.
+ * We need to copy any pointers in bootstage records that were added pre-
+ * relocation, since memory can be overritten later.
+ * @return Always returns 0, to indicate success
+ */
+int bootstage_relocate(void);
+
+/**
  * Add a new bootstage record
  *
  * @param id	Bootstage ID to use (ignored if flags & BOOTSTAGEF_ALLOC)
@@ -257,6 +267,19 @@
 ulong bootstage_mark_name(enum bootstage_id id, const char *name);
 
 /**
+ * Mark a time stamp in the given function and line number
+ *
+ * See BOOTSTAGE_MARKER() for a convenient macro.
+ *
+ * @param file		Filename to record (NULL if none)
+ * @param func		Function name to record
+ * @param linenum	Line number to record
+ * @return recorded time stamp
+ */
+ulong bootstage_mark_code(const char *file, const char *func,
+			  int linenum);
+
+/**
  * Mark the start of a bootstage activity. The end will be marked later with
  * bootstage_accum() and at that point we accumulate the time taken. Calling
  * this function turns the given id into a accumulator rather than and
@@ -315,11 +338,22 @@
 int bootstage_unstash(void *base, int size);
 
 #else
+static inline ulong bootstage_add_record(enum bootstage_id id,
+		const char *name, int flags, ulong mark)
+{
+	return 0;
+}
+
 /*
  * This is a dummy implementation which just calls show_boot_progress(),
  * and won't even do that unless CONFIG_SHOW_BOOT_PROGRESS is defined
  */
 
+static inline int bootstage_relocate(void)
+{
+	return 0;
+}
+
 static inline ulong bootstage_mark(enum bootstage_id id)
 {
 	show_boot_progress(id);
@@ -337,6 +371,22 @@
 	return 0;
 }
 
+static inline ulong bootstage_mark_code(const char *file, const char *func,
+					int linenum)
+{
+	return 0;
+}
+
+static inline uint32_t bootstage_start(enum bootstage_id id, const char *name)
+{
+	return 0;
+}
+
+static inline uint32_t bootstage_accum(enum bootstage_id id)
+{
+	return 0;
+}
+
 static inline int bootstage_stash(void *base, int size)
 {
 	return 0;	/* Pretend to succeed */
@@ -348,4 +398,8 @@
 }
 #endif /* CONFIG_BOOTSTAGE */
 
+/* Helper macro for adding a bootstage to a line of code */
+#define BOOTSTAGE_MARKER()	\
+		bootstage_mark_code(__FILE__, __func__, __LINE__)
+
 #endif
diff --git a/include/common.h b/include/common.h
index 8a1f3e4..126891d 100644
--- a/include/common.h
+++ b/include/common.h
@@ -71,8 +71,6 @@
 #include <mpc5xxx.h>
 #elif defined(CONFIG_MPC512X)
 #include <asm/immap_512x.h>
-#elif defined(CONFIG_MPC8220)
-#include <asm/immap_8220.h>
 #elif defined(CONFIG_8260)
 #if   defined(CONFIG_MPC8247) \
    || defined(CONFIG_MPC8248) \
@@ -199,18 +197,35 @@
  * General Purpose Utilities
  */
 #define min(X, Y)				\
-	({ typeof (X) __x = (X);		\
-		typeof (Y) __y = (Y);		\
+	({ typeof(X) __x = (X);			\
+		typeof(Y) __y = (Y);		\
 		(__x < __y) ? __x : __y; })
 
 #define max(X, Y)				\
-	({ typeof (X) __x = (X);		\
-		typeof (Y) __y = (Y);		\
+	({ typeof(X) __x = (X);			\
+		typeof(Y) __y = (Y);		\
 		(__x > __y) ? __x : __y; })
 
 #define MIN(x, y)  min(x, y)
 #define MAX(x, y)  max(x, y)
 
+#define min3(X, Y, Z)				\
+	({ typeof(X) __x = (X);			\
+		typeof(Y) __y = (Y);		\
+		typeof(Z) __z = (Z);		\
+		__x < __y ? (__x < __z ? __x : __z) :	\
+		(__y < __z ? __y : __z); })
+
+#define max3(X, Y, Z)				\
+	({ typeof(X) __x = (X);			\
+		typeof(Y) __y = (Y);		\
+		typeof(Z) __z = (Z);		\
+		__x > __y ? (__x > __z ? __x : __z) :	\
+		(__y > __z ? __y : __z); })
+
+#define MIN3(x, y, z)  min3(x, y, z)
+#define MAX3(x, y, z)  max3(x, y, z)
+
 /*
  * Return the absolute value of a number.
  *
@@ -295,9 +310,6 @@
 int	parse_line (char *, char *[]);
 void	init_cmd_timeout(void);
 void	reset_cmd_timeout(void);
-#ifdef CONFIG_MENU
-int	abortboot(int bootdelay);
-#endif
 extern char console_buffer[];
 
 /* arch/$(ARCH)/lib/board.c */
@@ -323,6 +335,16 @@
  */
 void board_show_dram(ulong size);
 
+/**
+ * arch_fixup_memory_node() - Write arch-specific memory information to fdt
+ *
+ * Defined in arch/$(ARCH)/lib/bootm.c
+ *
+ * @blob:	FDT blob to write to
+ * @return 0 if ok, or -ve FDT_ERR_... on failure
+ */
+int arch_fixup_memory_node(void *blob);
+
 /* common/flash.c */
 void flash_perror (int);
 
@@ -556,7 +578,6 @@
     defined (CONFIG_74x)	|| \
     defined (CONFIG_75x)	|| \
     defined (CONFIG_74xx)	|| \
-    defined (CONFIG_MPC8220)	|| \
     defined (CONFIG_MPC85xx)	|| \
     defined (CONFIG_MPC86xx)	|| \
     defined (CONFIG_MPC83xx)
@@ -648,9 +669,6 @@
 #elif defined(CONFIG_MPC5xxx)
 int	prt_mpc5xxx_clks (void);
 #endif
-#if defined(CONFIG_MPC8220)
-int	prt_mpc8220_clks (void);
-#endif
 #ifdef CONFIG_4xx
 ulong	get_OPB_freq (void);
 ulong	get_PCI_freq (void);
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index 53a2f05..d847069 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -40,6 +40,7 @@
 #define CONFIG_CMD_FDOS		/* Floppy DOS support		*/
 #define CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/
 #define CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#define CONFIG_CMD_FUSE		/* Device fuse support		*/
 #define CONFIG_CMD_GETTIME	/* Get time since boot         */
 #define CONFIG_CMD_HASH		/* calculate hash / digest	*/
 #define CONFIG_CMD_HWFLOW	/* RTS/CTS hw flow control	*/
diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h
deleted file mode 100644
index 39c29ec..0000000
--- a/include/configs/Alaska8220.h
+++ /dev/null
@@ -1,334 +0,0 @@
-/*
- * (C) Copyright 2004
- * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC8220		1
-#define CONFIG_ALASKA8220	1	/* ... on Alaska board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
-   determine the CPU speed. */
-#define CONFIG_SYS_MPC8220_CLKIN	30000000/* ... running at 30MHz */
-#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
-
-/*
- * Serial console configuration
- */
-
-/* Define this for PSC console
-#define CONFIG_PSC_CONSOLE	1
-*/
-
-#define CONFIG_EXTUART_CONSOLE	1
-
-#ifdef CONFIG_EXTUART_CONSOLE
-#   define CONFIG_CONS_INDEX	1
-#   define CONFIG_SYS_NS16550_SERIAL
-#   define CONFIG_SYS_NS16550
-#   define CONFIG_SYS_NS16550_REG_SIZE 1
-#   define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CPLD_BASE + 0x1008)
-#   define CONFIG_SYS_NS16550_CLK	18432000
-#endif
-
-#define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_TIMESTAMP			/* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_MII
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	5    /* autoboot after 5 seconds */
-#define CONFIG_BOOTARGS		"root=/dev/ram rw"
-#define CONFIG_ETHADDR		00:e0:0c:bc:e0:60
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		00:e0:0c:bc:e0:61
-#define CONFIG_IPADDR		192.162.1.2
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_SERVERIP		192.162.1.1
-#define CONFIG_GATEWAYIP	192.162.1.1
-#define CONFIG_HOSTNAME		Alaska
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_MODULE		1
-
-#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52	/* 1011000xb */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
-/*
-#define CONFIG_ENV_IS_IN_EEPROM	1
-#define CONFIG_ENV_OFFSET		0
-#define CONFIG_ENV_SIZE		256
-*/
-
-/* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
-   else undefined it will boot from Intel Strata flash */
-#define CONFIG_SYS_AMD_BOOT		1
-
-/*
- * Flexbus Chipselect configuration
- */
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_SYS_CS0_BASE		0xfff0
-#define CONFIG_SYS_CS0_MASK		0x00080000  /* 512 KB */
-#define CONFIG_SYS_CS0_CTRL		0x003f0d40
-
-#define CONFIG_SYS_CS1_BASE		0xfe00
-#define CONFIG_SYS_CS1_MASK		0x01000000  /* 16 MB */
-#define CONFIG_SYS_CS1_CTRL		0x003f1540
-#else
-#define CONFIG_SYS_CS0_BASE		0xff00
-#define CONFIG_SYS_CS0_MASK		0x01000000  /* 16 MB */
-#define CONFIG_SYS_CS0_CTRL		0x003f1540
-
-#define CONFIG_SYS_CS1_BASE		0xfe08
-#define CONFIG_SYS_CS1_MASK		0x00080000  /* 512 KB */
-#define CONFIG_SYS_CS1_CTRL		0x003f0d40
-#endif
-
-#define CONFIG_SYS_CS2_BASE		0xf100
-#define CONFIG_SYS_CS2_MASK		0x00040000
-#define CONFIG_SYS_CS2_CTRL		0x003f1140
-
-#define CONFIG_SYS_CS3_BASE		0xf200
-#define CONFIG_SYS_CS3_MASK		0x00040000
-#define CONFIG_SYS_CS3_CTRL		0x003f1100
-
-
-#define CONFIG_SYS_FLASH0_BASE		(CONFIG_SYS_CS0_BASE << 16)
-#define CONFIG_SYS_FLASH1_BASE		(CONFIG_SYS_CS1_BASE << 16)
-
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_SYS_AMD_BASE		CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_INTEL_BASE		CONFIG_SYS_FLASH1_BASE + 0xf00000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_AMD_BASE
-#else
-#define CONFIG_SYS_INTEL_BASE		CONFIG_SYS_FLASH0_BASE + 0xf00000
-#define CONFIG_SYS_AMD_BASE		CONFIG_SYS_FLASH1_BASE
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_INTEL_BASE
-#endif
-
-#define CONFIG_SYS_CPLD_BASE		(CONFIG_SYS_CS2_BASE << 16)
-#define CONFIG_SYS_FPGA_BASE		(CONFIG_SYS_CS3_BASE << 16)
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	4	/* max num of memory banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
-
-#define PHYS_AMD_SECT_SIZE	0x00010000 /*  64 KB sectors (x2) */
-#define PHYS_INTEL_SECT_SIZE	0x00020000 /* 128 KB sectors (x2) */
-
-#define CONFIG_SYS_FLASH_CHECKSUM
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
-#define CONFIG_ENV_SIZE		PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE	PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_ADDR		(CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
-#define CONFIG_ENV1_SIZE		PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_SECT_SIZE	PHYS_INTEL_SECT_SIZE
-#else
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
-#define CONFIG_ENV_SIZE		PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE	PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_ADDR		(CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
-#define CONFIG_ENV1_SIZE		PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_SECT_SIZE	PHYS_AMD_SECT_SIZE
-#endif
-
-#define CONFIG_ENV_OVERWRITE	1
-
-#if defined CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-#define CONFIG_SYS_SRAM_BASE		(CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_SRAM_SIZE		0x8000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
-
-/* SDRAM configuration */
-#define CONFIG_SYS_SDRAM_TOTAL_BANKS		2
-#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
-#define CONFIG_SYS_SDRAM_SPD_SIZE		0x40
-#define CONFIG_SYS_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */
-
-/* SDRAM drive strength register */
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
-					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
-					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
-					 (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
-					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBD_SHIFT))
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC8220_FEC	1
-#define CONFIG_FEC_10MBIT	1 /* Workaround for FEC 100Mbit problem */
-#define CONFIG_PHY_ADDR		0x18
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			    /* undef to save memory	*/
-#define CONFIG_SYS_PROMPT		"=> "	    /* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	    /* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE		256	    /* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	    /* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000  /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000    /* default load address */
-
-#define CONFIG_SYS_HZ			1000	    /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5   /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-/*
- * JFFS2 partitions
- */
-
-/* No command line, one static partition */
-/*
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0x00400000
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-*/
-
-/* mtdparts command line support */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor0=alaska-0"
-#define MTDPARTS_DEFAULT	"mtdparts=alaska-0:4m(user)"
-*/
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index b09119a..1c9d08e 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -36,7 +36,6 @@
 
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
-#define CONFIG_E6500
 #define CONFIG_E500			/* BOOKE e500 family */
 #define CONFIG_E500MC			/* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
@@ -528,6 +527,15 @@
 #define CONFIG_SF_DEFAULT_MODE          0
 
 /*
+ * MAPLE
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
+#else
+#define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
+#endif
+
+/*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
@@ -623,7 +631,11 @@
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x10
 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR	0x11
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	4
+
+/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7	 /*SLOT 1*/
+#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6	 /*SLOT 2*/
+
 
 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 1bc2c5a..536b755 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -238,7 +238,7 @@
 
 /* FPGA - Spartan 2 */
 /* experiment
-#define CONFIG_FPGA		CONFIG_SYS_SPARTAN3
+#define CONFIG_FPGA
 #define CONFIG_FPGA_COUNT	1
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_CHECK_CTRLC
diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h
index c296e3c..30fb6c2 100644
--- a/include/configs/MERGERBOX.h
+++ b/include/configs/MERGERBOX.h
@@ -606,7 +606,7 @@
  * FPGA
  */
 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA		CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 
diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h
index 6850965..7271468 100644
--- a/include/configs/MVBC_P.h
+++ b/include/configs/MVBC_P.h
@@ -310,7 +310,7 @@
 
 #undef FPGA_DEBUG
 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA		CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA	1
 #define CONFIG_FPGA_CYCLON2	1
 #define CONFIG_FPGA_COUNT	1
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index a99ad3c..a9c00ac 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -499,7 +499,7 @@
 	""
 
 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA		CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 
diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h
index bf2f44e..5d2ff14 100644
--- a/include/configs/MVSMR.h
+++ b/include/configs/MVSMR.h
@@ -280,7 +280,7 @@
 
 #undef FPGA_DEBUG
 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA		CONFIG_SYS_XILINX_SPARTAN2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_XILINX	1
 #define CONFIG_FPGA_SPARTAN2	1
 #define CONFIG_FPGA_COUNT	1
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 8b13b10..69412e4 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -316,7 +316,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 
 /* Video */
-#define CONFIG_FSL_DIU_FB
 
 #ifdef CONFIG_FSL_DIU_FB
 #define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)
@@ -336,7 +335,6 @@
 #endif
 
 #ifndef CONFIG_FSL_DIU_FB
-#define CONFIG_ATI
 #endif
 
 #ifdef CONFIG_ATI
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 76b3ca6..6dd5c0d 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -25,7 +25,6 @@
  */
 #define CONFIG_T4240QDS
 #define CONFIG_PHYS_64BIT
-#define CONFIG_PPC_T4240
 
 #define CONFIG_FSL_SATA_V2
 #define CONFIG_PCIE4
diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h
deleted file mode 100644
index 5f925b3..0000000
--- a/include/configs/Yukon8220.h
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * (C) Copyright 2004
- * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC8220		1
-#define CONFIG_YUKON8220	1	/* ... on Yukon board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
-   determine the CPU speed. */
-#define CONFIG_SYS_MPC8220_CLKIN	30000000/* ... running at 30MHz */
-#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
-
-/*
- * Serial console configuration
- */
-
-/* Define this for PSC console
-#define CONFIG_PSC_CONSOLE	1
-*/
-
-#define CONFIG_EXTUART_CONSOLE	1
-
-#ifdef CONFIG_EXTUART_CONSOLE
-#   define CONFIG_CONS_INDEX	1
-#   define CONFIG_SYS_NS16550_SERIAL
-#   define CONFIG_SYS_NS16550
-#   define CONFIG_SYS_NS16550_REG_SIZE 1
-#   define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CPLD_BASE + 0x1008)
-#   define CONFIG_SYS_NS16550_CLK	18432000
-#endif
-
-#define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_TIMESTAMP			/* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_MII
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	5    /* autoboot after 5 seconds */
-#define CONFIG_BOOTARGS		"root=/dev/ram rw"
-#define CONFIG_ETHADDR		00:e0:0c:bc:e0:60
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		00:e0:0c:bc:e0:61
-#define CONFIG_IPADDR		192.162.1.2
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_SERVERIP		192.162.1.1
-#define CONFIG_GATEWAYIP	192.162.1.1
-#define CONFIG_HOSTNAME		yukon
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_MODULE		1
-
-#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52	/* 1011000xb */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
-/*
-#define CONFIG_ENV_IS_IN_EEPROM	1
-#define CONFIG_ENV_OFFSET		0
-#define CONFIG_ENV_SIZE		256
-*/
-
-/* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
-   else undefined it will boot from Intel Strata flash */
-#define CONFIG_SYS_AMD_BOOT		1
-
-/*
- * Flexbus Chipselect configuration
- */
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_SYS_CS0_BASE		0xfff0
-#define CONFIG_SYS_CS0_MASK		0x00080000  /* 512 KB */
-#define CONFIG_SYS_CS0_CTRL		0x003f0d40
-
-#define CONFIG_SYS_CS1_BASE		0xfe00
-#define CONFIG_SYS_CS1_MASK		0x01000000  /* 16 MB */
-#define CONFIG_SYS_CS1_CTRL		0x003f1540
-#else
-#define CONFIG_SYS_CS0_BASE		0xff00
-#define CONFIG_SYS_CS0_MASK		0x01000000  /* 16 MB */
-#define CONFIG_SYS_CS0_CTRL		0x003f1540
-
-#define CONFIG_SYS_CS1_BASE		0xfe08
-#define CONFIG_SYS_CS1_MASK		0x00080000  /* 512 KB */
-#define CONFIG_SYS_CS1_CTRL		0x003f0d40
-#endif
-
-#define CONFIG_SYS_CS2_BASE		0xf100
-#define CONFIG_SYS_CS2_MASK		0x00040000
-#define CONFIG_SYS_CS2_CTRL		0x003f1140
-
-#define CONFIG_SYS_CS3_BASE		0xf200
-#define CONFIG_SYS_CS3_MASK		0x00040000
-#define CONFIG_SYS_CS3_CTRL		0x003f1100
-
-
-#define CONFIG_SYS_FLASH0_BASE		(CONFIG_SYS_CS0_BASE << 16)
-#define CONFIG_SYS_FLASH1_BASE		(CONFIG_SYS_CS1_BASE << 16)
-
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_SYS_AMD_BASE		CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_INTEL_BASE		CONFIG_SYS_FLASH1_BASE + 0xf00000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_AMD_BASE
-#else
-#define CONFIG_SYS_INTEL_BASE		CONFIG_SYS_FLASH0_BASE + 0xf00000
-#define CONFIG_SYS_AMD_BASE		CONFIG_SYS_FLASH1_BASE
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_INTEL_BASE
-#endif
-
-#define CONFIG_SYS_CPLD_BASE		(CONFIG_SYS_CS2_BASE << 16)
-#define CONFIG_SYS_FPGA_BASE		(CONFIG_SYS_CS3_BASE << 16)
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	4	/* max num of memory banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
-
-#define PHYS_AMD_SECT_SIZE	0x00010000 /*  64 KB sectors (x2) */
-#define PHYS_INTEL_SECT_SIZE	0x00020000 /* 128 KB sectors (x2) */
-
-#define CONFIG_SYS_FLASH_CHECKSUM
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
-#define CONFIG_ENV_SIZE		PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE	PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_ADDR		(CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
-#define CONFIG_ENV1_SIZE		PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_SECT_SIZE	PHYS_INTEL_SECT_SIZE
-#else
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
-#define CONFIG_ENV_SIZE		PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE	PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_ADDR		(CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
-#define CONFIG_ENV1_SIZE		PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_SECT_SIZE	PHYS_AMD_SECT_SIZE
-#endif
-
-#define CONFIG_ENV_OVERWRITE	1
-
-#if defined CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#ifndef CONFIG_SYS_JFFS2_FIRST_SECTOR
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR	0
-#endif
-#ifndef CONFIG_SYS_JFFS2_FIRST_BANK
-#define CONFIG_SYS_JFFS2_FIRST_BANK	0
-#endif
-#ifndef CONFIG_SYS_JFFS2_NUM_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS	1
-#endif
-#define CONFIG_SYS_JFFS2_LAST_BANK (CONFIG_SYS_JFFS2_FIRST_BANK + CONFIG_SYS_JFFS2_NUM_BANKS - 1)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-#define CONFIG_SYS_SRAM_BASE		(CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_SRAM_SIZE		0x8000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
-
-/* SDRAM configuration */
-#define CONFIG_SYS_SDRAM_TOTAL_BANKS		2
-#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
-#define CONFIG_SYS_SDRAM_SPD_SIZE		0x40
-#define CONFIG_SYS_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */
-
-/* SDRAM drive strength register */
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
-					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
-					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
-					 (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
-					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBD_SHIFT))
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC8220_FEC	1
-#define CONFIG_FEC_10MBIT	1 /* Workaround for FEC 100Mbit problem */
-#define CONFIG_PHY_ADDR		0x18
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			    /* undef to save memory	*/
-#define CONFIG_SYS_PROMPT		"=> "	    /* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	    /* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE		256	    /* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	    /* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000  /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000    /* default load address */
-
-#define CONFIG_SYS_HZ			1000	    /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5   /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index ac7e877..7cb10fb 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -368,6 +368,11 @@
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_FSL_IIM
+
+/*
  * EEPROM configuration for Atmel AT24C01:
  * 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode
  */
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index ef00306..cd2c078 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -17,6 +17,7 @@
 #define __CONFIG_AM335X_EVM_H
 
 #define CONFIG_AM33XX
+#define CONFIG_OMAP
 
 #include <asm/arch/omap.h>
 
@@ -196,7 +197,6 @@
 					+ (8 * 1024 * 1024))
 
 #define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
-#define CONFIG_SYS_HZ			1000 /* 1ms clock */
 
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
@@ -260,12 +260,11 @@
  /* Platform/Board specific defs */
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_HZ			1000	/* 1ms clock */
 
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SERIAL_MULTI
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
 #define CONFIG_SYS_NS16550_CLK		(48000000)
 #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
@@ -295,6 +294,9 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 110, 300, 600, 1200, 2400, \
 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
 
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
 #define CONFIG_ENV_OVERWRITE		1
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 
@@ -303,8 +305,13 @@
 /* Defines for SPL */
 #define CONFIG_SPL
 #define CONFIG_SPL_FRAMEWORK
+/*
+ * Place the image at the start of the ROM defined image space.
+ * We limit our size to the ROM-defined downloaded image area, and use the
+ * rest of the space for stack.
+ */
 #define CONFIG_SPL_TEXT_BASE		0x402F0400
-#define CONFIG_SPL_MAX_SIZE		(101 * 1024)
+#define CONFIG_SPL_MAX_SIZE		(0x4030C000 - CONFIG_SPL_TEXT_BASE)
 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
 
 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
@@ -360,11 +367,7 @@
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	14
 
-#define CONFIG_SYS_NAND_ECCSTEPS	4
-#define	CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * \
-						CONFIG_SYS_NAND_ECCSTEPS)
-
-#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 
diff --git a/include/configs/aria.h b/include/configs/aria.h
index b425399..5318aaf 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -383,7 +383,7 @@
 /*
  * IIM - IC Identification Module
  */
-#undef CONFIG_IIM
+#undef CONFIG_FSL_IIM
 
 /*
  * EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index ebcc69a..4328944 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -105,6 +105,8 @@
 #define CONFIG_CMD_PING		1
 #define CONFIG_CMD_DHCP		1
 #define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
 #define CONFIG_CMD_USB		1
 
 /*
@@ -128,6 +130,24 @@
 	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
 #endif
 
+/*
+ * The (arm)linux board id set by generic code depending on configured board
+ * (see boards.cfg for different boards)
+ */
+#ifdef CONFIG_AT91SAM9G20
+	/* the sam9g20 variants have two different board ids */
+# ifdef CONFIG_AT91SAM9G20EK_2MMC
+	/* we may be setup for the 2MMC variant of at91sam9g20ek */
+#  define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK_2MMC
+# else
+	/* or the normal at91sam9g20ek */
+#  define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK
+# endif
+#else
+	/* otherwise default to good old at91sam9260ek */
+# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9260EK
+#endif
+
 /* DataFlash */
 #ifndef CONFIG_AT91SAM9G20EK_2MMC
 #define CONFIG_ATMEL_DATAFLASH_SPI
@@ -158,6 +178,18 @@
 #define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
 #endif
 
+/* MMC */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+/* FAT */
+#ifdef CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
 /* NOR flash - no real flash on this board */
 #define CONFIG_SYS_NO_FLASH			1
 
@@ -170,13 +202,11 @@
 /* USB */
 #define CONFIG_USB_ATMEL
 #define CONFIG_USB_OHCI_NEW		1
-#define CONFIG_DOS_PARTITION		1
 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
 #define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9260_UHP_BASE */
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE		1
-#define CONFIG_CMD_FAT			1
 
 #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
 
@@ -211,7 +241,7 @@
 				"mtdparts=atmel_nand:-(root) "		\
 				"rw rootfstype=jffs2"
 
-#else /* CONFIG_SYS_USE_NANDFLASH */
+#elif defined(CONFIG_SYS_USE_NANDFLASH)
 
 /* bootstrap + u-boot + env + linux in nandflash */
 #define CONFIG_ENV_IS_IN_NAND	1
@@ -226,6 +256,22 @@
 	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
 	"root=/dev/mtdblock7 rw rootfstype=jffs2"
 
+#else	/* CONFIG_SYS_USE_MMC */
+/* bootstrap + u-boot + env + linux in mmc */
+#define CONFIG_ENV_IS_IN_MMC
+/* For FAT system, most cases it should be in the reserved sector */
+#define CONFIG_ENV_OFFSET		0x2000
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_BOOTCOMMAND						\
+	"fatload mmc 0:1 0x22000000 uImage; bootm"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"
 #endif
 
 #define CONFIG_SYS_PROMPT		"U-Boot> "
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
new file mode 100644
index 0000000..8d2673d
--- /dev/null
+++ b/include/configs/at91sam9n12ek.h
@@ -0,0 +1,232 @@
+/*
+ * (C) Copyright 2013 Atmel Corporation.
+ * Josh Wu <josh.wu@atmel.com>
+ *
+ * Configuation settings for the AT91SAM9N12-EK boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __AT91SAM9N12_CONFIG_H_
+#define __AT91SAM9N12_CONFIG_H_
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x26f00000
+
+#define CONFIG_ARM926EJS
+#define CONFIG_AT91FAMILY
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	16000000	/* main clock xtal */
+#define CONFIG_SYS_HZ			1000
+
+/* Misc CPU related */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_OF_LIBFDT
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+/* LCD */
+#define CONFIG_LCD
+#define LCD_BPP				LCD_COLOR16
+#define LCD_OUTPUT_BPP			24
+#define CONFIG_LCD_LOGO
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_HLCD
+#define CONFIG_ATMEL_LCD_RGB565
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTDELAY		3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+# define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#define CONFIG_ENV_SPI_MODE		SPI_MODE_3
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+#endif
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 4
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTD, 5
+
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP		2
+#define CONFIG_PMECC_SECTOR_SIZE	512
+#define CONFIG_PMECC_INDEX_TABLE_OFFSET	0x8000
+#endif
+
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT			"nand0=atmel_nand"
+#define MTDPARTS_DEFAULT						\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS                                       \
+	"console=console=ttyS0,115200\0"                                \
+	"mtdparts="MTDPARTS_DEFAULT"\0"					\
+	"bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\
+	"bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
+
+/* MMC */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+/* FAT */
+#ifdef CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x26e00000
+
+#ifdef CONFIG_SYS_USE_SPIFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET		0x5000
+#define CONFIG_ENV_SIZE			0x3000
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_BOOTCOMMAND						\
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_nand};"	\
+	"sf probe 0; sf read 0x22000000 0x100000 0x300000; "		\
+	"bootm 0x22000000"
+
+#elif defined(CONFIG_SYS_USE_NANDFLASH)
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0xc0000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE			0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND						\
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_nand};"	\
+	"nand read 0x21000000 0x180000 0x080000;"			\
+	"nand read 0x22000000 0x200000 0x400000;"			\
+	"bootm 0x22000000 - 0x21000000"
+
+#else /* CONFIG_SYS_USE_MMC */
+
+/* bootstrap + u-boot + env + linux in mmc */
+#define CONFIG_ENV_IS_IN_MMC
+/* For FAT system, most cases it should be in the reserved sector */
+#define CONFIG_ENV_OFFSET		0x2000
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_BOOTCOMMAND						\
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_mmc};"	\
+	"fatload mmc 0:1 0x21000000 dtb;"				\
+	"fatload mmc 0:1 0x22000000 uImage;"				\
+	"bootm 0x22000000 - 0x21000000"
+
+#endif
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "
+#define CONFIG_SYS_CBSIZE	256
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) \
+					+ 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(4 * 1024 * 1024)
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#endif
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index 7b51b53..db1b613 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -149,10 +149,15 @@
 #define CONFIG_MUSB_TIMEOUT 100000
 #endif
 
+/* Don't waste time transferring a logo over the UART */
+#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
+/*# define CONFIG_VIDEO*/
+#endif
 
 /*
  * Video Settings
  */
+#ifdef CONFIG_VIDEO
 #ifdef CONFIG_BF527_EZKIT_REV_2_1
 # define CONFIG_LQ035Q1_SPI_BUS	0
 # define CONFIG_LQ035Q1_SPI_CS	7
@@ -166,7 +171,7 @@
 #else
 # define EASYLOGO_HEADER <asm/bfin_logo_230x230_lzma.h>
 #endif
-
+#endif /* CONFIG_VIDEO */
 
 /*
  * Misc Settings
@@ -175,11 +180,6 @@
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
 
-/* Don't waste time transferring a logo over the UART */
-#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
-# define CONFIG_VIDEO
-#endif
-
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 05029d4..25cebf8 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -52,7 +52,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
 #define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
 
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(384 * 1024)
 
 
@@ -135,15 +135,17 @@
 /*
  * SPI_MMC Settings
  */
+#define CONFIG_MMC_SPI
+#ifdef CONFIG_MMC_SPI
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_MMC_SPI
-
+#endif
 
 /*
  * NAND Settings
  */
 /* #define CONFIG_NAND_PLAT */
+#ifdef CONFIG_NAND_PLAT
 #define CONFIG_SYS_NAND_BASE		0x20212000
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 
@@ -158,7 +160,7 @@
 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF3
-
+#endif /* CONFIG_NAND_PLAT */
 
 /*
  * CF-CARD IDE-HDD Support
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index e6b05db..da5f029 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -120,18 +120,16 @@
 #define CONFIG_ENV_SECT_SIZE	0x8000
 #endif
 
-
 /*
  * NAND Settings
  */
-#define CONFIG_BFIN_NFC_CTL_VAL	0x0033
 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-# define CONFIG_BFIN_NFC_BOOTROM_ECC
-#endif
+#define CONFIG_BFIN_NFC_CTL_VAL        0x0033
+#define CONFIG_BFIN_NFC_BOOTROM_ECC
 #define CONFIG_DRIVER_NAND_BFIN
-#define CONFIG_SYS_NAND_BASE		0 /* not actually used */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
+#define CONFIG_SYS_NAND_BASE           0 /* not actually used */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#endif
 
 /*
  * I2C Settings
@@ -184,13 +182,12 @@
 #define CONFIG_UART_CONSOLE	1
 #define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
 
-#ifndef __ADSPBF542__
-/* Don't waste time transferring a logo over the UART */
-# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
-#  define CONFIG_VIDEO
-#  define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h>
-# endif
-# define CONFIG_DEB_DMA_URGENT
+#define CONFIG_ADI_GPIO2
+
+#undef CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h >
+#define CONFIG_DEB_DMA_URGENT
 #endif
 
 /* Define if want to do post memory test */
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 1a9d27e..6ee1e4c 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -98,6 +98,11 @@
  */
 #define CONFIG_UART_CONSOLE	0
 
+/*
+ * Run core 1 from L1 SRAM start address when init uboot on core 0
+ */
+/* #define CONFIG_CORE1_RUN	1 */
+
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index 02149fa..1a43e1b 100644
--- a/include/configs/bf609-ezkit.h
+++ b/include/configs/bf609-ezkit.h
@@ -144,10 +144,13 @@
 #define CONFIG_UART_CONSOLE	0
 
 #define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_SOFTSWITCH
 
 #define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4)
 #define CONFIG_BFIN_SOFT_SWITCH
 
+#define CONFIG_ADI_GPIO2
+
 #if 0
 #define CONFIG_UART_MEM 1024
 #undef CONFIG_UART_CONSOLE
@@ -155,6 +158,13 @@
 #undef CONFIG_UART_CONSOLE_IS_JTAG
 #endif
 
+#define CONFIG_BOARD_SIZE_LIMIT $$((512 * 1024))
+
+/*
+ * Run core 1 from L1 SRAM start address when init uboot on core 0
+ */
+/* #define CONFIG_CORE1_RUN	1 */
+
 /*
  * Pull in common ADI header for remaining command/environment setup
  */
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index d3ae3a7..e1a6fe3 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -111,8 +111,8 @@
 #ifndef CONFIG_BAUDRATE
 # define CONFIG_BAUDRATE	57600
 #endif
-#ifndef CONFIG_DEBUG_EARLY_SERIAL
-# define CONFIG_SYS_BFIN_UART
+#ifdef CONFIG_UART_CONSOLE
+# define CONFIG_BFIN_SERIAL
 #endif
 
 /*
@@ -317,5 +317,13 @@
 #define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */
 #define CONFIG_LZMA
 #define CONFIG_MONITOR_IS_IN_RAM
-
+#ifdef CONFIG_HW_WATCHDOG
+# define CONFIG_BFIN_WATCHDOG
+# ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
+#  define CONFIG_WATCHDOG_TIMEOUT_MSECS 5000
+# endif
+#endif
+#ifndef CONFIG_ADI_GPIO2
+# define CONFIG_ADI_GPIO1
+#endif
 #endif
diff --git a/include/configs/ca9x4_ct_vxp.h b/include/configs/ca9x4_ct_vxp.h
deleted file mode 100644
index a7cd1d4..0000000
--- a/include/configs/ca9x4_ct_vxp.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * (C) Copyright 2010 Linaro
- * Matt Waddel, <matt.waddel@linaro.org>
- *
- * Configuration for Versatile Express. Parts were derived from other ARM
- *   configurations.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Board info register */
-#define SYS_ID				0x10000000
-#define CONFIG_REVISION_TAG		1
-#define CONFIG_SYS_TEXT_BASE		0x60800000
-
-#define CONFIG_SYS_MEMTEST_START	0x60000000
-#define CONFIG_SYS_MEMTEST_END		0x20000000
-#define CONFIG_SYS_HZ			1000
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_SYS_L2CACHE_OFF		1
-#define CONFIG_INITRD_TAG		1
-
-#define CONFIG_OF_LIBFDT		1
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
-
-#define SCTL_BASE			0x10001000
-#define VEXPRESS_FLASHPROG_FLVPPEN	(1 << 0)
-
-/* SMSC9115 Ethernet from SMSC9118 family */
-#define CONFIG_SMC911X			1
-#define CONFIG_SMC911X_32_BIT		1
-#define CONFIG_SMC911X_BASE		0x4E000000
-
-/* PL011 Serial Configuration */
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL011_CLOCK		24000000
-#define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
-					 (void *)CONFIG_SYS_SERIAL1}
-#define CONFIG_CONS_INDEX		0
-
-#define CONFIG_BAUDRATE			38400
-#define CONFIG_SYS_SERIAL0		0x10009000
-#define CONFIG_SYS_SERIAL1		0x1000A000
-
-/* Command line configuration */
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PXE
-#define CONFIG_MENU
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_RUN
-
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION		1
-#define CONFIG_MMC			1
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_ARM_PL180_MMCI
-#define CONFIG_ARM_PL180_MMCI_BASE	0x10005000
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT	127
-#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
-
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_PXE
-#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
-#define CONFIG_BOOTP_VCI_STRING		"U-boot.armv7.ca9x4_ct_vxp"
-
-/* Miscellaneous configurable options */
-#undef	CONFIG_SYS_CLKS_IN_HZ
-#define CONFIG_SYS_LOAD_ADDR		0x60008000	/* load address */
-#define LINUX_BOOT_PARAM_ADDR		0x60000200
-#define CONFIG_BOOTDELAY		2
-
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS		2
-#define PHYS_SDRAM_1			0x60000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_2			0x80000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE		0x20000000	/* 512 MB */
-#define PHYS_SDRAM_2_SIZE		0x20000000	/* 512 MB */
-
-/* additions for new relocation code */
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE		0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_BASE + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_GBL_DATA_OFFSET
-
-/* Basic environment settings */
-#define CONFIG_BOOTCOMMAND		"run bootflash;"
-#define CONFIG_EXTRA_ENV_SETTINGS \
-		"loadaddr=0x80008000\0" \
-		"ramdisk_addr_r=0x61000000\0" \
-		"kernel_addr=0x44100000\0" \
-		"ramdisk_addr=0x44800000\0" \
-		"maxramdisk=0x1800000\0" \
-		"pxefile_addr_r=0x88000000\0" \
-		"kernel_addr_r=0x80008000\0" \
-		"console=ttyAMA0,38400n8\0" \
-		"dram=1024M\0" \
-		"root=/dev/sda1 rw\0" \
-		"mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
-			"24M@0x2000000(initrd)\0" \
-		"flashargs=setenv bootargs root=${root} console=${console} " \
-			"mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
-			"devtmpfs.mount=0  vmalloc=256M\0" \
-		"bootflash=run flashargs; " \
-			"cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
-			"bootm ${kernel_addr} ${ramdisk_addr_r}\0"
-
-/* FLASH and environment organization */
-#define PHYS_FLASH_SIZE			0x04000000	/* 64MB */
-#define CONFIG_SYS_FLASH_CFI		1
-#define CONFIG_FLASH_CFI_DRIVER		1
-#define CONFIG_SYS_FLASH_SIZE		0x04000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	2
-#define CONFIG_SYS_FLASH_BASE0		0x40000000
-#define CONFIG_SYS_FLASH_BASE1		0x44000000
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE0
-
-/* Timeout values in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Erase Timeout */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Write Timeout */
-
-/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
-#define CONFIG_SYS_MAX_FLASH_SECT	259		/* Max sectors */
-#define FLASH_MAX_SECTOR_SIZE		0x00040000	/* 256 KB sectors */
-
-/* Room required on the stack for the environment data */
-#define CONFIG_ENV_SIZE			FLASH_MAX_SECTOR_SIZE
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
-
-/*
- * Amount of flash used for environment:
- * We don't know which end has the small erase blocks so we use the penultimate
- * sector location for the environment
- */
-#define CONFIG_ENV_SECT_SIZE		FLASH_MAX_SECTOR_SIZE
-#define CONFIG_ENV_OVERWRITE		1
-
-/* Store environment at top of flash */
-#define CONFIG_ENV_IS_IN_FLASH		1
-#define CONFIG_ENV_OFFSET		(PHYS_FLASH_SIZE - \
-					(2 * CONFIG_ENV_SECT_SIZE))
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE1 + \
-					 CONFIG_ENV_OFFSET)
-#define CONFIG_SYS_FLASH_PROTECTION	/* The devices have real protection */
-#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE0, \
-					  CONFIG_SYS_FLASH_BASE1 }
-
-/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PROMPT		"VExpress# "
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
-#define CONFIG_CMD_SOURCE
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING		1
-#define CONFIG_SYS_MAXARGS		16	/* max command args */
-
-#endif
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 726714d..c6e357a 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -135,12 +135,12 @@
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
 #define CONFIG_CMD_FAT		/* FAT support			*/
-#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
 #define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
 #define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
 #define MTDIDS_DEFAULT		"nand0=nand"
 #define MTDPARTS_DEFAULT	"mtdparts=nand:512k(x-loader),"\
-				"1920k(u-boot),128k(u-boot-env),"\
+				"1920k(u-boot),256k(u-boot-env),"\
 				"4m(kernel),-(fs)"
 
 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
@@ -182,14 +182,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV		"nand0"
-/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET	0x680000
-#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
-							/* partition */
-
 /* Environment information */
 #define CONFIG_BOOTDELAY		10
 #define CONFIG_ZERO_BOOTDELAY_CHECK
@@ -204,9 +196,9 @@
 	"defaultdisplay=dvi\0" \
 	"mmcdev=0\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
-	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
 	"nandroot=/dev/mtdblock4 rw\0" \
-	"nandrootfstype=jffs2\0" \
+	"nandrootfstype=ubifs\0" \
 	"mmcargs=setenv bootargs console=${console} " \
 		"mpurate=${mpurate} " \
 		"vram=${vram} " \
@@ -232,7 +224,7 @@
 		"bootm ${loadaddr}\0" \
 	"nandboot=echo Booting from nand ...; " \
 		"run nandargs; " \
-		"nand read ${loadaddr} 280000 400000; " \
+		"nand read ${loadaddr} 2a0000 400000; " \
 		"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 5bacc77..2fefdc8 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -38,7 +38,6 @@
 #define CONFIG_SHOW_BOOT_PROGRESS
 #define CONFIG_LAST_STAGE_INIT
 #define CONFIG_SYS_VSNPRINTF
-#define CONFIG_INTEL_CORE_ARCH	/* Sandy bridge and ivy bridge chipsets. */
 #define CONFIG_ZBOOT_32
 #define CONFIG_PHYSMEM
 #define CONFIG_SYS_EARLY_PCI_INIT
@@ -49,6 +48,19 @@
 #define CONFIG_OF_SEPARATE
 #define CONFIG_DEFAULT_DEVICE_TREE	link
 
+#define CONFIG_BOOTSTAGE
+#define CONFIG_BOOTSTAGE_REPORT
+#define CONFIG_BOOTSTAGE_FDT
+#define CONFIG_CMD_BOOTSTAGE
+/* Place to stash bootstage data from first-stage U-Boot */
+#define CONFIG_BOOTSTAGE_STASH		0x0110f000
+#define CONFIG_BOOTSTAGE_STASH_SIZE	0x7fc
+#define CONFIG_BOOTSTAGE_USER_COUNT	60
+
+#define CONFIG_LZO
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+
 /*-----------------------------------------------------------------------
  * Watchdog Configuration
  */
@@ -78,7 +90,8 @@
 #endif
 
 /* Generic TPM interfaced through LPC bus */
-#define CONFIG_GENERIC_LPC_TPM
+#define CONFIG_TPM
+#define CONFIG_TPM_TIS_LPC
 #define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
 
 /*-----------------------------------------------------------------------
@@ -218,7 +231,6 @@
 #define CONFIG_SYS_MEMTEST_END			0x01000000
 #define CONFIG_SYS_LOAD_ADDR			0x100000
 #define CONFIG_SYS_HZ				1000
-#define CONFIG_SYS_X86_ISR_TIMER
 
 /*-----------------------------------------------------------------------
  * SDRAM Configuration
@@ -235,8 +247,9 @@
  * CPU Features
  */
 
-#define CONFIG_SYS_GENERIC_TIMER
+#define CONFIG_SYS_X86_TSC_TIMER
 #define CONFIG_SYS_PCAT_INTERRUPTS
+#define CONFIG_SYS_PCAT_TIMER
 #define CONFIG_SYS_NUM_IRQS			16
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 5cc9b5a..2e2d439 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -38,6 +38,8 @@
 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
 #elif defined(CONFIG_P5020DS)
 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
+#elif defined(CONFIG_P5040DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
 #endif
 #endif
 
diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h
index f7ac256..198892b 100644
--- a/include/configs/da830evm.h
+++ b/include/configs/da830evm.h
@@ -109,8 +109,8 @@
 #define CONFIG_SYS_NAND_CS		3
 #define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 #define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_CLE_MASK		0x10
-#define CONFIG_SYS_ALE_MASK		0x8
+#define CONFIG_SYS_NAND_MASK_CLE		0x10
+#define CONFIG_SYS_NAND_MASK_ALE		0x8
 #define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
 #endif
 
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 583568d..c420967 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -199,8 +199,8 @@
 #define	CONFIG_SYS_NAND_PAGE_2K
 #define CONFIG_SYS_NAND_CS		3
 #define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_CLE_MASK		0x10
-#define CONFIG_SYS_ALE_MASK		0x8
+#define CONFIG_SYS_NAND_MASK_CLE		0x10
+#define CONFIG_SYS_NAND_MASK_ALE		0x8
 #undef CONFIG_SYS_NAND_HW_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
index 2d63b67..97bc972 100644
--- a/include/configs/enbw_cmc.h
+++ b/include/configs/enbw_cmc.h
@@ -118,8 +118,8 @@
 #define CONFIG_SYS_NAND_PAGE_2K
 #define CONFIG_SYS_NAND_CS		3
 #define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_CLE_MASK		0x10
-#define CONFIG_SYS_ALE_MASK		0x8
+#define CONFIG_SYS_NAND_MASK_CLE		0x10
+#define CONFIG_SYS_NAND_MASK_ALE		0x8
 #undef CONFIG_SYS_NAND_HW_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
 
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 8a82892..41d6cf9 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -142,9 +142,9 @@
 /* TPM */
 #define CONFIG_TPM
 #define CONFIG_CMD_TPM
-#define CONFIG_INFINEON_TPM_I2C
-#define CONFIG_INFINEON_TPM_I2C_BUS 3
-#define CONFIG_INFINEON_TPM_I2C_ADDR 0x20
+#define CONFIG_TPM_TIS_I2C
+#define CONFIG_TPM_TIS_I2C_BUS_NUMBER	3
+#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR	0x20
 
 /* MMC SPL */
 #define CONFIG_SPL
diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h
new file mode 100644
index 0000000..e776514
--- /dev/null
+++ b/include/configs/goflexhome.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+ *
+ * Based on dockstar.h originally written by
+ * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.h originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_GOFLEXHOME_H
+#define _CONFIG_GOFLEXHOME_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nSeagate GoFlex Home"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KIRKWOOD		1	/* SOC Family Name */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_MACH_GOFLEXHOME		/* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Default GPIO configuration and LED status
+ */
+#define GOFLEXHOME_OE_LOW               (~(0))
+#define GOFLEXHOME_OE_HIGH              (~(0))
+#define GOFLEXHOME_OE_VAL_LOW           (1 << 29)       /* USB_PWEN low */
+#define GOFLEXHOME_OE_VAL_HIGH          (1 << 17)       /* LED pin high */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG         10
+#define MV88E1116_CPRSP_CR3_REG         21
+#define MV88E1116_MAC_CTRL_REG          21
+#define MV88E1116_PGADR_REG             22
+#define MV88E1116_RGMII_TXTM_CTRL       (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL       (1 << 5)
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EXT4
+#define CONFIG_SYS_MVFS         /* Picks up Filesystem from mv-common.h */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_SYS_PROMPT	/* previously defined in mv-common.h */
+#define CONFIG_SYS_PROMPT	"GoFlexHome> "	/* Command Prompt */
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_ADDR			0xC0000
+#define CONFIG_ENV_OFFSET		0xC0000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+	"ubi part root; " \
+	"ubifsmount ubi:root; " \
+	"ubifsload 0x800000 ${kernel}; " \
+	"bootm 0x800000"
+
+#define CONFIG_MTDPARTS \
+	"mtdparts=orion_nand:1m(uboot),6M(uImage),-(root)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=console=ttyS0,115200\0" \
+	"mtdids=nand0=orion_nand\0" \
+	"mtdparts="CONFIG_MTDPARTS \
+	"kernel=/boot/uImage\0" \
+	"bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ *  * SATA Driver configuration
+ *   */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+/*
+ *  * RTC driver configuration
+ *   */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#endif /* _CONFIG_GOFLEXHOME_H */
diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h
new file mode 100644
index 0000000..12f28f8
--- /dev/null
+++ b/include/configs/igep0033.h
@@ -0,0 +1,293 @@
+/*
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_IGEP0033_H
+#define __CONFIG_IGEP0033_H
+
+#define CONFIG_AM33XX
+#define CONFIG_OMAP
+
+#include <asm/arch/omap.h>
+
+/* Mach type */
+#define MACH_TYPE_IGEP0033		4521	/* Until the next sync */
+#define CONFIG_MACH_TYPE		MACH_TYPE_IGEP0033
+
+/* Clock defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+/* DMA defines */
+#define CONFIG_DMA_COHERENT
+#define CONFIG_DMA_COHERENT_SIZE	(1 << 20)
+
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"U-Boot# "
+#define CONFIG_SYS_NO_FLASH
+
+/* Display cpuinfo */
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+/*
+ * Because the issues explained in doc/README.memory-test, the "mtest command
+ * is considered deprecated. It should not be enabled in most normal ports of
+ * U-Boot.
+ */
+#undef CONFIG_CMD_MEMTEST
+
+#define CONFIG_BOOTDELAY		1	/* negative for no autoboot */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"rdaddr=0x81000000\0" \
+	"bootfile=/boot/uImage\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+	"ramrootfstype=ext2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+	"loaduimagefat=load mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+	"loaduimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"ramboot=echo Booting from ramdisk ...; " \
+		"run ramargs; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run loaduimage; then " \
+			"run mmcboot;" \
+		"fi;" \
+	"fi;" \
+
+/* Max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
+#define CONFIG_SYS_HZ			1000 /* 1ms clock */
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
+#define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
+						GENERATED_GBL_DATA_SIZE)
+/* Platform/Board specific defs */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(48000000)
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_ENV_OVERWRITE		1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* MMC support */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* GPIO support */
+#define CONFIG_OMAP_GPIO
+
+/* Ethernet support */
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR			0
+#define CONFIG_PHY_SMSC
+
+/* NAND support */
+#define CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_SYS_NAND_BASE		(0x08000000)	/* phys address CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_ONFI_DETECTION	1
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+#define MTDIDS_DEFAULT			"nand0=nand"
+#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(SPL),"\
+					"1m(U-Boot),128k(U-Boot Env),"\
+					"5m(Kernel),-(File System)"
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+/*
+ * Place the image at the start of the ROM defined image space.
+ * We limit our size to the ROM-defined downloaded image area, and use the
+ * rest of the space for stack.
+ */
+#define CONFIG_SPL_TEXT_BASE		0x402F0400
+#define CONFIG_SPL_MAX_SIZE		(0x4030C000 - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+
+#define CONFIG_SYS_NAND_ECCSTEPS	4
+#define	CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * \
+						CONFIG_SYS_NAND_ECCSTEPS)
+
+#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80800000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#endif	/* ! __CONFIG_IGEP0033_H */
diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h
index c663700..327a866 100644
--- a/include/configs/ima3-mx53.h
+++ b/include/configs/ima3-mx53.h
@@ -26,7 +26,6 @@
 /* SOC type must be included before imx-regs.h */
 #define CONFIG_MX53
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -79,8 +78,6 @@
 /* SPI FLASH - not used for environment */
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_CS		(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11) \
-						 << 8) | 0
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED		25000000
 
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 4ce4058..5b3fa43 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -77,6 +77,7 @@
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_USB
+#define	CONFIG_VIDEO
 
 #define CONFIG_REGEX			/* Enable regular expression support */
 
@@ -271,6 +272,24 @@
 #endif
 
 /*
+ * LCD
+ */
+#ifdef	CONFIG_VIDEO
+#define	CONFIG_CFB_CONSOLE
+#define	CONFIG_VIDEO_MXS
+#define	CONFIG_VIDEO_LOGO
+#define	CONFIG_VIDEO_SW_CURSOR
+#define	CONFIG_VGA_AS_SINGLE_DEVICE
+#define	CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define	CONFIG_SPLASH_SCREEN
+#define	CONFIG_CMD_BMP
+#define	CONFIG_BMP_16BPP
+#define	CONFIG_VIDEO_BMP_RLE8
+#define	CONFIG_VIDEO_BMP_GZIP
+#define	CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(512 << 10)
+#endif
+
+/*
  * Boot Linux
  */
 #define CONFIG_CMDLINE_TAG
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
new file mode 100644
index 0000000..8403d51
--- /dev/null
+++ b/include/configs/m53evk.h
@@ -0,0 +1,256 @@
+/*
+ * DENX M53 configuration
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __M53EVK_CONFIG_H__
+#define __M53EVK_CONFIG_H__
+
+#define CONFIG_MX53
+#define CONFIG_MXC_GPIO
+#define CONFIG_SYS_HZ		1000
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SATA
+#define CONFIG_CMD_USB
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS		2
+#define PHYS_SDRAM_1			CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE		(512 * 1024 * 1024)
+#define PHYS_SDRAM_2			CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE		(512 * 1024 * 1024)
+#define PHYS_SDRAM_SIZE			(PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	0x70000000
+#define CONFIG_SYS_MEMTEST_END		0xaff00000
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_TEXT_BASE		0x71000000
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT	"=> "
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
+#define CONFIG_CMDLINE_EDITING			/* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART2_BASE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+#endif
+
+/*
+ * NAND
+ */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR_AXI
+#define CONFIG_MXC_NAND_IP_REGS_BASE	NFC_BASE_ADDR
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+/* Environment is in NAND */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_RANGE		(512 * 1024)
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET_REDUND	\
+		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT			"nand0=mxc-nand"
+#define MTDPARTS_DEFAULT			\
+	"mtdparts=mxc-nand:"			\
+		"1m(bootloader)ro,"		\
+		"512k(environment),"		\
+		"512k(redundant-environment),"	\
+		"4m(kernel),"			\
+		"128k(fdt),"			\
+		"8m(ramdisk),"			\
+		"-(filesystem)"
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x0
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#endif
+
+/*
+ * I2C
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE		I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+/*
+ * RTC
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_M41T62
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX5
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT		1
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"m53evk/uImage"
+#define CONFIG_BOOTARGS		"console=ttymxc1,115200"
+#define CONFIG_LOADADDR		0x70800000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+#define CONFIG_OF_LIBFDT
+
+/*
+ * NAND SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TARGET		"u-boot-with-nand-spl.imx"
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_TEXT_BASE		0x70008000
+#define CONFIG_SPL_PAD_TO		0x8000
+#define CONFIG_SPL_STACK		0x70004000
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+
+#endif	/* __M53EVK_CONFIG_H__ */
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index af30257..c4f245b 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -275,7 +275,7 @@
 /*
  * IIM - IC Identification Module
  */
-#undef CONFIG_IIM
+#undef CONFIG_FSL_IIM
 
 /*
  * EEPROM configuration
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 0c4e719..17f53ba 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -104,7 +104,7 @@
 
 /* gpio */
 #ifdef XILINX_GPIO_BASEADDR
-# define CONFIG_SYS_GPIO_0		1
+# define CONFIG_XILINX_GPIO
 # define CONFIG_SYS_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
 #endif
 
@@ -312,6 +312,7 @@
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MFSL
 #define CONFIG_CMD_ECHO
+#define CONFIG_CMD_GPIO
 
 #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
 # define CONFIG_CMD_CACHE
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 6e6af62..64ce52d 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -370,7 +370,7 @@
 /*
  * IIM - IC Identification Module
  */
-#undef CONFIG_IIM
+#undef CONFIG_FSL_IIM
 
 /*
  * EEPROM configuration
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 3747955..54d01f9 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -63,6 +63,7 @@
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
 
 /* Memory configurations */
 #define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index cb3d938..13d1839 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -53,6 +53,9 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_FSL_IIM
+#define CONFIG_CMD_FUSE
+
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONFIG_MXC_GPIO
@@ -149,32 +152,66 @@
 
 #define CONFIG_ETHPRIME		"FEC0"
 
-#define CONFIG_LOADADDR		0x90800000	/* loadaddr env var */
+#define CONFIG_LOADADDR		0x92000000	/* loadaddr env var */
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
 	"uimage=uImage\0" \
+	"fdt_file=imx51-babbage.dtb\0" \
+	"fdt_addr=0x91000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
 	"mmcdev=0\0" \
 	"mmcpart=2\0" \
-	"mmcroot=/dev/mmcblk0p3 rw\0" \
-	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
 	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
-		"root=${mmcroot} " \
-		"rootfstype=${mmcrootfstype}\0" \
+		"root=${mmcroot}\0" \
 	"loadbootscript=" \
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
 	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
-		"bootm\0" \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0" \
 	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
 		"root=/dev/nfs " \
 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
 	"netboot=echo Booting from net ...; " \
 		"run netargs; " \
-		"dhcp ${uimage}; bootm\0" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${uimage}; " \
+		"if test ${boot_fdt} = yes ||  test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo ERROR: Cannot load the DT; " \
+					"exit; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
 	"mmc dev ${mmcdev}; if mmc rescan; then " \
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 148f7a2..41974b1 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -34,6 +34,7 @@
 #define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
@@ -90,6 +91,7 @@
 #include <config_cmd_default.h>
 
 #undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_SETEXPR
 
 #define CONFIG_BOOTDELAY	3
 
@@ -100,45 +102,98 @@
 #define CONFIG_SMC911X_16_BIT
 #define CONFIG_SMC911X_BASE CS1_BASE_ADDR
 
-#define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */
+#define CONFIG_LOADADDR		0x72000000	/* loadaddr env var */
 #define CONFIG_SYS_TEXT_BASE    0x77800000
 
+#define CONFIG_DEFAULT_FDT_FILE		"imx53-ard.dtb"
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
 	"uimage=uImage\0" \
-	"mmcdev=0\0" \
-	"mmcpart=2\0" \
-	"mmcroot=/dev/mmcblk0p3 rw\0" \
-	"mmcrootfstype=ext3 rootwait\0" \
-	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
-		"root=${mmcroot} " \
-		"rootfstype=${mmcrootfstype}\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x71000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
+	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
 	"loadbootscript=" \
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
 	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
-		"bootm\0" \
-	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
-		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-	"netboot=echo Booting from net ...; " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
 		"run netargs; " \
-		"dhcp ${uimage}; bootm\0" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${uimage}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
-	"mmc dev ${mmcdev}; if mmc rescan; then " \
-		"if run loadbootscript; then " \
-			"run bootscript; " \
-		"else " \
-			"if run loaduimage; then " \
-				"run mmcboot; " \
-			"else run netboot; " \
-			"fi; " \
-		"fi; " \
-	"else run netboot; fi"
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loaduimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
 #define CONFIG_ARP_TIMEOUT	200UL
 
 /* Miscellaneous configurable options */
@@ -185,6 +240,7 @@
 #define CONFIG_ENV_SIZE        (8 * 1024)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_SYS_MMC_ENV_PART	2
 
 #define CONFIG_OF_LIBFDT
 
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index a0af3ee..822b926 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -34,6 +34,7 @@
 #define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
 
 #define CONFIG_OF_LIBFDT
 
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index 9e83319..942949d 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -34,6 +34,7 @@
 #define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index b333937..674bcd3 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -17,6 +17,7 @@
 #ifndef __MX6_COMMON_H
 #define __MX6_COMMON_H
 
+#define CONFIG_ARM_ERRATA_742230
 #define CONFIG_ARM_ERRATA_743622
 #define CONFIG_ARM_ERRATA_751472
 
diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h
index f5f115f..7298a76 100644
--- a/include/configs/mx6qsabre_common.h
+++ b/include/configs/mx6qsabre_common.h
@@ -78,6 +78,7 @@
 
 #define CONFIG_CMD_BMODE
 #define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_SETEXPR
 #undef CONFIG_CMD_IMLS
 
 #define CONFIG_BOOTDELAY               1
@@ -98,6 +99,19 @@
 	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
 	"mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 6d4b837..b814418 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -47,6 +47,11 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_MXC_GPIO
 
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE	       UART2_BASE
 
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
new file mode 100644
index 0000000..8a94efd
--- /dev/null
+++ b/include/configs/mx6slevk.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SL EVK board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <asm/sizes.h>
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MACH_TYPE_MX6SLEVK		4307
+#define CONFIG_MACH_TYPE		MACH_TYPE_MX6SLEVK
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_IPS_BASE_ADDR
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_LOADADDR			0x80800000
+#define CONFIG_SYS_TEXT_BASE		0x87800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx6sl-evk.dtb\0" \
+	"fdt_addr=0x81000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${uimage}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loaduimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + SZ_512M)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE		SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			SZ_1G
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET		(6 * SZ_64K)
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 93e7fe4..aea91bc 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -44,6 +44,11 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_MXC_GPIO
 
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE	       UART2_BASE
 
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
index 376a3d0..f9adc01 100644
--- a/include/configs/omap3_mvblx.h
+++ b/include/configs/omap3_mvblx.h
@@ -273,7 +273,7 @@
 #endif /* (CONFIG_CMD_NET) */
 
 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA          CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index 1fd3097..d6448b0 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -87,6 +87,10 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
+
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
 /* I2C  */
 #define CONFIG_HARD_I2C			1
 #define CONFIG_SYS_I2C_SPEED		100000
@@ -176,7 +180,9 @@
 		"if test $board_name = sdp4430; then " \
 			"setenv fdtfile omap4-sdp.dtb; fi; " \
 		"if test $board_name = panda; then " \
-			"setenv fdtfile omap4-panda-es.dtb; fi\0" \
+			"setenv fdtfile omap4-panda.dtb; fi;" \
+		"if test $board_name = panda-es; then " \
+			"setenv fdtfile omap4-panda-es.dtb; fi; \0" \
 	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
 
 #define CONFIG_BOOTCOMMAND \
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index eacb5f5..abf586b 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -66,4 +66,6 @@
 
 #define CONFIG_SYS_PROMPT		"Panda # "
 
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
 #endif /* __CONFIG_PANDA_H */
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
index c21c387..deb5e9f 100644
--- a/include/configs/omap5_common.h
+++ b/include/configs/omap5_common.h
@@ -86,6 +86,9 @@
 
 #define CONFIG_BAUDRATE			115200
 
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
 /* I2C  */
 #define CONFIG_HARD_I2C
 #define CONFIG_SYS_I2C_SPEED		100000
@@ -150,10 +153,12 @@
 	"usbtty=cdc_acm\0" \
 	"vram=16M\0" \
 	"partitions=" PARTS_DEFAULT "\0" \
+	"optargs=\0" \
 	"mmcdev=0\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
 	"mmcrootfstype=ext4 rootwait\0" \
 	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
 		"vram=${vram} " \
 		"root=${mmcroot} " \
 		"rootfstype=${mmcrootfstype}\0" \
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 550cabd..9e0339b 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -37,7 +37,7 @@
 
 /* TWL6035 */
 #ifndef CONFIG_SPL_BUILD
-#define CONFIG_TWL6035_POWER
+#define CONFIG_PALMAS_POWER
 #endif
 
 /* MMC ENV related defines */
@@ -56,4 +56,5 @@
 
 #define CONFIG_SYS_PROMPT		"OMAP5430 EVM # "
 
+#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
 #endif /* __CONFIG_OMAP5_EVM_H */
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index d0ea74e..2ecd105 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -20,6 +20,7 @@
 #define __CONFIG_PCM051_H
 
 #define CONFIG_AM33XX
+#define CONFIG_OMAP
 
 #include <asm/arch/omap.h>
 
@@ -129,7 +130,6 @@
 					+ (8 * 1024 * 1024))
 
 #define CONFIG_SYS_LOAD_ADDR		0x80007fc0 /* Default load address */
-#define CONFIG_SYS_HZ			1000 /* 1ms clock */
 
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
@@ -158,13 +158,12 @@
  /* Platform/Board specific defs */
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_HZ			1000	/* 1ms clock */
 
 #define CONFIG_CONS_INDEX		1
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SERIAL_MULTI
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
 #define CONFIG_SYS_NS16550_CLK		(48000000)
 #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
@@ -194,6 +193,9 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 110, 300, 600, 1200, 2400, \
 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
 
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 
@@ -202,8 +204,13 @@
 /* Defines for SPL */
 #define CONFIG_SPL
 #define CONFIG_SPL_FRAMEWORK
+/*
+ * Place the image at the start of the ROM defined image space.
+ * We limit our size to the ROM-defined downloaded image area, and use the
+ * rest of the space for stack.
+ */
 #define CONFIG_SPL_TEXT_BASE		0x402F0400
-#define CONFIG_SPL_MAX_SIZE		(101 * 1024)
+#define CONFIG_SPL_MAX_SIZE		(0x4030C000 - CONFIG_SPL_TEXT_BASE)
 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
 
 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
index 306abcc..db95cb0 100644
--- a/include/configs/pdm360ng.h
+++ b/include/configs/pdm360ng.h
@@ -341,6 +341,11 @@
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_FSL_IIM
+
+/*
  * EEPROM configuration
  */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16-bit EEPROM addr */
@@ -402,6 +407,8 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
+#undef CONFIG_CMD_FUSE
+
 #ifdef CONFIG_VIDEO
 #define CONFIG_CMD_BMP
 #endif
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index b60a9ad..6f6ddfa 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -355,7 +355,7 @@
 
 #define CONFIG_BOOTCOMMAND		"run flashboot"
 #define CONFIG_ROOTPATH			"/ronetix/rootfs"
-#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n", bootdelay
 
 #define CONFIG_CON_ROT			"fbcon=rotate:3 "
 #define CONFIG_BOOTARGS			"root=/dev/mtdblock4 rootfstype=jffs2 "\
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
new file mode 100644
index 0000000..c13e983
--- /dev/null
+++ b/include/configs/sama5d3xek.h
@@ -0,0 +1,245 @@
+/*
+ * Configuation settings for the SAMA5D3xEK board.
+ *
+ * Copyright (C) 2012 - 2013 Atmel
+ *
+ * based on at91sam9m10g45ek.h by:
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x26f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_HZ		        1000
+
+#define CONFIG_AT91FAMILY
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT		/* Device Tree support */
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_DBGU
+
+/*
+ * This needs to be defined for the OHCI code to work but it is defined as
+ * ATMEL_ID_UHPHS in the CPU specific header files.
+ */
+#define ATMEL_ID_UHP			ATMEL_ID_UHPHS
+
+/*
+ * Specify the clock enable bit in the PMC_SCER register.
+ */
+#define ATMEL_PMC_UHP			AT91SAM926x_PMC_UHP
+
+/* LCD */
+#define CONFIG_LCD
+#define LCD_BPP				LCD_COLOR16
+#define LCD_OUTPUT_BPP                  24
+#define CONFIG_LCD_LOGO
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_HLCD
+#define CONFIG_ATMEL_LCD_RGB565
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* board specific (not enough SRAM) */
+#define CONFIG_SAMA5D3_LCD_BASE		0x23E00000
+
+#define CONFIG_BOOTDELAY		3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* SerialFlash */
+#define CONFIG_CMD_SF
+
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#endif
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_MAX_CHIPS		1
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP		4
+#define CONFIG_PMECC_SECTOR_SIZE	512
+#define CONFIG_PMECC_INDEX_TABLE_OFFSET	ATMEL_PMECC_INDEX_OFFSET_512
+#define CONFIG_CMD_NAND_TRIMFFS
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB_SEARCH_PHY
+
+/* MMC */
+#define CONFIG_CMD_MMC
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define ATMEL_BASE_MMCI			ATMEL_BASE_MCI0
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"sama5d3"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+#endif
+
+#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
+#define CONFIG_CMD_FAT
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
+
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+/* bootstrap + u-boot + env + linux in serial flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET       0x5000
+#define CONFIG_ENV_SIZE         0x3000
+#define CONFIG_ENV_SECT_SIZE    0x1000
+#define CONFIG_BOOTCOMMAND      "sf probe 0; " \
+				"sf read 0x22000000 0x42000 0x300000; " \
+				"bootm 0x22000000"
+#elif CONFIG_SYS_USE_NANDFLASH
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0xc0000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_BOOTCOMMAND	"nand read 0x21000000 0x180000 0x80000;" \
+				"nand read 0x22000000 0x200000 0x600000;" \
+				"bootm 0x22000000 - 0x21000000"
+#elif CONFIG_SYS_USE_MMC
+/* bootstrap + u-boot + env in sd card */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET	0x2000
+#define CONFIG_ENV_SIZE		0x1000
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x21000000 dtb; " \
+				"fatload mmc 0:1 0x22000000 uImage; " \
+				"bootm 0x22000000 - 0x21000000"
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#else
+#define CONIG_ENV_IS_NOWHERE
+#endif
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"root=/dev/mmcblk0p2 rw rootwait"
+#else
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256K(env),256k(evn_redundent),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
+#endif
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+
+#endif
diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
deleted file mode 100644
index f67898e..0000000
--- a/include/configs/sorcery.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * (C) Copyright 2004
- * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC8220		1
-#define CONFIG_SORCERY		1	/* Sorcery board */
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
-   determine the CPU speed. */
-#define CONFIG_SYS_MPC8220_CLKIN	60000000 /* ... running at 60MHz */
-#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC */
-
-#define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* PCI */
-#define CONFIG_PCI              1
-#define CONFIG_PCI_PNP          1
-
-#define CONFIG_PCI_MEM_BUS      0x80000000
-#define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE     0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x71000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_PCI_CFG_BUS	0x70000000
-#define CONFIG_PCI_CFG_PHYS	CONFIG_PCI_CFG_BUS
-#define CONFIG_PCI_CFG_SIZE	0x01000000
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Default Environment
- */
-#define CONFIG_BOOTDELAY	5    /* autoboot after 5 seconds */
-#define CONFIG_HOSTNAME		sorcery
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$serverip:$rootpath\0"				\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs $bootargs "				\
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
-		":$hostname:$netdev:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm $kernel_addr\0"					\
-	"flash_self=run ramargs addip;"					\
-		"bootm $kernel_addr $ramdisk_addr\0"			\
-	"net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/sorcery/uImage\0"				\
-	"kernel_addr=FFE00000\0"					\
-	"ramdisk_addr=FFB00000\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-#define CONFIG_EEPRO100
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_MODULE		1
-#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Flexbus Chipselect configuration
- * Beware: Some CS# seem to be mandatory (if these CS# are not set,
- * board can hang-up in unpredictable place).
- * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
- */
-
-/* Flash */
-#define CONFIG_SYS_CS0_BASE		0xf800
-#define CONFIG_SYS_CS0_MASK		0x08000000 /* 128 MB (two chips) */
-#define CONFIG_SYS_CS0_CTRL		0x001019c0
-
-/* NVM */
-#define CONFIG_SYS_CS1_BASE		0xf7e8
-#define CONFIG_SYS_CS1_MASK		0x00040000 /* 256K */
-#define CONFIG_SYS_CS1_CTRL		0x00101940 /* 8bit port size */
-
-/* Atlas2 + Gemini */
-#define CONFIG_SYS_CS2_BASE		0xf7e7
-#define CONFIG_SYS_CS2_MASK		0x00010000 /* 64K*/
-#define CONFIG_SYS_CS2_CTRL		0x001011c0 /* 16bit port size */
-
-/* CAN Controller */
-#define CONFIG_SYS_CS3_BASE		0xf7e6
-#define CONFIG_SYS_CS3_MASK		0x00010000 /* 64K */
-#define CONFIG_SYS_CS3_CTRL		0x00102140 /* 8Bit port size */
-
-/* Foreign interface */
-#define CONFIG_SYS_CS4_BASE		0xf7e5
-#define CONFIG_SYS_CS4_MASK		0x00010000 /* 64K */
-#define CONFIG_SYS_CS4_CTRL		0x00101dc0 /* 16bit port size */
-
-/* CPLD */
-#define CONFIG_SYS_CS5_BASE		0xf7e4
-#define CONFIG_SYS_CS5_MASK		0x00010000 /* 64K */
-#define CONFIG_SYS_CS5_CTRL		0x001000c0 /* 16bit port size */
-
-#define CONFIG_SYS_FLASH0_BASE		(CONFIG_SYS_CS0_BASE << 16)
-#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_FLASH0_BASE)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,  \
-				CONFIG_SYS_FLASH_BASE+0x04000000 } /* two banks */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x8000000 - 0x40000)
-#define CONFIG_ENV_SIZE		0x4000                       /* 16K */
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + 0x20000)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
-
-#define CONFIG_ENV_OVERWRITE	1
-
-#if defined CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-#define CONFIG_SYS_SRAM_BASE		(CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_SRAM_SIZE		0x8000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
-
-/* SDRAM configuration (for SPD) */
-#define CONFIG_SYS_SDRAM_TOTAL_BANKS		1
-#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR		0x50		/* 7bit */
-#define CONFIG_SYS_SDRAM_SPD_SIZE		0x100
-#define CONFIG_SYS_SDRAM_CAS_LATENCY		5		/* (CL=2.5)x2 */
-
-/* SDRAM drive strength register (for SSTL_2 class II)*/
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
-					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
-					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
-					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
-					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC8220_FEC	1
-#define CONFIG_FEC_10MBIT	1 /* Workaround for FEC 100Mbit problem */
-#define CONFIG_PHY_ADDR		0x1F
-#define CONFIG_MII		1
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			    /* undef to save memory	*/
-#define CONFIG_SYS_PROMPT		"=> "	    /* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	    /* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE		256	    /* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	    /* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000  /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000    /* default load address */
-
-#define CONFIG_SYS_HZ			1000	    /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-
-/*
-#define CONFIG_SYS_HID0_INIT           HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL          HID0_ICE
-*/
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 2c665b8..fa1dcc3 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -29,13 +29,14 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
 #endif
 
 #define CONFIG_CMD_REGINFO
 
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
-#define CONFIG_E6500
 #define CONFIG_E500			/* BOOKE e500 family */
 #define CONFIG_E500MC			/* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
@@ -444,11 +445,19 @@
 #define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus multiplexer,primary */
 #define I2C_MUX_PCA_ADDR_SEC		0x76 /* I2C bus multiplexer,secondary */
 
-/* VSC Crossbar switches */
-#define CONFIG_VSC_CROSSBAR
 #define I2C_MUX_CH_DEFAULT	0x8
+#define I2C_MUX_CH_VOL_MONITOR	0xa
 #define I2C_MUX_CH_VSC3316_FS	0xc
 #define I2C_MUX_CH_VSC3316_BS	0xd
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR		0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+
+/* VSC Crossbar switches */
+#define CONFIG_VSC_CROSSBAR
 #define VSC3316_FSM_TX_ADDR	0x70
 #define VSC3316_FSM_RX_ADDR	0x71
 
@@ -504,7 +513,7 @@
  */
 #define CONFIG_FSL_ESPI
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_SST
 #define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
@@ -641,15 +650,10 @@
 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#define XFI_CARD_PORT1_PHY_ADDR	0x1 /* tmp, FIXME below addr */
-#define XFI_CARD_PORT2_PHY_ADDR	0x2
-#define XFI_CARD_PORT3_PHY_ADDR	0x3
-#define XFI_CARD_PORT4_PHY_ADDR	0x4
-#define QSGMII_CARD_PHY_ADDR	0x5
-#define FM1_10GEC1_PHY_ADDR	0x6
-#define FM1_10GEC2_PHY_ADDR	0x7
-#define FM2_10GEC1_PHY_ADDR	0x8
-#define FM2_10GEC2_PHY_ADDR	0x9
+#define FM1_10GEC1_PHY_ADDR	0x0
+#define FM1_10GEC2_PHY_ADDR	0x1
+#define FM2_10GEC1_PHY_ADDR	0x2
+#define FM2_10GEC2_PHY_ADDR	0x3
 #endif
 
 #ifdef CONFIG_PCI
@@ -783,8 +787,21 @@
 
 #define __USB_PHY_TYPE	utmi
 
+/*
+ * T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to
+ * cacheline interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
-	"hwconfig=fsl_ddr:ctlr_intlv=3way_4KB,"		\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
 	"bank_intlv=auto;"					\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index bf18699..6ed2fde 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -157,6 +157,8 @@
 /* overrides for SPL build here */
 #ifdef CONFIG_SPL_BUILD
 
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
 /* remove devicetree support */
 #ifdef CONFIG_OF_CONTROL
 #undef CONFIG_OF_CONTROL
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index c2986d8..721b29c 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -74,8 +74,6 @@
 #define CONFIG_SYS_SPL_MALLOC_START	0x80090000
 #define CONFIG_SPL_STACK		0x800ffffc
 
-#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/tegra114/u-boot-spl.lds"
-
 /* Total I2C ports on Tegra114 */
 #define TEGRA_I2C_NUM_CONTROLLERS	5
 
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index 395a657..d5abecb 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -88,8 +88,6 @@
 #define CONFIG_SYS_SPL_MALLOC_START	0x00090000
 #define CONFIG_SPL_STACK		0x000ffffc
 
-#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/tegra20/u-boot-spl.lds"
-
 /* Align LCD to 1MB boundary */
 #define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE
 
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index f6c07c6..ed36e11 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -87,8 +87,6 @@
 #define CONFIG_SYS_SPL_MALLOC_START	0x80090000
 #define CONFIG_SPL_STACK		0x800ffffc
 
-#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/tegra30/u-boot-spl.lds"
-
 /* Total I2C ports on Tegra30 */
 #define TEGRA_I2C_NUM_CONTROLLERS	5
 
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 16547e3..eac5ad0 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -19,6 +19,7 @@
 #define CONFIG_TI81XX
 #define CONFIG_TI814X
 #define CONFIG_SYS_NO_FLASH
+#define CONFIG_OMAP
 
 #include <asm/arch/omap.h>
 
@@ -162,6 +163,9 @@
 
 #define CONFIG_BAUDRATE			115200
 
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
@@ -218,4 +222,25 @@
 /* Unsupported features */
 #undef CONFIG_USE_IRQ
 
+/* Ethernet */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR			1
+#define CONFIG_PHY_ET1011C
+#define CONFIG_PHY_ET1011C_TX_CLK_FIX
+
 #endif	/* ! __CONFIG_TI814X_EVM_H */
diff --git a/include/configs/titanium.h b/include/configs/titanium.h
new file mode 100644
index 0000000..41e4513
--- /dev/null
+++ b/include/configs/titanium.h
@@ -0,0 +1,277 @@
+/*
+ * Copyright (C) 2013 Stefan Roese <sr@denx.de>
+ *
+ * Configuration settings for the ProjectionDesign / Barco
+ * Titanium board.
+ *
+ * Based on mx6qsabrelite.h which is:
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_MX6
+#define CONFIG_MX6Q
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MACH_TYPE_TITANIUM		3769
+#define CONFIG_MACH_TYPE		MACH_TYPE_TITANIUM
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_MXC_PHYADDR		4
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_LOADADDR			0x12000000
+#define CONFIG_SYS_TEXT_BASE		0x17800000
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (500 << 20))
+
+#define CONFIG_HOSTNAME			titanium
+#define CONFIG_UBI_PART			ubi
+#define CONFIG_UBIFS_VOLUME		rootfs0
+
+#define MTDIDS_DEFAULT		"nand0=gpmi-nand"
+#define MTDPARTS_DEFAULT	"mtdparts=gpmi-nand:16M(uboot),512k(env1)," \
+				"512k(env2),-(ubi)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
+	"kernel_fs=/boot/uImage\0"					\
+	"kernel_addr=11000000\0"					\
+	"dtb=" __stringify(CONFIG_HOSTNAME) "/"				\
+		__stringify(CONFIG_HOSTNAME) ".dtb\0"			\
+	"dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0"		\
+	"dtb_addr=12800000\0"						\
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"console=ttymxc0\0" \
+	"baudrate=115200\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"initrd_high=0xffffffff\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"uimage=uImage\0" \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
+		" ${script}\0" \
+	"bootscript=echo Running bootscript from mmc ...; source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot} rootwait rw\0" \
+	"bootmmc=run mmcargs; fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
+		" ${uimage}; bootm\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addcon=setenv bootargs ${bootargs} console=ttymxc0,"		\
+		"${baudrate}\0"						\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"rootpath=/opt/eldk-5.3/armv7a/rootfs-minimal-mtdutils\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0"		\
+	"part=" __stringify(CONFIG_UBI_PART) "\0"			\
+	"boot_vol=0\0"							\
+	"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0"			\
+	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0"			\
+	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}"	\
+		" ${filesize}\0"					\
+	"upd_ubifs=run load_ubifs update_ubifs\0"			\
+	"init_ubi=nand erase.part ubi;ubi part ${part};"		\
+		"ubi create ${vol} c800000\0"				\
+	"mtdids=" MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip"		\
+		" addcon addmtd;"					\
+		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
+	"ubifsargs=set bootargs ubi.mtd=ubi "				\
+		"root=ubi:rootfs${boot_vol} rootfstype=ubifs\0"		\
+	"ubifs_mount=ubi part ubi;ubifsmount ubi:rootfs${boot_vol}\0"	\
+	"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};"		\
+		"ubifsload ${dtb_addr} ${dtb_fs};\0"			\
+	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon "	\
+		"addmtd;bootm ${kernel_addr} - ${dtb_addr}\0"		\
+	"load_kernel=tftp ${kernel_addr} ${kernel}\0"			\
+	"load_dtb=tftp ${dtb_addr} ${dtb}\0"				\
+	"net_nfs=run load_dtb load_kernel; "				\
+		"run nfsargs addip addcon addmtd;"			\
+		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
+	"delenv=env default -a -f; saveenv; reset\0"
+
+#define CONFIG_BOOTCOMMAND		"run nand_ubifs"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"Titanium > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
+
+#define CONFIG_SYS_CBSIZE		256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			(512 << 20)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+/* Enable NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_TIME
+
+#ifdef CONFIG_CMD_NAND
+
+/* NAND stuff */
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+
+/* Environment in NAND */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(16 << 20)
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + (512 << 10))
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+#else /* CONFIG_CMD_NAND */
+
+/* Environment in MMC */
+#define CONFIG_ENV_SIZE			(8 << 10)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#endif /* CONFIG_CMD_NAND */
+
+/* UBI/UBIFS config options */
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif			       /* __CONFIG_H */
diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h
index d6371fc..cabc06e 100644
--- a/include/configs/tnetv107x_evm.h
+++ b/include/configs/tnetv107x_evm.h
@@ -82,8 +82,8 @@
 #define CONFIG_SYS_NAND_CS		2
 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 #define CONFIG_SYS_NAND_BASE		TNETV107X_ASYNC_EMIF_DATA_CE0_BASE
-#define CONFIG_SYS_CLE_MASK		0x10
-#define CONFIG_SYS_ALE_MASK		0x8
+#define CONFIG_SYS_NAND_MASK_CLE		0x10
+#define CONFIG_SYS_NAND_MASK_ALE		0x8
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_CMD_MTDPARTS
diff --git a/arch/arm/include/asm/arch-mx25/sys_proto.h b/include/configs/vexpress_ca15_tc2.h
similarity index 60%
copy from arch/arm/include/asm/arch-mx25/sys_proto.h
copy to include/configs/vexpress_ca15_tc2.h
index 46db341..9e230ad 100644
--- a/arch/arm/include/asm/arch-mx25/sys_proto.h
+++ b/include/configs/vexpress_ca15_tc2.h
@@ -1,6 +1,9 @@
 /*
- * (C) Copyright 2009
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ * (C) Copyright 2013 Linaro
+ * Andre Przywara, <andre.przywara@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -12,7 +15,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -21,12 +24,13 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
+#ifndef __VEXPRESS_CA15X2_TC2_h
+#define __VEXPRESS_CA15X2_TC2_h
 
-void mx25_uart1_init_pins(void);
-#if defined CONFIG_FEC_MXC
-extern void mx25_fec_init_pins(void);
-#endif
+#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
+#include "vexpress_common.h"
+#define CONFIG_BOOTP_VCI_STRING     "U-boot.armv7.vexpress_ca15x2_tc2"
+
+#define CONFIG_SYS_CLK_FREQ 24000000
 
 #endif
diff --git a/arch/arm/include/asm/arch-mx25/sys_proto.h b/include/configs/vexpress_ca5x2.h
similarity index 61%
rename from arch/arm/include/asm/arch-mx25/sys_proto.h
rename to include/configs/vexpress_ca5x2.h
index 46db341..9331134 100644
--- a/arch/arm/include/asm/arch-mx25/sys_proto.h
+++ b/include/configs/vexpress_ca5x2.h
@@ -1,6 +1,9 @@
 /*
- * (C) Copyright 2009
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ * (C) Copyright 2011 Linaro
+ * Ryan Harkin, <ryan.harkin@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -12,7 +15,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -21,12 +24,11 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
+#ifndef __VEXPRESS_CA5X2_h
+#define __VEXPRESS_CA5X2_h
 
-void mx25_uart1_init_pins(void);
-#if defined CONFIG_FEC_MXC
-extern void mx25_fec_init_pins(void);
-#endif
+#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
+#include "vexpress_common.h"
+#define CONFIG_BOOTP_VCI_STRING     "U-boot.armv7.vexpress_ca5x2"
 
-#endif
+#endif /* __VEXPRESS_CA5X2_h */
diff --git a/arch/arm/include/asm/arch-mx25/sys_proto.h b/include/configs/vexpress_ca9x4.h
similarity index 61%
copy from arch/arm/include/asm/arch-mx25/sys_proto.h
copy to include/configs/vexpress_ca9x4.h
index 46db341..c3b6986 100644
--- a/arch/arm/include/asm/arch-mx25/sys_proto.h
+++ b/include/configs/vexpress_ca9x4.h
@@ -1,6 +1,9 @@
 /*
- * (C) Copyright 2009
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ * (C) Copyright 2011 Linaro
+ * Ryan Harkin, <ryan.harkin@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -12,7 +15,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -21,12 +24,11 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
+#ifndef __VEXPRESS_CA9X4_H
+#define __VEXPRESS_CA9X4_H
 
-void mx25_uart1_init_pins(void);
-#if defined CONFIG_FEC_MXC
-extern void mx25_fec_init_pins(void);
-#endif
+#define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
+#include "vexpress_common.h"
+#define CONFIG_BOOTP_VCI_STRING     "U-boot.armv7.vexpress_ca9x4"
 
-#endif
+#endif /* VEXPRESS_CA9X4_H */
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
new file mode 100644
index 0000000..3c5683a
--- /dev/null
+++ b/include/configs/vexpress_common.h
@@ -0,0 +1,315 @@
+/*
+ * (C) Copyright 2011 ARM Limited
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __VEXPRESS_COMMON_H
+#define __VEXPRESS_COMMON_H
+
+/*
+ * Definitions copied from linux kernel:
+ * arch/arm/mach-vexpress/include/mach/motherboard.h
+ */
+#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
+/* CS register bases for the original memory map. */
+#define V2M_PA_CS0		0x40000000
+#define V2M_PA_CS1		0x44000000
+#define V2M_PA_CS2		0x48000000
+#define V2M_PA_CS3		0x4c000000
+#define V2M_PA_CS7		0x10000000
+
+#define V2M_PERIPH_OFFSET(x)	(x << 12)
+#define V2M_SYSREGS		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
+#define V2M_SYSCTL		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
+#define V2M_SERIAL_BUS_PCI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
+
+#define V2M_BASE		0x60000000
+#define CONFIG_SYS_TEXT_BASE	0x60800000
+#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
+/* CS register bases for the extended memory map. */
+#define V2M_PA_CS0		0x08000000
+#define V2M_PA_CS1		0x0c000000
+#define V2M_PA_CS2		0x14000000
+#define V2M_PA_CS3		0x18000000
+#define V2M_PA_CS7		0x1c000000
+
+#define V2M_PERIPH_OFFSET(x)	(x << 16)
+#define V2M_SYSREGS		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
+#define V2M_SYSCTL		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
+#define V2M_SERIAL_BUS_PCI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
+
+#define V2M_BASE		0x80000000
+#define CONFIG_SYS_TEXT_BASE	0x80800000
+#endif
+
+/*
+ * Physical addresses, offset from V2M_PA_CS0-3
+ */
+#define V2M_NOR0		(V2M_PA_CS0)
+#define V2M_NOR1		(V2M_PA_CS1)
+#define V2M_SRAM		(V2M_PA_CS2)
+#define V2M_VIDEO_SRAM		(V2M_PA_CS3 + 0x00000000)
+#define V2M_LAN9118		(V2M_PA_CS3 + 0x02000000)
+#define V2M_ISP1761		(V2M_PA_CS3 + 0x03000000)
+
+/* Common peripherals relative to CS7. */
+#define V2M_AACI		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
+#define V2M_MMCI		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
+#define V2M_KMI0		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
+#define V2M_KMI1		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
+
+#define V2M_UART0		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
+#define V2M_UART1		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
+#define V2M_UART2		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
+#define V2M_UART3		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
+
+#define V2M_WDT			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
+
+#define V2M_TIMER01		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
+#define V2M_TIMER23		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
+
+#define V2M_SERIAL_BUS_DVI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
+#define V2M_RTC			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
+
+#define V2M_CF			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
+
+#define V2M_CLCD		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
+#define V2M_SIZE_CS7		V2M_PERIPH_OFFSET(32)
+
+/* System register offsets. */
+#define V2M_SYS_CFGDATA		(V2M_SYSREGS + 0x0a0)
+#define V2M_SYS_CFGCTRL		(V2M_SYSREGS + 0x0a4)
+#define V2M_SYS_CFGSTAT		(V2M_SYSREGS + 0x0a8)
+
+/*
+ * Configuration
+ */
+#define SYS_CFG_START		(1 << 31)
+#define SYS_CFG_WRITE		(1 << 30)
+#define SYS_CFG_OSC		(1 << 20)
+#define SYS_CFG_VOLT		(2 << 20)
+#define SYS_CFG_AMP		(3 << 20)
+#define SYS_CFG_TEMP		(4 << 20)
+#define SYS_CFG_RESET		(5 << 20)
+#define SYS_CFG_SCC		(6 << 20)
+#define SYS_CFG_MUXFPGA		(7 << 20)
+#define SYS_CFG_SHUTDOWN	(8 << 20)
+#define SYS_CFG_REBOOT		(9 << 20)
+#define SYS_CFG_DVIMODE		(11 << 20)
+#define SYS_CFG_POWER		(12 << 20)
+#define SYS_CFG_SITE_MB		(0 << 16)
+#define SYS_CFG_SITE_DB1	(1 << 16)
+#define SYS_CFG_SITE_DB2	(2 << 16)
+#define SYS_CFG_STACK(n)	((n) << 12)
+
+#define SYS_CFG_ERR		(1 << 1)
+#define SYS_CFG_COMPLETE	(1 << 0)
+
+/* Board info register */
+#define SYS_ID				V2M_SYSREGS
+#define CONFIG_REVISION_TAG		1
+
+#define CONFIG_SYS_MEMTEST_START	V2M_BASE
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_SYS_L2CACHE_OFF		1
+#define CONFIG_INITRD_TAG		1
+
+#define CONFIG_OF_LIBFDT		1
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+#define SCTL_BASE			V2M_SYSCTL
+#define VEXPRESS_FLASHPROG_FLVPPEN	(1 << 0)
+
+/* SMSC9115 Ethernet from SMSC9118 family */
+#define CONFIG_SMC911X			1
+#define CONFIG_SMC911X_32_BIT		1
+#define CONFIG_SMC911X_BASE		V2M_LAN9118
+
+/* PL011 Serial Configuration */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK		24000000
+#define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
+					 (void *)CONFIG_SYS_SERIAL1}
+#define CONFIG_CONS_INDEX		0
+
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SERIAL0		V2M_UART0
+#define CONFIG_SYS_SERIAL1		V2M_UART1
+
+/* Command line configuration */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION		1
+#define CONFIG_MMC			1
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_ARM_PL180_MMCI
+#define CONFIG_ARM_PL180_MMCI_BASE	V2M_MMCI
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	127
+#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
+
+/* Miscellaneous configurable options */
+#undef	CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x8000)
+#define LINUX_BOOT_PARAM_ADDR		(V2M_BASE + 0x2000)
+#define CONFIG_BOOTDELAY		2
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		2
+#define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_2			(((unsigned int)V2M_BASE) + \
+					((unsigned int)0x20000000))
+#define PHYS_SDRAM_1_SIZE		0x20000000	/* 512 MB */
+#define PHYS_SDRAM_2_SIZE		0x20000000	/* 512 MB */
+
+/* additions for new relocation code */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE		0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_GBL_DATA_OFFSET
+
+/* Basic environment settings */
+#define CONFIG_BOOTCOMMAND		"run bootflash;"
+#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
+#define CONFIG_PLATFORM_ENV_SETTINGS \
+		"loadaddr=0x80008000\0" \
+		"ramdisk_addr_r=0x61000000\0" \
+		"kernel_addr=0x44100000\0" \
+		"ramdisk_addr=0x44800000\0" \
+		"maxramdisk=0x1800000\0" \
+		"pxefile_addr_r=0x88000000\0" \
+		"kernel_addr_r=0x80008000\0"
+#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
+#define CONFIG_PLATFORM_ENV_SETTINGS \
+		"loadaddr=0xa0008000\0" \
+		"ramdisk_addr_r=0x81000000\0" \
+		"kernel_addr=0x0c100000\0" \
+		"ramdisk_addr=0x0c800000\0" \
+		"maxramdisk=0x1800000\0" \
+		"pxefile_addr_r=0xa8000000\0" \
+		"kernel_addr_r=0xa0008000\0"
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+		CONFIG_PLATFORM_ENV_SETTINGS \
+		"console=ttyAMA0,38400n8\0" \
+		"dram=1024M\0" \
+		"root=/dev/sda1 rw\0" \
+		"mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
+			"24M@0x2000000(initrd)\0" \
+		"flashargs=setenv bootargs root=${root} console=${console} " \
+			"mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
+			"devtmpfs.mount=0  vmalloc=256M\0" \
+		"bootflash=run flashargs; " \
+			"cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
+			"bootm ${kernel_addr} ${ramdisk_addr_r}\0"
+
+/* FLASH and environment organization */
+#define PHYS_FLASH_SIZE			0x04000000	/* 64MB */
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define CONFIG_SYS_FLASH_SIZE		0x04000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+#define CONFIG_SYS_FLASH_BASE0		V2M_NOR0
+#define CONFIG_SYS_FLASH_BASE1		V2M_NOR1
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE0
+
+/* Timeout values in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Erase Timeout */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Write Timeout */
+
+/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
+#define CONFIG_SYS_MAX_FLASH_SECT	259		/* Max sectors */
+#define FLASH_MAX_SECTOR_SIZE		0x00040000	/* 256 KB sectors */
+
+/* Room required on the stack for the environment data */
+#define CONFIG_ENV_SIZE			FLASH_MAX_SECTOR_SIZE
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
+
+/*
+ * Amount of flash used for environment:
+ * We don't know which end has the small erase blocks so we use the penultimate
+ * sector location for the environment
+ */
+#define CONFIG_ENV_SECT_SIZE		FLASH_MAX_SECTOR_SIZE
+#define CONFIG_ENV_OVERWRITE		1
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_OFFSET		(PHYS_FLASH_SIZE - \
+					(2 * CONFIG_ENV_SECT_SIZE))
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE1 + \
+					 CONFIG_ENV_OFFSET)
+#define CONFIG_SYS_FLASH_PROTECTION	/* The devices have real protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE0, \
+					  CONFIG_SYS_FLASH_BASE1 }
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PROMPT		"VExpress# "
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_CMD_SOURCE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_SYS_MAXARGS		16	/* max command args */
+
+#endif /* VEXPRESS_COMMON_H */
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 120e3f6..9d7ec3f 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -32,6 +32,7 @@
 #define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MXC_GPIO
 
 #define CONFIG_MXC_UART
@@ -47,6 +48,9 @@
 
 #undef CONFIG_CMD_IMLS
 
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
 #define CONFIG_BOOTDELAY		5
 
 #define CONFIG_SYS_MEMTEST_START	0x10000000
@@ -57,6 +61,7 @@
 /* MMC Configuration */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM	2
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 
 #define CONFIG_MMC
@@ -97,9 +102,23 @@
 	"fdt_addr=0x11000000\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
-	"mmcdev=0\0" \
-	"mmcpart=2\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
 	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
@@ -198,6 +217,7 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
 #define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 2989e72..38f04f6 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -50,19 +50,50 @@
 #define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
 #define CONFIG_ZYNQ_SERIAL_CLOCK0	50000000
 
-/* SCU timer address is hardcoded */
-#define CONFIG_SCUTIMER_BASEADDR	0xF8F00600
-
 /* Ethernet driver */
 #define CONFIG_NET_MULTI
 #define CONFIG_ZYNQ_GEM
-#define CONFIG_ZYNQ_GEM_BASEADDR0	0xE000B000
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
+
+#define CONFIG_ZYNQ_SDHCI
+#define CONFIG_ZYNQ_SDHCI0
+
+/* MMC */
+#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
+# define CONFIG_MMC
+# define CONFIG_GENERIC_MMC
+# define CONFIG_SDHCI
+# define CONFIG_ZYNQ_SDHCI
+# define CONFIG_CMD_MMC
+# define CONFIG_CMD_FAT
+# define CONFIG_SUPPORT_VFAT
+# define CONFIG_CMD_EXT2
+# define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_ZYNQ_I2C0
+
+/* I2C */
+#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
+# define CONFIG_CMD_I2C
+# define CONFIG_ZYNQ_I2C
+# define CONFIG_HARD_I2C
+# define CONFIG_SYS_I2C_SPEED		100000
+# define CONFIG_SYS_I2C_SLAVE		1
+#endif
 
 #if defined(CONFIG_ZYNQ_DCC)
 # define CONFIG_ARM_DCC
 # define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
 #endif
 
+/* Enable the PL to be downloaded */
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_ZYNQPL
+#define CONFIG_CMD_FPGA
+
 #define CONFIG_BOOTP_SERVERIP
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
diff --git a/include/ext4fs.h b/include/ext4fs.h
index 025a2e8..379f7eb 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -141,4 +141,5 @@
 int ext4fs_probe(block_dev_desc_t *fs_dev_desc,
 		 disk_partition_t *fs_partition);
 int ext4_read_file(const char *filename, void *buf, int offset, int len);
+int ext4_read_superblock(char *buffer);
 #endif
diff --git a/include/ext_common.h b/include/ext_common.h
index 86373a6..78a7808 100644
--- a/include/ext_common.h
+++ b/include/ext_common.h
@@ -34,7 +34,6 @@
 #define __EXT_COMMON__
 #include <command.h>
 #define SECTOR_SIZE		0x200
-#define SECTOR_BITS		9
 
 /* Magic value used to identify an ext2 filesystem.  */
 #define	EXT2_MAGIC			0xEF53
@@ -58,18 +57,13 @@
 #define FILETYPE_INO_SYMLINK		0120000
 #define EXT2_ROOT_INO			2 /* Root inode */
 
-/* Bits used as offset in sector */
-#define DISK_SECTOR_BITS		9
 /* The size of an ext2 block in bytes.  */
 #define EXT2_BLOCK_SIZE(data)	   (1 << LOG2_BLOCK_SIZE(data))
 
-/* Log2 size of ext2 block in 512 blocks.  */
-#define LOG2_EXT2_BLOCK_SIZE(data) (__le32_to_cpu \
-				(data->sblock.log2_block_size) + 1)
-
 /* Log2 size of ext2 block in bytes.  */
-#define LOG2_BLOCK_SIZE(data)	   (__le32_to_cpu \
-		(data->sblock.log2_block_size) + 10)
+#define LOG2_BLOCK_SIZE(data)	   (__le32_to_cpu		   \
+				    (data->sblock.log2_block_size) \
+				    + EXT2_MIN_BLOCK_LOG_SIZE)
 #define INODE_SIZE_FILESYSTEM(data)	(__le32_to_cpu \
 			(data->sblock.inode_size))
 
diff --git a/include/faraday/ftsdc010.h b/include/faraday/ftsdc010.h
index c34dde7..8284f53 100644
--- a/include/faraday/ftsdc010.h
+++ b/include/faraday/ftsdc010.h
@@ -23,6 +23,7 @@
 #define __FTSDC010_H
 
 #ifndef __ASSEMBLY__
+
 /* sd controller register */
 struct ftsdc010_mmc {
 	unsigned int	cmd;		/* 0x00 - command reg		*/
@@ -143,6 +144,15 @@
 #define FTSDC010_STATUS_SDIO_IRPT		(1 << 16) /* SDIO card intr */
 #define FTSDC010_STATUS_DATA0_STATUS		(1 << 17)
 #endif /* CONFIG_FTSDC010_SDIO */
+#define FTSDC010_STATUS_RSP_ERROR	\
+	(FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_RSP_TIMEOUT)
+#define FTSDC010_STATUS_RSP_MASK	\
+	(FTSDC010_STATUS_RSP_ERROR | FTSDC010_STATUS_RSP_CRC_OK)
+#define FTSDC010_STATUS_DATA_ERROR	\
+	(FTSDC010_STATUS_DATA_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT)
+#define FTSDC010_STATUS_DATA_MASK	\
+	(FTSDC010_STATUS_DATA_ERROR | FTSDC010_STATUS_DATA_CRC_OK \
+	| FTSDC010_STATUS_DATA_END)
 
 /* 0x2c - clear register */
 #define FTSDC010_CLR_RSP_CRC_FAIL		(1 << 0)
@@ -192,21 +202,24 @@
 #define FTSDC010_CCR_CLK_DIV(x)			(((x) & 0x7f) << 0)
 #define FTSDC010_CCR_CLK_SD			(1 << 7) /* 0: MMC, 1: SD */
 #define FTSDC010_CCR_CLK_DIS			(1 << 8)
+#define FTSDC010_CCR_CLK_HISPD			(1 << 9) /* high speed */
 
 /* card type */
 #define FTSDC010_CARD_TYPE_SD			FTSDC010_CLOCK_REG_CARD_TYPE
 #define FTSDC010_CARD_TYPE_MMC			0x0
 
 /* 0x3c - bus width register */
-#define FTSDC010_BWR_SINGLE_BUS			(1 << 0)
-#define FTSDC010_BWR_WIDE_8_BUS			(1 << 1)
-#define FTSDC010_BWR_WIDE_4_BUS			(1 << 2)
-#define FTSDC010_BWR_WIDE_BUS_SUPPORT(x)	(((x) >> 3) & 0x3)
-#define FTSDC010_BWR_CARD_DETECT		(1 << 5)
-
-#define FTSDC010_BWR_1_BUS_SUPPORT		0x0
-#define FTSDC010_BWR_4_BUS_SUPPORT		0x1
-#define FTSDC010_BWR_8_BUS_SUPPORT		0x2
+#define FTSDC010_BWR_MODE_1BIT      (1 << 0) /* 1 bit mode enabled */
+#define FTSDC010_BWR_MODE_8BIT      (1 << 1) /* 8 bit mode enabled */
+#define FTSDC010_BWR_MODE_4BIT      (1 << 2) /* 4 bit mode enabled */
+#define FTSDC010_BWR_MODE_MASK      (7 << 0)
+#define FTSDC010_BWR_MODE_SHIFT     (0)
+#define FTSDC010_BWR_CAPS_1BIT      (0 << 3) /* 1 bits mode supported */
+#define FTSDC010_BWR_CAPS_4BIT      (1 << 3) /* 1,4 bits mode supported */
+#define FTSDC010_BWR_CAPS_8BIT      (2 << 3) /* 1,4,8 bits mode supported */
+#define FTSDC010_BWR_CAPS_MASK      (3 << 3)
+#define FTSDC010_BWR_CAPS_SHIFT     (3)
+#define FTSDC010_BWR_CARD_DETECT    (1 << 5)
 
 /* 0x44 or 0x9c - feature register */
 #define FTSDC010_FEATURE_FIFO_DEPTH(x)		(((x) >> 0) & 0xff)
diff --git a/include/fdt.h b/include/fdt.h
index f9612ed..526aedb 100644
--- a/include/fdt.h
+++ b/include/fdt.h
@@ -1,5 +1,56 @@
 #ifndef _FDT_H
 #define _FDT_H
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ * Copyright 2012 Kim Phillips, Freescale Semiconductor.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef __ASSEMBLY__
 
@@ -57,6 +108,4 @@
 #define FDT_V16_SIZE	FDT_V3_SIZE
 #define FDT_V17_SIZE	(FDT_V16_SIZE + sizeof(fdt32_t))
 
-/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
-#define FDT_RAMDISK_OVERHEAD	0x80
 #endif /* _FDT_H */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 2cccc35..8f07a67 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -78,11 +78,9 @@
 int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
 #endif
 
-#ifdef CONFIG_OF_BOARD_SETUP
 void ft_board_setup(void *blob, bd_t *bd);
 void ft_cpu_setup(void *blob, bd_t *bd);
 void ft_pci_setup(void *blob, bd_t *bd);
-#endif
 
 void set_working_fdt_addr(void *addr);
 int fdt_resize(void *blob);
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 4e8032b..1ece612 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -93,6 +93,7 @@
 	COMPAT_GENERIC_SPI_FLASH,	/* Generic SPI Flash chip */
 	COMPAT_MAXIM_98095_CODEC,	/* MAX98095 Codec */
 	COMPAT_INFINEON_SLB9635_TPM,	/* Infineon SLB9635 TPM */
+	COMPAT_INFINEON_SLB9645_TPM,	/* Infineon SLB9645 TPM */
 
 	COMPAT_COUNT,
 };
diff --git a/include/fm_eth.h b/include/fm_eth.h
index 495765b..8fcf172 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -88,7 +88,7 @@
 
 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
 {									\
-	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)	\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR)	\
 	.index		= idx,						\
 	.num		= n - 1,					\
 	.type		= FM_ETH_10G_E,					\
@@ -96,7 +96,7 @@
 	.rx_port_id	= RX_PORT_10G_BASE + n - 1,			\
 	.tx_port_id	= TX_PORT_10G_BASE + n - 1,			\
 	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
-				offsetof(struct ccsr_fman, memac[n-1]),\
+				offsetof(struct ccsr_fman, memac[n-1+8]),\
 }
 #else
 #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
diff --git a/include/fpga.h b/include/fpga.h
index 30a4e6a..38e9018 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -31,16 +31,6 @@
 #define CONFIG_MAX_FPGA_DEVICES		5
 #endif
 
-/* CONFIG_FPGA bit assignments */
-#define CONFIG_SYS_FPGA_MAN(x)		(x)
-#define CONFIG_SYS_FPGA_DEV(x)		((x) << 8 )
-#define CONFIG_SYS_FPGA_IF(x)		((x) << 16 )
-
-/* FPGA Manufacturer bits in CONFIG_FPGA */
-#define CONFIG_SYS_FPGA_XILINX		CONFIG_SYS_FPGA_MAN( 0x1 )
-#define CONFIG_SYS_FPGA_ALTERA		CONFIG_SYS_FPGA_MAN( 0x2 )
-
-
 /* fpga_xxxx function return value definitions */
 #define FPGA_SUCCESS		0
 #define FPGA_FAIL		-1
@@ -68,7 +58,10 @@
 extern int fpga_add(fpga_type devtype, void *desc);
 extern int fpga_count(void);
 extern int fpga_load(int devnum, const void *buf, size_t bsize);
+extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size);
 extern int fpga_dump(int devnum, const void *buf, size_t bsize);
 extern int fpga_info(int devnum);
+extern const fpga_desc *const fpga_validate(int devnum, const void *buf,
+					    size_t bsize, char *fn);
 
 #endif	/* _FPGA_H_ */
diff --git a/include/fuse.h b/include/fuse.h
new file mode 100644
index 0000000..b964137
--- /dev/null
+++ b/include/fuse.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2009-2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on the mpc512x iim code:
+ * Copyright 2008 Silicon Turnkey Express, Inc.
+ * Martha Marx <mmarx@silicontkx.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FUSE_H_
+#define _FUSE_H_
+
+/*
+ * Read/Sense/Program/Override interface:
+ *   bank:    Fuse bank
+ *   word:    Fuse word within the bank
+ *   val:     Value to read/write
+ *
+ *   Returns: 0 on success, not 0 on failure
+ */
+int fuse_read(u32 bank, u32 word, u32 *val);
+int fuse_sense(u32 bank, u32 word, u32 *val);
+int fuse_prog(u32 bank, u32 word, u32 val);
+int fuse_override(u32 bank, u32 word, u32 val);
+
+#endif	/* _FUSE_H_ */
diff --git a/include/hash.h b/include/hash.h
index 2dbbd9b..c402067 100644
--- a/include/hash.h
+++ b/include/hash.h
@@ -71,4 +71,26 @@
 int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag,
 		 int argc, char * const argv[]);
 
+/**
+ * hash_block() - Hash a block according to the requested algorithm
+ *
+ * The caller probably knows the hash length for the chosen algorithm, but
+ * in order to provide a general interface, and output_size parameter is
+ * provided.
+ *
+ * @algo_name:		Hash algorithm to use
+ * @data:		Data to hash
+ * @len:		Lengh of data to hash in bytes
+ * @output:		Place to put hash value
+ * @output_size:	On entry, pointer to the number of bytes available in
+ *			output. On exit, pointer to the number of bytes used.
+ *			If NULL, then it is assumed that the caller has
+ *			allocated enough space for the hash. This is possible
+ *			since the caller is selecting the algorithm.
+ * @return 0 if ok, -ve on error: -EPROTONOSUPPORT for an unknown algorithm,
+ * -ENOSPC if the output buffer is not large enough.
+ */
+int hash_block(const char *algo_name, const void *data, unsigned int len,
+	       uint8_t *output, int *output_size);
+
 #endif
diff --git a/include/image.h b/include/image.h
index 4ad0e6b..8ccc00b 100644
--- a/include/image.h
+++ b/include/image.h
@@ -36,6 +36,9 @@
 #include "compiler.h"
 #include <asm/byteorder.h>
 
+/* Define this to avoid #ifdefs later on */
+struct lmb;
+
 #ifdef USE_HOSTCC
 
 /* new uImage format support enabled on host */
@@ -43,19 +46,79 @@
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
 
+#define IMAGE_ENABLE_IGNORE	0
+#define IMAGE_INDENT_STRING	""
+
 #else
 
 #include <lmb.h>
 #include <asm/u-boot.h>
 #include <command.h>
 
+/* Take notice of the 'ignore' property for hashes */
+#define IMAGE_ENABLE_IGNORE	1
+#define IMAGE_INDENT_STRING	"   "
+
 #endif /* USE_HOSTCC */
 
 #if defined(CONFIG_FIT)
 #include <libfdt.h>
 #include <fdt_support.h>
-#define CONFIG_MD5		/* FIT images need MD5 support */
-#define CONFIG_SHA1		/* and SHA1 */
+# ifdef CONFIG_SPL_BUILD
+#  ifdef CONFIG_SPL_CRC32_SUPPORT
+#   define IMAGE_ENABLE_CRC32	1
+#  endif
+#  ifdef CONFIG_SPL_MD5_SUPPORT
+#   define IMAGE_ENABLE_MD5	1
+#  endif
+#  ifdef CONFIG_SPL_SHA1_SUPPORT
+#   define IMAGE_ENABLE_SHA1	1
+#  endif
+# else
+#  define CONFIG_CRC32		/* FIT images need CRC32 support */
+#  define CONFIG_MD5		/* and MD5 */
+#  define CONFIG_SHA1		/* and SHA1 */
+#  define IMAGE_ENABLE_CRC32	1
+#  define IMAGE_ENABLE_MD5	1
+#  define IMAGE_ENABLE_SHA1	1
+# endif
+
+#ifndef IMAGE_ENABLE_CRC32
+#define IMAGE_ENABLE_CRC32	0
+#endif
+
+#ifndef IMAGE_ENABLE_MD5
+#define IMAGE_ENABLE_MD5	0
+#endif
+
+#ifndef IMAGE_ENABLE_SHA1
+#define IMAGE_ENABLE_SHA1	0
+#endif
+
+#endif /* CONFIG_FIT */
+
+#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
+# define IMAGE_ENABLE_RAMDISK_HIGH	1
+#else
+# define IMAGE_ENABLE_RAMDISK_HIGH	0
+#endif
+
+#ifdef CONFIG_OF_LIBFDT
+# define IMAGE_ENABLE_OF_LIBFDT	1
+#else
+# define IMAGE_ENABLE_OF_LIBFDT	0
+#endif
+
+#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
+# define IMAGE_BOOT_GET_CMDLINE		1
+#else
+# define IMAGE_BOOT_GET_CMDLINE		0
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+# define IMAAGE_OF_BOARD_SETUP		1
+#else
+# define IMAAGE_OF_BOARD_SETUP		0
 #endif
 
 /*
@@ -244,9 +307,7 @@
 
 	ulong		rd_start, rd_end;/* ramdisk start/end */
 
-#ifdef CONFIG_OF_LIBFDT
 	char		*ft_addr;	/* flat dev tree address */
-#endif
 	ulong		ft_len;		/* length of flat device tree */
 
 	ulong		initrd_start;
@@ -333,34 +394,105 @@
 int genimg_get_comp_id(const char *name);
 void genimg_print_size(uint32_t size);
 
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || \
+	defined(USE_HOSTCC)
+#define IMAGE_ENABLE_TIMESTAMP 1
+#else
+#define IMAGE_ENABLE_TIMESTAMP 0
+#endif
+void genimg_print_time(time_t timestamp);
+
+/* What to do with a image load address ('load = <> 'in the FIT) */
+enum fit_load_op {
+	FIT_LOAD_IGNORED,	/* Ignore load address */
+	FIT_LOAD_OPTIONAL,	/* Can be provided, but optional */
+	FIT_LOAD_REQUIRED,	/* Must be provided */
+};
+
 #ifndef USE_HOSTCC
 /* Image format types, returned by _get_format() routine */
 #define IMAGE_FORMAT_INVALID	0x00
 #define IMAGE_FORMAT_LEGACY	0x01	/* legacy image_header based format */
 #define IMAGE_FORMAT_FIT	0x02	/* new, libfdt based format */
 
-int genimg_get_format(void *img_addr);
+int genimg_get_format(const void *img_addr);
 int genimg_has_config(bootm_headers_t *images);
 ulong genimg_get_image(ulong img_addr);
 
 int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
 		uint8_t arch, ulong *rd_start, ulong *rd_end);
 
+/**
+ * fit_image_load() - load an image from a FIT
+ *
+ * This deals with all aspects of loading an image from a FIT, including
+ * selecting the right image based on configuration, verifying it, printing
+ * out progress messages, checking the type/arch/os and optionally copying it
+ * to the right load address.
+ *
+ * @param images	Boot images structure
+ * @param prop_name	Property name to look up (FIT_..._PROP)
+ * @param addr		Address of FIT in memory
+ * @param fit_unamep	On entry this is the requested image name
+ *			(e.g. "kernel@1") or NULL to use the default. On exit
+ *			points to the selected image name
+ * @param fit_uname_config	Requested configuration name, or NULL for the
+ *			default
+ * @param arch		Expected architecture (IH_ARCH_...)
+ * @param image_type	Required image type (IH_TYPE_...). If this is
+ *			IH_TYPE_KERNEL then we allow IH_TYPE_KERNEL_NOLOAD
+ *			also.
+ * @param bootstage_id	ID of starting bootstage to use for progress updates.
+ *			This will be added to the BOOTSTAGE_SUB values when
+ *			calling bootstage_mark()
+ * @param load_op	Decribes what to do with the load address
+ * @param datap		Returns address of loaded image
+ * @param lenp		Returns length of loaded image
+ */
+int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr,
+		   const char **fit_unamep, const char *fit_uname_config,
+		   int arch, int image_type, int bootstage_id,
+		   enum fit_load_op load_op, ulong *datap, ulong *lenp);
 
-#ifdef CONFIG_OF_LIBFDT
-int boot_get_fdt(int flag, int argc, char * const argv[],
-		bootm_headers_t *images, char **of_flat_tree, ulong *of_size);
+/**
+ * fit_get_node_from_config() - Look up an image a FIT by type
+ *
+ * This looks in the selected conf@ node (images->fit_uname_cfg) for a
+ * particular image type (e.g. "kernel") and then finds the image that is
+ * referred to.
+ *
+ * For example, for something like:
+ *
+ * images {
+ *	kernel@1 {
+ *		...
+ *	};
+ * };
+ * configurations {
+ *	conf@1 {
+ *		kernel = "kernel@1";
+ *	};
+ * };
+ *
+ * the function will return the node offset of the kernel@1 node, assuming
+ * that conf@1 is the chosen configuration.
+ *
+ * @param images	Boot images structure
+ * @param prop_name	Property name to look up (FIT_..._PROP)
+ * @param addr		Address of FIT in memory
+ */
+int fit_get_node_from_config(bootm_headers_t *images, const char *prop_name,
+			ulong addr);
+
+int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
+		 bootm_headers_t *images,
+		 char **of_flat_tree, ulong *of_size);
 void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob);
 int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size);
-#endif
 
-#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
 int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
 		  ulong *initrd_start, ulong *initrd_end);
-#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */
-#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
 int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end);
-#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */
 #ifdef CONFIG_SYS_BOOT_GET_KBD
 int boot_get_kbd(struct lmb *lmb, bd_t **kbd);
 #endif /* CONFIG_SYS_BOOT_GET_KBD */
@@ -502,6 +634,31 @@
 }
 #endif /* USE_HOSTCC */
 
+/**
+ * Set up properties in the FDT
+ *
+ * This sets up properties in the FDT that is to be passed to linux.
+ *
+ * @images:	Images information
+ * @blob:	FDT to update
+ * @of_size:	Size of the FDT
+ * @lmb:	Points to logical memory block structure
+ * @return 0 if ok, <0 on failure
+ */
+int image_setup_libfdt(bootm_headers_t *images, void *blob,
+		       int of_size, struct lmb *lmb);
+
+/**
+ * Set up the FDT to use for booting a kernel
+ *
+ * This performs ramdisk setup, sets up the FDT if required, and adds
+ * paramters to the FDT if libfdt is available.
+ *
+ * @param images	Images information
+ * @return 0 if ok, <0 on failure
+ */
+int image_setup_linux(bootm_headers_t *images);
+
 /*******************************************************************/
 /* New uImage format specific code (prefixed with fit_) */
 /*******************************************************************/
@@ -543,7 +700,6 @@
 
 void fit_print_contents(const void *fit);
 void fit_image_print(const void *fit, int noffset, const char *p);
-void fit_image_print_hash(const void *fit, int noffset, const char *p);
 
 /**
  * fit_get_end - get FIT image size
@@ -599,18 +755,20 @@
 int fit_image_hash_get_algo(const void *fit, int noffset, char **algo);
 int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value,
 				int *value_len);
-#ifndef USE_HOSTCC
-int fit_image_hash_get_ignore(const void *fit, int noffset, int *ignore);
-#endif
 
 int fit_set_timestamp(void *fit, int noffset, time_t timestamp);
-int fit_set_hashes(void *fit);
-int fit_image_set_hashes(void *fit, int image_noffset);
-int fit_image_hash_set_value(void *fit, int noffset, uint8_t *value,
-				int value_len);
 
-int fit_image_check_hashes(const void *fit, int noffset);
-int fit_all_image_check_hashes(const void *fit);
+/**
+ * fit_add_verification_data() - Calculate and add hashes to FIT
+ *
+ * @fit:	Fit image to process
+ * @return 0 if ok, <0 for error
+ */
+int fit_add_verification_data(void *fit);
+
+int fit_image_verify(const void *fit, int noffset);
+int fit_config_verify(const void *fit, int conf_noffset);
+int fit_all_image_verify(const void *fit);
 int fit_image_check_os(const void *fit, int noffset, uint8_t os);
 int fit_image_check_arch(const void *fit, int noffset, uint8_t arch);
 int fit_image_check_type(const void *fit, int noffset, uint8_t type);
@@ -619,18 +777,58 @@
 
 int fit_conf_find_compat(const void *fit, const void *fdt);
 int fit_conf_get_node(const void *fit, const char *conf_uname);
-int fit_conf_get_kernel_node(const void *fit, int noffset);
-int fit_conf_get_ramdisk_node(const void *fit, int noffset);
-int fit_conf_get_fdt_node(const void *fit, int noffset);
+
+/**
+ * fit_conf_get_prop_node() - Get node refered to by a configuration
+ * @fit:	FIT to check
+ * @noffset:	Offset of conf@xxx node to check
+ * @prop_name:	Property to read from the conf node
+ *
+ * The conf@ nodes contain references to other nodes, using properties
+ * like 'kernel = "kernel@1"'. Given such a property name (e.g. "kernel"),
+ * return the offset of the node referred to (e.g. offset of node
+ * "/images/kernel@1".
+ */
+int fit_conf_get_prop_node(const void *fit, int noffset,
+		const char *prop_name);
 
 void fit_conf_print(const void *fit, int noffset, const char *p);
 
-#ifndef USE_HOSTCC
+int fit_check_ramdisk(const void *fit, int os_noffset,
+		uint8_t arch, int verify);
+
+int calculate_hash(const void *data, int data_len, const char *algo,
+			uint8_t *value, int *value_len);
+
+/*
+ * At present we only support verification on the device
+ */
+#if defined(CONFIG_FIT_SIGNATURE)
+# ifdef USE_HOSTCC
+#  define IMAGE_ENABLE_VERIFY	0
+#else
+#  define IMAGE_ENABLE_VERIFY	1
+# endif
+#else
+# define IMAGE_ENABLE_VERIFY	0
+#endif
+
+#ifdef USE_HOSTCC
+# define gd_fdt_blob()		NULL
+#else
+# define gd_fdt_blob()		(gd->fdt_blob)
+#endif
+
+#ifdef CONFIG_FIT_BEST_MATCH
+#define IMAGE_ENABLE_BEST_MATCH	1
+#else
+#define IMAGE_ENABLE_BEST_MATCH	0
+#endif
+
 static inline int fit_image_check_target_arch(const void *fdt, int node)
 {
 	return fit_image_check_arch(fdt, node, IH_ARCH_DEFAULT);
 }
-#endif /* USE_HOSTCC */
 
 #ifdef CONFIG_FIT_VERBOSE
 #define fit_unsupported(msg)	printf("! %s:%d " \
diff --git a/include/lattice.h b/include/lattice.h
index 6a2cf93..49871da 100644
--- a/include/lattice.h
+++ b/include/lattice.h
@@ -278,9 +278,6 @@
 	char		*desc;	/* description string */
 } Lattice_desc;			/* end, typedef Altera_desc */
 
-/* Lattice Model Type */
-#define CONFIG_SYS_XP2		CONFIG_SYS_FPGA_DEV(0x1)
-
 /* Board specific implementation specific function types */
 typedef void (*Lattice_jtag_init)(void);
 typedef void (*Lattice_jtag_set_tdi)(int v);
diff --git a/include/libfdt.h b/include/libfdt.h
index fc7f75b..c5ec2ac 100644
--- a/include/libfdt.h
+++ b/include/libfdt.h
@@ -136,6 +136,28 @@
 
 int fdt_next_node(const void *fdt, int offset, int *depth);
 
+/**
+ * fdt_first_subnode() - get offset of first direct subnode
+ *
+ * @fdt:	FDT blob
+ * @offset:	Offset of node to check
+ * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none
+ */
+int fdt_first_subnode(const void *fdt, int offset);
+
+/**
+ * fdt_next_subnode() - get offset of next direct subnode
+ *
+ * After first calling fdt_first_subnode(), call this function repeatedly to
+ * get direct subnodes of a parent node.
+ *
+ * @fdt:	FDT blob
+ * @offset:	Offset of previous subnode
+ * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more
+ * subnodes
+ */
+int fdt_next_subnode(const void *fdt, int offset);
+
 /**********************************************************************/
 /* General functions                                                  */
 /**********************************************************************/
@@ -582,7 +604,7 @@
  * value of the property named 'name' in the node /aliases.
  *
  * returns:
- *	a pointer to the expansion of the alias named 'name', of it exists
+ *	a pointer to the expansion of the alias named 'name', if it exists
  *	NULL, if the given alias or the /aliases node does not exist
  */
 const char *fdt_get_alias(const void *fdt, const char *name);
@@ -816,6 +838,20 @@
 int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
 				  const char *compatible);
 
+/**
+ * fdt_stringlist_contains - check a string list property for a string
+ * @strlist: Property containing a list of strings to check
+ * @listlen: Length of property
+ * @str: String to search for
+ *
+ * This is a utility function provided for convenience. The list contains
+ * one or more strings, each terminated by \0, as is found in a device tree
+ * "compatible" property.
+ *
+ * @return: 1 if the string is found in the list, 0 not found, or invalid list
+ */
+int fdt_stringlist_contains(const char *strlist, int listlen, const char *str);
+
 /**********************************************************************/
 /* Write-in-place functions                                           */
 /**********************************************************************/
diff --git a/include/libfdt_env.h b/include/libfdt_env.h
index 3e3defc..0821258 100644
--- a/include/libfdt_env.h
+++ b/include/libfdt_env.h
@@ -35,4 +35,7 @@
 #define fdt64_to_cpu(x)		be64_to_cpu(x)
 #define cpu_to_fdt64(x)		cpu_to_be64(x)
 
+/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
+#define FDT_RAMDISK_OVERHEAD	0x80
+
 #endif /* _LIBFDT_ENV_H */
diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h
new file mode 100644
index 0000000..a61d956
--- /dev/null
+++ b/include/linux/bitrev.h
@@ -0,0 +1,23 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Based on bitrev from the Linux kernel, by Akinobu Mita
+ */
+
+#ifndef _LINUX_BITREV_H
+#define _LINUX_BITREV_H
+
+#include <linux/types.h>
+
+extern u8 const byte_rev_table[256];
+
+static inline u8 bitrev8(u8 byte)
+{
+	return byte_rev_table[byte];
+}
+
+u16 bitrev16(u16 in);
+u32 bitrev32(u32 in);
+
+#endif /* _LINUX_BITREV_H */
diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h
index 8cbcdae..71292b1a 100644
--- a/include/linux/mtd/bbm.h
+++ b/include/linux/mtd/bbm.h
@@ -81,32 +81,53 @@
 #define NAND_BBT_LASTBLOCK	0x00000010
 /* The bbt is at the given page, else we must scan for the bbt */
 #define NAND_BBT_ABSPAGE	0x00000020
-/* The bbt is at the given page, else we must scan for the bbt */
-#define NAND_BBT_SEARCH		0x00000040
 /* bbt is stored per chip on multichip devices */
 #define NAND_BBT_PERCHIP	0x00000080
 /* bbt has a version counter at offset veroffs */
 #define NAND_BBT_VERSION	0x00000100
 /* Create a bbt if none exists */
 #define NAND_BBT_CREATE		0x00000200
+/*
+ * Create an empty BBT with no vendor information. Vendor's information may be
+ * unavailable, for example, if the NAND controller has a different data and OOB
+ * layout or if this information is already purged. Must be used in conjunction
+ * with NAND_BBT_CREATE.
+ */
+#define NAND_BBT_CREATE_EMPTY	0x00000400
 /* Search good / bad pattern through all pages of a block */
-#define NAND_BBT_SCANALLPAGES	0x00000400
+#define NAND_BBT_SCANALLPAGES	0x00000800
 /* Scan block empty during good / bad block scan */
-#define NAND_BBT_SCANEMPTY	0x00000800
+#define NAND_BBT_SCANEMPTY	0x00001000
 /* Write bbt if neccecary */
-#define NAND_BBT_WRITE		0x00001000
+#define NAND_BBT_WRITE		0x00002000
 /* Read and write back block contents when writing bbt */
-#define NAND_BBT_SAVECONTENT	0x00002000
+#define NAND_BBT_SAVECONTENT	0x00004000
 /* Search good / bad pattern on the first and the second page */
-#define NAND_BBT_SCAN2NDPAGE	0x00004000
+#define NAND_BBT_SCAN2NDPAGE	0x00008000
 /* Search good / bad pattern on the last page of the eraseblock */
-#define NAND_BBT_SCANLASTPAGE	0x00008000
-/* Chip stores bad block marker on BOTH 1st and 6th bytes of OOB */
-#define NAND_BBT_SCANBYTE1AND6 0x00100000
-/* The nand_bbt_descr was created dynamicaly and must be freed */
-#define NAND_BBT_DYNAMICSTRUCT 0x00200000
-/* The bad block table does not OOB for marker */
-#define NAND_BBT_NO_OOB		0x00400000
+#define NAND_BBT_SCANLASTPAGE	0x00010000
+/*
+ * Use a flash based bad block table. By default, OOB identifier is saved in
+ * OOB area. This option is passed to the default bad block table function.
+ */
+#define NAND_BBT_USE_FLASH	0x00020000
+/*
+ * Do not store flash based bad block table marker in the OOB area; store it
+ * in-band.
+ */
+#define NAND_BBT_NO_OOB		0x00040000
+/*
+ * Do not write new bad block markers to OOB; useful, e.g., when ECC covers
+ * entire spare area. Must be used with NAND_BBT_USE_FLASH.
+ */
+#define NAND_BBT_NO_OOB_BBM	0x00080000
+
+/*
+ * Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr
+ * was allocated dynamicaly and must be freed in nand_release(). Has no meaning
+ * in nand_chip.bbt_options.
+ */
+#define NAND_BBT_DYNAMICSTRUCT	0x80000000
 
 /* The maximum number of blocks to scan for a bbt */
 #define NAND_BBT_SCAN_MAXBLOCKS	4
diff --git a/include/linux/mtd/docg4.h b/include/linux/mtd/docg4.h
new file mode 100644
index 0000000..982f5ad
--- /dev/null
+++ b/include/linux/mtd/docg4.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ */
+
+#ifndef __DOCG4_H__
+#define __DOCG4_H__
+
+#include <common.h>
+#include <linux/mtd/nand.h>
+
+extern int docg4_nand_init(struct mtd_info *mtd,
+			   struct nand_chip *nand, int devnum);
+
+/* SPL-related definitions */
+#define DOCG4_IPL_LOAD_BLOCK_COUNT 2  /* number of blocks that IPL loads */
+#define DOCG4_BLOCK_CAPACITY_SPL 0x10000 /* reliable mode; redundant pages */
+
+#define DOC_IOSPACE_DATA		0x0800
+
+/* register offsets */
+#define DOC_CHIPID			0x1000
+#define DOC_DEVICESELECT		0x100a
+#define DOC_ASICMODE			0x100c
+#define DOC_DATAEND			0x101e
+#define DOC_NOP				0x103e
+
+#define DOC_FLASHSEQUENCE		0x1032
+#define DOC_FLASHCOMMAND		0x1034
+#define DOC_FLASHADDRESS		0x1036
+#define DOC_FLASHCONTROL		0x1038
+#define DOC_ECCCONF0			0x1040
+#define DOC_ECCCONF1			0x1042
+#define DOC_HAMMINGPARITY		0x1046
+#define DOC_BCH_SYNDROM(idx)		(0x1048 + idx)
+
+#define DOC_ASICMODECONFIRM		0x1072
+#define DOC_CHIPID_INV			0x1074
+#define DOC_POWERMODE			0x107c
+
+#define DOCG4_MYSTERY_REG		0x1050
+
+/* apparently used only to write oob bytes 6 and 7 */
+#define DOCG4_OOB_6_7			0x1052
+
+/* DOC_FLASHSEQUENCE register commands */
+#define DOC_SEQ_RESET			0x00
+#define DOCG4_SEQ_PAGE_READ		0x03
+#define DOCG4_SEQ_FLUSH			0x29
+#define DOCG4_SEQ_PAGEWRITE		0x16
+#define DOCG4_SEQ_PAGEPROG		0x1e
+#define DOCG4_SEQ_BLOCKERASE		0x24
+
+/* DOC_FLASHCOMMAND register commands */
+#define DOCG4_CMD_PAGE_READ             0x00
+#define DOC_CMD_ERASECYCLE2		0xd0
+#define DOCG4_CMD_FLUSH                 0x70
+#define DOCG4_CMD_READ2                 0x30
+#define DOC_CMD_PROG_BLOCK_ADDR		0x60
+#define DOCG4_CMD_PAGEWRITE		0x80
+#define DOC_CMD_PROG_CYCLE2		0x10
+#define DOC_CMD_RESET			0xff
+
+/* DOC_POWERMODE register bits */
+#define DOC_POWERDOWN_READY		0x80
+
+/* DOC_FLASHCONTROL register bits */
+#define DOC_CTRL_CE			0x10
+#define DOC_CTRL_UNKNOWN		0x40
+#define DOC_CTRL_FLASHREADY		0x01
+
+/* DOC_ECCCONF0 register bits */
+#define DOC_ECCCONF0_READ_MODE		0x8000
+#define DOC_ECCCONF0_UNKNOWN		0x2000
+#define DOC_ECCCONF0_ECC_ENABLE	        0x1000
+#define DOC_ECCCONF0_DATA_BYTES_MASK	0x07ff
+
+/* DOC_ECCCONF1 register bits */
+#define DOC_ECCCONF1_BCH_SYNDROM_ERR	0x80
+#define DOC_ECCCONF1_ECC_ENABLE         0x07
+#define DOC_ECCCONF1_PAGE_IS_WRITTEN	0x20
+
+/* DOC_ASICMODE register bits */
+#define DOC_ASICMODE_RESET		0x00
+#define DOC_ASICMODE_NORMAL		0x01
+#define DOC_ASICMODE_POWERDOWN		0x02
+#define DOC_ASICMODE_MDWREN		0x04
+#define DOC_ASICMODE_BDETCT_RESET	0x08
+#define DOC_ASICMODE_RSTIN_RESET	0x10
+#define DOC_ASICMODE_RAM_WE		0x20
+
+/* good status values read after read/write/erase operations */
+#define DOCG4_PROGSTATUS_GOOD          0x51
+#define DOCG4_PROGSTATUS_GOOD_2        0xe0
+
+/*
+ * On read operations (page and oob-only), the first byte read from I/O reg is a
+ * status.  On error, it reads 0x73; otherwise, it reads either 0x71 (first read
+ * after reset only) or 0x51, so bit 1 is presumed to be an error indicator.
+ */
+#define DOCG4_READ_ERROR           0x02 /* bit 1 indicates read error */
+
+/* anatomy of the device */
+#define DOCG4_CHIP_SIZE        0x8000000
+#define DOCG4_PAGE_SIZE        0x200
+#define DOCG4_PAGES_PER_BLOCK  0x200
+#define DOCG4_BLOCK_SIZE       (DOCG4_PAGES_PER_BLOCK * DOCG4_PAGE_SIZE)
+#define DOCG4_NUMBLOCKS        (DOCG4_CHIP_SIZE / DOCG4_BLOCK_SIZE)
+#define DOCG4_OOB_SIZE         0x10
+#define DOCG4_CHIP_SHIFT       27    /* log_2(DOCG4_CHIP_SIZE) */
+#define DOCG4_PAGE_SHIFT       9     /* log_2(DOCG4_PAGE_SIZE) */
+#define DOCG4_ERASE_SHIFT      18    /* log_2(DOCG4_BLOCK_SIZE) */
+
+/* all but the last byte is included in ecc calculation */
+#define DOCG4_BCH_SIZE         (DOCG4_PAGE_SIZE + DOCG4_OOB_SIZE - 1)
+
+#define DOCG4_USERDATA_LEN     520 /* 512 byte page plus 8 oob avail to user */
+
+/* expected values from the ID registers */
+#define DOCG4_IDREG1_VALUE     0x0400
+#define DOCG4_IDREG2_VALUE     0xfbff
+
+/* primitive polynomial used to build the Galois field used by hw ecc gen */
+#define DOCG4_PRIMITIVE_POLY   0x4443
+
+#define DOCG4_M                14  /* Galois field is of order 2^14 */
+#define DOCG4_T                4   /* BCH alg corrects up to 4 bit errors */
+
+#define DOCG4_FACTORY_BBT_PAGE 16 /* page where read-only factory bbt lives */
+
+#endif	/* __DOCG4_H__ */
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 141c960..6f44abd 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -9,7 +9,8 @@
 
 #include <linux/types.h>
 #include <div64.h>
-#include <linux/mtd/mtd-abi.h>
+#include <mtd/mtd-abi.h>
+#include <asm/errno.h>
 
 #define MTD_CHAR_MAJOR 90
 #define MTD_BLOCK_MAJOR 31
@@ -65,22 +66,6 @@
 	unsigned long *lockmap;		/* If keeping bitmap of locks */
 };
 
-/*
- * oob operation modes
- *
- * MTD_OOB_PLACE:	oob data are placed at the given offset
- * MTD_OOB_AUTO:	oob data are automatically placed at the free areas
- *			which are defined by the ecclayout
- * MTD_OOB_RAW:		mode to read raw data+oob in one chunk. The oob data
- *			is inserted into the data. Thats a raw image of the
- *			flash contents.
- */
-typedef enum {
-	MTD_OOB_PLACE,
-	MTD_OOB_AUTO,
-	MTD_OOB_RAW,
-} mtd_oob_mode_t;
-
 /**
  * struct mtd_oob_ops - oob operation operands
  * @mode:	operation mode
@@ -92,7 +77,7 @@
  * @ooblen:	number of oob bytes to write/read
  * @oobretlen:	number of oob bytes written/read
  * @ooboffs:	offset of oob data in the oob area (only relevant when
- *		mode = MTD_OOB_PLACE)
+ *		mode = MTD_OPS_PLACE_OOB or MTD_OPS_RAW)
  * @datbuf:	data buffer - if NULL only oob data are read/written
  * @oobbuf:	oob data buffer
  *
@@ -101,7 +86,7 @@
  * OOB area.
  */
 struct mtd_oob_ops {
-	mtd_oob_mode_t	mode;
+	unsigned int	mode;
 	size_t		len;
 	size_t		retlen;
 	size_t		ooblen;
@@ -133,13 +118,25 @@
 	u_int32_t oobsize;   /* Amount of OOB data per block (e.g. 16) */
 	u_int32_t oobavail;  /* Available OOB bytes per block */
 
+	/*
+	 * read ops return -EUCLEAN if max number of bitflips corrected on any
+	 * one region comprising an ecc step equals or exceeds this value.
+	 * Settable by driver, else defaults to ecc_strength.  User can override
+	 * in sysfs.  N.B. The meaning of the -EUCLEAN return code has changed;
+	 * see Documentation/ABI/testing/sysfs-class-mtd for more detail.
+	 */
+	unsigned int bitflip_threshold;
+
 	/* Kernel-only stuff starts here. */
 	const char *name;
 	int index;
 
-	/* ecc layout structure pointer - read only ! */
+	/* ECC layout structure pointer - read only! */
 	struct nand_ecclayout *ecclayout;
 
+	/* max number of correctible bit errors per ecc step */
+	unsigned int ecc_strength;
+
 	/* Data for variable erase regions. If numeraseregions is zero,
 	 * it means that the whole device has erasesize as given above.
 	 */
@@ -147,25 +144,17 @@
 	struct mtd_erase_region_info *eraseregions;
 
 	/*
-	 * Erase is an asynchronous operation.  Device drivers are supposed
-	 * to call instr->callback() whenever the operation completes, even
-	 * if it completes with a failure.
-	 * Callers are supposed to pass a callback function and wait for it
-	 * to be called before writing to the block.
+	 * Do not call via these pointers, use corresponding mtd_*()
+	 * wrappers instead.
 	 */
-	int (*erase) (struct mtd_info *mtd, struct erase_info *instr);
-
-	/* This stuff for eXecute-In-Place */
-	/* phys is optional and may be set to NULL */
-	int (*point) (struct mtd_info *mtd, loff_t from, size_t len,
+	int (*_erase) (struct mtd_info *mtd, struct erase_info *instr);
+	int (*_point) (struct mtd_info *mtd, loff_t from, size_t len,
 			size_t *retlen, void **virt, phys_addr_t *phys);
-
-	/* We probably shouldn't allow XIP if the unpoint isn't a NULL */
-	void (*unpoint) (struct mtd_info *mtd, loff_t from, size_t len);
-
-
-	int (*read) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
-	int (*write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf);
+	void (*_unpoint) (struct mtd_info *mtd, loff_t from, size_t len);
+	int (*_read) (struct mtd_info *mtd, loff_t from, size_t len,
+		     size_t *retlen, u_char *buf);
+	int (*_write) (struct mtd_info *mtd, loff_t to, size_t len,
+		      size_t *retlen, const u_char *buf);
 
 	/* In blackbox flight recorder like scenarios we want to make successful
 	   writes in interrupt context. panic_write() is only intended to be
@@ -174,24 +163,35 @@
 	   longer, this function can break locks and delay to ensure the write
 	   succeeds (but not sleep). */
 
-	int (*panic_write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf);
+	int (*_panic_write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf);
 
-	int (*read_oob) (struct mtd_info *mtd, loff_t from,
+	int (*_read_oob) (struct mtd_info *mtd, loff_t from,
 			 struct mtd_oob_ops *ops);
-	int (*write_oob) (struct mtd_info *mtd, loff_t to,
+	int (*_write_oob) (struct mtd_info *mtd, loff_t to,
 			 struct mtd_oob_ops *ops);
-
+	int (*_get_fact_prot_info) (struct mtd_info *mtd, struct otp_info *buf,
+				   size_t len);
+	int (*_read_fact_prot_reg) (struct mtd_info *mtd, loff_t from,
+				   size_t len, size_t *retlen, u_char *buf);
+	int (*_get_user_prot_info) (struct mtd_info *mtd, struct otp_info *buf,
+				   size_t len);
+	int (*_read_user_prot_reg) (struct mtd_info *mtd, loff_t from,
+				   size_t len, size_t *retlen, u_char *buf);
+	int (*_write_user_prot_reg) (struct mtd_info *mtd, loff_t to, size_t len,
+				    size_t *retlen, u_char *buf);
+	int (*_lock_user_prot_reg) (struct mtd_info *mtd, loff_t from,
+				   size_t len);
+	void (*_sync) (struct mtd_info *mtd);
+	int (*_lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
+	int (*_unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
+	int (*_block_isbad) (struct mtd_info *mtd, loff_t ofs);
+	int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs);
 	/*
-	 * Methods to access the protection register area, present in some
-	 * flash devices. The user data is one time programmable but the
-	 * factory data is read only.
+	 * If the driver is something smart, like UBI, it may need to maintain
+	 * its own reference counting. The below functions are only for driver.
 	 */
-	int (*get_fact_prot_info) (struct mtd_info *mtd, struct otp_info *buf, size_t len);
-	int (*read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
-	int (*get_user_prot_info) (struct mtd_info *mtd, struct otp_info *buf, size_t len);
-	int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
-	int (*write_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
-	int (*lock_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len);
+	int (*_get_device) (struct mtd_info *mtd);
+	void (*_put_device) (struct mtd_info *mtd);
 
 /* XXX U-BOOT XXX */
 #if 0
@@ -201,18 +201,6 @@
 	*/
 	int (*writev) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, size_t *retlen);
 #endif
-
-	/* Sync */
-	void (*sync) (struct mtd_info *mtd);
-
-	/* Chip-supported device locking */
-	int (*lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
-	int (*unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
-
-	/* Bad block management functions */
-	int (*block_isbad) (struct mtd_info *mtd, loff_t ofs);
-	int (*block_markbad) (struct mtd_info *mtd, loff_t ofs);
-
 /* XXX U-BOOT XXX */
 #if 0
 	struct notifier_block reboot_notifier;  /* default mode before reboot */
@@ -227,15 +215,59 @@
 
 	struct module *owner;
 	int usecount;
-
-	/* If the driver is something smart, like UBI, it may need to maintain
-	 * its own reference counting. The below functions are only for driver.
-	 * The driver may register its callbacks. These callbacks are not
-	 * supposed to be called by MTD users */
-	int (*get_device) (struct mtd_info *mtd);
-	void (*put_device) (struct mtd_info *mtd);
 };
 
+int mtd_erase(struct mtd_info *mtd, struct erase_info *instr);
+int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+	     u_char *buf);
+int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+	      const u_char *buf);
+int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+		    const u_char *buf);
+
+int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops);
+
+static inline int mtd_write_oob(struct mtd_info *mtd, loff_t to,
+				struct mtd_oob_ops *ops)
+{
+	ops->retlen = ops->oobretlen = 0;
+	if (!mtd->_write_oob)
+		return -EOPNOTSUPP;
+	if (!(mtd->flags & MTD_WRITEABLE))
+		return -EROFS;
+	return mtd->_write_oob(mtd, to, ops);
+}
+
+int mtd_get_fact_prot_info(struct mtd_info *mtd, struct otp_info *buf,
+			   size_t len);
+int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+			   size_t *retlen, u_char *buf);
+int mtd_get_user_prot_info(struct mtd_info *mtd, struct otp_info *buf,
+			   size_t len);
+int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+			   size_t *retlen, u_char *buf);
+int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len,
+			    size_t *retlen, u_char *buf);
+int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len);
+
+/* XXX U-BOOT XXX */
+#if 0
+int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
+	       unsigned long count, loff_t to, size_t *retlen);
+#endif
+
+static inline void mtd_sync(struct mtd_info *mtd)
+{
+	if (mtd->_sync)
+		mtd->_sync(mtd);
+}
+
+int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs);
+int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs);
+
 static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd)
 {
 	do_div(sz, mtd->erasesize);
@@ -247,6 +279,16 @@
 	return do_div(sz, mtd->erasesize);
 }
 
+static inline int mtd_has_oob(const struct mtd_info *mtd)
+{
+	return mtd->_read_oob && mtd->_write_oob;
+}
+
+static inline int mtd_can_have_bb(const struct mtd_info *mtd)
+{
+	return !!mtd->_block_isbad;
+}
+
 	/* Kernel-side ioctl definitions */
 
 extern int add_mtd_device(struct mtd_info *mtd);
@@ -269,12 +311,6 @@
 
 extern void register_mtd_user (struct mtd_notifier *new);
 extern int unregister_mtd_user (struct mtd_notifier *old);
-
-int default_mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
-		       unsigned long count, loff_t to, size_t *retlen);
-
-int default_mtd_readv(struct mtd_info *mtd, struct kvec *vecs,
-		      unsigned long count, loff_t from, size_t *retlen);
 #endif
 
 #ifdef CONFIG_MTD_PARTITIONS
@@ -296,17 +332,34 @@
 #define MTD_DEBUG_LEVEL3	(3)	/* Noisy   */
 
 #ifdef CONFIG_MTD_DEBUG
+#define pr_debug(args...)	MTDDEBUG(MTD_DEBUG_LEVEL0, args)
 #define MTDDEBUG(n, args...)				\
 	do {						\
 		if (n <= CONFIG_MTD_DEBUG_VERBOSE)	\
 			printk(KERN_INFO args);		\
 	} while(0)
 #else /* CONFIG_MTD_DEBUG */
+#define pr_debug(args...)
 #define MTDDEBUG(n, args...)				\
 	do {						\
 		if (0)					\
 			printk(KERN_INFO args);		\
 	} while(0)
 #endif /* CONFIG_MTD_DEBUG */
+#define pr_info(args...)	MTDDEBUG(MTD_DEBUG_LEVEL0, args)
+#define pr_warn(args...)	MTDDEBUG(MTD_DEBUG_LEVEL0, args)
+#define pr_err(args...)		MTDDEBUG(MTD_DEBUG_LEVEL0, args)
+
+static inline int mtd_is_bitflip(int err) {
+	return err == -EUCLEAN;
+}
+
+static inline int mtd_is_eccerr(int err) {
+	return err == -EBADMSG;
+}
+
+static inline int mtd_is_bitflip_or_eccerr(int err) {
+	return mtd_is_bitflip(err) || mtd_is_eccerr(err);
+}
 
 #endif /* __MTD_MTD_H__ */
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 98bf255..2055584 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -46,7 +46,7 @@
  * is supported now. If you add a chip with bigger oobsize/page
  * adjust this accordingly.
  */
-#define NAND_MAX_OOBSIZE	576
+#define NAND_MAX_OOBSIZE	640
 #define NAND_MAX_PAGESIZE	8192
 
 /*
@@ -82,6 +82,8 @@
 #define NAND_CMD_READID		0x90
 #define NAND_CMD_ERASE2		0xd0
 #define NAND_CMD_PARAM		0xec
+#define NAND_CMD_GET_FEATURES	0xee
+#define NAND_CMD_SET_FEATURES	0xef
 #define NAND_CMD_RESET		0xff
 
 #define NAND_CMD_LOCK		0x2a
@@ -142,7 +144,7 @@
 #define NAND_ECC_READ		0
 /* Reset Hardware ECC for write */
 #define NAND_ECC_WRITE		1
-/* Enable Hardware ECC before syndrom is read back from flash */
+/* Enable Hardware ECC before syndrome is read back from flash */
 #define NAND_ECC_READSYN	2
 
 /* Bit mask for flags passed to do_nand_read_ecc */
@@ -153,9 +155,7 @@
  * Option constants for bizarre disfunctionality and real
  * features.
  */
-/* Chip can not auto increment pages */
-#define NAND_NO_AUTOINCR	0x00000001
-/* Buswitdh is 16 bit */
+/* Buswidth is 16 bit */
 #define NAND_BUSWIDTH_16	0x00000002
 /* Device supports partial programming without padding */
 #define NAND_NO_PADDING		0x00000004
@@ -179,12 +179,6 @@
  * This happens with the Renesas AG-AND chips, possibly others.
  */
 #define BBT_AUTO_REFRESH	0x00000080
-/*
- * Chip does not require ready check on read. true
- * for all large page devices, as they do not support
- * autoincrement.
- */
-#define NAND_NO_READRDY		0x00000100
 /* Chip does not allow subpage writes */
 #define NAND_NO_SUBPAGE_WRITE	0x00000200
 
@@ -202,34 +196,21 @@
 	(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
 
 /* Macros to identify the above */
-#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
 
 /* Non chip related options */
-/*
- * Use a flash based bad block table. OOB identifier is saved in OOB area.
- * This option is passed to the default bad block table function.
- */
-#define NAND_USE_FLASH_BBT	0x00010000
 /* This option skips the bbt scan during initialization. */
-#define NAND_SKIP_BBTSCAN	0x00020000
+#define NAND_SKIP_BBTSCAN	0x00010000
 /*
  * This option is defined if the board driver allocates its own buffers
  * (e.g. because it needs them DMA-coherent).
  */
-#define NAND_OWN_BUFFERS	0x00040000
+#define NAND_OWN_BUFFERS	0x00020000
 /* Chip may not exist, so silence any errors in scan */
-#define NAND_SCAN_SILENT_NODEV	0x00080000
-/*
- * If passed additionally to NAND_USE_FLASH_BBT then BBT code will not touch
- * the OOB area.
- */
-#define NAND_USE_FLASH_BBT_NO_OOB	0x00800000
-/* Create an empty BBT with no vendor information if the BBT is available */
-#define NAND_CREATE_EMPTY_BBT		0x01000000
+#define NAND_SCAN_SILENT_NODEV	0x00040000
 
 /* Options set by nand scan */
 /* bbt has already been read */
@@ -244,6 +225,21 @@
 /* Keep gcc happy */
 struct nand_chip;
 
+/* ONFI timing mode, used in both asynchronous and synchronous mode */
+#define ONFI_TIMING_MODE_0		(1 << 0)
+#define ONFI_TIMING_MODE_1		(1 << 1)
+#define ONFI_TIMING_MODE_2		(1 << 2)
+#define ONFI_TIMING_MODE_3		(1 << 3)
+#define ONFI_TIMING_MODE_4		(1 << 4)
+#define ONFI_TIMING_MODE_5		(1 << 5)
+#define ONFI_TIMING_MODE_UNKNOWN	(1 << 6)
+
+/* ONFI feature address */
+#define ONFI_FEATURE_ADDR_TIMING_MODE	0x1
+
+/* ONFI subfeature parameters length */
+#define ONFI_SUBFEATURE_PARAM_LEN	4
+
 struct nand_onfi_params {
 	/* rev info and features block */
 	/* 'O' 'N' 'F' 'I'  */
@@ -326,27 +322,32 @@
 };
 
 /**
- * struct nand_ecc_ctrl - Control structure for ecc
- * @mode:	ecc mode
- * @steps:	number of ecc steps per page
- * @size:	data bytes per ecc step
- * @bytes:	ecc bytes per step
- * @total:	total number of ecc bytes per page
- * @prepad:	padding information for syndrome based ecc generators
- * @postpad:	padding information for syndrome based ecc generators
+ * struct nand_ecc_ctrl - Control structure for ECC
+ * @mode:	ECC mode
+ * @steps:	number of ECC steps per page
+ * @size:	data bytes per ECC step
+ * @bytes:	ECC bytes per step
+ * @strength:	max number of correctible bits per ECC step
+ * @total:	total number of ECC bytes per page
+ * @prepad:	padding information for syndrome based ECC generators
+ * @postpad:	padding information for syndrome based ECC generators
  * @layout:	ECC layout control struct pointer
- * @priv:	pointer to private ecc control data
- * @hwctl:	function to control hardware ecc generator. Must only
+ * @priv:	pointer to private ECC control data
+ * @hwctl:	function to control hardware ECC generator. Must only
  *		be provided if an hardware ECC is available
- * @calculate:	function for ecc calculation or readback from ecc hardware
- * @correct:	function for ecc correction, matching to ecc generator (sw/hw)
+ * @calculate:	function for ECC calculation or readback from ECC hardware
+ * @correct:	function for ECC correction, matching to ECC generator (sw/hw)
  * @read_page_raw:	function to read a raw page without ECC
  * @write_page_raw:	function to write a raw page without ECC
- * @read_page:	function to read a page according to the ecc generator
+ * @read_page:	function to read a page according to the ECC generator
+ *		requirements; returns maximum number of bitflips corrected in
+ *		any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
+ * @read_subpage:	function to read parts of the page covered by ECC;
+ *			returns same as read_page()
+ * @write_page:	function to write a page according to the ECC generator
  *		requirements.
- * @read_subpage:	function to read parts of the page covered by ECC.
- * @write_page:	function to write a page according to the ecc generator
- *		requirements.
+ * @write_oob_raw:	function to write chip OOB data without ECC
+ * @read_oob_raw:	function to read chip OOB data without ECC
  * @read_oob:	function to read chip OOB data
  * @write_oob:	function to write chip OOB data
  */
@@ -356,6 +357,7 @@
 	int size;
 	int bytes;
 	int total;
+	int strength;
 	int prepad;
 	int postpad;
 	struct nand_ecclayout	*layout;
@@ -366,25 +368,28 @@
 	int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
 			uint8_t *calc_ecc);
 	int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
-			uint8_t *buf, int page);
-	void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
-			const uint8_t *buf);
+			uint8_t *buf, int oob_required, int page);
+	int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+			const uint8_t *buf, int oob_required);
 	int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
-			uint8_t *buf, int page);
+			uint8_t *buf, int oob_required, int page);
 	int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 			uint32_t offs, uint32_t len, uint8_t *buf);
-	void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
-			const uint8_t *buf);
-	int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page,
-			int sndcmd);
+	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
+			const uint8_t *buf, int oob_required);
+	int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+			int page);
+	int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+			int page);
+	int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
 	int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
 			int page);
 };
 
 /**
  * struct nand_buffers - buffer structure for read/write
- * @ecccalc:	buffer for calculated ecc
- * @ecccode:	buffer for ecc read from flash
+ * @ecccalc:	buffer for calculated ECC
+ * @ecccode:	buffer for ECC read from flash
  * @databuf:	buffer for data - dynamically sized
  *
  * Do not change the order of buffers. databuf and oobrbuf must be in
@@ -418,7 +423,7 @@
  *			mtd->oobsize, mtd->writesize and so on.
  *			@id_data contains the 8 bytes values of NAND_CMD_READID.
  *			Return with the bus width.
- * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accesing
+ * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accessing
  *			device ready/busy line. If set to NULL no access to
  *			ready/busy is available and the ready/busy information
  *			is read from the chip status register.
@@ -426,17 +431,17 @@
  *			commands to the chip.
  * @waitfunc:		[REPLACEABLE] hardwarespecific function for wait on
  *			ready.
- * @ecc:		[BOARDSPECIFIC] ecc control ctructure
+ * @ecc:		[BOARDSPECIFIC] ECC control structure
  * @buffers:		buffer structure for read/write
  * @hwcontrol:		platform-specific hardware control structure
- * @ops:		oob operation operands
  * @erase_cmd:		[INTERN] erase command write function, selectable due
  *			to AND support.
  * @scan_bbt:		[REPLACEABLE] function to scan bad block table
  * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transferring
  *			data from array to read regs (tR).
  * @state:		[INTERN] the current state of the NAND device
- * @oob_poi:		poison value buffer
+ * @oob_poi:		"poison value buffer," used for laying out OOB data
+ *			before writing
  * @page_shift:		[INTERN] number of address bits in a page (column
  *			address bits).
  * @phys_erase_shift:	[INTERN] number of address bits in a physical eraseblock
@@ -445,10 +450,14 @@
  * @options:		[BOARDSPECIFIC] various chip options. They can partly
  *			be set to inform nand_scan about special functionality.
  *			See the defines for further explanation.
+ * @bbt_options:	[INTERN] bad block specific options. All options used
+ *			here must come from bbm.h. By default, these options
+ *			will be copied to the appropriate nand_bbt_descr's.
  * @badblockpos:	[INTERN] position of the bad block marker in the oob
  *			area.
- * @badblockbits:	[INTERN] number of bits to left-shift the bad block
- *			number
+ * @badblockbits:	[INTERN] minimum number of set bits in a good block's
+ *			bad block marker position; i.e., BBM == 11110111b is
+ *			not bad when badblockbits == 7
  * @cellinfo:		[INTERN] MLC/multichip data from chip ident
  * @numchips:		[INTERN] number of physical chips
  * @chipsize:		[INTERN] the size of one chip for multichip arrays
@@ -460,7 +469,9 @@
  *			non 0 if ONFI supported.
  * @onfi_params:	[INTERN] holds the ONFI page parameter when ONFI is
  *			supported, 0 otherwise.
- * @ecclayout:		[REPLACEABLE] the default ecc placement scheme
+ * @onfi_set_features	[REPLACEABLE] set the features for ONFI nand
+ * @onfi_get_features	[REPLACEABLE] get the features for ONFI nand
+ * @ecclayout:		[REPLACEABLE] the default ECC placement scheme
  * @bbt:		[INTERN] bad block table pointer
  * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash
  *			lookup.
@@ -468,9 +479,9 @@
  * @badblock_pattern:	[REPLACEABLE] bad block scan pattern used for initial
  *			bad block scan.
  * @controller:		[REPLACEABLE] a pointer to a hardware controller
- *			structure which is shared among multiple independend
+ *			structure which is shared among multiple independent
  *			devices.
- * @priv:		[OPTIONAL] pointer to private chip date
+ * @priv:		[OPTIONAL] pointer to private chip data
  * @errstat:		[OPTIONAL] hardware specific function to perform
  *			additional error status checks (determine if errors are
  *			correctable).
@@ -501,10 +512,16 @@
 	int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
 			int status, int page);
 	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
-			const uint8_t *buf, int page, int cached, int raw);
+			const uint8_t *buf, int oob_required, int page,
+			int cached, int raw);
+	int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
+			int feature_addr, uint8_t *subfeature_para);
+	int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
+			int feature_addr, uint8_t *subfeature_para);
 
 	int chip_delay;
 	unsigned int options;
+	unsigned int bbt_options;
 
 	int page_shift;
 	int phys_erase_shift;
@@ -534,8 +551,6 @@
 	struct nand_buffers *buffers;
 	struct nand_hw_control hwcontrol;
 
-	struct mtd_oob_ops ops;
-
 	uint8_t *bbt;
 	struct nand_bbt_descr *bbt_td;
 	struct nand_bbt_descr *bbt_md;
@@ -557,6 +572,8 @@
 #define NAND_MFR_HYNIX		0xad
 #define NAND_MFR_MICRON		0x2c
 #define NAND_MFR_AMD		0x01
+#define NAND_MFR_MACRONIX	0xc2
+#define NAND_MFR_EON		0x92
 
 /**
  * struct nand_flash_dev - NAND Flash Device ID Structure
@@ -615,9 +632,9 @@
  * @partitions:		mtd partition list
  * @chip_delay:		R/B delay value in us
  * @options:		Option flags, e.g. 16bit buswidth
- * @ecclayout:		ecc layout info structure
+ * @bbt_options:	BBT option flags, e.g. NAND_BBT_USE_FLASH
+ * @ecclayout:		ECC layout info structure
  * @part_probe_types:	NULL-terminated array of probe types
- * @priv:		hardware controller specific settings
  */
 struct platform_nand_chip {
 	int nr_chips;
@@ -627,8 +644,8 @@
 	struct nand_ecclayout *ecclayout;
 	int chip_delay;
 	unsigned int options;
+	unsigned int bbt_options;
 	const char **part_probe_types;
-	void *priv;
 };
 
 /* Keep gcc happy */
@@ -650,6 +667,7 @@
 	int (*dev_ready)(struct mtd_info *mtd);
 	void (*select_chip)(struct mtd_info *mtd, int chip);
 	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
+	unsigned char (*read_byte)(struct mtd_info *mtd);
 	void *priv;
 };
 
@@ -679,4 +697,23 @@
 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
 uint8_t nand_read_byte(struct mtd_info *mtd);
 
+/* return the supported asynchronous timing mode. */
+
+#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
+static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
+{
+	if (!chip->onfi_version)
+		return ONFI_TIMING_MODE_UNKNOWN;
+	return le16_to_cpu(chip->onfi_params.async_timing_mode);
+}
+
+/* return the supported synchronous timing mode. */
+static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
+{
+	if (!chip->onfi_version)
+		return ONFI_TIMING_MODE_UNKNOWN;
+	return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
+}
+#endif
+
 #endif /* __LINUX_MTD_NAND_H */
diff --git a/include/linux/string.h b/include/linux/string.h
index e9b134d..8e44855 100644
--- a/include/linux/string.h
+++ b/include/linux/string.h
@@ -85,6 +85,9 @@
 #ifndef __HAVE_ARCH_MEMCHR
 extern void * memchr(const void *,int,__kernel_size_t);
 #endif
+#ifndef __HAVE_ARCH_MEMCHR_INV
+void *memchr_inv(const void *, int, size_t);
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/include/lmb.h b/include/lmb.h
index 5d1f4b6..43082a3 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -1,7 +1,6 @@
 #ifndef _LINUX_LMB_H
 #define _LINUX_LMB_H
 #ifdef __KERNEL__
-#ifdef CONFIG_LMB
 
 #include <asm/types.h>
 /*
@@ -57,7 +56,6 @@
 void board_lmb_reserve(struct lmb *lmb);
 void arch_lmb_reserve(struct lmb *lmb);
 
-#endif /* CONFIG_LMB */
 #endif /* __KERNEL__ */
 
 #endif /* _LINUX_LMB_H */
diff --git a/include/mmc.h b/include/mmc.h
index 8bbc6b6..566db59 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -68,6 +68,7 @@
 #define UNUSABLE_ERR		-17 /* Unusable Card */
 #define COMM_ERR		-18 /* Communications Error */
 #define TIMEOUT			-19
+#define IN_PROGRESS		-20 /* operation is in progress */
 
 #define MMC_CMD_GO_IDLE_STATE		0
 #define MMC_CMD_SEND_OP_COND		1
@@ -270,6 +271,10 @@
 	int (*getcd)(struct mmc *mmc);
 	int (*getwp)(struct mmc *mmc);
 	uint b_max;
+	char op_cond_pending;	/* 1 if we are waiting on an op_cond command */
+	char init_in_progress;	/* 1 if we have done mmc_start_init() */
+	char preinit;		/* start init as early as possible */
+	uint op_cond_response;	/* the response byte from the last op_cond */
 };
 
 int mmc_register(struct mmc *mmc);
@@ -287,6 +292,31 @@
 int mmc_getwp(struct mmc *mmc);
 void spl_mmc_load(void) __noreturn;
 
+/**
+ * Start device initialization and return immediately; it does not block on
+ * polling OCR (operation condition register) status.  Then you should call
+ * mmc_init, which would block on polling OCR status and complete the device
+ * initializatin.
+ *
+ * @param mmc	Pointer to a MMC device struct
+ * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
+ */
+int mmc_start_init(struct mmc *mmc);
+
+/**
+ * Set preinit flag of mmc device.
+ *
+ * This will cause the device to be pre-inited during mmc_initialize(),
+ * which may save boot time if the device is not accessed until later.
+ * Some eMMC devices take 200-300ms to init, but unfortunately they
+ * must be sent a series of commands to even get them to start preparing
+ * for operation.
+ *
+ * @param mmc		Pointer to a MMC device struct
+ * @param preinit	preinit flag value
+ */
+void mmc_set_preinit(struct mmc *mmc, int preinit);
+
 #ifdef CONFIG_GENERIC_MMC
 #define mmc_host_is_spi(mmc)	((mmc)->host_caps & MMC_MODE_SPI)
 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
diff --git a/include/mpc8220.h b/include/mpc8220.h
deleted file mode 100644
index c4900a0..0000000
--- a/include/mpc8220.h
+++ /dev/null
@@ -1,717 +0,0 @@
-/*
- * include/mpc8220.h
- *
- * Prototypes, etc. for the Motorola MPC8220
- * embedded cpu chips
- *
- * 2004 (c) Freescale, Inc.
- * Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __MPC8220_H__
-#define __MPC8220_H__
-
-/* Processor name */
-#if defined(CONFIG_MPC8220)
-#define CPU_ID_STR	    "MPC8220"
-#endif
-
-/* Exception offsets (PowerPC standard) */
-#define EXC_OFF_SYS_RESET   0x0100
-#define _START_OFFSET	EXC_OFF_SYS_RESET
-
-/* Internal memory map */
-/* MPC8220 Internal Register MMAP */
-#define MMAP_MBAR	(CONFIG_SYS_MBAR + 0x00000000) /* chip selects		     */
-#define MMAP_MEMCTL	(CONFIG_SYS_MBAR + 0x00000100) /* sdram controller	     */
-#define MMAP_XLBARB	(CONFIG_SYS_MBAR + 0x00000200) /* xlb arbitration control   */
-#define MMAP_CDM	(CONFIG_SYS_MBAR + 0x00000300) /* clock distribution module */
-#define MMAP_VDOPLL	(CONFIG_SYS_MBAR + 0x00000400) /* video PLL		     */
-#define MMAP_FB		(CONFIG_SYS_MBAR + 0x00000500) /* flex bus controller	     */
-#define MMAP_PCFG	(CONFIG_SYS_MBAR + 0x00000600) /* port config		     */
-#define MMAP_ICTL	(CONFIG_SYS_MBAR + 0x00000700) /* interrupt controller	     */
-#define MMAP_GPTMR	(CONFIG_SYS_MBAR + 0x00000800) /* general purpose timers    */
-#define MMAP_SLTMR	(CONFIG_SYS_MBAR + 0x00000900) /* slice timers		     */
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00000A00) /* gpio module		     */
-#define MMAP_XCPCI	(CONFIG_SYS_MBAR + 0x00000B00) /* pci controller	     */
-#define MMAP_PCIARB	(CONFIG_SYS_MBAR + 0x00000C00) /* pci arbiter		     */
-#define MMAP_EXTDMA1	(CONFIG_SYS_MBAR + 0x00000D00) /* external dma1	     */
-#define MMAP_EXTDMA2	(CONFIG_SYS_MBAR + 0x00000E00) /* external dma1	     */
-#define MMAP_USBH	(CONFIG_SYS_MBAR + 0x00001000) /* usb host		     */
-#define MMAP_CMTMR	(CONFIG_SYS_MBAR + 0x00007f00) /* comm timers		     */
-#define MMAP_DMA	(CONFIG_SYS_MBAR + 0x00008000) /* dma			     */
-#define MMAP_USBD	(CONFIG_SYS_MBAR + 0x00008200) /* usb device		     */
-#define MMAP_COMMPCI	(CONFIG_SYS_MBAR + 0x00008400) /* pci comm Bus regs	     */
-#define MMAP_1284	(CONFIG_SYS_MBAR + 0x00008500) /* 1284			     */
-#define MMAP_PEV	(CONFIG_SYS_MBAR + 0x00008600) /* print engine video	     */
-#define MMAP_PSC1	(CONFIG_SYS_MBAR + 0x00008800) /* psc1 block		     */
-#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00008f00) /* i2c controller	     */
-#define MMAP_FEC1	(CONFIG_SYS_MBAR + 0x00009000) /* fast ethernet 1	     */
-#define MMAP_FEC2	(CONFIG_SYS_MBAR + 0x00009800) /* fast ethernet 2	     */
-#define MMAP_JBIGRAM	(CONFIG_SYS_MBAR + 0x0000a000) /* jbig RAM		     */
-#define MMAP_JBIG	(CONFIG_SYS_MBAR + 0x0000c000) /* jbig			     */
-#define MMAP_PDLA	(CONFIG_SYS_MBAR + 0x00010000) /*			     */
-#define MMAP_SRAMCFG	(CONFIG_SYS_MBAR + 0x0001ff00) /* SRAM config		     */
-#define MMAP_SRAM	(CONFIG_SYS_MBAR + 0x00020000) /* SRAM			     */
-
-#define SRAM_SIZE	0x8000			/* 32 KB */
-
-/* ------------------------------------------------------------------------ */
-/*
- * Macro for Programmable Serial Channel
- */
-/* equates for mode reg. 1 for channel	A or B */
-#define PSC_MR1_RX_RTS		0x80000000    /* receiver RTS enabled */
-#define PSC_MR1_RX_INT		0x40000000    /* receiver intrupt enabled */
-#define PSC_MR1_ERR_MODE	0x20000000    /* block error mode */
-#define PSC_MR1_PAR_MODE_MULTI	0x18000000    /* multi_drop mode */
-#define PSC_MR1_NO_PARITY	0x10000000    /* no parity mode */
-#define PSC_MR1_ALWAYS_0	0x08000000    /* force parity mode */
-#define PSC_MR1_ALWAYS_1	0x0c000000    /* force parity mode */
-#define PSC_MR1_EVEN_PARITY	0x00000000    /* parity mode */
-#define PSC_MR1_ODD_PARITY	0x04000000    /* 0 = even, 1 = odd */
-#define PSC_MR1_BITS_CHAR_8	0x03000000    /* 8 bits */
-#define PSC_MR1_BITS_CHAR_7	0x02000000    /* 7 bits */
-#define PSC_MR1_BITS_CHAR_6	0x01000000    /* 6 bits */
-#define PSC_MR1_BITS_CHAR_5	0x00000000    /* 5 bits */
-
-/* equates for mode reg. 2 for channel	A or B */
-#define PSC_MR2_NORMAL_MODE	0x00000000    /* normal channel mode */
-#define PSC_MR2_AUTO_MODE	0x40000000    /* automatic channel mode */
-#define PSC_MR2_LOOPBACK_LOCL	0x80000000    /* local loopback channel mode */
-#define PSC_MR2_LOOPBACK_REMT	0xc0000000    /* remote loopback channel mode */
-#define PSC_MR2_TX_RTS		0x20000000    /* transmitter RTS enabled */
-#define PSC_MR2_TX_CTS		0x10000000    /* transmitter CTS enabled */
-#define PSC_MR2_STOP_BITS_2	0x0f000000    /* 2 stop bits */
-#define PSC_MR2_STOP_BITS_1	0x07000000    /* 1 stop bit */
-
-/* equates for status reg. A or B */
-#define PSC_SR_BREAK		0x80000000    /* received break */
-#define PSC_SR_NEOF		PSC_SR_BREAK  /* Next byte is EOF - MIR/FIR */
-#define PSC_SR_FRAMING		0x40000000    /* framing error */
-#define PSC_SR_PHYERR		PSC_SR_FRAMING/* Physical Layer error - MIR/FIR */
-#define PSC_SR_PARITY		0x20000000    /* parity error */
-#define PSC_SR_CRCERR		PSC_SR_PARITY /* CRC error */
-#define PSC_SR_OVERRUN		0x10000000    /* overrun error */
-#define PSC_SR_TXEMT		0x08000000    /* transmitter empty */
-#define PSC_SR_TXRDY		0x04000000    /* transmitter ready*/
-#define PSC_SR_FFULL		0x02000000    /* fifo full */
-#define PSC_SR_RXRDY		0x01000000    /* receiver ready */
-#define PSC_SR_DEOF		0x00800000    /* Detect EOF or RX-FIFO contain EOF */
-#define PSC_SR_ERR		0x00400000    /* Error Status including FIFO */
-
-/* equates for clock select reg. */
-#define PSC_CSRX16EXT_CLK	0x1110	/* x 16 ext_clock */
-#define PSC_CSRX1EXT_CLK	0x1111	/* x 1 ext_clock  */
-
-/* equates for command reg. A or B */
-#define PSC_CR_NO_COMMAND	0x00000000    /* no command */
-#define PSC_CR_RST_MR_PTR_CMD	0x10000000    /* reset mr pointer command */
-#define PSC_CR_RST_RX_CMD	0x20000000    /* reset receiver command */
-#define PSC_CR_RST_TX_CMD	0x30000000    /* reset transmitter command */
-#define PSC_CR_RST_ERR_STS_CMD	0x40000000    /* reset error status cmnd */
-#define PSC_CR_RST_BRK_INT_CMD	0x50000000    /* reset break int. command */
-#define PSC_CR_STR_BREAK_CMD	0x60000000    /* start break command */
-#define PSC_CR_STP_BREAK_CMD	0x70000000    /* stop break command */
-#define PSC_CR_RX_ENABLE	0x01000000    /* receiver enabled */
-#define PSC_CR_RX_DISABLE	0x02000000    /* receiver disabled */
-#define PSC_CR_TX_ENABLE	0x04000000    /* transmitter enabled */
-#define PSC_CR_TX_DISABLE	0x08000000    /* transmitter disabled */
-
-/* equates for input port change reg. */
-#define PSC_IPCR_SYNC		0x80000000    /* Sync Detect */
-#define PSC_IPCR_D_CTS		0x10000000    /* Delta CTS */
-#define PSC_IPCR_CTS		0x01000000    /* CTS - current state of PSC_CTS */
-
-/* equates for auxiliary control reg. (timer and counter clock selects) */
-#define PSC_ACR_BRG		0x80000000    /* for 68681 compatibility
-						 baud rate gen select
-						 0 = set 1; 1 = set 2
-						 equates are set 2 ONLY */
-#define PSC_ACR_TMR_EXT_CLK_16	0x70000000    /* xtnl clock divided by 16 */
-#define PSC_ACR_TMR_EXT_CLK	0x60000000    /* external clock */
-#define PSC_ACR_TMR_IP2_16	0x50000000    /* ip2 divided by 16 */
-#define PSC_ACR_TMR_IP2		0x40000000    /* ip2 */
-#define PSC_ACR_CTR_EXT_CLK_16	0x30000000    /* xtnl clock divided by 16 */
-#define PSC_ACR_CTR_TXCB	0x20000000    /* channel B xmitr clock */
-#define PSC_ACR_CTR_TXCA	0x10000000    /* channel A xmitr clock */
-#define PSC_ACR_CTR_IP2		0x00000000    /* ip2 */
-#define PSC_ACR_IEC0		0x01000000    /* interrupt enable ctrl for D_CTS */
-
-/* equates for int. status reg. */
-#define PSC_ISR_IPC		0x80000000    /* input port change*/
-#define PSC_ISR_BREAK		0x04000000    /* delta break */
-#define PSC_ISR_RX_RDY		0x02000000    /* receiver rdy /fifo full */
-#define PSC_ISR_TX_RDY		0x01000000    /* transmitter ready */
-#define PSC_ISR_DEOF		0x00800000    /* Detect EOF / RX-FIFO contains EOF */
-#define PSC_ISR_ERR		0x00400000    /* Error Status including FIFO */
-
-/* equates for int. mask reg. */
-#define PSC_IMR_CLEAR		0xff000000    /* Clear the imr */
-#define PSC_IMR_IPC		0x80000000    /* input port change*/
-#define PSC_IMR_BREAK		0x04000000    /* delta break */
-#define PSC_IMR_RX_RDY		0x02000000    /* rcvr ready / fifo full */
-#define PSC_IMR_TX_RDY		0x01000000    /* transmitter ready */
-#define PSC_IMR_DEOF		0x00800000    /* Detect EOF / RX-FIFO contains EOF */
-#define PSC_IMR_ERR		0x00400000    /* Error Status including FIFO */
-
-/* equates for input port reg. */
-#define PSC_IP_LPWRB		0x80000000    /* Low power mode in Ac97 */
-#define PSC_IP_TGL		0x40000000    /* test usage */
-#define PSC_IP_CTS		0x01000000    /* CTS */
-
-/* equates for output port bit set reg. */
-#define PSC_OPSET_RTS		0x01000000    /* Assert PSC_RTS output */
-
-/* equates for output port bit reset reg. */
-#define PSC_OPRESET_RTS		0x01000000    /* Assert PSC_RTS output */
-
-/* equates for rx FIFO number of data reg. */
-#define PSC_RFNUM(x)		((x&0xff)<<24)/* receive count */
-
-/* equates for tx FIFO number of data reg. */
-#define PSC_TFNUM(x)		((x&0xff)<<24)/* receive count */
-
-/* equates for rx FIFO status reg */
-#define PSC_RFSTAT_TAG(x)	((x&3)<<28)   /* tag */
-#define PSC_RFSTAT_FRAME0	0x08	      /* Frame Indicator 0 */
-#define PSC_RFSTAT_FRAME1	0x04	      /* Frame Indicator 1 */
-#define PSC_RFSTAT_FRAME2	0x02	      /* Frame Indicator 2 */
-#define PSC_RFSTAT_FRAME3	0x01	      /* Frame Indicator 3 */
-#define PSC_RFSTAT_FRAME(x)	((x&0x0f)<<24)/* Frame indicator */
-#define PSC_RFSTAT_ERR		0x00400000    /* Fifo err */
-#define PSC_RFSTAT_UF		0x00200000    /* Underflow */
-#define PSC_RFSTAT_OF		0x00100000    /* overflow */
-#define PSC_RFSTAT_FR		0x00080000    /* frame ready */
-#define PSC_RFSTAT_FULL		0x00040000    /* full */
-#define PSC_RFSTAT_ALARM	0x00020000    /* alarm */
-#define PSC_RFSTAT_EMPTY	0x00010000    /* empty */
-
-/* equates for tx FIFO status reg */
-#define PSC_TFSTAT_TAG(x)	((x&3)<<28)   /* tag */
-#define PSC_TFSTAT_FRAME0	0x08	      /* Frame Indicator 0 */
-#define PSC_TFSTAT_FRAME1	0x04	      /* Frame Indicator 1 */
-#define PSC_TFSTAT_FRAME2	0x02	      /* Frame Indicator 2 */
-#define PSC_TFSTAT_FRAME3	0x01	      /* Frame Indicator 3 */
-#define PSC_TFSTAT_FRAME(x)	((x&0x0f)<<24)/* Frame indicator */
-#define PSC_TFSTAT_ERR		0x00400000    /* Fifo err */
-#define PSC_TFSTAT_UF		0x00200000    /* Underflow */
-#define PSC_TFSTAT_OF		0x00100000    /* overflow */
-#define PSC_TFSTAT_FR		0x00080000    /* frame ready */
-#define PSC_TFSTAT_FULL		0x00040000    /* full */
-#define PSC_TFSTAT_ALARM	0x00020000    /* alarm */
-#define PSC_TFSTAT_EMPTY	0x00010000    /* empty */
-
-/* equates for rx FIFO control reg. */
-#define PSC_RFCNTL_WTAG(x)	((x&3)<<29)   /* Write tag */
-#define PSC_RFCNTL_FRAME	0x08000000    /* Frame mode enable */
-#define PSC_RFCNTL_GR(x)	((x&7)<<24)   /* Granularity */
-
-/* equates for tx FIFO control reg. */
-#define PSC_TFCNTL_WTAG(x)	((x&3)<<29)   /* Write tag */
-#define PSC_TFCNTL_FRAME	0x08000000    /* Frame mode enable */
-#define PSC_TFCNTL_GR(x)	((x&7)<<24)   /* Granularity */
-
-/* equates for rx FIFO alarm reg */
-#define PSC_RFALARM(x)		(x&0x1ff)     /* Alarm */
-
-/* equates for tx FIFO alarm reg */
-#define PSC_TFALARM(x)		(x&0x1ff)     /* Alarm */
-
-/* equates for rx FIFO read pointer */
-#define PSC_RFRPTR(x)		(x&0x1ff)     /* read pointer */
-
-/* equates for tx FIFO read pointer */
-#define PSC_TFRPTR(x)		(x&0x1ff)     /* read pointer */
-
-/* equates for rx FIFO write pointer */
-#define PSC_RFWPTR(x)		(x&0x1ff)     /* write pointer */
-
-/* equates for rx FIFO write pointer */
-#define PSC_TFWPTR(x)		(x&0x1ff)     /* write pointer */
-
-/* equates for rx FIFO last read frame pointer reg */
-#define PSC_RFLRFPTR(x)		(x&0x1ff)     /* last read frame pointer */
-
-/* equates for tx FIFO last read frame pointer reg */
-#define PSC_TFLRFPTR(x)		(x&0x1ff)     /* last read frame pointer */
-
-/* equates for rx FIFO last write frame pointer reg */
-#define PSC_RFLWFPTR(x)		(x&0x1ff)     /* last write frame pointer */
-
-/* equates for tx FIFO last write frame pointer reg */
-#define PSC_TFLWFPTR(x)		(x&0x1ff)     /* last write frame pointer */
-
-/* PCI configuration (only for PLL determination)*/
-#define PCI_REG_PCIGSCR		(MMAP_XCPCI + 0x60) /* Global status/control register */
-#define PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK	0x07000000
-#define PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT		24
-
-#define PCI_REG_PCICAR		(MMAP_XCPCI + 0xF8) /* Configuration Address Register */
-
-/* ------------------------------------------------------------------------ */
-/*
- * Macro for General Purpose Timer
- */
-/* Enable and Mode Select */
-#define GPT_OCT(x)	    (x & 0x3)<<4/* Output Compare Type */
-#define GPT_ICT(x)	    (x & 0x3)	/* Input Capture Type */
-#define GPT_CTRL_WDEN	    0x80	/* Watchdog Enable */
-#define GPT_CTRL_CE	    0x10	/* Counter Enable */
-#define GPT_CTRL_STPCNT	    0x04	/* Stop continous */
-#define GPT_CTRL_ODRAIN	    0x02	/* Open Drain */
-#define GPT_CTRL_INTEN	    0x01	/* Interrupt Enable */
-#define GPT_MODE_GPIO(x)    (x & 0x3)<<4/* Gpio Mode Type */
-#define GPT_TMS_ICT	    0x01	/* Input Capture Enable */
-#define GPT_TMS_OCT	    0x02	/* Output Capture Enable */
-#define GPT_TMS_PWM	    0x03	/* PWM Capture Enable */
-#define GPT_TMS_SGPIO	    0x04	/* PWM Capture Enable */
-
-#define GPT_PWM_WIDTH(x)    (x & 0xffff)
-
-/* Status */
-#define GPT_STA_CAPTURE(x)  (x & 0xffff)/* Read of internal counter */
-
-#define GPT_OVFPIN_OVF(x)   (x & 0x70)	/* Internal counter roll over */
-#define GPT_OVFPIN_PIN	    0x01	/* Input pin - Timer 0 and 1 */
-
-#define GPT_INT_TEXP	    0x08	/* Timer Expired in Internal Timer mode */
-#define GPT_INT_PWMP	    0x04	/* PWM end of period occurred */
-#define GPT_INT_COMP	    0x02	/* OC reference event occurred */
-#define GPT_INT_CAPT	    0x01	/* IC reference event occurred */
-
-/* ------------------------------------------------------------------------ */
-/*
- * Port configuration
- */
-#define CONFIG_SYS_FEC1_PORT0_CONFIG	0x00000000
-#define CONFIG_SYS_FEC1_PORT1_CONFIG	0x00000000
-#define CONFIG_SYS_1284_PORT0_CONFIG  0x00000000
-#define CONFIG_SYS_1284_PORT1_CONFIG  0x00000000
-#define CONFIG_SYS_FEC2_PORT2_CONFIG	0x00000000
-#define CONFIG_SYS_PEV_PORT2_CONFIG   0x00000000
-#define CONFIG_SYS_GP0_PORT0_CONFIG   0x00000000
-#define CONFIG_SYS_GP1_PORT2_CONFIG   0xaaaaaac0
-#define CONFIG_SYS_PSC_PORT3_CONFIG   0x00020000
-#define CONFIG_SYS_CS1_PORT3_CONFIG   0x00000000
-#define CONFIG_SYS_CS2_PORT3_CONFIG	0x10000000
-#define CONFIG_SYS_CS3_PORT3_CONFIG	0x40000000
-#define CONFIG_SYS_CS4_PORT3_CONFIG	0x00000400
-#define CONFIG_SYS_CS5_PORT3_CONFIG	0x00000200
-#define CONFIG_SYS_PCI_PORT3_CONFIG   0x01400180
-#define CONFIG_SYS_I2C_PORT3_CONFIG   0x00000000
-#define CONFIG_SYS_GP2_PORT3_CONFIG   0x000200a0
-
-/* ------------------------------------------------------------------------ */
-/*
- * DRAM configuration
- */
-
-/* Field definitions for the control register */
-#define CTL_MODE_ENABLE_SHIFT	    31
-#define CTL_CKE_SHIFT		    30
-#define CTL_DDR_SHIFT		    29
-#define CTL_REFRESH_SHIFT	    28
-#define CTL_ADDRMUX_SHIFT	    24
-#define CTL_PRECHARGE_SHIFT	    23
-#define CTL_DRIVE_RULE_SHIFT	    22
-#define CTL_REFRESH_INTERVAL_SHIFT  16
-#define CTL_DQSOEN_SHIFT	    8
-#define CTL_BUFFERED_SHIFT	    4
-#define CTL_REFRESH_CMD_SHIFT	    2
-#define CTL_PRECHARGE_CMD_SHIFT	    1
-
-#define CTL_MODE_ENABLE		    (1<<CTL_MODE_ENABLE_SHIFT)
-#define CTL_CKE_HIGH		    (1<<CTL_CKE_SHIFT)
-#define CTL_DDR_MODE		    (1<<CTL_DDR_SHIFT)
-#define CTL_REFRESH_ENABLE	    (1<<CTL_REFRESH_SHIFT)
-#define CTL_ADDRMUX(value)	    ((value)<<CTL_ADDRMUX_SHIFT)
-#define CTL_A8PRECHARGE		    (1<<CTL_PRECHARGE_SHIFT)
-#define CTL_REFRESH_INTERVAL(value) ((value)<<CTL_REFRESH_INTERVAL_SHIFT)
-#define CTL_DQSOEN(value)	    ((value)<<CTL_DQSOEN_SHIFT)
-#define CTL_BUFFERED		    (1<<CTL_BUFFERED_SHIFT)
-#define CTL_REFRESH_CMD		    (1<<CTL_REFRESH_CMD_SHIFT)
-#define CTL_PRECHARGE_CMD	    (1<<CTL_PRECHARGE_CMD_SHIFT)
-
-/* Field definitions for config register 1 */
-
-#define CFG1_SRD2RWP_SHIFT	    28
-#define CFG1_SWT2RWP_SHIFT	    24
-#define CFG1_RLATENCY_SHIFT	    20
-#define CFG1_ACT2WR_SHIFT	    16
-#define CFG1_PRE2ACT_SHIFT	    12
-#define CFG1_REF2ACT_SHIFT	    8
-#define CFG1_WLATENCY_SHIFT	    4
-
-#define CFG1_SRD2RWP(value)	    ((value)<<CFG1_SRD2RWP_SHIFT)
-#define CFG1_SWT2RWP(value)	    ((value)<<CFG1_SWT2RWP_SHIFT)
-#define CFG1_RLATENCY(value)	    ((value)<<CFG1_RLATENCY_SHIFT)
-#define CFG1_ACT2WR(value)	    ((value)<<CFG1_ACT2WR_SHIFT)
-#define CFG1_PRE2ACT(value)	    ((value)<<CFG1_PRE2ACT_SHIFT)
-#define CFG1_REF2ACT(value)	    ((value)<<CFG1_REF2ACT_SHIFT)
-#define CFG1_WLATENCY(value)	    ((value)<<CFG1_WLATENCY_SHIFT)
-
-/* Field definitions for config register 2 */
-#define CFG2_BRD2RP_SHIFT	    28
-#define CFG2_BWT2RWP_SHIFT	    24
-#define CFG2_BRD2WT_SHIFT	    20
-#define CFG2_BURSTLEN_SHIFT	    16
-
-#define CFG2_BRD2RP(value)	    ((value)<<CFG2_BRD2RP_SHIFT)
-#define CFG2_BWT2RWP(value)	    ((value)<<CFG2_BWT2RWP_SHIFT)
-#define CFG2_BRD2WT(value)	    ((value)<<CFG2_BRD2WT_SHIFT)
-#define CFG2_BURSTLEN(value)	    ((value)<<CFG2_BURSTLEN_SHIFT)
-
-/* Field definitions for the mode/extended mode register - mode
- * register access
- */
-#define MODE_REG_SHIFT		    30
-#define MODE_OPMODE_SHIFT	    25
-#define MODE_CL_SHIFT		    22
-#define MODE_BT_SHIFT		    21
-#define MODE_BURSTLEN_SHIFT	    18
-#define MODE_CMD_SHIFT		    16
-
-#define MODE_MODE		    0
-#define MODE_OPMODE(value)	    ((value)<<MODE_OPMODE_SHIFT)
-#define MODE_CL(value)		    ((value)<<MODE_CL_SHIFT)
-#define MODE_BT_INTERLEAVED	    (1<<MODE_BT_SHIFT)
-#define MODE_BT_SEQUENTIAL	    (0<<MODE_BT_SHIFT)
-#define MODE_BURSTLEN(value)	    ((value)<<MODE_BURSTLEN_SHIFT)
-#define MODE_CMD		    (1<<MODE_CMD_SHIFT)
-
-#define MODE_BURSTLEN_8		    3
-#define MODE_BURSTLEN_4		    2
-#define MODE_BURSTLEN_2		    1
-
-#define MODE_CL_2		    2
-#define MODE_CL_2p5		    6
-#define MODE_OPMODE_NORMAL	    0
-#define MODE_OPMODE_RESETDLL	    2
-
-
-/* Field definitions for the mode/extended mode register - extended
- * mode register access
- */
-#define MODE_X_DLL_SHIFT	    18 /* DLL enable/disable */
-#define MODE_X_DS_SHIFT		    19 /* Drive strength normal/reduced */
-#define MODE_X_QFC_SHIFT	    20 /* QFC function (whatever that is) */
-#define MODE_X_OPMODE_SHIFT	    21
-
-#define MODE_EXTENDED		    (1<<MODE_REG_SHIFT)
-#define MODE_X_DLL_ENABLE	    0
-#define MODE_X_DLL_DISABLE	    (1<<MODE_X_DLL_SHIFT)
-#define MODE_X_DS_NORMAL	    0
-#define MODE_X_DS_REDUCED	    (1<<MODE_X_DS_SHIFT)
-#define MODE_X_QFC_DISABLED	    0
-#define MODE_X_OPMODE(value)	    ((value)<<MODE_X_OPMODE_SHIFT)
-
-#ifndef __ASSEMBLY__
-/*
- * DMA control/status registers.
- */
-struct mpc8220_dma {
-    u32 taskBar;	/* DMA + 0x00 */
-    u32 currentPointer; /* DMA + 0x04 */
-    u32 endPointer;	/* DMA + 0x08 */
-    u32 variablePointer;/* DMA + 0x0c */
-
-    u8 IntVect1;	/* DMA + 0x10 */
-    u8 IntVect2;	/* DMA + 0x11 */
-    u16 PtdCntrl;	/* DMA + 0x12 */
-
-    u32 IntPend;	/* DMA + 0x14 */
-    u32 IntMask;	/* DMA + 0x18 */
-
-    u16 tcr_0;		/* DMA + 0x1c */
-    u16 tcr_1;		/* DMA + 0x1e */
-    u16 tcr_2;		/* DMA + 0x20 */
-    u16 tcr_3;		/* DMA + 0x22 */
-    u16 tcr_4;		/* DMA + 0x24 */
-    u16 tcr_5;		/* DMA + 0x26 */
-    u16 tcr_6;		/* DMA + 0x28 */
-    u16 tcr_7;		/* DMA + 0x2a */
-    u16 tcr_8;		/* DMA + 0x2c */
-    u16 tcr_9;		/* DMA + 0x2e */
-    u16 tcr_a;		/* DMA + 0x30 */
-    u16 tcr_b;		/* DMA + 0x32 */
-    u16 tcr_c;		/* DMA + 0x34 */
-    u16 tcr_d;		/* DMA + 0x36 */
-    u16 tcr_e;		/* DMA + 0x38 */
-    u16 tcr_f;		/* DMA + 0x3a */
-
-    u8 IPR0;		/* DMA + 0x3c */
-    u8 IPR1;		/* DMA + 0x3d */
-    u8 IPR2;		/* DMA + 0x3e */
-    u8 IPR3;		/* DMA + 0x3f */
-    u8 IPR4;		/* DMA + 0x40 */
-    u8 IPR5;		/* DMA + 0x41 */
-    u8 IPR6;		/* DMA + 0x42 */
-    u8 IPR7;		/* DMA + 0x43 */
-    u8 IPR8;		/* DMA + 0x44 */
-    u8 IPR9;		/* DMA + 0x45 */
-    u8 IPR10;		/* DMA + 0x46 */
-    u8 IPR11;		/* DMA + 0x47 */
-    u8 IPR12;		/* DMA + 0x48 */
-    u8 IPR13;		/* DMA + 0x49 */
-    u8 IPR14;		/* DMA + 0x4a */
-    u8 IPR15;		/* DMA + 0x4b */
-    u8 IPR16;		/* DMA + 0x4c */
-    u8 IPR17;		/* DMA + 0x4d */
-    u8 IPR18;		/* DMA + 0x4e */
-    u8 IPR19;		/* DMA + 0x4f */
-    u8 IPR20;		/* DMA + 0x50 */
-    u8 IPR21;		/* DMA + 0x51 */
-    u8 IPR22;		/* DMA + 0x52 */
-    u8 IPR23;		/* DMA + 0x53 */
-    u8 IPR24;		/* DMA + 0x54 */
-    u8 IPR25;		/* DMA + 0x55 */
-    u8 IPR26;		/* DMA + 0x56 */
-    u8 IPR27;		/* DMA + 0x57 */
-    u8 IPR28;		/* DMA + 0x58 */
-    u8 IPR29;		/* DMA + 0x59 */
-    u8 IPR30;		/* DMA + 0x5a */
-    u8 IPR31;		/* DMA + 0x5b */
-
-    u32 res1;		/* DMA + 0x5c */
-    u32 res2;		/* DMA + 0x60 */
-    u32 res3;		/* DMA + 0x64 */
-    u32 MDEDebug;	/* DMA + 0x68 */
-    u32 ADSDebug;	/* DMA + 0x6c */
-    u32 Value1;		/* DMA + 0x70 */
-    u32 Value2;		/* DMA + 0x74 */
-    u32 Control;	/* DMA + 0x78 */
-    u32 Status;		/* DMA + 0x7c */
-    u32 EU00;		/* DMA + 0x80 */
-    u32 EU01;		/* DMA + 0x84 */
-    u32 EU02;		/* DMA + 0x88 */
-    u32 EU03;		/* DMA + 0x8c */
-    u32 EU04;		/* DMA + 0x90 */
-    u32 EU05;		/* DMA + 0x94 */
-    u32 EU06;		/* DMA + 0x98 */
-    u32 EU07;		/* DMA + 0x9c */
-    u32 EU10;		/* DMA + 0xa0 */
-    u32 EU11;		/* DMA + 0xa4 */
-    u32 EU12;		/* DMA + 0xa8 */
-    u32 EU13;		/* DMA + 0xac */
-    u32 EU14;		/* DMA + 0xb0 */
-    u32 EU15;		/* DMA + 0xb4 */
-    u32 EU16;		/* DMA + 0xb8 */
-    u32 EU17;		/* DMA + 0xbc */
-    u32 EU20;		/* DMA + 0xc0 */
-    u32 EU21;		/* DMA + 0xc4 */
-    u32 EU22;		/* DMA + 0xc8 */
-    u32 EU23;		/* DMA + 0xcc */
-    u32 EU24;		/* DMA + 0xd0 */
-    u32 EU25;		/* DMA + 0xd4 */
-    u32 EU26;		/* DMA + 0xd8 */
-    u32 EU27;		/* DMA + 0xdc */
-    u32 EU30;		/* DMA + 0xe0 */
-    u32 EU31;		/* DMA + 0xe4 */
-    u32 EU32;		/* DMA + 0xe8 */
-    u32 EU33;		/* DMA + 0xec */
-    u32 EU34;		/* DMA + 0xf0 */
-    u32 EU35;		/* DMA + 0xf4 */
-    u32 EU36;		/* DMA + 0xf8 */
-    u32 EU37;		/* DMA + 0xfc */
-};
-
-/*
- * PCI Header Registers
- */
-typedef struct mpc8220_xcpci {
-	u32	dev_ven_id;		/* 0xb00 - device/vendor ID */
-	u32	stat_cmd_reg;		/* 0xb04 - status command register */
-	u32	class_code_rev_id;	/* 0xb08 - class code / revision ID */
-	u32	bist_htyp_lat_cshl;	/* 0xb0c - BIST/HeaderType/Latency/cache line */
-	u32	base0;			/* 0xb10 - base address 0 */
-	u32	base1;			/* 0xb14 - base address 1 */
-	u32	reserved1[4];		/* 0xb18->0xd27 - base address 2 - 5 */
-	u32	cis;			/* 0xb28 - cardBus CIS pointer */
-	u32	sub_sys_ven_id;		/* 0xb2c - sub system ID/ subsystem vendor ID */
-	u32	reserved2;		/* 0xb30 - expansion ROM base address */
-	u32	reserved3;		/* 0xb00 - reserved */
-	u32	reserved4;		/* 0xb00 - reserved */
-	u32	mlat_mgnt_ipl;		/* 0xb3c - MaxLat/MinGnt/ int pin/int line */
-	u32	reserved5[8];
-	/* MPC8220 specific - not accessible in PCI header space externally */
-	u32	glb_stat_ctl;		/* 0xb60 - Global Status Control */
-	u32	target_bar0;		/* 0xb64 - Target Base Address 0 */
-	u32	target_bar1;		/* 0xb68 - Target Base Address 1 */
-	u32	target_ctrl;		/* 0xb6c - Target Control */
-	u32	init_win0;		/* 0xb70 - Initiator Window 0 Base/Translation */
-	u32	init_win1;		/* 0xb74 - Initiator Window 1 Base/Translation */
-	u32	init_win2;		/* 0xb78 - Initiator Window 2 Base/Translation */
-	u32	reserved6;		/* 0xb7c - reserved  */
-	u32	init_win_cfg;		/* 0xb80 */
-	u32	init_ctrl;		/* 0xb84 */
-	u32	init_stat;		/* 0xb88 */
-	u32	reserved7[27];
-	u32	cfg_adr;		/* 0xbf8 */
-	u32	reserved8;
-} mpc8220_xcpci_t;
-
-/* PCI->XLB space translation (MPC8220 target), reg0 can address max 256MB,
-   reg1 - 1GB */
-#define PCI_BASE_ADDR_REG0			0x40000000
-#define PCI_BASE_ADDR_REG1			(CONFIG_SYS_SDRAM_BASE)
-#define PCI_TARGET_BASE_ADDR_REG0		(CONFIG_SYS_MBAR)
-#define PCI_TARGET_BASE_ADDR_REG1		(CONFIG_SYS_SDRAM_BASE)
-#define PCI_TARGET_BASE_ADDR_EN			1<<0
-
-
-/* PCI Global Status/Control Register (PCIGSCR) */
-#define PCI_GLB_STAT_CTRL_PE_SHIFT		29
-#define PCI_GLB_STAT_CTRL_SE_SHIFT		28
-#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_SHIFT	24
-#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_MASK	0x7
-#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_SHIFT	16
-#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_MASK	0x7
-#define PCI_GLB_STAT_CTRL_PEE_SHIFT		13
-#define PCI_GLB_STAT_CTRL_SEE_SHIFT		12
-#define PCI_GLB_STAT_CTRL_PR_SHIFT		0
-
-#define PCI_GLB_STAT_CTRL_PE			(1<<PCI_GLB_STAT_CTRL_PE_SHIFT)
-#define PCI_GLB_STAT_CTRL_SE			(1<<PCI_GLB_STAT_CTRL_SE_SHIFT)
-#define PCI_GLB_STAT_CTRL_PEE			(1<<PCI_GLB_STAT_CTRL_PEE_SHIFT)
-#define PCI_GLB_STAT_CTRL_SEE			(1<<PCI_GLB_STAT_CTRL_SEE_SHIFT)
-#define PCI_GLB_STAT_CTRL_PR			(1<<PCI_GLB_STAT_CTRL_PR_SHIFT)
-
-/* PCI Target Control Register (PCITCR) */
-#define PCI_TARGET_CTRL_LD_SHIFT		24
-#define PCI_TARGET_CTRL_P_SHIFT			16
-
-#define PCI_TARGET_CTRL_LD			(1<<PCI_TARGET_CTRL_LD_SHIFT)
-#define PCI_TARGET_CTRL_P			(1<<PCI_TARGET_CTRL_P_SHIFT)
-
-/* PCI Initiator Window Configuration Register (PCIIWCR) */
-#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT	27
-#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_SHIFT	25
-#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_MASK	0x3
-#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT	24
-#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT	19
-#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_SHIFT	17
-#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_MASK	0x3
-#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT	16
-#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT	11
-#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_SHIFT	9
-#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_MASK	0x3
-#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT	8
-
-#define PCI_INIT_WIN_CFG_WIN_MEM_READ		0x0
-#define PCI_INIT_WIN_CFG_WIN_MEM_READ_LINE	0x1
-#define PCI_INIT_WIN_CFG_WIN_MEM_READ_MULTIPLE	0x2
-
-#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT)
-#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT)
-#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT)
-#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT)
-#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT)
-#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT)
-
-/* PCI Initiator Control Register (PCIICR) */
-#define PCI_INIT_CTRL_REE_SHIFT			26
-#define PCI_INIT_CTRL_IAE_SHIFT			25
-#define PCI_INIT_CTRL_TAE_SHIFT			24
-#define PCI_INIT_CTRL_MAX_RETRIES_SHIFT		0
-#define PCI_INIT_CTRL_MAX_RETRIES_MASK		0xff
-
-#define PCI_INIT_CTRL_REE			(1<<PCI_INIT_CTRL_REE_SHIFT)
-#define PCI_INIT_CTRL_IAE			(1<<PCI_INIT_CTRL_IAE_SHIFT)
-#define PCI_INIT_CTRL_TAE			(1<<PCI_INIT_CTRL_TAE_SHIFT)
-
-/* PCI Status/Command Register (PCISCR) - PCI Dword 1 */
-#define PCI_STAT_CMD_PE_SHIFT			31
-#define PCI_STAT_CMD_SE_SHIFT			30
-#define PCI_STAT_CMD_MA_SHIFT			29
-#define PCI_STAT_CMD_TR_SHIFT			28
-#define PCI_STAT_CMD_TS_SHIFT			27
-#define PCI_STAT_CMD_DT_SHIFT			25
-#define PCI_STAT_CMD_DT_MASK			0x3
-#define PCI_STAT_CMD_DP_SHIFT			24
-#define PCI_STAT_CMD_FC_SHIFT			23
-#define PCI_STAT_CMD_R_SHIFT			22
-#define PCI_STAT_CMD_66M_SHIFT			21
-#define PCI_STAT_CMD_C_SHIFT			20
-#define PCI_STAT_CMD_F_SHIFT			9
-#define PCI_STAT_CMD_S_SHIFT			8
-#define PCI_STAT_CMD_ST_SHIFT			7
-#define PCI_STAT_CMD_PER_SHIFT			6
-#define PCI_STAT_CMD_V_SHIFT			5
-#define PCI_STAT_CMD_MW_SHIFT			4
-#define PCI_STAT_CMD_SP_SHIFT			3
-#define PCI_STAT_CMD_B_SHIFT			2
-#define PCI_STAT_CMD_M_SHIFT			1
-#define PCI_STAT_CMD_IO_SHIFT			0
-
-#define PCI_STAT_CMD_PE			(1<<PCI_STAT_CMD_PE_SHIFT)
-#define PCI_STAT_CMD_SE			(1<<PCI_STAT_CMD_SE_SHIFT)
-#define PCI_STAT_CMD_MA			(1<<PCI_STAT_CMD_MA_SHIFT)
-#define PCI_STAT_CMD_TR			(1<<PCI_STAT_CMD_TR_SHIFT)
-#define PCI_STAT_CMD_TS			(1<<PCI_STAT_CMD_TS_SHIFT)
-#define PCI_STAT_CMD_DP			(1<<PCI_STAT_CMD_DP_SHIFT)
-#define PCI_STAT_CMD_FC			(1<<PCI_STAT_CMD_FC_SHIFT)
-#define PCI_STAT_CMD_R				(1<<PCI_STAT_CMD_R_SHIFT)
-#define PCI_STAT_CMD_66M			(1<<PCI_STAT_CMD_66M_SHIFT)
-#define PCI_STAT_CMD_C				(1<<PCI_STAT_CMD_C_SHIFT)
-#define PCI_STAT_CMD_F				(1<<PCI_STAT_CMD_F_SHIFT)
-#define PCI_STAT_CMD_S				(1<<PCI_STAT_CMD_S_SHIFT)
-#define PCI_STAT_CMD_ST			(1<<PCI_STAT_CMD_ST_SHIFT)
-#define PCI_STAT_CMD_PER			(1<<PCI_STAT_CMD_PER_SHIFT)
-#define PCI_STAT_CMD_V				(1<<PCI_STAT_CMD_V_SHIFT)
-#define PCI_STAT_CMD_MW			(1<<PCI_STAT_CMD_MW_SHIFT)
-#define PCI_STAT_CMD_SP			(1<<PCI_STAT_CMD_SP_SHIFT)
-#define PCI_STAT_CMD_B				(1<<PCI_STAT_CMD_B_SHIFT)
-#define PCI_STAT_CMD_M				(1<<PCI_STAT_CMD_M_SHIFT)
-#define PCI_STAT_CMD_IO			(1<<PCI_STAT_CMD_IO_SHIFT)
-
-/* PCI Configuration 1 Register (PCICR1) - PCI Dword 3 */
-#define PCI_CFG1_HT_SHIFT			16
-#define PCI_CFG1_HT_MASK			0xff
-#define PCI_CFG1_LT_SHIFT			8
-#define PCI_CFG1_LT_MASK			0xff
-#define PCI_CFG1_CLS_SHIFT			0
-#define PCI_CFG1_CLS_MASK			0xf
-
-/* function prototypes */
-void loadtask(int basetask, int tasks);
-u32 dramSetup(void);
-
-#if defined(CONFIG_PSC_CONSOLE)
-int psc_serial_init (void);
-void psc_serial_putc(const char c);
-void psc_serial_puts (const char *s);
-int psc_serial_getc(void);
-int psc_serial_tstc(void);
-void psc_serial_setbrg(void);
-#endif
-
-#if defined (CONFIG_EXTUART_CONSOLE)
-int ext_serial_init (void);
-void ext_serial_putc(const char c);
-void ext_serial_puts (const char *s);
-int ext_serial_getc(void);
-int ext_serial_tstc(void);
-void ext_serial_setbrg(void);
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __MPC8220_H__ */
diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h
index 966b5e0..b644b91 100644
--- a/include/mtd/cfi_flash.h
+++ b/include/mtd/cfi_flash.h
@@ -129,12 +129,16 @@
 } cfiword_t;
 
 /* CFI standard query structure */
+/* The offsets and sizes of this packed structure members correspond
+ * to the actual layout in CFI Flash chips. Some 16- and 32-bit members
+ * are unaligned and must be accessed with explicit unaligned access macros.
+ */
 struct cfi_qry {
 	u8	qry[3];
-	u16	p_id;
-	u16	p_adr;
-	u16	a_id;
-	u16	a_adr;
+	u16	p_id;			/* unaligned */
+	u16	p_adr;			/* unaligned */
+	u16	a_id;			/* unaligned */
+	u16	a_adr;			/* unaligned */
 	u8	vcc_min;
 	u8	vcc_max;
 	u8	vpp_min;
@@ -148,10 +152,10 @@
 	u8	block_erase_timeout_max;
 	u8	chip_erase_timeout_max;
 	u8	dev_size;
-	u16	interface_desc;
-	u16	max_buf_write_size;
+	u16	interface_desc;		/* aligned */
+	u16	max_buf_write_size;	/* aligned */
 	u8	num_erase_regions;
-	u32	erase_region_info[NUM_ERASE_REGIONS];
+	u32	erase_region_info[NUM_ERASE_REGIONS];	/* unaligned */
 } __attribute__((packed));
 
 struct cfi_pri_hdr {
diff --git a/include/linux/mtd/mtd-abi.h b/include/mtd/mtd-abi.h
similarity index 65%
rename from include/linux/mtd/mtd-abi.h
rename to include/mtd/mtd-abi.h
index 8bdd231..d51c1ab 100644
--- a/include/linux/mtd/mtd-abi.h
+++ b/include/mtd/mtd-abi.h
@@ -24,6 +24,25 @@
 	unsigned char __user *ptr;
 };
 
+/*
+ * MTD operation modes
+ *
+ * @MTD_OPS_PLACE_OOB:	OOB data are placed at the given offset (default)
+ * @MTD_OPS_AUTO_OOB:	OOB data are automatically placed at the free areas
+ *			which are defined by the internal ecclayout
+ * @MTD_OPS_RAW:	data are transferred as-is, with no error correction;
+ *			this mode implies %MTD_OPS_PLACE_OOB
+ *
+ * These modes can be passed to ioctl(MEMWRITE) and are also used internally.
+ * See notes on "MTD file modes" for discussion on %MTD_OPS_RAW vs.
+ * %MTD_FILE_MODE_RAW.
+ */
+enum {
+	MTD_OPS_PLACE_OOB = 0,
+	MTD_OPS_AUTO_OOB = 1,
+	MTD_OPS_RAW = 2,
+};
+
 #define MTD_ABSENT		0
 #define MTD_RAM			1
 #define MTD_ROM			2
@@ -82,24 +101,42 @@
 	uint32_t locked;
 };
 
+/* Get basic MTD characteristics info (better to use sysfs) */
 #define MEMGETINFO		_IOR('M', 1, struct mtd_info_user)
+/* Erase segment of MTD */
 #define MEMERASE		_IOW('M', 2, struct erase_info_user)
+/* Write out-of-band data from MTD */
 #define MEMWRITEOOB		_IOWR('M', 3, struct mtd_oob_buf)
+/* Read out-of-band data from MTD */
 #define MEMREADOOB		_IOWR('M', 4, struct mtd_oob_buf)
+/* Lock a chip (for MTD that supports it) */
 #define MEMLOCK			_IOW('M', 5, struct erase_info_user)
+/* Unlock a chip (for MTD that supports it) */
 #define MEMUNLOCK		_IOW('M', 6, struct erase_info_user)
+/* Get the number of different erase regions */
 #define MEMGETREGIONCOUNT	_IOR('M', 7, int)
+/* Get information about the erase region for a specific index */
 #define MEMGETREGIONINFO	_IOWR('M', 8, struct region_info_user)
+/* Get info about OOB modes (e.g., RAW, PLACE, AUTO) - legacy interface */
 #define MEMSETOOBSEL		_IOW('M', 9, struct nand_oobinfo)
 #define MEMGETOOBSEL		_IOR('M', 10, struct nand_oobinfo)
+/* Check if an eraseblock is bad */
 #define MEMGETBADBLOCK		_IOW('M', 11, loff_t)
+/* Mark an eraseblock as bad */
 #define MEMSETBADBLOCK		_IOW('M', 12, loff_t)
+/* Set OTP (One-Time Programmable) mode (factory vs. user) */
 #define OTPSELECT		_IOR('M', 13, int)
+/* Get number of OTP (One-Time Programmable) regions */
 #define OTPGETREGIONCOUNT	_IOW('M', 14, int)
+/* Get all OTP (One-Time Programmable) info about MTD */
 #define OTPGETREGIONINFO	_IOW('M', 15, struct otp_info)
+/* Lock a given range of user data (must be in mode %MTD_FILE_MODE_OTP_USER) */
 #define OTPLOCK			_IOR('M', 16, struct otp_info)
+/* Get ECC layout (deprecated) */
 #define ECCGETLAYOUT		_IOR('M', 17, struct nand_ecclayout)
+/* Get statistics about corrected/uncorrected errors */
 #define ECCGETSTATS		_IOR('M', 18, struct mtd_ecc_stats)
+/* Set MTD mode on a per-file-descriptor basis (see "MTD file modes") */
 #define MTDFILEMODE		_IO('M', 19)
 
 /*
@@ -146,7 +183,21 @@
 };
 
 /*
- * Read/write file modes for access to MTD
+ * MTD file modes - for read/write access to MTD
+ *
+ * @MTD_FILE_MODE_NORMAL:	OTP disabled, ECC enabled
+ * @MTD_FILE_MODE_OTP_FACTORY:	OTP enabled in factory mode
+ * @MTD_FILE_MODE_OTP_USER:	OTP enabled in user mode
+ * @MTD_FILE_MODE_RAW:		OTP disabled, ECC disabled
+ *
+ * These modes can be set via ioctl(MTDFILEMODE). The mode mode will be retained
+ * separately for each open file descriptor.
+ *
+ * Note: %MTD_FILE_MODE_RAW provides the same functionality as %MTD_OPS_RAW -
+ * raw access to the flash, without error correction or autoplacement schemes.
+ * Wherever possible, the MTD_OPS_* mode will override the MTD_FILE_MODE_* mode
+ * (e.g., when using ioctl(MEMWRITE)), but in some cases, the MTD_FILE_MODE is
+ * used out of necessity (e.g., `write()', ioctl(MEMWRITEOOB64)).
  */
 enum mtd_file_modes {
 	MTD_MODE_NORMAL = MTD_OTP_OFF,
diff --git a/include/nand.h b/include/nand.h
index f0f3bf9..26190e4 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -31,7 +31,8 @@
  * at the same time, so do it here.  When all drivers are
  * converted, this will go away.
  */
-#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)
+#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\
+	|| defined(CONFIG_NAND_FSL_IFC)
 #define CONFIG_SYS_NAND_SELF_INIT
 #endif
 
@@ -55,17 +56,17 @@
 
 static inline int nand_read(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
 {
-	return info->read(info, ofs, *len, (size_t *)len, buf);
+	return mtd_read(info, ofs, *len, (size_t *)len, buf);
 }
 
 static inline int nand_write(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
 {
-	return info->write(info, ofs, *len, (size_t *)len, buf);
+	return mtd_write(info, ofs, *len, (size_t *)len, buf);
 }
 
 static inline int nand_block_isbad(nand_info_t *info, loff_t ofs)
 {
-	return info->block_isbad(info, ofs);
+	return mtd_block_isbad(info, ofs);
 }
 
 static inline int nand_erase(nand_info_t *info, loff_t off, size_t size)
@@ -77,7 +78,7 @@
 	instr.len = size;
 	instr.callback = 0;
 
-	return info->erase(info, &instr);
+	return mtd_erase(info, &instr);
 }
 
 
diff --git a/include/net.h b/include/net.h
index 970d4d1..23fb947 100644
--- a/include/net.h
+++ b/include/net.h
@@ -695,6 +695,9 @@
 /* get a random source port */
 extern unsigned int random_port(void);
 
+/* Update U-Boot over TFTP */
+extern int update_tftp(ulong addr);
+
 /**********************************************************************/
 
 #endif /* __NET_H__ */
diff --git a/include/netdev.h b/include/netdev.h
index fd3e243..df454b5 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -77,7 +77,6 @@
 int mcffec_initialize(bd_t *bis);
 int mpc512x_fec_initialize(bd_t *bis);
 int mpc5xxx_fec_initialize(bd_t *bis);
-int mpc8220_fec_initialize(bd_t *bis);
 int mpc82xx_scc_enet_initialize(bd_t *bis);
 int mvgbe_initialize(bd_t *bis);
 int natsemi_initialize(bd_t *bis);
@@ -104,7 +103,7 @@
 							int txpp, int rxpp);
 int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
 						unsigned long ctrl_addr);
-int zynq_gem_initialize(bd_t *bis, int base_addr);
+int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio);
 /*
  * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
  * exported by a public hader file, we need a global definition at this point.
diff --git a/include/twl6035.h b/include/palmas.h
similarity index 68%
rename from include/twl6035.h
rename to include/palmas.h
index ce74348..3b18589 100644
--- a/include/twl6035.h
+++ b/include/palmas.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2012
+ * (C) Copyright 2012-2013
  * Texas Instruments, <www.ti.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -20,12 +20,14 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef PALMAS_H
+#define PALMAS_H
 
 #include <common.h>
 #include <i2c.h>
 
 /* I2C chip addresses */
-#define TWL6035_CHIP_ADDR	0x48
+#define PALMAS_CHIP_ADDR	0x48
 
 /* 0x1XY translates to page 1, register address 0xXY */
 #define LDO9_CTRL		0x60
@@ -36,7 +38,21 @@
 #define LDO_MODE_SLEEP		(1 << 2)
 #define LDO_MODE_ACTIVE		(1 << 0)
 
-int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg);
-int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg);
-void twl6035_init_settings(void);
-int twl6035_mmc1_poweron_ldo(void);
+/*
+ * Functions to read and write from TPS659038/TWL6035/TWL6037
+ * or other Palmas family of TI PMICs
+ */
+static inline int palmas_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
+{
+	return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
+{
+	return i2c_read(chip_no, reg, 1, val, 1);
+}
+
+void palmas_init_settings(void);
+int palmas_mmc1_poweron_ldo(void);
+
+#endif /* PALMAS_H */
diff --git a/include/phy.h b/include/phy.h
index 58ca273..75bf3b4 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -52,6 +52,7 @@
 	PHY_INTERFACE_MODE_MII,
 	PHY_INTERFACE_MODE_GMII,
 	PHY_INTERFACE_MODE_SGMII,
+	PHY_INTERFACE_MODE_QSGMII,
 	PHY_INTERFACE_MODE_TBI,
 	PHY_INTERFACE_MODE_RMII,
 	PHY_INTERFACE_MODE_RGMII,
@@ -67,6 +68,7 @@
 	[PHY_INTERFACE_MODE_MII]		= "mii",
 	[PHY_INTERFACE_MODE_GMII]		= "gmii",
 	[PHY_INTERFACE_MODE_SGMII]		= "sgmii",
+	[PHY_INTERFACE_MODE_QSGMII]		= "qsgmii",
 	[PHY_INTERFACE_MODE_TBI]		= "tbi",
 	[PHY_INTERFACE_MODE_RMII]		= "rmii",
 	[PHY_INTERFACE_MODE_RGMII]		= "rgmii",
@@ -223,6 +225,7 @@
 int phy_atheros_init(void);
 int phy_broadcom_init(void);
 int phy_davicom_init(void);
+int phy_et1011c_init(void);
 int phy_lxt_init(void);
 int phy_marvell_init(void);
 int phy_micrel_init(void);
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 2db4784..c0f8cc8 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -175,7 +175,7 @@
 #define IM_IMMR		(IM_REGBASE+0x01a8)
 #define IM_SCCR		(IM_REGBASE+0x0c80)
 
-#elif defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8220)
+#elif defined(CONFIG_MPC5xxx)
 
 #define HID0_ICE_BITPOS	16
 #define HID0_DCE_BITPOS	17
diff --git a/include/spl.h b/include/spl.h
index b40be80..4bc1dd1 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -44,7 +44,6 @@
 #define SPL_COPY_PAYLOAD_ONLY	1
 
 extern struct spl_image_info spl_image;
-extern u32 *boot_params_ptr;
 
 /* SPL common functions */
 void preloader_console_init(void);
diff --git a/include/twl4030.h b/include/twl4030.h
index 5aa1841..569ad27 100644
--- a/include/twl4030.h
+++ b/include/twl4030.h
@@ -638,12 +638,12 @@
  *   examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and
  *   TWL4030_LED_LEDEN.
  */
-static inline int twl4030_i2c_write_u8(u8 chip_no, u8 val, u8 reg)
+static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
 {
 	return i2c_write(chip_no, reg, 1, &val, 1);
 }
 
-static inline int twl4030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg)
+static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
 {
 	return i2c_read(chip_no, reg, 1, val, 1);
 }
diff --git a/include/twl6030.h b/include/twl6030.h
index a9fcadb..029b21f 100644
--- a/include/twl6030.h
+++ b/include/twl6030.h
@@ -21,6 +21,9 @@
  * MA 02111-1307 USA
  */
 
+#ifndef TWL6030_H
+#define TWL6030_H
+
 #include <common.h>
 #include <i2c.h>
 
@@ -126,6 +129,17 @@
 #define GPCH0_LSB	0x57
 #define GPCH0_MSB	0x58
 
+/* Functions to read and write from TWL6030 */
+static inline int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
+{
+	return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int twl6030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
+{
+	return i2c_read(chip_no, reg, 1, val, 1);
+}
+
 void twl6030_init_battery_charging(void);
 void twl6030_usb_device_settings(void);
 void twl6030_start_usb_charging(void);
@@ -133,3 +147,5 @@
 int twl6030_get_battery_voltage(void);
 int twl6030_get_battery_current(void);
 void twl6030_power_mmc_init(void);
+
+#endif /* TWL6030_H */
diff --git a/include/usb.h b/include/usb.h
index d79c865..d7b082d 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -76,6 +76,12 @@
 	unsigned char	act_altsetting;
 
 	struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
+	/*
+	 * Super Speed Device will have Super Speed Endpoint
+	 * Companion Descriptor  (section 9.6.7 of usb 3.0 spec)
+	 * Revision 1.0 June 6th 2011
+	 */
+	struct usb_ss_ep_comp_descriptor ss_ep_comp_desc[USB_MAXENDPOINTS];
 } __attribute__ ((packed));
 
 /* Configuration information.. */
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index a1438d6..29b136d 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -277,10 +277,4 @@
 /* Board-specific initialization */
 int board_ehci_hcd_init(int port);
 
-/* CPU-specific abstracted-out IOMUX init */
-#ifdef CONFIG_MX51
-void setup_iomux_usb_h1(void);
-void setup_iomux_usb_h2(void);
-#endif
-
 #endif /* _EHCI_FSL_H */
diff --git a/include/usb_defs.h b/include/usb_defs.h
index 9502544..4f3601a 100644
--- a/include/usb_defs.h
+++ b/include/usb_defs.h
@@ -150,6 +150,18 @@
 #define USB_REQ_SET_IDLE            0x0A
 #define USB_REQ_SET_PROTOCOL        0x0B
 
+/* Device features */
+#define USB_FEAT_HALT               0x00
+#define USB_FEAT_WAKEUP             0x01
+#define USB_FEAT_TEST               0x02
+
+/* Test modes */
+#define USB_TEST_MODE_J             0x01
+#define USB_TEST_MODE_K             0x02
+#define USB_TEST_MODE_SE0_NAK       0x03
+#define USB_TEST_MODE_PACKET        0x04
+#define USB_TEST_MODE_FORCE_ENABLE  0x05
+
 
 /* "pipe" definitions */
 
@@ -208,6 +220,18 @@
 #define USB_PORT_FEAT_C_SUSPEND      18
 #define USB_PORT_FEAT_C_OVER_CURRENT 19
 #define USB_PORT_FEAT_C_RESET        20
+#define USB_PORT_FEAT_TEST           21
+
+/*
+ * Changes to Port feature numbers for Super speed,
+ * from USB 3.0 spec Table 10-8
+ */
+#define USB_SS_PORT_FEAT_U1_TIMEOUT	23
+#define USB_SS_PORT_FEAT_U2_TIMEOUT	24
+#define USB_SS_PORT_FEAT_C_LINK_STATE	25
+#define USB_SS_PORT_FEAT_C_CONFIG_ERROR	26
+#define USB_SS_PORT_FEAT_BH_RESET	28
+#define USB_SS_PORT_FEAT_C_BH_RESET	29
 
 /* wPortStatus bits */
 #define USB_PORT_STAT_CONNECTION    0x0001
@@ -218,9 +242,19 @@
 #define USB_PORT_STAT_POWER         0x0100
 #define USB_PORT_STAT_LOW_SPEED     0x0200
 #define USB_PORT_STAT_HIGH_SPEED    0x0400	/* support for EHCI */
-#define USB_PORT_STAT_SPEED	\
+#define USB_PORT_STAT_SUPER_SPEED   0x0600	/* faking support to XHCI */
+#define USB_PORT_STAT_SPEED_MASK	\
 	(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED)
 
+/*
+ * Changes to wPortStatus bit field in USB 3.0
+ * See USB 3.0 spec Table 10-11
+ */
+#define USB_SS_PORT_STAT_LINK_STATE	0x01e0
+#define USB_SS_PORT_STAT_POWER		0x0200
+#define USB_SS_PORT_STAT_SPEED		0x1c00
+#define USB_SS_PORT_STAT_SPEED_5GBPS	0x0000
+
 /* wPortChange bits */
 #define USB_PORT_STAT_C_CONNECTION  0x0001
 #define USB_PORT_STAT_C_ENABLE      0x0002
@@ -228,13 +262,21 @@
 #define USB_PORT_STAT_C_OVERCURRENT 0x0008
 #define USB_PORT_STAT_C_RESET       0x0010
 
+/*
+ * Changes to wPortChange bit fields in USB 3.0
+ * See USB 3.0 spec Table 10-12
+ */
+#define USB_SS_PORT_STAT_C_BH_RESET	0x0020
+#define USB_SS_PORT_STAT_C_LINK_STATE	0x0040
+#define USB_SS_PORT_STAT_C_CONFIG_ERROR	0x0080
+
 /* wHubCharacteristics (masks) */
 #define HUB_CHAR_LPSM               0x0003
 #define HUB_CHAR_COMPOUND           0x0004
 #define HUB_CHAR_OCPM               0x0018
 
 /*
- *Hub Status & Hub Change bit masks
+ * Hub Status & Hub Change bit masks
  */
 #define HUB_STATUS_LOCAL_POWER	0x0001
 #define HUB_STATUS_OVERCURRENT	0x0002
diff --git a/include/watchdog.h b/include/watchdog.h
index 97ec186..d95e4b1 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -108,8 +108,7 @@
 	void reset_4xx_watchdog(void);
 #endif
 
-/* Freescale i.MX */
-#if defined(CONFIG_IMX_WATCHDOG) && !defined(__ASSEMBLY__)
+#if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__)
 	void hw_watchdog_init(void);
 #endif
 #endif /* _WATCHDOG_H_ */
diff --git a/include/xilinx.h b/include/xilinx.h
index 5f25b7a..9a64771 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -27,28 +27,6 @@
 #ifndef _XILINX_H_
 #define _XILINX_H_
 
-/* Xilinx Model definitions
- *********************************************************************/
-#define CONFIG_SYS_SPARTAN2			CONFIG_SYS_FPGA_DEV( 0x1 )
-#define CONFIG_SYS_VIRTEX_E			CONFIG_SYS_FPGA_DEV( 0x2 )
-#define CONFIG_SYS_VIRTEX2			CONFIG_SYS_FPGA_DEV( 0x4 )
-#define CONFIG_SYS_SPARTAN3			CONFIG_SYS_FPGA_DEV( 0x8 )
-#define CONFIG_SYS_XILINX_SPARTAN2	(CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN2)
-#define CONFIG_SYS_XILINX_VIRTEX_E	(CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX_E)
-#define CONFIG_SYS_XILINX_VIRTEX2	(CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX2)
-#define CONFIG_SYS_XILINX_SPARTAN3	(CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN3)
-/* XXX - Add new models here */
-
-
-/* Xilinx Interface definitions
- *********************************************************************/
-#define CONFIG_SYS_XILINX_IF_SS	CONFIG_SYS_FPGA_IF( 0x1 )	/* slave serial		*/
-#define CONFIG_SYS_XILINX_IF_MS	CONFIG_SYS_FPGA_IF( 0x2 )	/* master serial	*/
-#define CONFIG_SYS_XILINX_IF_SP	CONFIG_SYS_FPGA_IF( 0x4 )	/* slave parallel	*/
-#define CONFIG_SYS_XILINX_IF_JTAG	CONFIG_SYS_FPGA_IF( 0x8 )	/* jtag			*/
-#define CONFIG_SYS_XILINX_IF_MSM	CONFIG_SYS_FPGA_IF( 0x10 )	/* master selectmap	*/
-#define CONFIG_SYS_XILINX_IF_SSM	CONFIG_SYS_FPGA_IF( 0x20 )	/* slave selectmap	*/
-
 /* Xilinx types
  *********************************************************************/
 typedef enum {			/* typedef Xilinx_iface */
@@ -59,6 +37,7 @@
 	jtag_mode,		/* jtag/tap serial (not used ) */
 	master_selectmap,	/* master SelectMap (virtex2)           */
 	slave_selectmap,	/* slave SelectMap (virtex2)            */
+	devcfg,			/* devcfg interface (zynq) */
 	max_xilinx_iface_type	/* insert all new types before this */
 } Xilinx_iface;			/* end, typedef Xilinx_iface */
 
@@ -68,6 +47,7 @@
 	Xilinx_VirtexE,		/* Virtex-E Family */
 	Xilinx_Virtex2,		/* Virtex2 Family */
 	Xilinx_Spartan3,	/* Spartan-III Family */
+	xilinx_zynq,		/* Zynq Family */
 	max_xilinx_type		/* insert all new types before this */
 } Xilinx_Family;		/* end, typedef Xilinx_Family */
 
@@ -77,6 +57,7 @@
 	size_t size;		/* bytes of data part can accept */
 	void *iface_fns;	/* interface function table */
 	int cookie;		/* implementation specific cookie */
+	char *name;		/* device name in bitstream */
 } Xilinx_desc;			/* end, typedef Xilinx_desc */
 
 /* Generic Xilinx Functions
diff --git a/include/zynqpl.h b/include/zynqpl.h
new file mode 100644
index 0000000..0247ef6
--- /dev/null
+++ b/include/zynqpl.h
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2012-2013, Xilinx, Michal Simek
+ *
+ * (C) Copyright 2012
+ * Joe Hershberger <joe.hershberger@ni.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ZYNQPL_H_
+#define _ZYNQPL_H_
+
+#include <xilinx.h>
+
+extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size);
+extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+extern int zynq_info(Xilinx_desc *desc);
+
+#define XILINX_ZYNQ_7010	0x2
+#define XILINX_ZYNQ_7020	0x7
+#define XILINX_ZYNQ_7030	0xc
+#define XILINX_ZYNQ_7045	0x11
+
+/* Device Image Sizes */
+#define XILINX_XC7Z010_SIZE	16669920/8
+#define XILINX_XC7Z020_SIZE	32364512/8
+#define XILINX_XC7Z030_SIZE	47839328/8
+#define XILINX_XC7Z045_SIZE	106571232/8
+
+/* Descriptor Macros */
+#define XILINX_XC7Z010_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
+
+#define XILINX_XC7Z020_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }
+
+#define XILINX_XC7Z030_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, "7z030" }
+
+#define XILINX_XC7Z045_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }
+
+#endif /* _ZYNQPL_H_ */
diff --git a/lib/Makefile b/lib/Makefile
index 8f81862..5d58609 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -55,6 +55,7 @@
 COBJS-y	+= strmhz.o
 COBJS-$(CONFIG_TPM) += tpm.o
 COBJS-$(CONFIG_RBTREE)	+= rbtree.o
+COBJS-$(CONFIG_BITREVERSE) += bitrev.o
 endif
 
 ifdef CONFIG_SPL_BUILD
diff --git a/lib/bitrev.c b/lib/bitrev.c
new file mode 100644
index 0000000..160021a
--- /dev/null
+++ b/lib/bitrev.c
@@ -0,0 +1,59 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Based on bitrev from the Linux kernel, by Akinobu Mita
+ */
+
+
+#include <linux/types.h>
+#include <linux/bitrev.h>
+
+const u8 byte_rev_table[256] = {
+	0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
+	0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
+	0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
+	0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
+	0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
+	0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
+	0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
+	0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
+	0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
+	0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
+	0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
+	0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
+	0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
+	0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
+	0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
+	0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
+	0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
+	0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
+	0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
+	0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
+	0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
+	0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
+	0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
+	0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
+	0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
+	0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
+	0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
+	0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
+	0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
+	0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
+	0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
+	0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
+};
+
+u16 bitrev16(u16 x)
+{
+	return (bitrev8(x & 0xff) << 8) | bitrev8(x >> 8);
+}
+
+/**
+ * bitrev32 - reverse the order of bits in a u32 value
+ * @x: value to be bit-reversed
+ */
+u32 bitrev32(u32 x)
+{
+	return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16);
+}
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index ac1fe0b..005ad3d 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -66,6 +66,7 @@
 	COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
 	COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"),
 	COMPAT(INFINEON_SLB9635_TPM, "infineon,slb9635-tpm"),
+	COMPAT(INFINEON_SLB9645_TPM, "infineon,slb9645-tpm"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
diff --git a/lib/hashtable.c b/lib/hashtable.c
index 6050dd0..4cdbc95 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -901,6 +901,12 @@
 		*sp++ = '\0';	/* terminate value */
 		++dp;
 
+		if (*name == 0) {
+			debug("INSERT: unable to use an empty key\n");
+			__set_errno(EINVAL);
+			return 0;
+		}
+
 		/* Skip variables which are not supposed to be processed */
 		if (!drop_var_from_set(name, nvars, localvars))
 			continue;
diff --git a/lib/libfdt/fdt.c b/lib/libfdt/fdt.c
index 387e354..154e9a4 100644
--- a/lib/libfdt/fdt.c
+++ b/lib/libfdt/fdt.c
@@ -202,6 +202,34 @@
 	return offset;
 }
 
+int fdt_first_subnode(const void *fdt, int offset)
+{
+	int depth = 0;
+
+	offset = fdt_next_node(fdt, offset, &depth);
+	if (offset < 0 || depth != 1)
+		return -FDT_ERR_NOTFOUND;
+
+	return offset;
+}
+
+int fdt_next_subnode(const void *fdt, int offset)
+{
+	int depth = 1;
+
+	/*
+	 * With respect to the parent, the depth of the next subnode will be
+	 * the same as the last.
+	 */
+	do {
+		offset = fdt_next_node(fdt, offset, &depth);
+		if (offset < 0 || depth < 1)
+			return -FDT_ERR_NOTFOUND;
+	} while (depth > 1);
+
+	return offset;
+}
+
 const char *_fdt_find_string(const char *strtab, int tabsize, const char *s)
 {
 	int len = strlen(s) + 1;
diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c
index 1a461c3..b65f4e2 100644
--- a/lib/libfdt/fdt_ro.c
+++ b/lib/libfdt/fdt_ro.c
@@ -519,8 +519,7 @@
 	return offset; /* error from fdt_next_node() */
 }
 
-static int _fdt_stringlist_contains(const char *strlist, int listlen,
-				    const char *str)
+int fdt_stringlist_contains(const char *strlist, int listlen, const char *str)
 {
 	int len = strlen(str);
 	const char *p;
@@ -546,7 +545,7 @@
 	prop = fdt_getprop(fdt, nodeoffset, "compatible", &len);
 	if (!prop)
 		return len;
-	if (_fdt_stringlist_contains(prop, len, compatible))
+	if (fdt_stringlist_contains(prop, len, compatible))
 		return 0;
 	else
 		return 1;
diff --git a/lib/string.c b/lib/string.c
index 09dfae0..3a82efa 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -617,3 +617,62 @@
 }
 
 #endif
+#ifndef __HAVE_ARCH_MEMCHR_INV
+static void *check_bytes8(const u8 *start, u8 value, unsigned int bytes)
+{
+	while (bytes) {
+		if (*start != value)
+			return (void *)start;
+		start++;
+		bytes--;
+	}
+	return NULL;
+}
+/**
+ * memchr_inv - Find an unmatching character in an area of memory.
+ * @start: The memory area
+ * @c: Find a character other than c
+ * @bytes: The size of the area.
+ *
+ * returns the address of the first character other than @c, or %NULL
+ * if the whole buffer contains just @c.
+ */
+void *memchr_inv(const void *start, int c, size_t bytes)
+{
+	u8 value = c;
+	u64 value64;
+	unsigned int words, prefix;
+
+	if (bytes <= 16)
+		return check_bytes8(start, value, bytes);
+
+	value64 = value;
+	value64 |= value64 << 8;
+	value64 |= value64 << 16;
+	value64 |= value64 << 32;
+
+	prefix = (unsigned long)start % 8;
+	if (prefix) {
+		u8 *r;
+
+		prefix = 8 - prefix;
+		r = check_bytes8(start, value, prefix);
+		if (r)
+			return r;
+		start += prefix;
+		bytes -= prefix;
+	}
+
+	words = bytes / 8;
+
+	while (words) {
+		if (*(u64 *)start != value64)
+			return check_bytes8(start, value, 8);
+		start += 8;
+		words--;
+	}
+
+	return check_bytes8(start, value, bytes % 8);
+}
+#endif
+
diff --git a/spl/Makefile b/spl/Makefile
index b5a8de7..8b655c4 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -88,12 +88,20 @@
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
+endif
+
 ifneq ($(CONFIG_TEGRA),)
 LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
 LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
 LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
 endif
 
+ifneq ($(CONFIG_MX23)$(CONFIG_MX35),)
+LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
+endif
+
 # Add GCC lib
 ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
 PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o
diff --git a/test/image/test-fit.py b/test/image/test-fit.py
new file mode 100755
index 0000000..c4e8211
--- /dev/null
+++ b/test/image/test-fit.py
@@ -0,0 +1,422 @@
+#!/usr/bin/python
+#
+# Copyright (c) 2013, Google Inc.
+#
+# Sanity check of the FIT handling in U-Boot
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# To run this:
+#
+# make O=sandbox sandbox_config
+# make O=sandbox
+# ./test/image/test-fit.py -u sandbox/u-boot
+
+import doctest
+from optparse import OptionParser
+import os
+import shutil
+import struct
+import sys
+import tempfile
+
+# The 'command' library in patman is convenient for running commands
+base_path = os.path.dirname(sys.argv[0])
+patman = os.path.join(base_path, '../../tools/patman')
+sys.path.append(patman)
+
+import command
+
+# Define a base ITS which we can adjust using % and a dictionary
+base_its = '''
+/dts-v1/;
+
+/ {
+        description = "Chrome OS kernel image with one or more FDT blobs";
+        #address-cells = <1>;
+
+        images {
+                kernel@1 {
+                        data = /incbin/("%(kernel)s");
+                        type = "kernel";
+                        arch = "sandbox";
+                        os = "linux";
+                        compression = "none";
+                        load = <0x40000>;
+                        entry = <0x8>;
+                };
+                fdt@1 {
+                        description = "snow";
+                        data = /incbin/("u-boot.dtb");
+                        type = "flat_dt";
+                        arch = "sandbox";
+                        %(fdt_load)s
+                        compression = "none";
+                        signature@1 {
+                                algo = "sha1,rsa2048";
+                                key-name-hint = "dev";
+                        };
+                };
+                ramdisk@1 {
+                        description = "snow";
+                        data = /incbin/("%(ramdisk)s");
+                        type = "ramdisk";
+                        arch = "sandbox";
+                        os = "linux";
+                        %(ramdisk_load)s
+                        compression = "none";
+                };
+        };
+        configurations {
+                default = "conf@1";
+                conf@1 {
+                        kernel = "kernel@1";
+                        fdt = "fdt@1";
+                        %(ramdisk_config)s
+                };
+        };
+};
+'''
+
+# Define a base FDT - currently we don't use anything in this
+base_fdt = '''
+/dts-v1/;
+
+/ {
+        model = "Sandbox Verified Boot Test";
+        compatible = "sandbox";
+
+};
+'''
+
+# This is the U-Boot script that is run for each test. First load the fit,
+# then do the 'bootm' command, then save out memory from the places where
+# we expect 'bootm' to write things. Then quit.
+base_script = '''
+sb load host 0 %(fit_addr)x %(fit)s
+fdt addr %(fit_addr)x
+bootm start %(fit_addr)x
+bootm loados
+sb save host 0 %(kernel_out)s %(kernel_addr)x %(kernel_size)x
+sb save host 0 %(fdt_out)s %(fdt_addr)x %(fdt_size)x
+sb save host 0 %(ramdisk_out)s %(ramdisk_addr)x %(ramdisk_size)x
+reset
+'''
+
+def make_fname(leaf):
+    """Make a temporary filename
+
+    Args:
+        leaf: Leaf name of file to create (within temporary directory)
+    Return:
+        Temporary filename
+    """
+    global base_dir
+
+    return os.path.join(base_dir, leaf)
+
+def filesize(fname):
+    """Get the size of a file
+
+    Args:
+        fname: Filename to check
+    Return:
+        Size of file in bytes
+    """
+    return os.stat(fname).st_size
+
+def read_file(fname):
+    """Read the contents of a file
+
+    Args:
+        fname: Filename to read
+    Returns:
+        Contents of file as a string
+    """
+    with open(fname, 'r') as fd:
+        return fd.read()
+
+def make_dtb():
+    """Make a sample .dts file and compile it to a .dtb
+
+    Returns:
+        Filename of .dtb file created
+    """
+    src = make_fname('u-boot.dts')
+    dtb = make_fname('u-boot.dtb')
+    with open(src, 'w') as fd:
+        print >>fd, base_fdt
+    command.Output('dtc', src, '-O', 'dtb', '-o', dtb)
+    return dtb
+
+def make_its(params):
+    """Make a sample .its file with parameters embedded
+
+    Args:
+        params: Dictionary containing parameters to embed in the %() strings
+    Returns:
+        Filename of .its file created
+    """
+    its = make_fname('test.its')
+    with open(its, 'w') as fd:
+        print >>fd, base_its % params
+    return its
+
+def make_fit(mkimage, params):
+    """Make a sample .fit file ready for loading
+
+    This creates a .its script with the selected parameters and uses mkimage to
+    turn this into a .fit image.
+
+    Args:
+        mkimage: Filename of 'mkimage' utility
+        params: Dictionary containing parameters to embed in the %() strings
+    Return:
+        Filename of .fit file created
+    """
+    fit = make_fname('test.fit')
+    its = make_its(params)
+    command.Output(mkimage, '-f', its, fit)
+    with open(make_fname('u-boot.dts'), 'w') as fd:
+        print >>fd, base_fdt
+    return fit
+
+def make_kernel():
+    """Make a sample kernel with test data
+
+    Returns:
+        Filename of kernel created
+    """
+    fname = make_fname('test-kernel.bin')
+    data = ''
+    for i in range(100):
+        data += 'this kernel %d is unlikely to boot\n' % i
+    with open(fname, 'w') as fd:
+        print >>fd, data
+    return fname
+
+def make_ramdisk():
+    """Make a sample ramdisk with test data
+
+    Returns:
+        Filename of ramdisk created
+    """
+    fname = make_fname('test-ramdisk.bin')
+    data = ''
+    for i in range(100):
+        data += 'ramdisk %d was seldom used in the middle ages\n' % i
+    with open(fname, 'w') as fd:
+        print >>fd, data
+    return fname
+
+def find_matching(text, match):
+    """Find a match in a line of text, and return the unmatched line portion
+
+    This is used to extract a part of a line from some text. The match string
+    is used to locate the line - we use the first line that contains that
+    match text.
+
+    Once we find a match, we discard the match string itself from the line,
+    and return what remains.
+
+    TODO: If this function becomes more generally useful, we could change it
+    to use regex and return groups.
+
+    Args:
+        text: Text to check (each line separated by \n)
+        match: String to search for
+    Return:
+        String containing unmatched portion of line
+    Exceptions:
+        ValueError: If match is not found
+
+    >>> find_matching('first line:10\\nsecond_line:20', 'first line:')
+    '10'
+    >>> find_matching('first line:10\\nsecond_line:20', 'second linex')
+    Traceback (most recent call last):
+      ...
+    ValueError: Test aborted
+    >>> find_matching('first line:10\\nsecond_line:20', 'second_line:')
+    '20'
+    """
+    for line in text.splitlines():
+        pos = line.find(match)
+        if pos != -1:
+            return line[:pos] + line[pos + len(match):]
+
+    print "Expected '%s' but not found in output:"
+    print text
+    raise ValueError('Test aborted')
+
+def set_test(name):
+    """Set the name of the current test and print a message
+
+    Args:
+        name: Name of test
+    """
+    global test_name
+
+    test_name = name
+    print name
+
+def fail(msg):
+    """Raise an error with a helpful failure message
+
+    Args:
+        msg: Message to display
+    """
+    raise ValueError("Test '%s' failed: %s" % (test_name, msg))
+
+def run_fit_test(mkimage, u_boot):
+    """Basic sanity check of FIT loading in U-Boot
+
+    TODO: Almost everything:
+       - hash algorithms - invalid hash/contents should be detected
+       - signature algorithms - invalid sig/contents should be detected
+       - compression
+       - checking that errors are detected like:
+            - image overwriting
+            - missing images
+            - invalid configurations
+            - incorrect os/arch/type fields
+            - empty data
+            - images too large/small
+            - invalid FDT (e.g. putting a random binary in instead)
+       - default configuration selection
+       - bootm command line parameters should have desired effect
+       - run code coverage to make sure we are testing all the code
+    """
+    global test_name
+
+    # Set up invariant files
+    control_dtb = make_dtb()
+    kernel = make_kernel()
+    ramdisk = make_ramdisk()
+    kernel_out = make_fname('kernel-out.bin')
+    fdt_out = make_fname('fdt-out.dtb')
+    ramdisk_out = make_fname('ramdisk-out.bin')
+
+    # Set up basic parameters with default values
+    params = {
+        'fit_addr' : 0x1000,
+
+        'kernel' : kernel,
+        'kernel_out' : kernel_out,
+        'kernel_addr' : 0x40000,
+        'kernel_size' : filesize(kernel),
+
+        'fdt_out' : fdt_out,
+        'fdt_addr' : 0x80000,
+        'fdt_size' : filesize(control_dtb),
+        'fdt_load' : '',
+
+        'ramdisk' : ramdisk,
+        'ramdisk_out' : ramdisk_out,
+        'ramdisk_addr' : 0xc0000,
+        'ramdisk_size' : filesize(ramdisk),
+        'ramdisk_load' : '',
+        'ramdisk_config' : '',
+    }
+
+    # Make a basic FIT and a script to load it
+    fit = make_fit(mkimage, params)
+    params['fit'] = fit
+    cmd = base_script % params
+
+    # First check that we can load a kernel
+    # We could perhaps reduce duplication with some loss of readability
+    set_test('Kernel load')
+    stdout = command.Output(u_boot, '-d', control_dtb, '-c', cmd)
+    if read_file(kernel) != read_file(kernel_out):
+        fail('Kernel not loaded')
+    if read_file(control_dtb) == read_file(fdt_out):
+        fail('FDT loaded but should be ignored')
+    if read_file(ramdisk) == read_file(ramdisk_out):
+        fail('Ramdisk loaded but should not be')
+
+    # Find out the offset in the FIT where U-Boot has found the FDT
+    line = find_matching(stdout, 'Booting using the fdt blob at ')
+    fit_offset = int(line, 16) - params['fit_addr']
+    fdt_magic = struct.pack('>L', 0xd00dfeed)
+    data = read_file(fit)
+
+    # Now find where it actually is in the FIT (skip the first word)
+    real_fit_offset = data.find(fdt_magic, 4)
+    if fit_offset != real_fit_offset:
+        fail('U-Boot loaded FDT from offset %#x, FDT is actually at %#x' %
+                (fit_offset, real_fit_offset))
+
+    # Now a kernel and an FDT
+    set_test('Kernel + FDT load')
+    params['fdt_load'] = 'load = <%#x>;' % params['fdt_addr']
+    fit = make_fit(mkimage, params)
+    stdout = command.Output(u_boot, '-d', control_dtb, '-c', cmd)
+    if read_file(kernel) != read_file(kernel_out):
+        fail('Kernel not loaded')
+    if read_file(control_dtb) != read_file(fdt_out):
+        fail('FDT not loaded')
+    if read_file(ramdisk) == read_file(ramdisk_out):
+        fail('Ramdisk loaded but should not be')
+
+    # Try a ramdisk
+    set_test('Kernel + FDT + Ramdisk load')
+    params['ramdisk_config'] = 'ramdisk = "ramdisk@1";'
+    params['ramdisk_load'] = 'load = <%#x>;' % params['ramdisk_addr']
+    fit = make_fit(mkimage, params)
+    stdout = command.Output(u_boot, '-d', control_dtb, '-c', cmd)
+    if read_file(ramdisk) != read_file(ramdisk_out):
+        fail('Ramdisk not loaded')
+
+def run_tests():
+    """Parse options, run the FIT tests and print the result"""
+    global base_path, base_dir
+
+    # Work in a temporary directory
+    base_dir = tempfile.mkdtemp()
+    parser = OptionParser()
+    parser.add_option('-u', '--u-boot',
+            default=os.path.join(base_path, 'u-boot'),
+            help='Select U-Boot sandbox binary')
+    parser.add_option('-k', '--keep', action='store_true',
+            help="Don't delete temporary directory even when tests pass")
+    parser.add_option('-t', '--selftest', action='store_true',
+            help='Run internal self tests')
+    (options, args) = parser.parse_args()
+
+    # Find the path to U-Boot, and assume mkimage is in its tools/mkimage dir
+    base_path = os.path.dirname(options.u_boot)
+    mkimage = os.path.join(base_path, 'tools/mkimage')
+
+    # There are a few doctests - handle these here
+    if options.selftest:
+        doctest.testmod()
+        return
+
+    title = 'FIT Tests'
+    print title, '\n', '=' * len(title)
+
+    run_fit_test(mkimage, options.u_boot)
+
+    print '\nTests passed'
+    print 'Caveat: this is only a sanity check - test coverage is poor'
+
+    # Remove the tempoerary directory unless we are asked to keep it
+    if options.keep:
+        print "Output files are in '%s'" % base_dir
+    else:
+        shutil.rmtree(base_dir)
+
+run_tests()
diff --git a/tools/Makefile b/tools/Makefile
index 889c897..26eb500 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -78,6 +78,7 @@
 # Source files which exist outside the tools directory
 EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o
 EXT_OBJ_FILES-y += common/image.o
+EXT_OBJ_FILES-$(CONFIG_FIT) += common/image-fit.o
 EXT_OBJ_FILES-y += lib/crc32.o
 EXT_OBJ_FILES-y += lib/md5.o
 EXT_OBJ_FILES-y += lib/sha1.o
@@ -95,6 +96,7 @@
 NOPED_OBJ_FILES-y += kwbimage.o
 NOPED_OBJ_FILES-y += pblimage.o
 NOPED_OBJ_FILES-y += imximage.o
+NOPED_OBJ_FILES-y += image-host.o
 NOPED_OBJ_FILES-y += omapimage.o
 NOPED_OBJ_FILES-y += mkenvimage.o
 NOPED_OBJ_FILES-y += mkimage.o
@@ -209,7 +211,9 @@
 			$(obj)crc32.o \
 			$(obj)default_image.o \
 			$(obj)fit_image.o \
+			$(obj)image-fit.o \
 			$(obj)image.o \
+			$(obj)image-host.o \
 			$(obj)imximage.o \
 			$(obj)kwbimage.o \
 			$(obj)pblimage.o \
diff --git a/tools/aisimage.c b/tools/aisimage.c
index c645708..659df8c 100644
--- a/tools/aisimage.c
+++ b/tools/aisimage.c
@@ -32,7 +32,6 @@
 #define WORD_ALIGN0	4
 #define WORD_ALIGN(len) (((len)+WORD_ALIGN0-1) & ~(WORD_ALIGN0-1))
 #define MAX_CMD_BUFFER	4096
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 
 static uint32_t ais_img_size;
 
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 8d7b9b5..4319ce7 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -111,6 +111,10 @@
             print col.Color(col.RED, str)
             sys.exit(1)
         count = gitutil.CountCommitsInBranch(options.git_dir, options.branch)
+        if count is None:
+            str = "Branch '%s' not found or has no upstream" % options.branch
+            print col.Color(col.RED, str)
+            sys.exit(1)
         count += 1   # Build upstream commit also
 
     if not count:
@@ -137,6 +141,11 @@
     upstream_commit = gitutil.GetUpstream(options.git_dir, options.branch)
     series = patchstream.GetMetaDataForList(upstream_commit, options.git_dir,
             1)
+    # Conflicting tags are not a problem for buildman, since it does not use
+    # them. For example, Series-version is not useful for buildman. On the
+    # other hand conflicting tags will cause an error. So allow later tags
+    # to overwrite earlier ones.
+    series.allow_overwrite = True
     series = patchstream.GetMetaDataForList(range_expr, options.git_dir, None,
             series)
 
diff --git a/tools/checkpatch.pl b/tools/checkpatch.pl
index 9f23901..896e2bc 100755
--- a/tools/checkpatch.pl
+++ b/tools/checkpatch.pl
@@ -273,6 +273,7 @@
 	WARN(?:_RATELIMIT|_ONCE|)|
 	panic|
 	debug|
+	printf|
 	MODULE_[A-Z_]+
 )};
 
diff --git a/tools/fit_image.c b/tools/fit_image.c
index 76bbba1..cc123dd 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -47,6 +47,48 @@
 		return EXIT_FAILURE;
 }
 
+int mmap_fdt(struct mkimage_params *params, const char *fname, void **blobp,
+		struct stat *sbuf)
+{
+	void *ptr;
+	int fd;
+
+	/* Load FIT blob into memory (we need to write hashes/signatures) */
+	fd = open(fname, O_RDWR | O_BINARY);
+
+	if (fd < 0) {
+		fprintf(stderr, "%s: Can't open %s: %s\n",
+			params->cmdname, fname, strerror(errno));
+		unlink(fname);
+		return -1;
+	}
+
+	if (fstat(fd, sbuf) < 0) {
+		fprintf(stderr, "%s: Can't stat %s: %s\n",
+			params->cmdname, fname, strerror(errno));
+		unlink(fname);
+		return -1;
+	}
+
+	ptr = mmap(0, sbuf->st_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
+	if (ptr == MAP_FAILED) {
+		fprintf(stderr, "%s: Can't read %s: %s\n",
+			params->cmdname, fname, strerror(errno));
+		unlink(fname);
+		return -1;
+	}
+
+	/* check if ptr has a valid blob */
+	if (fdt_check_header(ptr)) {
+		fprintf(stderr, "%s: Invalid FIT blob\n", params->cmdname);
+		unlink(fname);
+		return -1;
+	}
+
+	*blobp = ptr;
+	return fd;
+}
+
 /**
  * fit_handle_file - main FIT file processing function
  *
@@ -65,7 +107,7 @@
 	char cmd[MKIMAGE_MAX_DTC_CMDLINE_LEN];
 	int tfd;
 	struct stat sbuf;
-	unsigned char *ptr;
+	void *ptr;
 
 	/* Flattened Image Tree (FIT) format  handling */
 	debug ("FIT format handling\n");
@@ -87,57 +129,25 @@
 	if (system (cmd) == -1) {
 		fprintf (stderr, "%s: system(%s) failed: %s\n",
 				params->cmdname, cmd, strerror(errno));
-		unlink (tmpfile);
-		return (EXIT_FAILURE);
+		goto err_system;
 	}
 
-	/* load FIT blob into memory */
-	tfd = open (tmpfile, O_RDWR|O_BINARY);
-
-	if (tfd < 0) {
-		fprintf (stderr, "%s: Can't open %s: %s\n",
-				params->cmdname, tmpfile, strerror(errno));
-		unlink (tmpfile);
-		return (EXIT_FAILURE);
-	}
-
-	if (fstat (tfd, &sbuf) < 0) {
-		fprintf (stderr, "%s: Can't stat %s: %s\n",
-				params->cmdname, tmpfile, strerror(errno));
-		unlink (tmpfile);
-		return (EXIT_FAILURE);
-	}
-
-	ptr = mmap (0, sbuf.st_size, PROT_READ|PROT_WRITE, MAP_SHARED,
-				tfd, 0);
-	if (ptr == MAP_FAILED) {
-		fprintf (stderr, "%s: Can't read %s: %s\n",
-				params->cmdname, tmpfile, strerror(errno));
-		unlink (tmpfile);
-		return (EXIT_FAILURE);
-	}
-
-	/* check if ptr has a valid blob */
-	if (fdt_check_header (ptr)) {
-		fprintf (stderr, "%s: Invalid FIT blob\n", params->cmdname);
-		unlink (tmpfile);
-		return (EXIT_FAILURE);
-	}
+	tfd = mmap_fdt(params, tmpfile, &ptr, &sbuf);
+	if (tfd < 0)
+		goto err_mmap;
 
 	/* set hashes for images in the blob */
-	if (fit_set_hashes (ptr)) {
+	if (fit_add_verification_data(ptr)) {
 		fprintf (stderr, "%s Can't add hashes to FIT blob",
 				params->cmdname);
-		unlink (tmpfile);
-		return (EXIT_FAILURE);
+		goto err_add_hashes;
 	}
 
 	/* add a timestamp at offset 0 i.e., root  */
 	if (fit_set_timestamp (ptr, 0, sbuf.st_mtime)) {
 		fprintf (stderr, "%s: Can't add image timestamp\n",
 				params->cmdname);
-		unlink (tmpfile);
-		return (EXIT_FAILURE);
+		goto err_add_timestamp;
 	}
 	debug ("Added timestamp successfully\n");
 
@@ -153,6 +163,14 @@
 		return (EXIT_FAILURE);
 	}
 	return (EXIT_SUCCESS);
+
+err_add_timestamp:
+err_add_hashes:
+	munmap(ptr, sbuf.st_size);
+err_mmap:
+err_system:
+	unlink(tmpfile);
+	return -1;
 }
 
 static int fit_check_params (struct mkimage_params *params)
diff --git a/tools/image-host.c b/tools/image-host.c
new file mode 100644
index 0000000..d944d0f
--- /dev/null
+++ b/tools/image-host.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "mkimage.h"
+#include <bootstage.h>
+#include <image.h>
+#include <sha1.h>
+#include <time.h>
+#include <u-boot/crc.h>
+#include <u-boot/md5.h>
+
+/**
+ * fit_set_hash_value - set hash value in requested has node
+ * @fit: pointer to the FIT format image header
+ * @noffset: hash node offset
+ * @value: hash value to be set
+ * @value_len: hash value length
+ *
+ * fit_set_hash_value() attempts to set hash value in a node at offset
+ * given and returns operation status to the caller.
+ *
+ * returns
+ *     0, on success
+ *     -1, on failure
+ */
+static int fit_set_hash_value(void *fit, int noffset, uint8_t *value,
+				int value_len)
+{
+	int ret;
+
+	ret = fdt_setprop(fit, noffset, FIT_VALUE_PROP, value, value_len);
+	if (ret) {
+		printf("Can't set hash '%s' property for '%s' node(%s)\n",
+		       FIT_VALUE_PROP, fit_get_name(fit, noffset, NULL),
+		       fdt_strerror(ret));
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * fit_image_process_hash - Process a single subnode of the images/ node
+ *
+ * Check each subnode and process accordingly. For hash nodes we generate
+ * a hash of the supplised data and store it in the node.
+ *
+ * @fit:	pointer to the FIT format image header
+ * @image_name:	name of image being processes (used to display errors)
+ * @noffset:	subnode offset
+ * @data:	data to process
+ * @size:	size of data in bytes
+ * @return 0 if ok, -1 on error
+ */
+static int fit_image_process_hash(void *fit, const char *image_name,
+		int noffset, const void *data, size_t size)
+{
+	uint8_t value[FIT_MAX_HASH_LEN];
+	const char *node_name;
+	int value_len;
+	char *algo;
+
+	node_name = fit_get_name(fit, noffset, NULL);
+
+	if (fit_image_hash_get_algo(fit, noffset, &algo)) {
+		printf("Can't get hash algo property for '%s' hash node in '%s' image node\n",
+		       node_name, image_name);
+		return -1;
+	}
+
+	if (calculate_hash(data, size, algo, value, &value_len)) {
+		printf("Unsupported hash algorithm (%s) for '%s' hash node in '%s' image node\n",
+		       algo, node_name, image_name);
+		return -1;
+	}
+
+	if (fit_set_hash_value(fit, noffset, value, value_len)) {
+		printf("Can't set hash value for '%s' hash node in '%s' image node\n",
+		       node_name, image_name);
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * fit_image_add_verification_data() - calculate/set hash data for image node
+ *
+ * This adds hash values for a component image node.
+ *
+ * All existing hash subnodes are checked, if algorithm property is set to
+ * one of the supported hash algorithms, hash value is computed and
+ * corresponding hash node property is set, for example:
+ *
+ * Input component image node structure:
+ *
+ * o image@1 (at image_noffset)
+ *   | - data = [binary data]
+ *   o hash@1
+ *     |- algo = "sha1"
+ *
+ * Output component image node structure:
+ *
+ * o image@1 (at image_noffset)
+ *   | - data = [binary data]
+ *   o hash@1
+ *     |- algo = "sha1"
+ *     |- value = sha1(data)
+ *
+ * For signature details, please see doc/uImage.FIT/signature.txt
+ *
+ * @fit:	Pointer to the FIT format image header
+ * @image_noffset: Requested component image node
+ * @return: 0 on success, <0 on failure
+ */
+int fit_image_add_verification_data(void *fit, int image_noffset)
+{
+	const char *image_name;
+	const void *data;
+	size_t size;
+	int noffset;
+
+	/* Get image data and data length */
+	if (fit_image_get_data(fit, image_noffset, &data, &size)) {
+		printf("Can't get image data/size\n");
+		return -1;
+	}
+
+	image_name = fit_get_name(fit, image_noffset, NULL);
+
+	/* Process all hash subnodes of the component image node */
+	for (noffset = fdt_first_subnode(fit, image_noffset);
+	     noffset >= 0;
+	     noffset = fdt_next_subnode(fit, noffset)) {
+		const char *node_name;
+		int ret = 0;
+
+		/*
+		 * Check subnode name, must be equal to "hash" or "signature".
+		 * Multiple hash nodes require unique unit node
+		 * names, e.g. hash@1, hash@2, signature@1, etc.
+		 */
+		node_name = fit_get_name(fit, noffset, NULL);
+		if (!strncmp(node_name, FIT_HASH_NODENAME,
+			     strlen(FIT_HASH_NODENAME))) {
+			ret = fit_image_process_hash(fit, image_name, noffset,
+						data, size);
+		}
+		if (ret)
+			return -1;
+	}
+
+	return 0;
+}
+
+int fit_add_verification_data(void *fit)
+{
+	int images_noffset;
+	int noffset;
+	int ret;
+
+	/* Find images parent node offset */
+	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
+	if (images_noffset < 0) {
+		printf("Can't find images parent node '%s' (%s)\n",
+		       FIT_IMAGES_PATH, fdt_strerror(images_noffset));
+		return images_noffset;
+	}
+
+	/* Process its subnodes, print out component images details */
+	for (noffset = fdt_first_subnode(fit, images_noffset);
+	     noffset >= 0;
+	     noffset = fdt_next_subnode(fit, noffset)) {
+		/*
+		 * Direct child node of the images parent node,
+		 * i.e. component image node.
+		 */
+		ret = fit_image_add_verification_data(fit, noffset);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
diff --git a/tools/imximage.c b/tools/imximage.c
index fa308c9..5e8e470 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -37,6 +37,7 @@
  */
 static table_entry_t imximage_cmds[] = {
 	{CMD_BOOT_FROM,         "BOOT_FROM",            "boot command",	  },
+	{CMD_BOOT_OFFSET,       "BOOT_OFFSET",          "Boot offset",	  },
 	{CMD_DATA,              "DATA",                 "Reg Write Data", },
 	{CMD_IMAGE_VERSION,     "IMAGE_VERSION",        "image version",  },
 	{-1,                    "",                     "",	          },
@@ -352,6 +353,11 @@
 		if (unlikely(cmd_ver_first != 1))
 			cmd_ver_first = 0;
 		break;
+	case CMD_BOOT_OFFSET:
+		imxhdr->flash_offset = get_cfg_value(token, name, lineno);
+		if (unlikely(cmd_ver_first != 1))
+			cmd_ver_first = 0;
+		break;
 	case CMD_DATA:
 		value = get_cfg_value(token, name, lineno);
 		(*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len);
@@ -518,11 +524,14 @@
 
 	/*
 	 * ROM bug alert
-	 * mx53 only loads 512 byte multiples.
-	 * The remaining fraction of a block bytes would
-	 * not be loaded.
+	 *
+	 * MX53 only loads 512 byte multiples in case of SD boot.
+	 * MX53 only loads NAND page multiples in case of NAND boot and
+	 * supports up to 4096 byte large pages, thus align to 4096.
+	 *
+	 * The remaining fraction of a block bytes would not be loaded!
 	 */
-	*header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 512);
+	*header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 4096);
 }
 
 int imximage_check_params(struct mkimage_params *params)
diff --git a/tools/imximage.h b/tools/imximage.h
index 42b6090..5c929e4 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -31,6 +31,11 @@
 
 #define HEADER_OFFSET	0x400
 
+/*
+ * NOTE: This file must be kept in sync with arch/arm/include/asm/\
+ *       imx-common/imximage.cfg because tools/imximage.c can not
+ *       cross-include headers from arch/arm/ and vice-versa.
+ */
 #define CMD_DATA_STR	"DATA"
 #define FLASH_OFFSET_UNDEFINED	0xFFFFFFFF
 #define FLASH_OFFSET_STANDARD	0x400
@@ -52,6 +57,7 @@
 	CMD_INVALID,
 	CMD_IMAGE_VERSION,
 	CMD_BOOT_FROM,
+	CMD_BOOT_OFFSET,
 	CMD_DATA
 };
 
@@ -151,13 +157,14 @@
 	dcd_v2_t dcd_table;
 } imx_header_v2_t;
 
+/* The header must be aligned to 4k on MX53 for NAND boot */
 struct imx_header {
 	union {
 		imx_header_v1_t hdr_v1;
 		imx_header_v2_t hdr_v2;
 	} header;
 	uint32_t flash_offset;
-};
+} __attribute__((aligned(4096)));
 
 typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
 					char *name, int lineno,
diff --git a/tools/mkimage.h b/tools/mkimage.h
index ea45f5c..03c6c8f 100644
--- a/tools/mkimage.h
+++ b/tools/mkimage.h
@@ -42,12 +42,26 @@
 #define debug(fmt,args...)
 #endif /* MKIMAGE_DEBUG */
 
+#define ARRAY_SIZE(x)		(sizeof(x) / sizeof((x)[0]))
+
+static inline void *map_sysmem(ulong paddr, unsigned long len)
+{
+	return (void *)(uintptr_t)paddr;
+}
+
+static inline ulong map_to_sysmem(void *ptr)
+{
+	return (ulong)(uintptr_t)ptr;
+}
+
 #define MKIMAGE_TMPFILE_SUFFIX		".tmp"
 #define MKIMAGE_MAX_TMPFILE_LEN		256
 #define MKIMAGE_DEFAULT_DTC_OPTIONS	"-I dts -O dtb -p 500"
 #define MKIMAGE_MAX_DTC_CMDLINE_LEN	512
 #define MKIMAGE_DTC			"dtc"   /* assume dtc is in $PATH */
 
+#define IH_ARCH_DEFAULT		IH_ARCH_INVALID
+
 /*
  * This structure defines all such variables those are initialized by
  * mkimage main core and need to be referred by image type specific
diff --git a/tools/mxsboot.c b/tools/mxsboot.c
index 6c05aa4..d92c39f 100644
--- a/tools/mxsboot.c
+++ b/tools/mxsboot.c
@@ -551,7 +551,7 @@
 
 	fsize = lseek(infd, 0, SEEK_END);
 	lseek(infd, 0, SEEK_SET);
-	size = fsize + 512;
+	size = fsize + 4 * 512;
 
 	buf = malloc(size);
 	if (!buf) {
@@ -559,7 +559,7 @@
 		goto err0;
 	}
 
-	ret = read(infd, (uint8_t *)buf + 512, fsize);
+	ret = read(infd, (uint8_t *)buf + 4 * 512, fsize);
 	if (ret != fsize) {
 		ret = -1;
 		goto err1;
@@ -574,8 +574,8 @@
 	cb->drv_info[0].chip_num = 0x0;
 	cb->drv_info[0].drive_type = 0x0;
 	cb->drv_info[0].tag = 0x1;
-	cb->drv_info[0].first_sector_number = sd_sector + 1;
-	cb->drv_info[0].sector_count = (size - 1) / 512;
+	cb->drv_info[0].first_sector_number = sd_sector + 4;
+	cb->drv_info[0].sector_count = (size - 4) / 512;
 
 	wr_size = write(outfd, buf, size);
 	if (wr_size != size) {
diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py
index e31da15..b7f6739 100644
--- a/tools/patman/gitutil.py
+++ b/tools/patman/gitutil.py
@@ -56,10 +56,14 @@
     Returns:
         Name of upstream branch (e.g. 'upstream/master') or None if none
     """
-    remote = command.OutputOneLine('git', '--git-dir', git_dir, 'config',
-            'branch.%s.remote' % branch)
-    merge = command.OutputOneLine('git', '--git-dir', git_dir, 'config',
-            'branch.%s.merge' % branch)
+    try:
+        remote = command.OutputOneLine('git', '--git-dir', git_dir, 'config',
+                                       'branch.%s.remote' % branch)
+        merge = command.OutputOneLine('git', '--git-dir', git_dir, 'config',
+                                      'branch.%s.merge' % branch)
+    except:
+        return None
+
     if remote == '.':
         return merge
     elif remote and merge:
@@ -78,9 +82,11 @@
         branch: Name of branch
     Return:
         Expression in the form 'upstream..branch' which can be used to
-        access the commits.
+        access the commits. If the branch does not exist, returns None.
     """
     upstream = GetUpstream(git_dir, branch)
+    if not upstream:
+        return None
     return '%s%s..%s' % (upstream, '~' if include_upstream else '', branch)
 
 def CountCommitsInBranch(git_dir, branch, include_upstream=False):
@@ -90,9 +96,12 @@
         git_dir: Directory containing git repo
         branch: Name of branch
     Return:
-        Number of patches that exist on top of the branch
+        Number of patches that exist on top of the branch, or None if the
+        branch does not exist.
     """
     range_expr = GetRangeInBranch(git_dir, branch, include_upstream)
+    if not range_expr:
+        return None
     pipe = [['git', '--git-dir', git_dir, 'log', '--oneline', '--no-decorate',
              range_expr],
             ['wc', '-l']]
diff --git a/tools/patman/patman.py b/tools/patman/patman.py
index a8061a9..7a317c5 100755
--- a/tools/patman/patman.py
+++ b/tools/patman/patman.py
@@ -1,4 +1,4 @@
-#!/usr/bin/python
+#!/usr/bin/env python
 #
 # Copyright (c) 2011 The Chromium OS Authors.
 #
diff --git a/tools/patman/series.py b/tools/patman/series.py
index 783b3dd..85ed316 100644
--- a/tools/patman/series.py
+++ b/tools/patman/series.py
@@ -40,6 +40,7 @@
         notes: List of lines in the notes
         changes: (dict) List of changes for each version, The key is
             the integer version number
+        allow_overwrite: Allow tags to overwrite an existing tag
     """
     def __init__(self):
         self.cc = []
@@ -49,6 +50,7 @@
         self.cover = None
         self.notes = []
         self.changes = {}
+        self.allow_overwrite = False
 
         # Written in MakeCcFile()
         #  key: name of patch file
@@ -72,7 +74,7 @@
         """
         # If we already have it, then add to our list
         name = name.replace('-', '_')
-        if name in self:
+        if name in self and not self.allow_overwrite:
             values = value.split(',')
             values = [str.strip() for str in values]
             if type(self[name]) != type([]):