Merge branch 'master' of git://git.denx.de/u-boot-mips
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig
index 524b193..f013dc3 100644
--- a/arch/arm/cpu/armv7/uniphier/Kconfig
+++ b/arch/arm/cpu/armv7/uniphier/Kconfig
@@ -23,4 +23,13 @@
endchoice
+config CMD_PINMON
+ bool "Enable boot mode pins monitor command"
+ depends on !SPL_BUILD
+ default y
+ help
+ The command "pinmon" shows the state of the boot mode pins.
+ The boot mode pins are latched when the system reset is deasserted
+ and determine which device the system should load a boot image from.
+
endmenu
diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile
index 7ceddda..dd57469 100644
--- a/arch/arm/cpu/armv7/uniphier/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/Makefile
@@ -12,7 +12,7 @@
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-$(CONFIG_UNIPHIER_SMP) += smp.o
-obj-$(if $(CONFIG_SPL_BUILD),,y) += cmd_pinmon.o
+obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
obj-y += board_common.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index e7bb3e3..9d38ef7 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -10,4 +10,4 @@
extra-y = start.o
obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
-obj-y += interrupts.o cpu.o
+obj-y += interrupts.o cpu.o call64.o
diff --git a/arch/x86/cpu/call64.S b/arch/x86/cpu/call64.S
new file mode 100644
index 0000000..74dd5a8
--- /dev/null
+++ b/arch/x86/cpu/call64.S
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2014 Google, Inc
+ * Copyright (C) 1991, 1992, 1993 Linus Torvalds
+ *
+ * Parts of this copied from Linux arch/x86/boot/compressed/head_64.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/global_data.h>
+#include <asm/msr-index.h>
+#include <asm/processor-flags.h>
+
+.code32
+.globl cpu_call64
+cpu_call64:
+ /*
+ * cpu_call64(ulong pgtable, ulong setup_base, ulong target)
+ *
+ * eax - pgtable
+ * edx - setup_base
+ * ecx - target
+ */
+ cli
+ push %ecx /* arg2 = target */
+ push %edx /* arg1 = setup_base */
+ mov %eax, %ebx
+
+ /* Load new GDT with the 64bit segments using 32bit descriptor */
+ leal gdt, %eax
+ movl %eax, gdt+2
+ lgdt gdt
+
+ /* Enable PAE mode */
+ movl $(X86_CR4_PAE), %eax
+ movl %eax, %cr4
+
+ /* Enable the boot page tables */
+ leal (%ebx), %eax
+ movl %eax, %cr3
+
+ /* Enable Long mode in EFER (Extended Feature Enable Register) */
+ movl $MSR_EFER, %ecx
+ rdmsr
+ btsl $_EFER_LME, %eax
+ wrmsr
+
+ /* After gdt is loaded */
+ xorl %eax, %eax
+ lldt %ax
+ movl $0x20, %eax
+ ltr %ax
+
+ /*
+ * Setup for the jump to 64bit mode
+ *
+ * When the jump is performed we will be in long mode but
+ * in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
+ * (and in turn EFER.LMA = 1). To jump into 64bit mode we use
+ * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
+ * We place all of the values on our mini stack so lret can
+ * used to perform that far jump. See the gdt below.
+ */
+ pop %esi /* setup_base */
+
+ pushl $0x10
+ leal lret_target, %eax
+ pushl %eax
+
+ /* Enter paged protected Mode, activating Long Mode */
+ movl $(X86_CR0_PG | X86_CR0_PE), %eax
+ movl %eax, %cr0
+
+ /* Jump from 32bit compatibility mode into 64bit mode. */
+ lret
+
+code64:
+lret_target:
+ pop %eax /* target */
+ mov %eax, %eax /* Clear bits 63:32 */
+ jmp *%eax /* Jump to the 64-bit target */
+
+ .data
+gdt:
+ .word gdt_end - gdt
+ .long gdt
+ .word 0
+ .quad 0x0000000000000000 /* NULL descriptor */
+ .quad 0x00af9a000000ffff /* __KERNEL_CS */
+ .quad 0x00cf92000000ffff /* __KERNEL_DS */
+ .quad 0x0080890000000000 /* TS descriptor */
+ .quad 0x0000000000000000 /* TS continued */
+gdt_end:
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 623e3af..2e25253 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -18,7 +18,10 @@
#include <common.h>
#include <command.h>
+#include <errno.h>
+#include <malloc.h>
#include <asm/control_regs.h>
+#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <asm/interrupt.h>
@@ -240,3 +243,144 @@
{
return 1;
}
+
+void cpu_enable_paging_pae(ulong cr3)
+{
+ __asm__ __volatile__(
+ /* Load the page table address */
+ "movl %0, %%cr3\n"
+ /* Enable pae */
+ "movl %%cr4, %%eax\n"
+ "orl $0x00000020, %%eax\n"
+ "movl %%eax, %%cr4\n"
+ /* Enable paging */
+ "movl %%cr0, %%eax\n"
+ "orl $0x80000000, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ :
+ : "r" (cr3)
+ : "eax");
+}
+
+void cpu_disable_paging_pae(void)
+{
+ /* Turn off paging */
+ __asm__ __volatile__ (
+ /* Disable paging */
+ "movl %%cr0, %%eax\n"
+ "andl $0x7fffffff, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ /* Disable pae */
+ "movl %%cr4, %%eax\n"
+ "andl $0xffffffdf, %%eax\n"
+ "movl %%eax, %%cr4\n"
+ :
+ :
+ : "eax");
+}
+
+static bool has_cpuid(void)
+{
+ unsigned long flag;
+
+ asm volatile("pushf\n" \
+ "pop %%eax\n"
+ "mov %%eax, %%ecx\n" /* ecx = flags */
+ "xor %1, %%eax\n"
+ "push %%eax\n"
+ "popf\n" /* flags ^= $2 */
+ "pushf\n"
+ "pop %%eax\n" /* eax = flags */
+ "push %%ecx\n"
+ "popf\n" /* flags = ecx */
+ "xor %%ecx, %%eax\n"
+ "mov %%eax, %0"
+ : "=r" (flag)
+ : "i" (1 << 21)
+ : "eax", "ecx", "memory");
+
+ return flag != 0;
+}
+
+static bool can_detect_long_mode(void)
+{
+ unsigned long flag;
+
+ asm volatile("mov $0x80000000, %%eax\n"
+ "cpuid\n"
+ "mov %%eax, %0"
+ : "=r" (flag)
+ :
+ : "eax", "ebx", "ecx", "edx", "memory");
+
+ return flag > 0x80000000UL;
+}
+
+static bool has_long_mode(void)
+{
+ unsigned long flag;
+
+ asm volatile("mov $0x80000001, %%eax\n"
+ "cpuid\n"
+ "mov %%edx, %0"
+ : "=r" (flag)
+ :
+ : "eax", "ebx", "ecx", "edx", "memory");
+
+ return flag & (1 << 29) ? true : false;
+}
+
+int cpu_has_64bit(void)
+{
+ return has_cpuid() && can_detect_long_mode() &&
+ has_long_mode();
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86");
+
+ return 0;
+}
+
+#define PAGETABLE_SIZE (6 * 4096)
+
+/**
+ * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
+ *
+ * @pgtable: Pointer to a 24iKB block of memory
+ */
+static void build_pagetable(uint32_t *pgtable)
+{
+ uint i;
+
+ memset(pgtable, '\0', PAGETABLE_SIZE);
+
+ /* Level 4 needs a single entry */
+ pgtable[0] = (uint32_t)&pgtable[1024] + 7;
+
+ /* Level 3 has one 64-bit entry for each GiB of memory */
+ for (i = 0; i < 4; i++) {
+ pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
+ 0x1000 * i + 7;
+ }
+
+ /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
+ for (i = 0; i < 2048; i++)
+ pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
+}
+
+int cpu_jump_to_64bit(ulong setup_base, ulong target)
+{
+ uint32_t *pgtable;
+
+ pgtable = memalign(4096, PAGETABLE_SIZE);
+ if (!pgtable)
+ return -ENOMEM;
+
+ build_pagetable(pgtable);
+ cpu_call64((ulong)pgtable, setup_base, target);
+ free(pgtable);
+
+ return -EFAULT;
+}
diff --git a/arch/x86/include/asm/bootm.h b/arch/x86/include/asm/bootm.h
index 033ab79..f6a64ce 100644
--- a/arch/x86/include/asm/bootm.h
+++ b/arch/x86/include/asm/bootm.h
@@ -9,4 +9,20 @@
void bootm_announce_and_cleanup(void);
+/**
+ * boot_linux_kernel() - boot a linux kernel
+ *
+ * This boots a kernel image, either 32-bit or 64-bit. It will also work with
+ * a self-extracting kernel, if you set @image_64bit to false.
+ *
+ * @setup_base: Pointer to the setup.bin information for the kernel
+ * @load_address: Pointer to the start of the kernel image
+ * @image_64bit: true if the image is a raw 64-bit kernel, false if it
+ * is raw 32-bit or any type of self-extracting kernel
+ * such as a bzImage.
+ * @return -ve error code. This function does not return if the kernel was
+ * booted successfully.
+ */
+int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit);
+
#endif
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
new file mode 100644
index 0000000..6c6774a
--- /dev/null
+++ b/arch/x86/include/asm/cpu.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2014 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __X86_CPU_H
+#define __X86_CPU_H
+
+ /**
+ * cpu_enable_paging_pae() - Enable PAE-paging
+ *
+ * @pdpt: Value to set in cr3 (PDPT or PML4T)
+ */
+void cpu_enable_paging_pae(ulong cr3);
+
+/**
+ * cpu_disable_paging_pae() - Disable paging and PAE
+ */
+void cpu_disable_paging_pae(void);
+
+/**
+ * cpu_has_64bit() - Check if the CPU has 64-bit support
+ *
+ * @return 1 if this CPU supports long mode (64-bit), 0 if not
+ */
+int cpu_has_64bit(void);
+
+/**
+ * cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
+ *
+ * The kernel is uncompressed and the 64-bit entry point is expected to be
+ * at @target.
+ *
+ * This function is used internally - see cpu_jump_to_64bit() for a more
+ * useful function.
+ *
+ * @pgtable: Address of 24KB area containing the page table
+ * @setup_base: Pointer to the setup.bin information for the kernel
+ * @target: Pointer to the start of the kernel image
+ */
+void cpu_call64(ulong pgtable, ulong setup_base, ulong target);
+
+/**
+ * cpu_jump_to_64bit() - Jump to a 64-bit Linux kernel
+ *
+ * The kernel is uncompressed and the 64-bit entry point is expected to be
+ * at @target.
+ *
+ * @setup_base: Pointer to the setup.bin information for the kernel
+ * @target: Pointer to the start of the kernel image
+ */
+int cpu_jump_to_64bit(ulong setup_base, ulong target);
+
+#endif
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 0a36e17..6027d59 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -44,12 +44,16 @@
#define MSR_IA32_PERFCTR0 0x000000c1
#define MSR_IA32_PERFCTR1 0x000000c2
#define MSR_FSB_FREQ 0x000000cd
+#define MSR_NHM_PLATFORM_INFO 0x000000ce
#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
#define NHM_C3_AUTO_DEMOTE (1UL << 25)
#define NHM_C1_AUTO_DEMOTE (1UL << 26)
#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
+#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
+#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
+#define MSR_PLATFORM_INFO 0x000000ce
#define MSR_MTRRcap 0x000000fe
#define MSR_IA32_BBL_CR_CTL 0x00000119
#define MSR_IA32_BBL_CR_CTL3 0x0000011e
@@ -64,10 +68,20 @@
#define MSR_OFFCORE_RSP_0 0x000001a6
#define MSR_OFFCORE_RSP_1 0x000001a7
+#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad
+#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae
+
+#define MSR_LBR_SELECT 0x000001c8
+#define MSR_LBR_TOS 0x000001c9
+#define MSR_LBR_NHM_FROM 0x00000680
+#define MSR_LBR_NHM_TO 0x000006c0
+#define MSR_LBR_CORE_FROM 0x00000040
+#define MSR_LBR_CORE_TO 0x00000060
#define MSR_IA32_PEBS_ENABLE 0x000003f1
#define MSR_IA32_DS_AREA 0x00000600
#define MSR_IA32_PERF_CAPABILITIES 0x00000345
+#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
#define MSR_MTRRfix64K_00000 0x00000250
#define MSR_MTRRfix16K_80000 0x00000258
@@ -91,7 +105,8 @@
#define MSR_IA32_LASTINTTOIP 0x000001de
/* DEBUGCTLMSR bits (others vary by model): */
-#define DEBUGCTLMSR_LBR (1UL << 0)
+#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
+/* single-step on branches */
#define DEBUGCTLMSR_BTF (1UL << 1)
#define DEBUGCTLMSR_TR (1UL << 6)
#define DEBUGCTLMSR_BTS (1UL << 7)
@@ -100,11 +115,50 @@
#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
+#define MSR_IA32_POWER_CTL 0x000001fc
+
#define MSR_IA32_MC0_CTL 0x00000400
#define MSR_IA32_MC0_STATUS 0x00000401
#define MSR_IA32_MC0_ADDR 0x00000402
#define MSR_IA32_MC0_MISC 0x00000403
+/* C-state Residency Counters */
+#define MSR_PKG_C3_RESIDENCY 0x000003f8
+#define MSR_PKG_C6_RESIDENCY 0x000003f9
+#define MSR_PKG_C7_RESIDENCY 0x000003fa
+#define MSR_CORE_C3_RESIDENCY 0x000003fc
+#define MSR_CORE_C6_RESIDENCY 0x000003fd
+#define MSR_CORE_C7_RESIDENCY 0x000003fe
+#define MSR_PKG_C2_RESIDENCY 0x0000060d
+#define MSR_PKG_C8_RESIDENCY 0x00000630
+#define MSR_PKG_C9_RESIDENCY 0x00000631
+#define MSR_PKG_C10_RESIDENCY 0x00000632
+
+/* Run Time Average Power Limiting (RAPL) Interface */
+
+#define MSR_RAPL_POWER_UNIT 0x00000606
+
+#define MSR_PKG_POWER_LIMIT 0x00000610
+#define MSR_PKG_ENERGY_STATUS 0x00000611
+#define MSR_PKG_PERF_STATUS 0x00000613
+#define MSR_PKG_POWER_INFO 0x00000614
+
+#define MSR_DRAM_POWER_LIMIT 0x00000618
+#define MSR_DRAM_ENERGY_STATUS 0x00000619
+#define MSR_DRAM_PERF_STATUS 0x0000061b
+#define MSR_DRAM_POWER_INFO 0x0000061c
+
+#define MSR_PP0_POWER_LIMIT 0x00000638
+#define MSR_PP0_ENERGY_STATUS 0x00000639
+#define MSR_PP0_POLICY 0x0000063a
+#define MSR_PP0_PERF_STATUS 0x0000063b
+
+#define MSR_PP1_POWER_LIMIT 0x00000640
+#define MSR_PP1_ENERGY_STATUS 0x00000641
+#define MSR_PP1_POLICY 0x00000642
+
+#define MSR_CORE_C1_RES 0x00000660
+
#define MSR_AMD64_MC0_MASK 0xc0010044
#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
@@ -123,18 +177,31 @@
#define MSR_P6_EVNTSEL0 0x00000186
#define MSR_P6_EVNTSEL1 0x00000187
+#define MSR_KNC_PERFCTR0 0x00000020
+#define MSR_KNC_PERFCTR1 0x00000021
+#define MSR_KNC_EVNTSEL0 0x00000028
+#define MSR_KNC_EVNTSEL1 0x00000029
+
+/* Alternative perfctr range with full access. */
+#define MSR_IA32_PMC0 0x000004c1
+
/* AMD64 MSRs. Not complete. See the architecture manual for a more
complete list. */
#define MSR_AMD64_PATCH_LEVEL 0x0000008b
+#define MSR_AMD64_TSC_RATIO 0xc0000104
#define MSR_AMD64_NB_CFG 0xc001001f
#define MSR_AMD64_PATCH_LOADER 0xc0010020
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
#define MSR_AMD64_OSVW_STATUS 0xc0010141
+#define MSR_AMD64_LS_CFG 0xc0011020
#define MSR_AMD64_DC_CFG 0xc0011022
+#define MSR_AMD64_BU_CFG2 0xc001102a
#define MSR_AMD64_IBSFETCHCTL 0xc0011030
#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
+#define MSR_AMD64_IBSFETCH_REG_COUNT 3
+#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
#define MSR_AMD64_IBSOPCTL 0xc0011033
#define MSR_AMD64_IBSOPRIP 0xc0011034
#define MSR_AMD64_IBSOPDATA 0xc0011035
@@ -142,12 +209,21 @@
#define MSR_AMD64_IBSOPDATA3 0xc0011037
#define MSR_AMD64_IBSDCLINAD 0xc0011038
#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
+#define MSR_AMD64_IBSOP_REG_COUNT 7
+#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
#define MSR_AMD64_IBSCTL 0xc001103a
#define MSR_AMD64_IBSBRTARGET 0xc001103b
+#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
+
+/* Fam 16h MSRs */
+#define MSR_F16H_L2I_PERF_CTL 0xc0010230
+#define MSR_F16H_L2I_PERF_CTR 0xc0010231
/* Fam 15h MSRs */
#define MSR_F15H_PERF_CTL 0xc0010200
#define MSR_F15H_PERF_CTR 0xc0010201
+#define MSR_F15H_NB_PERF_CTL 0xc0010240
+#define MSR_F15H_NB_PERF_CTR 0xc0010241
/* Fam 10h MSRs */
#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
@@ -226,7 +302,9 @@
#define MSR_IA32_PLATFORM_ID 0x00000017
#define MSR_IA32_EBL_CR_POWERON 0x0000002a
#define MSR_EBC_FREQUENCY_ID 0x0000002c
+#define MSR_SMI_COUNT 0x00000034
#define MSR_IA32_FEATURE_CONTROL 0x0000003a
+#define MSR_IA32_TSC_ADJUST 0x0000003b
#define FEATURE_CONTROL_LOCKED (1<<0)
#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
@@ -237,11 +315,16 @@
#define MSR_IA32_APICBASE_ENABLE (1<<11)
#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
+#define MSR_IA32_TSCDEADLINE 0x000006e0
+
#define MSR_IA32_UCODE_WRITE 0x00000079
#define MSR_IA32_UCODE_REV 0x0000008b
#define MSR_IA32_PERF_STATUS 0x00000198
#define MSR_IA32_PERF_CTL 0x00000199
+#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
+#define MSR_AMD_PERF_STATUS 0xc0010063
+#define MSR_AMD_PERF_CTL 0xc0010062
#define MSR_IA32_MPERF 0x000000e7
#define MSR_IA32_APERF 0x000000e8
@@ -267,6 +350,9 @@
#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
+#define ENERGY_PERF_BIAS_PERFORMANCE 0
+#define ENERGY_PERF_BIAS_NORMAL 6
+#define ENERGY_PERF_BIAS_POWERSAVE 15
#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
@@ -320,6 +406,8 @@
#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
+#define MSR_IA32_TSC_DEADLINE 0x000006E0
+
/* P4/Xeon+ specific */
#define MSR_IA32_MCG_EAX 0x00000180
#define MSR_IA32_MCG_EBX 0x00000181
@@ -446,7 +534,23 @@
#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
+#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
+#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
+#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
+#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
+#define MSR_IA32_VMX_VMFUNC 0x00000491
+/* VMX_BASIC bits and bitmasks */
+#define VMX_BASIC_VMCS_SIZE_SHIFT 32
+#define VMX_BASIC_64 0x0001000000000000LLU
+#define VMX_BASIC_MEM_TYPE_SHIFT 50
+#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
+#define VMX_BASIC_MEM_TYPE_WB 6LLU
+#define VMX_BASIC_INOUT 0x0040000000000000LLU
+
+/* MSR_IA32_VMX_MISC bits */
+#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
+#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
/* AMD-V MSRs */
#define MSR_VM_CR 0xc0010114
diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index 0f36662..8e7dd42 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h
@@ -35,10 +35,8 @@
unsigned install_e820_map(unsigned max_entries, struct e820entry *);
struct boot_params *load_zimage(char *image, unsigned long kernel_size,
- void **load_address);
+ ulong *load_addressp);
int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
unsigned long initrd_addr, unsigned long initrd_size);
-void boot_zimage(void *setup_base, void *load_address);
-
#endif
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 4c5c7f5..86030cf 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -10,10 +10,12 @@
#include <common.h>
#include <command.h>
+#include <errno.h>
#include <fdt_support.h>
#include <image.h>
#include <u-boot/zlib.h>
#include <asm/bootparam.h>
+#include <asm/cpu.h>
#include <asm/byteorder.h>
#include <asm/zimage.h>
#ifdef CONFIG_SYS_COREBOOT
@@ -109,17 +111,17 @@
}
if (is_zimage) {
- void *load_address;
+ ulong load_address;
char *base_ptr;
base_ptr = (char *)load_zimage(data, len, &load_address);
- images->os.load = (ulong)load_address;
+ images->os.load = load_address;
cmd_line_dest = base_ptr + COMMAND_LINE_OFFSET;
images->ep = (ulong)base_ptr;
} else if (images->ep) {
cmd_line_dest = (void *)images->ep + COMMAND_LINE_OFFSET;
} else {
- printf("## Kernel loading failed (no setup) ...\n");
+ printf("## Kernel loading failed (missing x86 kernel setup) ...\n");
goto error;
}
@@ -139,16 +141,50 @@
return 1;
}
+int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit)
+{
+ bootm_announce_and_cleanup();
+
+#ifdef CONFIG_SYS_COREBOOT
+ timestamp_add_now(TS_U_BOOT_START_KERNEL);
+#endif
+ if (image_64bit) {
+ if (!cpu_has_64bit()) {
+ puts("Cannot boot 64-bit kernel on 32-bit machine\n");
+ return -EFAULT;
+ }
+ return cpu_jump_to_64bit(setup_base, load_address);
+ } else {
+ /*
+ * Set %ebx, %ebp, and %edi to 0, %esi to point to the
+ * boot_params structure, and then jump to the kernel. We
+ * assume that %cs is 0x10, 4GB flat, and read/execute, and
+ * the data segments are 0x18, 4GB flat, and read/write.
+ * U-boot is setting them up that way for itself in
+ * arch/i386/cpu/cpu.c.
+ */
+ __asm__ __volatile__ (
+ "movl $0, %%ebp\n"
+ "cli\n"
+ "jmp *%[kernel_entry]\n"
+ :: [kernel_entry]"a"(load_address),
+ [boot_params] "S"(setup_base),
+ "b"(0), "D"(0)
+ );
+ }
+
+ /* We can't get to here */
+ return -EFAULT;
+}
+
/* Subcommand: GO */
static int boot_jump_linux(bootm_headers_t *images)
{
debug("## Transferring control to Linux (at address %08lx, kernel %08lx) ...\n",
images->ep, images->os.load);
- boot_zimage((struct boot_params *)images->ep, (void *)images->os.load);
- /* does not return */
-
- return 1;
+ return boot_linux_kernel(images->ep, images->os.load,
+ images->os.arch == IH_ARCH_X86_64);
}
int do_bootm_linux(int flag, int argc, char * const argv[],
@@ -161,10 +197,8 @@
if (flag & BOOTM_STATE_OS_PREP)
return boot_prep_linux(images);
- if (flag & BOOTM_STATE_OS_GO) {
- boot_jump_linux(images);
- return 0;
- }
+ if (flag & BOOTM_STATE_OS_GO)
+ return boot_jump_linux(images);
return boot_jump_linux(images);
}
diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c
index b57b2c3..c3c709e 100644
--- a/arch/x86/lib/physmem.c
+++ b/arch/x86/lib/physmem.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <physmem.h>
+#include <asm/cpu.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -112,41 +113,13 @@
x86_phys_map_page(page_addr, page_addr, 0);
}
- /* Turn on paging */
- __asm__ __volatile__(
- /* Load the page table address */
- "movl %0, %%cr3\n\t"
- /* Enable pae */
- "movl %%cr4, %%eax\n\t"
- "orl $0x00000020, %%eax\n\t"
- "movl %%eax, %%cr4\n\t"
- /* Enable paging */
- "movl %%cr0, %%eax\n\t"
- "orl $0x80000000, %%eax\n\t"
- "movl %%eax, %%cr0\n\t"
- :
- : "r" (pdpt)
- : "eax"
- );
+ cpu_enable_paging_pae((ulong)pdpt);
}
/* Disable paging and PAE mode. */
static void x86_phys_exit_paging(void)
{
- /* Turn off paging */
- __asm__ __volatile__ (
- /* Disable paging */
- "movl %%cr0, %%eax\n\t"
- "andl $0x7fffffff, %%eax\n\t"
- "movl %%eax, %%cr0\n\t"
- /* Disable pae */
- "movl %%cr4, %%eax\n\t"
- "andl $0xffffffdf, %%eax\n\t"
- "movl %%eax, %%cr4\n\t"
- :
- :
- : "eax"
- );
+ cpu_disable_paging_pae();
}
/*
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index b190283..566b048 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -103,7 +103,7 @@
}
struct boot_params *load_zimage(char *image, unsigned long kernel_size,
- void **load_address)
+ ulong *load_addressp)
{
struct boot_params *setup_base;
int setup_size;
@@ -155,9 +155,9 @@
/* Determine load address */
if (big_image)
- *load_address = (void *)BZIMAGE_LOAD_ADDR;
+ *load_addressp = BZIMAGE_LOAD_ADDR;
else
- *load_address = (void *)ZIMAGE_LOAD_ADDR;
+ *load_addressp = ZIMAGE_LOAD_ADDR;
printf("Building boot_params at 0x%8.8lx\n", (ulong)setup_base);
memset(setup_base, 0, sizeof(*setup_base));
@@ -204,10 +204,10 @@
return 0;
}
- printf("Loading %s at address %p (%ld bytes)\n",
- big_image ? "bzImage" : "zImage", *load_address, kernel_size);
+ printf("Loading %s at address %lx (%ld bytes)\n",
+ big_image ? "bzImage" : "zImage", *load_addressp, kernel_size);
- memmove(*load_address, image + setup_size, kernel_size);
+ memmove((void *)*load_addressp, image + setup_size, kernel_size);
return setup_base;
}
@@ -261,30 +261,6 @@
return 0;
}
-void boot_zimage(void *setup_base, void *load_address)
-{
- bootm_announce_and_cleanup();
-
-#ifdef CONFIG_SYS_COREBOOT
- timestamp_add_now(TS_U_BOOT_START_KERNEL);
-#endif
- /*
- * Set %ebx, %ebp, and %edi to 0, %esi to point to the boot_params
- * structure, and then jump to the kernel. We assume that %cs is
- * 0x10, 4GB flat, and read/execute, and the data segments are 0x18,
- * 4GB flat, and read/write. U-boot is setting them up that way for
- * itself in arch/i386/cpu/cpu.c.
- */
- __asm__ __volatile__ (
- "movl $0, %%ebp\n"
- "cli\n"
- "jmp *%[kernel_entry]\n"
- :: [kernel_entry]"a"(load_address),
- [boot_params] "S"(setup_base),
- "b"(0), "D"(0)
- );
-}
-
void setup_pcat_compatibility(void)
__attribute__((weak, alias("__setup_pcat_compatibility")));
@@ -296,7 +272,7 @@
{
struct boot_params *base_ptr;
void *bzImage_addr = NULL;
- void *load_address;
+ ulong load_address;
char *s;
ulong bzImage_size = 0;
ulong initrd_addr = 0;
@@ -331,20 +307,17 @@
base_ptr = load_zimage(bzImage_addr, bzImage_size, &load_address);
if (!base_ptr) {
- printf("## Kernel loading failed ...\n");
+ puts("## Kernel loading failed ...\n");
return -1;
}
if (setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET,
0, initrd_addr, initrd_size)) {
- printf("Setting up boot parameters failed ...\n");
+ puts("Setting up boot parameters failed ...\n");
return -1;
}
/* we assume that the kernel is in place */
- boot_zimage(base_ptr, load_address);
- /* does not return */
-
- return -1;
+ return boot_linux_kernel((ulong)base_ptr, load_address, false);
}
U_BOOT_CMD(
diff --git a/common/bootm.c b/common/bootm.c
index 81e3261..6b3ea8c 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -167,7 +167,8 @@
}
/* If we have a valid setup.bin, we will use that for entry (x86) */
- if (images.os.arch == IH_ARCH_I386) {
+ if (images.os.arch == IH_ARCH_I386 ||
+ images.os.arch == IH_ARCH_X86_64) {
ulong len;
ret = boot_get_setup(&images, IH_ARCH_I386, &images.ep, &len);
diff --git a/common/image-fit.c b/common/image-fit.c
index a272ea2..4ffc5aa 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1114,7 +1114,8 @@
if (fit_image_get_arch(fit, noffset, &image_arch))
return 0;
- return (arch == image_arch);
+ return (arch == image_arch) ||
+ (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64);
}
/**
diff --git a/common/image.c b/common/image.c
index eb92e63..b75a5ce 100644
--- a/common/image.c
+++ b/common/image.c
@@ -85,6 +85,7 @@
{ IH_ARCH_SANDBOX, "sandbox", "Sandbox", },
{ IH_ARCH_ARM64, "arm64", "AArch64", },
{ IH_ARCH_ARC, "arc", "ARC", },
+ { IH_ARCH_X86_64, "x86_64", "AMD x86_64", },
{ -1, "", "", },
};
diff --git a/doc/SPI/README.altera_spi b/doc/SPI/README.altera_spi
new file mode 100644
index 0000000..b07449f
--- /dev/null
+++ b/doc/SPI/README.altera_spi
@@ -0,0 +1,6 @@
+SoCFPGA EPCS/EPCQx1 mini howto:
+- Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild
+- The controller base address is the "Base" in QSys + 0x400
+- Set MSEL[4:0]=10010 (AS Standard)
+- Load the bitstream into FPGA, enable bridges
+- Only then will the driver work
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
index 9114b3e..3f3d415 100644
--- a/drivers/serial/serial_uniphier.c
+++ b/drivers/serial/serial_uniphier.c
@@ -55,7 +55,7 @@
#define uniphier_serial_port(dev) \
((struct uniphier_serial_private_data *)dev_get_priv(dev))->membase
-int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
+static int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
{
struct uniphier_serial_platform_data *plat = dev_get_platdata(dev);
struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
@@ -93,7 +93,17 @@
return 0;
}
-int uniphier_serial_probe(struct udevice *dev)
+static int uniphier_serial_pending(struct udevice *dev, bool input)
+{
+ struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
+
+ if (input)
+ return readb(&port->lsr) & UART_LSR_DR;
+ else
+ return !(readb(&port->lsr) & UART_LSR_THRE);
+}
+
+static int uniphier_serial_probe(struct udevice *dev)
{
struct uniphier_serial_private_data *priv = dev_get_priv(dev);
struct uniphier_serial_platform_data *plat = dev_get_platdata(dev);
@@ -106,7 +116,7 @@
return 0;
}
-int uniphier_serial_remove(struct udevice *dev)
+static int uniphier_serial_remove(struct udevice *dev)
{
unmap_sysmem(uniphier_serial_port(dev));
@@ -134,6 +144,7 @@
.setbrg = uniphier_serial_setbrg,
.getc = uniphier_serial_getc,
.putc = uniphier_serial_putc,
+ .pending = uniphier_serial_pending,
};
U_BOOT_DRIVER(uniphier_serial) = {
diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c
index 5accbb5..a4d03d9 100644
--- a/drivers/spi/altera_spi.c
+++ b/drivers/spi/altera_spi.c
@@ -12,58 +12,62 @@
#include <malloc.h>
#include <spi.h>
-#define ALTERA_SPI_RXDATA 0
-#define ALTERA_SPI_TXDATA 4
-#define ALTERA_SPI_STATUS 8
-#define ALTERA_SPI_CONTROL 12
-#define ALTERA_SPI_SLAVE_SEL 20
-
-#define ALTERA_SPI_STATUS_ROE_MSK (0x8)
-#define ALTERA_SPI_STATUS_TOE_MSK (0x10)
-#define ALTERA_SPI_STATUS_TMT_MSK (0x20)
-#define ALTERA_SPI_STATUS_TRDY_MSK (0x40)
-#define ALTERA_SPI_STATUS_RRDY_MSK (0x80)
-#define ALTERA_SPI_STATUS_E_MSK (0x100)
-
-#define ALTERA_SPI_CONTROL_IROE_MSK (0x8)
-#define ALTERA_SPI_CONTROL_ITOE_MSK (0x10)
-#define ALTERA_SPI_CONTROL_ITRDY_MSK (0x40)
-#define ALTERA_SPI_CONTROL_IRRDY_MSK (0x80)
-#define ALTERA_SPI_CONTROL_IE_MSK (0x100)
-#define ALTERA_SPI_CONTROL_SSO_MSK (0x400)
+#ifndef CONFIG_ALTERA_SPI_IDLE_VAL
+#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff
+#endif
#ifndef CONFIG_SYS_ALTERA_SPI_LIST
#define CONFIG_SYS_ALTERA_SPI_LIST { CONFIG_SYS_SPI_BASE }
#endif
+struct altera_spi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 status;
+ u32 control;
+ u32 _reserved;
+ u32 slave_sel;
+};
+
+#define ALTERA_SPI_STATUS_ROE_MSK (1 << 3)
+#define ALTERA_SPI_STATUS_TOE_MSK (1 << 4)
+#define ALTERA_SPI_STATUS_TMT_MSK (1 << 5)
+#define ALTERA_SPI_STATUS_TRDY_MSK (1 << 6)
+#define ALTERA_SPI_STATUS_RRDY_MSK (1 << 7)
+#define ALTERA_SPI_STATUS_E_MSK (1 << 8)
+
+#define ALTERA_SPI_CONTROL_IROE_MSK (1 << 3)
+#define ALTERA_SPI_CONTROL_ITOE_MSK (1 << 4)
+#define ALTERA_SPI_CONTROL_ITRDY_MSK (1 << 6)
+#define ALTERA_SPI_CONTROL_IRRDY_MSK (1 << 7)
+#define ALTERA_SPI_CONTROL_IE_MSK (1 << 8)
+#define ALTERA_SPI_CONTROL_SSO_MSK (1 << 10)
+
static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST;
struct altera_spi_slave {
- struct spi_slave slave;
- ulong base;
+ struct spi_slave slave;
+ struct altera_spi_regs *regs;
};
#define to_altera_spi_slave(s) container_of(s, struct altera_spi_slave, slave)
-__attribute__((weak))
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+__weak int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus < ARRAY_SIZE(altera_spi_base_list) && cs < 32;
}
-__attribute__((weak))
-void spi_cs_activate(struct spi_slave *slave)
+__weak void spi_cs_activate(struct spi_slave *slave)
{
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
- writel(1 << slave->cs, altspi->base + ALTERA_SPI_SLAVE_SEL);
- writel(ALTERA_SPI_CONTROL_SSO_MSK, altspi->base + ALTERA_SPI_CONTROL);
+ writel(1 << slave->cs, &altspi->regs->slave_sel);
+ writel(ALTERA_SPI_CONTROL_SSO_MSK, &altspi->regs->control);
}
-__attribute__((weak))
-void spi_cs_deactivate(struct spi_slave *slave)
+__weak void spi_cs_deactivate(struct spi_slave *slave)
{
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
- writel(0, altspi->base + ALTERA_SPI_CONTROL);
- writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL);
+ writel(0, &altspi->regs->control);
+ writel(0, &altspi->regs->slave_sel);
}
void spi_init(void)
@@ -87,9 +91,8 @@
if (!altspi)
return NULL;
- altspi->base = altera_spi_base_list[bus];
- debug("%s: bus:%i cs:%i base:%lx\n", __func__,
- bus, cs, altspi->base);
+ altspi->regs = (struct altera_spi_regs *)altera_spi_base_list[bus];
+ debug("%s: bus:%i cs:%i base:%p\n", __func__, bus, cs, altspi->regs);
return &altspi->slave;
}
@@ -105,8 +108,8 @@
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
- writel(0, altspi->base + ALTERA_SPI_CONTROL);
- writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL);
+ writel(0, &altspi->regs->control);
+ writel(0, &altspi->regs->slave_sel);
return 0;
}
@@ -115,24 +118,22 @@
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
- writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL);
+ writel(0, &altspi->regs->slave_sel);
}
-#ifndef CONFIG_ALTERA_SPI_IDLE_VAL
-# define CONFIG_ALTERA_SPI_IDLE_VAL 0xff
-#endif
-
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
/* assume spi core configured to do 8 bit transfers */
- uint bytes = bitlen / 8;
- const uchar *txp = dout;
- uchar *rxp = din;
+ unsigned int bytes = bitlen / 8;
+ const unsigned char *txp = dout;
+ unsigned char *rxp = din;
+ uint32_t reg, data, start;
debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
- slave->bus, slave->cs, bitlen, bytes, flags);
+ slave->bus, slave->cs, bitlen, bytes, flags);
+
if (bitlen == 0)
goto done;
@@ -142,25 +143,40 @@
}
/* empty read buffer */
- if (readl(altspi->base + ALTERA_SPI_STATUS) &
- ALTERA_SPI_STATUS_RRDY_MSK)
- readl(altspi->base + ALTERA_SPI_RXDATA);
+ if (readl(&altspi->regs->status) & ALTERA_SPI_STATUS_RRDY_MSK)
+ readl(&altspi->regs->rxdata);
+
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
while (bytes--) {
- uchar d = txp ? *txp++ : CONFIG_ALTERA_SPI_IDLE_VAL;
- debug("%s: tx:%x ", __func__, d);
- writel(d, altspi->base + ALTERA_SPI_TXDATA);
- while (!(readl(altspi->base + ALTERA_SPI_STATUS) &
- ALTERA_SPI_STATUS_RRDY_MSK))
- ;
- d = readl(altspi->base + ALTERA_SPI_RXDATA);
+ if (txp)
+ data = *txp++;
+ else
+ data = CONFIG_ALTERA_SPI_IDLE_VAL;
+
+ debug("%s: tx:%x ", __func__, data);
+ writel(data, &altspi->regs->txdata);
+
+ start = get_timer(0);
+ while (1) {
+ reg = readl(&altspi->regs->status);
+ if (reg & ALTERA_SPI_STATUS_RRDY_MSK)
+ break;
+ if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
+ printf("%s: Transmission timed out!\n", __func__);
+ goto done;
+ }
+ }
+
+ data = readl(&altspi->regs->rxdata);
if (rxp)
- *rxp++ = d;
- debug("rx:%x\n", d);
+ *rxp++ = data & 0xff;
+
+ debug("rx:%x\n", data);
}
- done:
+
+done:
if (flags & SPI_XFER_END)
spi_cs_deactivate(slave);
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index be10269..23f2ba6 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -49,6 +49,8 @@
#endif
int gpio;
int ss_pol;
+ unsigned int max_hz;
+ unsigned int mode;
};
static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
@@ -83,12 +85,13 @@
}
#ifdef MXC_CSPI
-static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
unsigned int ctrl_reg;
u32 clk_src;
u32 div;
+ unsigned int max_hz = mxcs->max_hz;
+ unsigned int mode = mxcs->mode;
clk_src = mxc_get_clock(MXC_CSPI_CLK);
@@ -120,19 +123,15 @@
#endif
#ifdef MXC_ECSPI
-static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
s32 reg_ctrl, reg_config;
u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
u32 pre_div = 0, post_div = 0;
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
-
- if (max_hz == 0) {
- printf("Error: desired clock is 0\n");
- return -1;
- }
+ unsigned int max_hz = mxcs->max_hz;
+ unsigned int mode = mxcs->mode;
/*
* Reset SPI and set all CSs to master mode, if toggling
@@ -169,9 +168,6 @@
reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
MXC_CSPICTRL_POSTDIV(post_div);
- /* We need to disable SPI before changing registers */
- reg_ctrl &= ~MXC_CSPICTRL_EN;
-
if (mode & SPI_CS_HIGH)
ss_pol = 1;
@@ -412,6 +408,11 @@
if (bus >= ARRAY_SIZE(spi_bases))
return NULL;
+ if (max_hz == 0) {
+ printf("Error: desired clock is 0\n");
+ return NULL;
+ }
+
mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
if (!mxcs) {
puts("mxc_spi: SPI Slave not allocated !\n");
@@ -427,13 +428,9 @@
}
mxcs->base = spi_bases[bus];
+ mxcs->max_hz = max_hz;
+ mxcs->mode = mode;
- ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
- if (ret) {
- printf("mxc_spi: cannot setup SPI controller\n");
- free(mxcs);
- return NULL;
- }
return &mxcs->slave;
}
@@ -446,12 +443,17 @@
int spi_claim_bus(struct spi_slave *slave)
{
+ int ret;
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
reg_write(®s->rxdata, 1);
udelay(1);
- reg_write(®s->ctrl, mxcs->ctrl_reg);
+ ret = spi_cfg_mxc(mxcs, slave->cs);
+ if (ret) {
+ printf("mxc_spi: cannot setup SPI controller\n");
+ return ret;
+ }
reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
reg_write(®s->intr, 0);
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 69c0336..cdccbef 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2003-2005
+ * (C) Copyright 2003-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2006
@@ -19,6 +19,8 @@
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index cc22045..0d5a2b9 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
@@ -19,6 +19,8 @@
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 4fd070f..e765a03 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
@@ -19,6 +19,8 @@
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index ca3750d..bbdc3f8 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
@@ -19,6 +19,8 @@
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index 659c9ad..5fc87f2 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
@@ -19,6 +19,8 @@
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index 906d79b..589d168 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
@@ -19,6 +19,8 @@
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index 44d456e..60acb56 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
@@ -19,6 +19,8 @@
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index 855b0cd..ebc5571 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
@@ -19,6 +19,8 @@
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 8109379..f4ce07f 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
@@ -19,6 +19,8 @@
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index da4af93..97db519 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
@@ -20,6 +20,8 @@
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
#define CONFIG_MPC862 1
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index ec3a57b..25d60a7 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
@@ -20,6 +20,8 @@
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
#define CONFIG_MPC862 1
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index cb8b84d..928b879 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
@@ -19,6 +19,8 @@
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index d1e6c5b..598020c 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2006
@@ -22,6 +22,8 @@
#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 4b90dc2..fef267f 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -26,6 +26,7 @@
#define CONFIG_PHYSMEM
#define CONFIG_SYS_EARLY_PCI_INIT
#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DM
#define CONFIG_CMD_DM
@@ -48,6 +49,7 @@
#define CONFIG_FIT
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
+#define CONFIG_SYS_BOOTM_LEN (16 << 20)
/*-----------------------------------------------------------------------
* Watchdog Configuration
@@ -221,7 +223,7 @@
#define CONFIG_SYS_MEMTEST_START 0x00100000
#define CONFIG_SYS_MEMTEST_END 0x01000000
-#define CONFIG_SYS_LOAD_ADDR 0x02000000
+#define CONFIG_SYS_LOAD_ADDR 0x20000000
/*-----------------------------------------------------------------------
* SDRAM Configuration
diff --git a/include/image.h b/include/image.h
index a13a302..07e9aed 100644
--- a/include/image.h
+++ b/include/image.h
@@ -173,6 +173,7 @@
#define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */
#define IH_ARCH_ARM64 22 /* ARM64 */
#define IH_ARCH_ARC 23 /* Synopsys DesignWare ARC */
+#define IH_ARCH_X86_64 24 /* AMD x86_64, Intel and Via */
/*
* Image Types