diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index a30037f..74b786d 100644
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -847,7 +847,7 @@
 
 	/*
 	 * Try to set the mac address now. The fec mac address is
-	 * a garbage after reset. When not using fec for booting 
+	 * a garbage after reset. When not using fec for booting
 	 * the Linux fec driver will try to work with this garbage.
 	 */
 	tmp = getenv("ethaddr");
diff --git a/cpu/mpc5xxx/i2c.c b/cpu/mpc5xxx/i2c.c
index 74a610f..ea37fb0 100644
--- a/cpu/mpc5xxx/i2c.c
+++ b/cpu/mpc5xxx/i2c.c
@@ -133,13 +133,13 @@
 	mpc_reg_out(&regs->mcr, I2C_TX, I2C_TX);
 	mpc_reg_out(&regs->mdr, chip, 0);
 
-        if (wait_for_pin(&status)) {
-                return -2;
-        }
+	if (wait_for_pin(&status)) {
+		return -2;
+	}
 
-        if (status & I2C_RXAK) {
-                return -3;
-        }
+	if (status & I2C_RXAK) {
+		return -3;
+	}
 
 	return 0;
 }
@@ -250,7 +250,7 @@
 		ipb = gd->ipb_clk;
 		for (i = 7; i >= 0; i--) {
 			for (j = 7; j >= 0; j--) {
-				scl = 2 * (scltap[j].scl2tap + 
+				scl = 2 * (scltap[j].scl2tap +
 					(SCL_Tap[i] - 1) * scltap[j].tap2tap + 2);
 				if (ipb <= speed*scl) {
 					if ((speed*scl - ipb) < bestmatch) {
@@ -344,13 +344,13 @@
 	xaddr[2] = (addr >>  8) & 0xFF;
 	xaddr[3] =  addr	& 0xFF;
 
-        if (wait_for_bb()) {
+	if (wait_for_bb()) {
 		printf("i2c_write: bus is busy\n");
 		goto Done;
 	}
 
-        mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
-        if (do_address(chip, 0)) {
+	mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
+	if (do_address(chip, 0)) {
 		printf("i2c_write: failed to address chip\n");
 		goto Done;
 	}
diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index 48f41cf..0c2114a 100644
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -101,22 +101,22 @@
 
 	/* GPIO Multiplexing - enable PCI */
 	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
-	
+
 	/* Set host bridge as pci master and enable memory decoding */
 	*(vu_long *)MPC5XXX_PCI_CMD |=
 		PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	
+
 	/* Set maximum latency timer */
 	*(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);
 
 	/* Set cache line size */
 	*(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
 		(CFG_CACHELINE_SIZE / 4);
-	
+
 	/* Map MBAR to PCI space */
 	*(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
 	*(vu_long *)MPC5XXX_PCI_TBATR1 = CFG_MBAR | 1;
-	
+
 	/* Map RAM to PCI space */
 	*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
 	*(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
@@ -133,14 +133,14 @@
 	/* Enable piplining */
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
 #endif
-	
+
 	/* Disable interrupts from PCI controller */
 	*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
 	*(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
-	
+
 	/* Disable initiator windows */
 	*(vu_long *)MPC5XXX_PCI_IWCR = 0;
-	
+
 	/* Map PCI memory to physical space */
 	*(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
 		(((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
@@ -166,7 +166,7 @@
 		pci_hose_write_config_byte_via_dword,
 		pci_hose_write_config_word_via_dword,
 		mpc5200_write_config_dword);
-	
+
 	udelay(1000);
 
 #ifdef CONFIG_PCI_SCAN_SHOW