| commit | 40c76dfed29ac2173bd32d730979ef2531029048 | [log] [tgz] |
|---|---|---|
| author | Zong Li <zong.li@sifive.com> | Thu Dec 14 14:09:37 2023 +0000 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Wed Dec 27 17:28:57 2023 +0800 |
| tree | e481fe5e4eed432724f4891497b7c026cef938ec | |
| parent | 64e8482f1c94ab6e1fb4837a8744ca8a156c507e [diff] |
riscv: cache: support cache enable in SPL stage The power gating feature of pl2 should be enabled as early as possible, it would be better to put it in SPL stage. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>