| commit | 40727391702a1a48c58b0a3c6e69013ff8af6cb2 | [log] [tgz] |
|---|---|---|
| author | Tom Rini <trini@konsulko.com> | Tue Sep 10 07:50:05 2024 -0600 |
| committer | Tom Rini <trini@konsulko.com> | Tue Sep 10 07:50:05 2024 -0600 |
| tree | 84b20693c9f3dd5d5cc831d0b999bd5523523c35 | |
| parent | aded8e4aaee1efa32f2ce7e3c45205f523afc2da [diff] | |
| parent | 1806fed0ce6b56365ecf6b84ce6d17aafd3af979 [diff] |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/22292 - Add rdcycle to RISC-V exception command - Some fixes and refactoring
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index e1cd6f8..9b895a6 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -111,6 +111,8 @@ #endif #address-cells = <1>; + offset = <0x57c00>; + images { uboot { arch = "arm64";