tree 82f066b5bc2ddd5d0c09c6fdddefefc70b842ac5
parent eb6b458cef28c86603d56a27b9ee699b13c60c14
author Shengzhou Liu <Shengzhou.Liu@freescale.com> 1389589266 +0800
committer York Sun <yorksun@freescale.com> 1390341741 -0800

t2080qds/ddr: update ddr parameters

- Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s.
- Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are
  unrelated to DDR3/3L.

Tested with UDIMM 9JSF25672AZ-2G1K1 and verified speed 1200/1866/2133MT/s.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>