commit 3cb86f3e40d2a80356177434a99f75bc8baa9caf
author Stefan Roese <sr@denx.de> Sat Mar 24 15:45:34 2007 +0100
committer Stefan Roese <sr@denx.de> Sat Mar 24 15:45:34 2007 +0100
tree 0086e4cf102f4ca0ed4d9c1516fb962d204de6eb
parent 16c0cc1c82081a493ab87c51980b28336ce1bce8

[PATCH] Clean up 40EZ/Acadia support

This patch cleans up all the open issue of the preliminary
Acadia support.

Signed-off-by: Stefan Roese <sr@denx.de>

board/amcc/acadia/cpr.c

diff --git a/board/amcc/acadia/cpr.c b/board/amcc/acadia/cpr.c
index 10d8290..9dcce35 100644
--- a/board/amcc/acadia/cpr.c
+++ b/board/amcc/acadia/cpr.c
@@ -76,19 +76,19 @@
 	 * | UART0 |   28.57    |   7 (0x07)|
 	 * | UART1 |   28.57    |   7 (0x07)|
 	 * | DAC   |   28.57    |   7 (0xA7)|
-	 * | ADC   |    4     	|  50 (0x32)|
+	 * | ADC   |    4       |  50 (0x32)|
 	 * | PWM   |   28.57    |   7 (0x07)|
 	 * | EMAC  |    4       |  50 (0x32)|
 	 * -----------------------------------
 	 */
 
 	/* Initialize PLL */
-	mtcpr(cprpllc,   0x20000238);
-	mtcpr(cprplld,   0x03010400);
+	mtcpr(cprpllc, 0x20000238);
+	mtcpr(cprplld, 0x03010400);
 	mtcpr(cprprimad, 0x03050a0a);
-	mtcpr(cprperc0,  0x00000000);
-	mtcpr(cprperd0,  0x070a0707);	/* SPI clk div. eq. OPB clk div. */
-	mtcpr(cprperd1,  0x07323200);
+	mtcpr(cprperc0, 0x00000000);
+	mtcpr(cprperd0, 0x070a0707);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(cprperd1, 0x07323200);
 	mtcpr(cprclkupd, 0x40000000);
 }
 
@@ -117,11 +117,11 @@
 	 */
 
 	/* Initialize PLL */
-	mtcpr(cprpllc,   0x0000033C);
-	mtcpr(cprplld,   0x0a010000);
+	mtcpr(cprpllc, 0x0000033C);
+	mtcpr(cprplld, 0x0a010000);
 	mtcpr(cprprimad, 0x02040808);
-	mtcpr(cprperd0,  0x02080505);	/* SPI clk div. eq. OPB clk div. */
-	mtcpr(cprperd1,  0xA6A60300);
+	mtcpr(cprperd0, 0x02080505);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(cprperd1, 0xA6A60300);
 	mtcpr(cprclkupd, 0x40000000);
 }
 
@@ -143,20 +143,20 @@
 	 */
 
 	/* Initialize PLL */
-	mtcpr(cprpllc,   0x000003BC);
-	mtcpr(cprplld,   0x06060600);
+	mtcpr(cprpllc, 0x000003BC);
+	mtcpr(cprplld, 0x06060600);
 	mtcpr(cprprimad, 0x02020004);
-	mtcpr(cprperd0,  0x04002828);	/* SPI clk div. eq. OPB clk div. */
-	mtcpr(cprperd1,  0xC8C81600);
+	mtcpr(cprperd0, 0x04002828);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(cprperd1, 0xC8C81600);
 	mtcpr(cprclkupd, 0x40000000);
 }
-#endif /* CPU_<speed>_405EZ */
+#endif				/* CPU_<speed>_405EZ */
 
 #if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
 /*
  * Get timebase clock frequency
  */
-unsigned long get_tbclk (void)
+unsigned long get_tbclk(void)
 {
 	unsigned long cpr_plld;
 	unsigned long cpr_primad;
@@ -184,12 +184,12 @@
 	/*
 	 * Determine FBK_DIV.
 	 */
-        pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
-        if (pllFbkDiv == 0)
-                pllFbkDiv = 256;
+	pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
+	if (pllFbkDiv == 0)
+		pllFbkDiv = 256;
 
 	freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
 
 	return (freqProcessor);
 }
-#endif	/* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
+#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */