ppc4xx: Fix common ECC generation code for 440GP style platforms
This patch makes the common 4xx ECC code really usable on 440GP style
platforms.
Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
we need to make some processor dependant defines used later on by the
driver.
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c
index 95b941d..3e87c84 100644
--- a/cpu/ppc4xx/ecc.c
+++ b/cpu/ppc4xx/ecc.c
@@ -76,7 +76,7 @@
void ecc_init(unsigned long * const start, unsigned long size)
{
const unsigned long pattern = CFG_ECC_PATTERN;
- unsigned * const end = (unsigned long * const)((long)start + size);
+ unsigned long * const end = (unsigned long * const)((long)start + size);
unsigned long * current = start;
unsigned long mcopt1;
long increment;
@@ -84,12 +84,12 @@
if (start >= end)
return;
- mfsdram(SDRAM_MCOPT1, mcopt1);
+ mfsdram(SDRAM_ECC_CFG, mcopt1);
/* Enable ECC generation without checking or reporting */
- mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) |
- SDRAM_MCOPT1_MCHK_GEN));
+ mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) |
+ SDRAM_ECC_CFG_MCHK_GEN));
increment = sizeof(u32);
@@ -99,7 +99,7 @@
* can skip words when writing.
*/
- if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) != SDRAM_MCOPT1_DMWD_32)
+ if ((mcopt1 & SDRAM_ECC_CFG_DMWD_MASK) != SDRAM_ECC_CFG_DMWD_32)
increment = sizeof(u64);
#endif /* defined(CONFIG_440) */
@@ -114,8 +114,8 @@
/* Enable ECC generation with checking and no reporting */
- mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) |
- SDRAM_MCOPT1_MCHK_CHK));
+ mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) |
+ SDRAM_ECC_CFG_MCHK_CHK));
}
#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */