armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index ba652ca..533fae7 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -10,6 +10,8 @@
#ifndef __CONFIG_TI816X_EVM_H
#define __CONFIG_TI816X_EVM_H
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#define CONFIG_TI81XX
#define CONFIG_TI816X
#define CONFIG_SYS_NO_FLASH