armv8: ls2080ardb: Add LS2081ARDB board support
LS2081ARDB board is similar to LS2080ARDB board with few differences
It hosts LS2081A SoC
Default boot source is QSPI-boot
It does not have IFC interface
RTC and QSPI flash device are different
It provides QIXIS access via I2C
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
diff --git a/arch/arm/dts/fsl-ls2081a-rdb.dts b/arch/arm/dts/fsl-ls2081a-rdb.dts
new file mode 100644
index 0000000..6489362
--- /dev/null
+++ b/arch/arm/dts/fsl-ls2081a-rdb.dts
@@ -0,0 +1,59 @@
+/*
+ * NXP LS2081A RDB board device tree source for QSPI-boot
+ *
+ * Author: Priyanka Jain <priyanka.jain@nxp.com>
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "fsl-ls2080a.dtsi"
+
+/ {
+ model = "Freescale Layerscape 2081a RDB Board";
+ compatible = "fsl,ls2081a-rdb", "fsl,ls2080a";
+
+ aliases {
+ spi0 = &qspi;
+ spi1 = &dspi;
+ };
+};
+
+&dspi {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash0: n25q512a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: n25q512a@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+
+ qflash1: n25q512a@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <1>;
+ };
+};