board: stm32mp1: update vddcore in SPL
For board using STPMIC1, the vddcore is provided by BUCK1 of STPMIC1
and need to be updated for 800MHz support and only after the clock
tree initialization.
The VDDCORE voltage value is provided by clock driver, saved in global
variable opp_voltage_mv and udpated in SPL board_early_init_f(),
just after clock tree initialization.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c
index 85f9505..3aa379e 100644
--- a/board/st/common/stpmic1.c
+++ b/board/st/common/stpmic1.c
@@ -164,8 +164,25 @@
return 0;
}
+static int stmpic_buck1_set(struct udevice *dev, u32 voltage_mv)
+{
+ u32 value;
+
+ /* VDDCORE= STMPCI1 BUCK1 ramp=+25mV, 5 => 725mV, 36 => 1500mV */
+ value = ((voltage_mv - 725) / 25) + 5;
+ if (value < 5)
+ value = 5;
+ if (value > 36)
+ value = 36;
+
+ return pmic_clrsetbits(dev,
+ STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK1),
+ STPMIC1_BUCK_VOUT_MASK,
+ STPMIC1_BUCK_VOUT(value));
+}
+
/* early init of PMIC */
-void stpmic1_init(void)
+void stpmic1_init(u32 voltage_mv)
{
struct udevice *dev;
@@ -173,6 +190,10 @@
DM_GET_DRIVER(pmic_stpmic1), &dev))
return;
+ /* update VDDCORE = BUCK1 */
+ if (voltage_mv)
+ stmpic_buck1_set(dev, voltage_mv);
+
/* Keep vdd on during the reset cycle */
pmic_clrsetbits(dev,
STPMIC1_BUCKS_MRST_CR,