Coding stylke cleanup; update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
diff --git a/CHANGELOG b/CHANGELOG
index 0bb6bc5..184e941 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,9 +1,44 @@
+commit 885ec89b648a899a2f32393fd3ffd9f7234c4402
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat May 5 18:05:02 2007 +0200
+
+ Add STX GP3 SSA board to MAKEALL script; update CHANGELOG.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit 5499645b3fe17a548af9dfc479ca6e2455f179a2
Author: Wolfgang Denk <wd@denx.de>
Date: Sat May 5 17:15:50 2007 +0200
Make "file" command happy with some config.mk files; update CHANGELOG
+commit e3b8c78bc2489c27ae020986ef0eaca684866cef
+Author: Jeffrey Mann <mannj@embeddedplanet.com>
+Date: Sat May 5 08:32:14 2007 +0200
+
+ ppc4xx: Detect if the sysclk on Sequoia is 33 or 33.333 MHz
+
+ The AMCC Secquoia board has been changed in a new revision from using a
+ 33.000 MHz clock to a 33.333 MHz system clock. A bit in the CPLD
+ indicates the difference. This patch reads that bit and uses the correct
+ clock speed for the board. This code is backward compatable will all
+ prior boards. All prior boards will be read as 33.000.
+
+ Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f544ff6656fca263ed1ebe39899b6d95da67c8b8
+Author: Stefan Roese <sr@denx.de>
+Date: Sat May 5 08:29:01 2007 +0200
+
+ ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND booting
+
+ Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+ for the 4k NAND boot image so define bus_frequency to 133MHz here
+ which is save for the refresh counter setup.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
commit a79886590593ba1d667c840caa4940c61639f18f
Author: Thomas Knobloch <knobloch@siemens.com>
Date: Sat May 5 07:04:42 2007 +0200
@@ -124,6 +159,22 @@
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
+commit 8b39501d28754e72726ce7fb02310e56dbdf116a
+Author: Stefan Roese <sr@denx.de>
+Date: Sun Apr 29 14:13:01 2007 +0200
+
+ ppc4xx: Bamboo: Use current NAND driver and *not* the legacy driver
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 37ed6cdd4159195bfad68d8a237f6adda8f482cb
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Tue Apr 24 14:03:45 2007 +0200
+
+ ppc4xx: setup 440EPx/GRx ZMII/RGMII bridge depending on PFC register content.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
commit 66ed6cca3f340f7a8a06d9272ae2ef8e96f0273d
Author: Andy Fleming <afleming@freescale.com>
Date: Mon Apr 23 02:37:47 2007 -0500
@@ -429,6 +480,20 @@
Also moved the libfdt.a requirement into the main Makefile. That is
The U-Boot Way.
+commit d21686263574e95cb3e9e9b0496f968b1b897fdb
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Apr 19 09:53:52 2007 +0200
+
+ ppc4xx: Fix chip select timing for SysACE access on AMCC Katmai
+
+ Previous versions used full wait states for the chip select #1 which
+ is connected to the Xilinix SystemACE controller on the AMCC Katmai
+ evaluation board. This leads to really slow access and therefore low
+ performance. This patch now sets up the chip select a lot faster
+ resulting in much better read/write performance of the Linux driver.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
commit 37837828d89084879bee2f2b8c7c68d4695940df
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Apr 18 17:49:29 2007 +0200
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 9059934..4ff1da9 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -52,7 +52,7 @@
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
- if ((uint)&gur->porpllsr != 0xe00e0000) {
+ if ((uint)&gur->porpllsr != 0xe00e0000) {
printf("immap size error %x\n",&gur->porpllsr);
}
printf ("Board: MPC8544DS\n");
@@ -79,7 +79,6 @@
return dram_size;
}
-
#if defined(CFG_DRAM_TEST)
int
testdram(void)
@@ -119,8 +118,6 @@
}
#endif
-
-
int last_stage_init(void)
{
return 0;
@@ -190,16 +187,15 @@
void
ft_board_setup(void *blob, bd_t *bd)
{
- u32 *p;
- int len;
+ u32 *p;
+ int len;
- ft_cpu_setup(blob, bd);
+ ft_cpu_setup(blob, bd);
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
+ }
}
#endif
-
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 63176d2..7735a52 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -71,14 +71,14 @@
puts("8548_E");
break;
case SVR_8544:
- puts("8544");
- break;
- case SVR_8544_E:
- puts("8544_E");
- break;
- case SVR_8568_E:
- puts("8568_E");
- break;
+ puts("8544");
+ break;
+ case SVR_8544_E:
+ puts("8544_E");
+ break;
+ case SVR_8568_E:
+ puts("8568_E");
+ break;
default:
puts("Unknown");
break;
@@ -157,7 +157,7 @@
/* e500 v2 core has reset control register */
volatile unsigned int * rstcr;
rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
- *rstcr = 0x2; /* HRESET_REQ */
+ *rstcr = 0x2; /* HRESET_REQ */
}else{
/*
* Initiate hard reset in debug control register DBCR0
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index be4e824..1200d02 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -344,7 +344,7 @@
mfsdr(sdr_pfc1, pfc1);
pfc1 &= SDR0_PFC1_SELECT_MASK;
- switch (pfc1) {
+ switch (pfc1) {
case SDR0_PFC1_SELECT_CONFIG_2:
/* 1 x GMII port */
out32 (ZMII_FER, 0x00);
@@ -361,7 +361,7 @@
break;
case SDR0_PFC1_SELECT_CONFIG_6:
/* 2 x SMII ports */
- out32 (ZMII_FER,
+ out32 (ZMII_FER,
((ZMII_FER_SMII) << ZMII_FER_V(0)) |
((ZMII_FER_SMII) << ZMII_FER_V(1)));
out32 (RGMII_FER, 0x00000000);
diff --git a/drivers/tsec.c b/drivers/tsec.c
index 25566a7..b418773 100644
--- a/drivers/tsec.c
+++ b/drivers/tsec.c
@@ -67,7 +67,7 @@
static struct tsec_info_struct tsec_info[] = {
#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
#if defined(CONFIG_MPC8544DS)
- {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
+ {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
#else
{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
#endif
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 66293c5..3f65644 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -149,7 +149,7 @@
#define CFG_BR1_PRELIM 0xf8000801
#define CFG_OR1_PRELIM 0xffffe9f7
-//#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
+/*#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
#undef CFG_FLASH_CHECKSUM