Correction patch
diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c
index e2c6277..064d143 100644
--- a/board/apollon/apollon.c
+++ b/board/apollon/apollon.c
@@ -31,18 +31,32 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_info.h>
#include <asm/arch/mem.h>
-#include <i2c.h>
#include <asm/mach-types.h>
void wait_for_command_complete(unsigned int wd_base);
+DECLARE_GLOBAL_DATA_PTR;
+
+#define write_config_reg(reg, value) \
+do { \
+ writeb(value, reg); \
+} while (0)
+
+#define mask_config_reg(reg, mask) \
+do { \
+ char value = readb(reg) & ~(mask); \
+ writeb(value, reg); \
+} while (0)
+
/*******************************************************
* Routine: delay
* Description: spinning delay to use before udelay works
-******************************************************/
-static inline void delay(unsigned long loops) {
- __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0"(loops)); }
+ ******************************************************/
+static inline void delay(unsigned long loops)
+{
+ __asm__("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
/*****************************************
* Routine: board_init
@@ -50,8 +64,6 @@
*****************************************/
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gpmc_init(); /* in SRAM or SDRM, finish GPMC */
gd->bd->bi_arch_number = 919;
@@ -68,7 +80,6 @@
**********************************************************/
void s_init(void)
{
-
watchdog_init();
set_muxconf_regs();
delay(100);
@@ -80,7 +91,7 @@
/*******************************************************
* Routine: misc_init_r
* Description: Init ethernet (done here so udelay works)
-********************************************************/
+ ********************************************************/
int misc_init_r(void)
{
ether_init(); /* better done here so timers are init'ed */
@@ -102,22 +113,24 @@
__raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
#define MPU_WD_CLOCKED 1
-#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
+#if MPU_WD_CLOCKED
+ /* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
__raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
wait_for_command_complete(WD3_BASE);
__raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);
__raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
wait_for_command_complete(WD4_BASE);
- __raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
-#endif
+ __raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
+#endif
}
/******************************************************
* Routine: wait_for_command_complete
* Description: Wait for posting to finish on watchdog
-******************************************************/
-void wait_for_command_complete(unsigned int wd_base) {
+ ******************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
int pending = 1;
do {
pending = __raw_readl(wd_base + WWPS);
@@ -160,7 +173,7 @@
} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
udelay(1000);
- *((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01;
+ mask_config_reg(ETH_CONTROL_REG, 0x01);
udelay(1000);
eth_reset_err_out:
@@ -171,10 +184,9 @@
/**********************************************
* Routine: dram_init
* Description: sets uboots idea of sdram size
-**********************************************/
+ **********************************************/
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
u32 mtype, btype, rev = 0, cpu = 0;
#define NOT_EARLY 0
@@ -187,8 +199,8 @@
display_board_info(btype);
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
- printf("ddr combo\n");
- do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
+ /* init other chip select */
+ do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
}
size0 = get_sdr_cs_size(SDRC_CS0_OSET);
@@ -224,7 +236,7 @@
/*****************************************************************
* Routine: peripheral_enable
* Description: Enable the clks & power for perifs (GPT2, UART1,...)
-******************************************************************/
+ ******************************************************************/
void peripheral_enable(void)
{
unsigned int v, if_clks = 0, func_clks = 0;
@@ -232,7 +244,8 @@
/* Enable GP2 timer. */
if_clks |= BIT4 | BIT3;
func_clks |= BIT4 | BIT3;
- v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2; /* Sys_clk input OMAP2420_GPT2 */
+ /* Sys_clk input OMAP2420_GPT2 */
+ v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2;
__raw_writel(v, CM_CLKSEL2_CORE);
__raw_writel(0x1, CM_CLKSEL_WKUP);
@@ -241,9 +254,11 @@
func_clks |= BIT21;
if_clks |= BIT21;
#endif
- v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
+ /* Interface clocks on */
+ v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;
__raw_writel(v, CM_ICLKEN1_CORE);
- v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
+ /* Functional Clocks on */
+ v = __raw_readl(CM_FCLKEN1_CORE) | func_clks;
__raw_writel(v, CM_FCLKEN1_CORE);
delay(1000);
@@ -261,199 +276,110 @@
}
/****************************************
- * Routine: muxSetupUsb0 (ostboot)
+ * Routine: muxSetupUsb0 (ostboot)
* Description: Setup usb muxing
*****************************************/
void muxSetupUsb0(void)
{
- volatile uint8 *MuxConfigReg;
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
- *MuxConfigReg &= (uint8) (~0x1F);
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
- *MuxConfigReg &= (uint8) (~0x1F);
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
- *MuxConfigReg &= (uint8) (~0x1F);
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
- *MuxConfigReg &= (uint8) (~0x1F);
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
- *MuxConfigReg &= (uint8) (~0x1F);
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
- *MuxConfigReg &= (uint8) (~0x1F);
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
- *MuxConfigReg &= (uint8) (~0x1F);
+ mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f);
+ mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f);
+ mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f);
+ mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f);
+ mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f);
+ mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f);
+ mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f);
}
-#define CONTROL_PADCONF_USB1_RCV ((volatile uint8 *)0x480000EB)
-#define CONTROL_PADCONF_USB1_TXEN ((volatile uint8 *)0x480000EC)
-#define CONTROL_PADCONF_GPIO69 ((volatile uint8 *)0x480000ED)
-#define CONTROL_PADCONF_GPIO70 ((volatile uint8 *)0x480000EE)
-
-#define CONTROL_PADCONF_GPIO102 ((volatile uint8 *)0x48000116)
-#define CONTROL_PADCONF_GPIO103 ((volatile uint8 *)0x48000117)
-#define CONTROL_PADCONF_GPIO104 ((volatile uint8 *)0x48000118)
-#define CONTROL_PADCONF_GPIO105 ((volatile uint8 *)0x48000119)
/****************************************
- * Routine: muxSetupUSBHost (ostboot)
+ * Routine: muxSetupUSBHost (ostboot)
* Description: Setup USB Host muxing
*****************************************/
void muxSetupUsbHost(void)
{
- volatile uint8 *MuxConfigReg;
-
/* V19 */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB1_RCV;
- *MuxConfigReg = 1;
+ write_config_reg(CONTROL_PADCONF_USB1_RCV, 1);
/* W20 */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB1_TXEN;
- *MuxConfigReg = 1;
+ write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1);
/* N14 */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO69;
- *MuxConfigReg = 3;
+ write_config_reg(CONTROL_PADCONF_GPIO69, 3);
/* P15 */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO70;
- *MuxConfigReg = 3;
-
+ write_config_reg(CONTROL_PADCONF_GPIO70, 3);
/* L18 */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO102;
- *MuxConfigReg = 3;
+ write_config_reg(CONTROL_PADCONF_GPIO102, 3);
/* L19 */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO103;
- *MuxConfigReg = 3;
+ write_config_reg(CONTROL_PADCONF_GPIO103, 3);
/* K15 */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO104;
- *MuxConfigReg = 3;
+ write_config_reg(CONTROL_PADCONF_GPIO104, 3);
/* K14 */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO105;
- *MuxConfigReg = 3;
+ write_config_reg(CONTROL_PADCONF_GPIO105, 3);
}
/****************************************
- * Routine: muxSetupUART1 (ostboot)
+ * Routine: muxSetupUART1 (ostboot)
* Description: Set up uart1 muxing
*****************************************/
void muxSetupUART1(void)
{
- volatile unsigned char *MuxConfigReg;
-
- /* UART1_CTS pin configuration, PIN = D21 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* UART1_RTS pin configuration, PIN = H21 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* UART1_TX pin configuration, PIN = L20 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* UART1_RX pin configuration, PIN = T21 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
+ /* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
+ /* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
+ /* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
+ /* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
}
/****************************************
- * Routine: muxSetupLCD (ostboot)
+ * Routine: muxSetupLCD (ostboot)
* Description: Setup lcd muxing
*****************************************/
void muxSetupLCD(void)
{
- volatile unsigned char *MuxConfigReg;
-
- /* LCD_D0 pin configuration, PIN = Y7 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D1 pin configuration, PIN = P10 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D2 pin configuration, PIN = V8 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D3 pin configuration, PIN = Y8 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D4 pin configuration, PIN = W8 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D5 pin configuration, PIN = R10 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D6 pin configuration, PIN = Y9 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D7 pin configuration, PIN = V9 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D8 pin configuration, PIN = W9 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D9 pin configuration, PIN = P11 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D10 pin configuration, PIN = V10 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D11 pin configuration, PIN = Y10 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D12 pin configuration, PIN = W10 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D13 pin configuration, PIN = R11 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D14 pin configuration, PIN = V11 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D15 pin configuration, PIN = W11 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D16 pin configuration, PIN = P12 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D17 pin configuration, PIN = R12 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_PCLK pin configuration, PIN = W6 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_VSYNC pin configuration, PIN = V7 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_HSYNC pin configuration, PIN = Y6 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_ACBIAS pin configuration, PIN = W7 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
+ /* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D0, 0);
+ /* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D1, 0);
+ /* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D2, 0);
+ /* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D3, 0);
+ /* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D4, 0);
+ /* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D5, 0);
+ /* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D6, 0);
+ /* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D7, 0);
+ /* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D8, 0);
+ /* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D9, 0);
+ /* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D10, 0);
+ /* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D11, 0);
+ /* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D12, 0);
+ /* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D13, 0);
+ /* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D14, 0);
+ /* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D15, 0);
+ /* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D16, 0);
+ /* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_D17, 0);
+ /* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0);
+ /* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0);
+ /* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0);
+ /* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0);
}
/****************************************
@@ -462,146 +388,84 @@
*****************************************/
void muxSetupMMCSD(void)
{
- volatile unsigned char *MuxConfigReg;
-
- /* SDMMC_CLKI pin configuration, PIN = H15 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* SDMMC_CLKO pin configuration, PIN = G19 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* SDMMC_CMD pin configuration, PIN = H18 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
- /* External pull-ups are present. */
- /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
- /* SDMMC_DAT0 pin configuration, PIN = F20 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
- /* External pull-ups are present. */
- /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
- /* SDMMC_DAT1 pin configuration, PIN = H14 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
- /* External pull-ups are present. */
- /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
- /* SDMMC_DAT2 pin configuration, PIN = E19 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
- /* External pull-ups are present. */
- /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
- /* SDMMC_DAT3 pin configuration, PIN = D19 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
- /* External pull-ups are present. */
- /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
- /* SDMMC_DDIR0 pin configuration, PIN = F19 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* SDMMC_DDIR1 pin configuration, PIN = E20 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* SDMMC_DDIR2 pin configuration, PIN = F18 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* SDMMC_DDIR3 pin configuration, PIN = E18 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* SDMMC_CDIR pin configuration, PIN = G18 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
+ /* SDMMC_CLKI pin configuration, PIN = H15, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0);
+ /* SDMMC_CLKO pin configuration, PIN = G19, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0);
+ /* SDMMC_CMD pin configuration, PIN = H18, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_MMC_CMD, 0);
+ /* SDMMC_DAT0 pin configuration, PIN = F20, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0);
+ /* SDMMC_DAT1 pin configuration, PIN = H14, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0);
+ /* SDMMC_DAT2 pin configuration, PIN = E19, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0);
+ /* SDMMC_DAT3 pin configuration, PIN = D19, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0);
+ /* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0);
+ /* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0);
+ /* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0);
+ /* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0);
+ /* SDMMC_CDIR pin configuration, PIN = G18, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0);
}
/******************************************
* Routine: muxSetupTouchScreen (ostboot)
- * Description: Set up touch screen muxing
-*******************************************/
+ * Description: Set up touch screen muxing
+ *******************************************/
void muxSetupTouchScreen(void)
{
- volatile unsigned char *MuxConfigReg;
-
- /* SPI1_CLK pin configuration, PIN = U18 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* SPI1_MOSI pin configuration, PIN = V20 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* SPI1_MISO pin configuration, PIN = T18 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
- /* SPI1_nCS0 pin configuration, PIN = U19 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0;
- *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
-
+ /* SPI1_CLK pin configuration, PIN = U18, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0);
+ /* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0);
+ /* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0);
+ /* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0);
#define CONTROL_PADCONF_GPIO85 CONTROL_PADCONF_SPI1_NCS1
-
- /* PEN_IRQ pin configuration, PIN = N15 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_GPIO85;
- *MuxConfigReg = 0x03; /* Mode = 3, PUPD=Disabled */
+ /* PEN_IRQ pin configuration, PIN = N15, Mode = 3, PUPD=Disabled */
+ write_config_reg(CONTROL_PADCONF_GPIO85, 3);
}
/***************************************************************
* Routine: muxSetupGPMC (ostboot)
* Description: Configures balls which cam up in protected mode
-***************************************************************/
+ ***************************************************************/
void muxSetupGPMC(void)
{
- volatile uint8 *MuxConfigReg;
- volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
-
- /* gpmc_io_dir */
- *MCR = 0x19000000;
+ /* gpmc_io_dir, MCR */
+ writel(0x4800008C, 0x19000000);
/* NOR FLASH CS0 */
- /* signal - Gpmc_clk;
- pin - J4; offset - 0x0088; mode - 0; Byte-3 Pull/up - N/A */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3;
- *MuxConfigReg = 0x00;
-
+ /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */
+ write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0);
/* MPDB(Multi Port Debug Port) CS1 */
- /* signal - gpmc_ncs1;
- pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1;
- *MuxConfigReg = 0x00;
-
- /* signal - Gpmc_ncs2;
- pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2;
- *MuxConfigReg = 0x00;
-
- /* signal - Gpmc_ncs3;
- pin - N2; offset - 0x008C; mode - 0; Byte-3 Pull/up - N/A */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3;
- *MuxConfigReg = 0x00;
-
- MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000090);
- *MuxConfigReg = 0x00;
- MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000091);
- *MuxConfigReg = 0x00;
- MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000092);
- *MuxConfigReg = 0x00;
- MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000093);
- *MuxConfigReg = 0x00;
+ /* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */
+ write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0);
+ /* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */
+ write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0);
+ /* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */
+ write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0);
+ /* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */
+ write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0);
+ /* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */
+ write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0);
+ /* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */
+ write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0);
+ /* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */
+ write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0);
}
/****************************************************************
- * Routine: muxSetupSDRC (ostboot)
+ * Routine: muxSetupSDRC (ostboot)
* Description: Configures balls which come up in protected mode
-****************************************************************/
+ ****************************************************************/
void muxSetupSDRC(void)
{
/* It's set by IPL */