x86: ivybridge: Add early LPC init so that serial works
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.
Signed-off-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index f2fcb39..63933aa 100644
--- a/arch/x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
@@ -53,6 +53,7 @@
compatible = "intel,lpc";
#address-cells = <1>;
#size-cells = <1>;
+ gen-dec = <0x800 0xfc 0x900 0xfc>;
cros-ec@200 {
compatible = "google,cros-ec";
reg = <0x204 1 0x200 1 0x880 0x80>;