| commit | 2ae44edf1d341db1a0102150e02f463c90d657a0 | [log] [tgz] |
|---|---|---|
| author | Heesub Shin <heesub@gmail.com> | Sun Apr 28 23:24:02 2024 +0900 |
| committer | Patrice Chotard <patrice.chotard@foss.st.com> | Tue Jun 18 08:55:52 2024 +0200 |
| tree | bf0d2f8555e5e0f4e082ea29cb834d15f3c4ecf9 | |
| parent | 69374aa86aa2fd6e301f7e4acfd2f3fb4441c68a [diff] |
ARM: dts: stm32: set PLL4_P to 125Mhz for ETH_CLK for stm32mp157c-odyssey Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to 125, 62.5 and 62.5Mhz in respectively. Signed-off-by: Heesub Shin <heesub@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>