Merge tag 'u-boot-rockchip-20191231' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Fix latest mainline kernel for rk3308
- Update rk3288-evb config to suport OP-TEE
- Fix for firefly-px30 DEBUG_UART channel and make it standalone
- Script make_fit_atf add python3 support
- Fix rk3328 timer with correct COUNTER_FREQUENCY
- Fix rk3328 ATF support with enable spl-fifo-mode
diff --git a/.gitignore b/.gitignore
index f980ae6..2e1c8bf 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,6 +7,7 @@
#
.*
*.a
+*.asn1.[ch]
*.bin
*.cfgout
*.dtb
diff --git a/.mailmap b/.mailmap
index 98d2131..61802f9 100644
--- a/.mailmap
+++ b/.mailmap
@@ -29,6 +29,7 @@
Jagan Teki <jaganna@xilinx.com>
Jagan Teki <jagannadh.teki@gmail.com>
Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
+Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
Markus Klotzbuecher <mk@denx.de>
Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
Prabhakar Kushwaha <prabhakar@freescale.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f9dab07..36c9c2f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -17,7 +17,7 @@
be loaded to and run from that address. This option lifts that
restriction, thus allowing the code to be loaded to and executed
from almost any address. This logic relies on the relocation
- information that is embedded into the binary to support U-Boot
+ information that is embedded in the binary to support U-Boot
relocating itself to the top-of-RAM later during execution.
config INIT_SP_RELATIVE
@@ -26,7 +26,7 @@
U-Boot typically uses a hard-coded value for the stack pointer
before relocation. Enable this option to instead calculate the
initial SP at run-time. This is useful to avoid hard-coding addresses
- into U-Boot, so that can be loaded and executed at arbitrary
+ into U-Boot, so that it can be loaded and executed at arbitrary
addresses and thus avoid using arbitrary addresses at runtime.
If this option is enabled, the early stack pointer is set to
@@ -57,7 +57,7 @@
hex
help
The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
- TEXT_OFFSET value written in to the Linux kernel image header.
+ TEXT_OFFSET value written to the Linux kernel image header.
endif
endif
@@ -121,7 +121,7 @@
select SYS_ARM_CACHE_CP15
help
Select if you want MMU-based virtualised addressing space
- support by paged memory management.
+ support via paged memory management.
config SYS_ARM_MPU
bool 'Use the ARM v7 PMSA Compliant MPU'
@@ -136,8 +136,8 @@
# startup. Note that in general these options force the workarounds to be
# applied; no CPU-type/version detection exists, unlike the similar options in
# the Linux kernel. Do not set these options unless they apply! Also note that
-# the following can be machine specific errata. These do have ability to
-# provide rudimentary version and machine specific checks, but expect no
+# the following can be machine-specific errata. These do have ability to
+# provide rudimentary version and machine-specific checks, but expect no
# product checks:
# CONFIG_ARM_ERRATA_430973
# CONFIG_ARM_ERRATA_454179
@@ -332,7 +332,7 @@
config ARCH_CPU_INIT
bool "Enable ARCH_CPU_INIT"
help
- Some architectures require a call to arch_cpu_init()
+ Some architectures require a call to arch_cpu_init().
Say Y here to enable it
config SYS_ARCH_TIMER
@@ -342,7 +342,7 @@
help
The ARM Generic Timer (aka arch-timer) provides an architected
interface to a timer source on an SoC.
- It is mandantory for ARMv8 implementation and widely available
+ It is mandatory for ARMv8 implementation and widely available
on ARMv7 systems.
config ARM_SMCCC
@@ -385,7 +385,7 @@
default y if SYS_THUMB_BUILD
depends on TPL && !ARM64
help
- Use this flag to build SPL using the Thumb instruction set for
+ Use this flag to build TPL using the Thumb instruction set for
ARM architectures. Thumb instruction set provides better code
density. For ARM architectures that support Thumb2 this flag will
result in Thumb2 code generated by GCC.
@@ -394,7 +394,7 @@
config SYS_L2CACHE_OFF
bool "L2cache off"
help
- If SoC does not support L2CACHE or one do not want to enable
+ If SoC does not support L2CACHE or one does not want to enable
L2CACHE, choose this option.
config ENABLE_ARM_SOC_BOOT0_HOOK
@@ -414,7 +414,7 @@
depends on !ARM64
help
Enable the generation of an optimized version of memcpy.
- Such implementation may be faster under some conditions
+ Such an implementation may be faster under some conditions
but may increase the binary size.
config SPL_USE_ARCH_MEMCPY
@@ -423,7 +423,7 @@
depends on !ARM64 && SPL
help
Enable the generation of an optimized version of memcpy.
- Such implementation may be faster under some conditions
+ Such an implementation may be faster under some conditions
but may increase the binary size.
config TPL_USE_ARCH_MEMCPY
@@ -432,7 +432,7 @@
depends on !ARM64 && TPL
help
Enable the generation of an optimized version of memcpy.
- Such implementation may be faster under some conditions
+ Such an implementation may be faster under some conditions
but may increase the binary size.
config USE_ARCH_MEMSET
@@ -441,7 +441,7 @@
depends on !ARM64
help
Enable the generation of an optimized version of memset.
- Such implementation may be faster under some conditions
+ Such an implementation may be faster under some conditions
but may increase the binary size.
config SPL_USE_ARCH_MEMSET
@@ -450,7 +450,7 @@
depends on !ARM64 && SPL
help
Enable the generation of an optimized version of memset.
- Such implementation may be faster under some conditions
+ Such an implementation may be faster under some conditions
but may increase the binary size.
config TPL_USE_ARCH_MEMSET
@@ -459,7 +459,7 @@
depends on !ARM64 && TPL
help
Enable the generation of an optimized version of memset.
- Such implementation may be faster under some conditions
+ Such an implementation may be faster under some conditions
but may increase the binary size.
config SET_STACK_SIZE
@@ -467,14 +467,14 @@
default y if ARCH_VERSAL || ARCH_ZYNQMP
help
This will enable an option to set max stack size that can be
- used by u-boot.
+ used by U-Boot.
config STACK_SIZE
- hex "Define max stack size that can be used by u-boot"
+ hex "Define max stack size that can be used by U-Boot"
depends on SET_STACK_SIZE
default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
help
- Defines Max stack size that can be used by u-boot so that the
+ Define Max stack size that can be used by U-Boot so that the
initrd_high will be calculated as base stack pointer minus this
stack size.
@@ -689,7 +689,7 @@
help
Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
ARMv8 Cortex-A57 processors targeting a broad range of networking
- applications
+ applications.
config ARCH_EXYNOS
bool "Samsung EXYNOS"
@@ -1101,8 +1101,8 @@
select ARMV8_MULTIENTRY
select FSL_DDR_SYNC_REFRESH
help
- Support for Freescale LS2080A_EMU platform
- The LS2080A Development System (EMULATOR) is a pre silicon
+ Support for Freescale LS2080A_EMU platform.
+ The LS2080A Development System (EMULATOR) is a pre-silicon
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
@@ -1114,7 +1114,7 @@
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
help
- Support for Freescale LS2080A_SIMU platform
+ Support for Freescale LS2080A_SIMU platform.
The LS2080A Development System (QDS) is a pre silicon
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
@@ -1130,7 +1130,7 @@
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SD_BOOT
help
- Support for NXP LS1088AQDS platform
+ Support for NXP LS1088AQDS platform.
The LS1088A Development System (QDS) is a high-performance
development platform that supports the QorIQ LS1088A
Layerscape Architecture processor.
@@ -1149,7 +1149,7 @@
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE if !SPL
help
- Support for Freescale LS2080AQDS platform
+ Support for Freescale LS2080AQDS platform.
The LS2080A Development System (QDS) is a high-performance
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
@@ -1649,7 +1649,7 @@
default n
help
Enabling this will make a U-Boot binary that is capable of being
- booted via TF-A.
+ booted via TF-A (Trusted Firmware for Cortex-A).
config TI_SECURE_DEVICE
bool "HS Device Type Support"
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index 2c5d99e..5b68900 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -75,7 +75,7 @@
isb();
}
-static void __secure clamp_release(u32 __maybe_unused *clamp)
+static void __secure clamp_release(void __maybe_unused *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_H3) || \
@@ -90,7 +90,7 @@
#endif
}
-static void __secure clamp_set(u32 __maybe_unused *clamp)
+static void __secure clamp_set(void __maybe_unused *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_H3) || \
@@ -99,22 +99,28 @@
#endif
}
-static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on,
+static void __secure sunxi_power_switch(void *clamp, void *pwroff_ptr, bool on,
int cpu)
{
+ u32 pwroff;
+
+ memcpy(&pwroff, pwroff_ptr, sizeof(u32));
+
if (on) {
/* Release power clamp */
clamp_release(clamp);
/* Clear power gating */
- clrbits_le32(pwroff, BIT(cpu));
+ clrbits_le32(&pwroff, BIT(cpu));
} else {
/* Set power gating */
- setbits_le32(pwroff, BIT(cpu));
+ setbits_le32(&pwroff, BIT(cpu));
/* Activate power clamp */
clamp_set(clamp);
}
+
+ memcpy(pwroff_ptr, &pwroff, sizeof(u32));
}
#ifdef CONFIG_MACH_SUN8I_R40
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 68cad33..0127a91 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -523,7 +523,8 @@
sun8i-h3-orangepi-pc.dtb \
sun8i-h3-orangepi-pc-plus.dtb \
sun8i-h3-orangepi-plus.dtb \
- sun8i-h3-orangepi-plus2e.dtb
+ sun8i-h3-orangepi-plus2e.dtb \
+ sun8i-h3-orangepi-zero-plus2.dtb
dtb-$(CONFIG_MACH_SUN8I_R40) += \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v40-bananapi-m2-berry.dtb
diff --git a/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts
new file mode 100644
index 0000000..f2f7b7a
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ * Copyright (C) 2018 Diego Rondini <diego.rondini@kynetics.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun8i-h3.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "OrangePi Zero Plus2 H3";
+ compatible = "xunlong,orangepi-zero-plus2-h3", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&de {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index 58a3689..767d1ff 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -202,7 +202,7 @@
#ifndef __ASSEMBLY__
#include <linux/compiler.h>
-struct __packed sunxi_prcm_reg {
+struct sunxi_prcm_reg {
u32 cpus_cfg; /* 0x000 */
u8 res0[0x8]; /* 0x004 */
u32 apb0_ratio; /* 0x00c */
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index fee6d56..4ce2799 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -113,3 +113,14 @@
config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"
depends on IMX8MN
+
+config IMX_DCD_ADDR
+ hex "DCD Blocks location on the image"
+ default 0x00910000 if !ARCH_MX7ULP
+ default 0x2f010000 if ARCH_MX7ULP
+ help
+ Indicates where the Device Configuration Data, a binary table used by
+ the ROM code to configure the device at early boot stage, is located.
+ This information is shared with the user via mkimage -l just so the
+ image can be signed.
+
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index ef816a2..1e5df9a 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -424,6 +424,7 @@
imply USB_ETHER_MCS7830
imply USB_ETHER_SMSC95XX
imply USB_HOST_ETHER
+ select MX6QDL
config TARGET_OPOS6ULDEV
bool "Armadeus OPOS6ULDev board"
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 33653b5..5018167 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -57,6 +57,8 @@
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+#define RGB_PAD_CTRL PAD_CTL_DSE_120ohm
+
#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_SRE_SLOW)
@@ -67,6 +69,56 @@
#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
+/* Prevent compiler error if gpio number 08 or 09 is used */
+#define not_octal(gp) ((((0x##gp >> 4) & 0xf) * 10) + ((0x##gp & 0xf)))
+
+#define _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \
+ sda_pad, sda_bank, sda_gp, pad_ctrl, join_io) { \
+ .scl = { \
+ .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##scl_pad##__##i2cnum##_SCL,\
+ pad_ctrl), \
+ .gpio_mode = NEW_PAD_CTRL( \
+ cpu##_PAD_##scl_pad##__GPIO##scl_bank##join_io##scl_gp,\
+ pad_ctrl), \
+ .gp = IMX_GPIO_NR(scl_bank, not_octal(scl_gp)) \
+ }, \
+ .sda = { \
+ .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##sda_pad##__##i2cnum##_SDA,\
+ pad_ctrl), \
+ .gpio_mode = NEW_PAD_CTRL( \
+ cpu##_PAD_##sda_pad##__GPIO##sda_bank##join_io##sda_gp,\
+ pad_ctrl), \
+ .gp = IMX_GPIO_NR(sda_bank, not_octal(sda_gp)) \
+ } \
+}
+
+#define I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \
+ sda_pad, sda_bank, sda_gp, pad_ctrl) \
+ _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \
+ sda_pad, sda_bank, sda_gp, pad_ctrl, _IO)
+
+#if defined(CONFIG_MX6QDL)
+#define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp, \
+ sda_pad, sda_bank, sda_gp, pad_ctrl) \
+ I2C_PADS_INFO_CPU(MX6Q, i2cnum, scl_pad, scl_bank, scl_gp, \
+ sda_pad, sda_bank, sda_gp, pad_ctrl), \
+ I2C_PADS_INFO_CPU(MX6DL, i2cnum, scl_pad, scl_bank, scl_gp, \
+ sda_pad, sda_bank, sda_gp, pad_ctrl)
+#define I2C_PADS_INFO_ENTRY_SPACING 2
+
+#define IOMUX_PAD_CTRL(name, pad_ctrl) \
+ NEW_PAD_CTRL(MX6Q_PAD_##name, pad_ctrl), \
+ NEW_PAD_CTRL(MX6DL_PAD_##name, pad_ctrl)
+#else
+#define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp, \
+ sda_pad, sda_bank, sda_gp, pad_ctrl) \
+ I2C_PADS_INFO_CPU(MX6, i2cnum, scl_pad, scl_bank, scl_gp, \
+ sda_pad, sda_bank, sda_gp, pad_ctrl)
+#define I2C_PADS_INFO_ENTRY_SPACING 1
+
+#define IOMUX_PAD_CTRL(name, pad_ctrl) NEW_PAD_CTRL(MX6_PAD_##name, pad_ctrl)
+#endif
+
int dram_init(void)
{
gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
@@ -75,140 +127,105 @@
}
static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
};
static iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
};
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-/* I2C1, SGTL5000 */
-static struct i2c_pads_info i2c_pad_info0 = {
- .scl = {
- .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
- .gp = IMX_GPIO_NR(3, 21)
- },
- .sda = {
- .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
- .gp = IMX_GPIO_NR(3, 28)
- }
+static struct i2c_pads_info i2c_pads[] = {
+ /* I2C1, SGTL5000 */
+ I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
+ /* I2C2 Camera, MIPI */
+ I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13,
+ I2C_PAD_CTRL),
+ /* I2C3, J15 - RGB connector */
+ I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
};
-/* I2C2 Camera, MIPI */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-/* I2C3, J15 - RGB connector */
-static struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
- .gp = IMX_GPIO_NR(1, 5)
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
- .gp = IMX_GPIO_NR(7, 11)
- }
-};
+#define I2C_BUS_CNT 3
static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, NO_PAD_CTRL), /* CD */
};
static iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, NO_PAD_CTRL), /* CD */
};
static iomux_v3_cfg_t const enet_pads1[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
/* pin 35 - 1 (PHY_AD2) on reset */
- MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_RXC__GPIO6_IO30, NO_PAD_CTRL),
/* pin 32 - 1 - (MODE0) all */
- MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_RD0__GPIO6_IO25, NO_PAD_CTRL),
/* pin 31 - 1 - (MODE1) all */
- MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_RD1__GPIO6_IO27, NO_PAD_CTRL),
/* pin 28 - 1 - (MODE2) all */
- MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_RD2__GPIO6_IO28, NO_PAD_CTRL),
/* pin 27 - 1 - (MODE3) all */
- MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_RD3__GPIO6_IO29, NO_PAD_CTRL),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
- MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_RX_CTL__GPIO6_IO24, NO_PAD_CTRL),
/* pin 42 PHY nRST */
- MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D23__GPIO3_IO23, NO_PAD_CTRL),
+ IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, NO_PAD_CTRL),
};
static iomux_v3_cfg_t const enet_pads2[] = {
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL),
+ IOMUX_PAD_CTRL(RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL),
};
static iomux_v3_cfg_t const misc_pads[] = {
- MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
+ IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
/* OTG Power enable */
- MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM),
+ IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
};
/* wl1271 pads on nitrogen6x */
static iomux_v3_cfg_t const wl12xx_pads[] = {
- (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
- | MUX_PAD_CTRL(WEAK_PULLDOWN),
- (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
- | MUX_PAD_CTRL(OUTPUT_40OHM),
- (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
- | MUX_PAD_CTRL(OUTPUT_40OHM),
+ IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
+ IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
+ IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
};
#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
#define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
@@ -217,17 +234,17 @@
/* Button assignments for J14 */
static iomux_v3_cfg_t const button_pads[] = {
/* Menu */
- MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, BUTTON_PAD_CTRL),
/* Back */
- MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, BUTTON_PAD_CTRL),
/* Labelled Search (mapped to Power under Android) */
- MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, BUTTON_PAD_CTRL),
/* Home */
- MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, BUTTON_PAD_CTRL),
/* Volume Down */
- MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, BUTTON_PAD_CTRL),
/* Volume Up */
- MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, BUTTON_PAD_CTRL),
};
static void setup_iomux_enet(void)
@@ -239,7 +256,7 @@
gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
- imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+ SETUP_IOMUX_PADS(enet_pads1);
gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
/* Need delay 10ms according to KSZ9021 spec */
@@ -247,24 +264,24 @@
gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
- imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+ SETUP_IOMUX_PADS(enet_pads2);
udelay(100); /* Wait 100 us before using mii interface */
}
static iomux_v3_cfg_t const usb_pads[] = {
- MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, NO_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
- imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+ SETUP_IOMUX_PADS(uart1_pads);
+ SETUP_IOMUX_PADS(uart2_pads);
}
#ifdef CONFIG_USB_EHCI_MX6
int board_ehci_hcd_init(int port)
{
- imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+ SETUP_IOMUX_PADS(usb_pads);
/* Reset USB hub */
gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
@@ -314,12 +331,10 @@
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ SETUP_IOMUX_PADS(usdhc3_pads);
break;
case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ SETUP_IOMUX_PADS(usdhc4_pads);
break;
default:
printf("Warning: you configured more USDHC controllers"
@@ -345,16 +360,15 @@
static iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
- MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, NO_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
};
static void setup_spi(void)
{
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
- ARRAY_SIZE(ecspi1_pads));
+ SETUP_IOMUX_PADS(ecspi1_pads);
}
#endif
@@ -424,52 +438,51 @@
static void setup_buttons(void)
{
- imx_iomux_v3_setup_multiple_pads(button_pads,
- ARRAY_SIZE(button_pads));
+ SETUP_IOMUX_PADS(button_pads);
}
#if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const backlight_pads[] = {
/* Backlight on RGB connector: J15 */
- MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, NO_PAD_CTRL),
#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
/* Backlight on LVDS connector: J6 */
- MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, NO_PAD_CTRL),
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
};
static iomux_v3_cfg_t const rgb_pads[] = {
- MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
- MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
- MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
- MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
- MX6_PAD_DI0_PIN4__GPIO4_IO20,
- MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
- MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
- MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
- MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
- MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
- MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
- MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
- MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
- MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
- MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
- MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
- MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
- MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
- MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
- MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
- MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
- MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
- MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
- MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
- MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
- MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
- MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
- MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
- MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
+ IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
};
static void do_enable_hdmi(struct display_info_t const *dev)
@@ -507,9 +520,7 @@
static void enable_rgb(struct display_info_t const *dev)
{
- imx_iomux_v3_setup_multiple_pads(
- rgb_pads,
- ARRAY_SIZE(rgb_pads));
+ SETUP_IOMUX_PADS(rgb_pads);
gpio_direction_output(RGB_BACKLIGHT_GP, 1);
}
@@ -810,8 +821,7 @@
writel(reg, &iomux->gpr[3]);
/* backlights off until needed */
- imx_iomux_v3_setup_multiple_pads(backlight_pads,
- ARRAY_SIZE(backlight_pads));
+ SETUP_IOMUX_PADS(backlight_pads);
gpio_direction_input(LVDS_BACKLIGHT_GP);
gpio_direction_input(RGB_BACKLIGHT_GP);
}
@@ -819,24 +829,24 @@
static iomux_v3_cfg_t const init_pads[] = {
/* SGTL5000 sys_mclk */
- NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
+ IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
/* J5 - Camera MCLK */
- NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
+ IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
/* wl1271 pads on nitrogen6x */
/* WL12XX_WL_IRQ_GP */
- NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
+ IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
/* WL12XX_WL_ENABLE_GP */
- NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
+ IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
/* WL12XX_BT_ENABLE_GP */
- NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
+ IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
/* USB otg power */
- NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
- NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
- NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
- NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
- NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
+ IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
+ IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
+ IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
+ IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
+ IOMUX_PAD_CTRL(GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
};
#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
@@ -871,8 +881,8 @@
set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
gpio_direction_input(WL12XX_WL_IRQ_GP);
- imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
- imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
+ SETUP_IOMUX_PADS(wl12xx_pads);
+ SETUP_IOMUX_PADS(init_pads);
setup_buttons();
#if defined(CONFIG_VIDEO_IPUV3)
@@ -893,12 +903,20 @@
int board_init(void)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ struct i2c_pads_info *p = i2c_pads;
+ int i;
+ int stride = 1;
+#if defined(CONFIG_MX6QDL)
+ stride = 2;
+ if (!is_mx6dq() && !is_mx6dqp())
+ p += 1;
+#endif
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUXC_GPR1_OTG_ID_MASK,
IOMUXC_GPR1_OTG_ID_GPIO1);
- imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
+ SETUP_IOMUX_PADS(misc_pads);
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
@@ -906,11 +924,11 @@
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ for (i = 0; i < I2C_BUS_CNT; i++) {
+ setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, p);
+ p += stride;
+ }
#ifdef CONFIG_SATA
setup_sata();
diff --git a/board/davinci/da8xxevm/MAINTAINERS b/board/davinci/da8xxevm/MAINTAINERS
index 42324a3..16f1032 100644
--- a/board/davinci/da8xxevm/MAINTAINERS
+++ b/board/davinci/da8xxevm/MAINTAINERS
@@ -8,7 +8,7 @@
F: configs/da850evm_direct_nor_defconfig
OMAPL138_LCDK BOARD
-M: Peter Howard <phoward@gme.net.au>
+M: Lokesh Vutla <lokeshvutla@ti.com>
S: Maintained
F: include/configs/omap1l38_lcdk.h
F: configs/omapl138_lcdk_defconfig
diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
index 03ebe4e..6dca229 100644
--- a/board/freescale/common/pfuze.c
+++ b/board/freescale/common/pfuze.c
@@ -136,7 +136,7 @@
int ret;
unsigned int reg, dev_id, rev_id;
- ret = pmic_get("pfuze100", &dev);
+ ret = pmic_get("pfuze100@8", &dev);
if (ret == -ENODEV)
return NULL;
diff --git a/board/freescale/imx8mq_evk/README b/board/freescale/imx8mq_evk/README
index c1d400b..4f671b0 100644
--- a/board/freescale/imx8mq_evk/README
+++ b/board/freescale/imx8mq_evk/README
@@ -11,7 +11,7 @@
======================================
Note: srctree is U-Boot source directory
Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
-branch: imx_4.14.62_1.0.0_beta
+branch: imx_4.19.35_1.0.0
$ make PLAT=imx8mq bl31
$ cp build/imx8mq/release/bl31.bin $(srctree)
diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c
index 5b65847..ba69c96 100644
--- a/board/logicpd/imx6/imx6logic.c
+++ b/board/logicpd/imx6/imx6logic.c
@@ -156,29 +156,49 @@
{
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned int reg = readl(&psrc->sbmr1) >> 11;
- /*
- * Upon reading BOOT_CFG register the following map is done:
- * Bit 11 and 12 of BOOT_CFG register can determine the current
- * mmc port
- * 0x1 SD1-SOM
- * 0x2 SD2-Baseboard
- */
+ u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK;
+ unsigned int bmode = readl(&src_base->sbmr2);
- reg &= 0x3; /* Only care about bottom 2 bits */
- switch (reg) {
- case 0:
- spl_boot_list[0] = BOOT_DEVICE_MMC1;
+ /* If bmode is serial or USB phy is active, return serial */
+ if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) {
+ spl_boot_list[0] = BOOT_DEVICE_BOARD;
+ return;
+ }
+
+ switch (boot_mode >> IMX6_BMODE_SHIFT) {
+ case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
+ spl_boot_list[0] = BOOT_DEVICE_NAND;
break;
- case 1:
- spl_boot_list[0] = BOOT_DEVICE_MMC2;
+ case IMX6_BMODE_SD:
+ case IMX6_BMODE_ESD:
+ case IMX6_BMODE_MMC:
+ case IMX6_BMODE_EMMC:
+ /*
+ * Upon reading BOOT_CFG register the following map is done:
+ * Bit 11 and 12 of BOOT_CFG register can determine the current
+ * mmc port
+ * 0x1 SD1-SOM
+ * 0x2 SD2-Baseboard
+ */
+
+ reg &= 0x3; /* Only care about bottom 2 bits */
+ switch (reg) {
+ case 0:
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
+ break;
+ case 1:
+ spl_boot_list[0] = BOOT_DEVICE_MMC2;
+ break;
+ }
+ break;
+ default:
+ /* By default use USB downloader */
+ spl_boot_list[0] = BOOT_DEVICE_BOARD;
break;
}
- /* If we cannot find a valid MMC/SD card, try NAND */
- spl_boot_list[1] = BOOT_DEVICE_NAND;
-
/* As a last resort, use serial downloader */
- spl_boot_list[2] = BOOT_DEVICE_BOARD;
+ spl_boot_list[1] = BOOT_DEVICE_BOARD;
}
static void ccgr_init(void)
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index a2adf89..4a89bb0 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -405,6 +405,11 @@
S: Maintained
F: configs/orangepi_zero_plus2_defconfig
+ORANGEPI ZERO PLUS 2 H3 BOARD
+M: Diego Rondini <diego.rondini@kynetics.com>
+S: Maintained
+F: configs/orangepi_zero_plus2_h3_defconfig
+
ORANGEPI PC 2 BOARD
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 10c595d..a5cd858 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -83,7 +83,7 @@
MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
/* Colibri MMC */
iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -304,7 +304,7 @@
}
#endif
-#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
/* use the following sequence: eMMC, MMC */
struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
{USDHC3_BASE_ADDR},
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index 1505459..a2af8ae 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -3,7 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x97800000
CONFIG_TARGET_MX51EVK=y
CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x60000
+CONFIG_ENV_OFFSET=0xC0000
CONFIG_NR_DRAM_BANKS=1
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig
new file mode 100644
index 0000000..3000a97
--- /dev/null
+++ b/configs/orangepi_zero_plus2_h3_defconfig
@@ -0,0 +1,19 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=672
+# CONFIG_DRAM_ODT_EN is not set
+CONFIG_MMC0_CD_PIN="PH13"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-zero-plus2"
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index d6e915c..21af66e 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -24,7 +24,7 @@
{
unsigned int tmp, initial_drate, target_freq;
- printf("DDRINFO: start DRAM init\n");
+ debug("DDRINFO: start DRAM init\n");
/* Step1: Follow the power up procedure */
if (is_imx8mq()) {
@@ -109,7 +109,7 @@
tmp = reg32_read(DDRPHY_CalBusy(0));
} while ((tmp & 0x1));
- printf("DDRINFO:ddrphy calibration done\n");
+ debug("DDRINFO:ddrphy calibration done\n");
/* Step15: Set SWCTL.sw_done to 0 */
reg32_write(DDRC_SWCTL(0), 0x00000000);
@@ -161,7 +161,7 @@
/* enable port 0 */
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
- printf("DDRINFO: ddrmix config done\n");
+ debug("DDRINFO: ddrmix config done\n");
/* save the dram timing config into memory */
dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 5a8c084..eb49a6c 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -546,6 +546,9 @@
dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
(long long)instr->len);
+ if (!instr->len)
+ return 0;
+
div_u64_rem(instr->len, mtd->erasesize, &rem);
if (rem)
return -EINVAL;
@@ -1226,6 +1229,9 @@
dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
+ if (!len)
+ return 0;
+
for (i = 0; i < len; ) {
ssize_t written;
loff_t addr = to + i;
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index d3b8457..973b6f8 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -108,6 +108,11 @@
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
+ INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
+ {
INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c
index e7e78e3..0c59552 100644
--- a/drivers/phy/ti-pipe3-phy.c
+++ b/drivers/phy/ti-pipe3-phy.c
@@ -41,27 +41,110 @@
#define SATA_PLL_SOFT_RESET (1<<18)
/* PHY POWER CONTROL Register */
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
+#define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14)
+#define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
+#define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22)
+#define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
-#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
-#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
+#define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
+#define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
+/* PHY RX Registers */
+#define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C
+#define INTERFACE_MASK GENMASK(31, 27)
+#define INTERFACE_SHIFT 27
+#define INTERFACE_MODE_USBSS BIT(4)
+#define INTERFACE_MODE_SATA_1P5 BIT(3)
+#define INTERFACE_MODE_SATA_3P0 BIT(2)
+#define INTERFACE_MODE_PCIE BIT(0)
+
+#define LOSD_MASK GENMASK(17, 14)
+#define LOSD_SHIFT 14
+#define MEM_PLLDIV GENMASK(6, 5)
+
+#define PIPE3_PHY_RX_TRIM 0x0000001C
+#define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)
+#define MEM_DLL_TRIM_SHIFT 30
+
+#define PIPE3_PHY_RX_DLL 0x00000024
+#define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)
+#define MEM_DLL_PHINT_RATE_SHIFT 30
+
+#define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028
+#define MEM_HS_RATE_MASK GENMASK(28, 27)
+#define MEM_HS_RATE_SHIFT 27
+#define MEM_OVRD_HS_RATE BIT(26)
+#define MEM_OVRD_HS_RATE_SHIFT 26
+#define MEM_CDR_FASTLOCK BIT(23)
+#define MEM_CDR_FASTLOCK_SHIFT 23
+#define MEM_CDR_LBW_MASK GENMASK(22, 21)
+#define MEM_CDR_LBW_SHIFT 21
+#define MEM_CDR_STEPCNT_MASK GENMASK(20, 19)
+#define MEM_CDR_STEPCNT_SHIFT 19
+#define MEM_CDR_STL_MASK GENMASK(18, 16)
+#define MEM_CDR_STL_SHIFT 16
+#define MEM_CDR_THR_MASK GENMASK(15, 13)
+#define MEM_CDR_THR_SHIFT 13
+#define MEM_CDR_THR_MODE BIT(12)
+#define MEM_CDR_THR_MODE_SHIFT 12
+#define MEM_CDR_2NDO_SDM_MODE BIT(11)
+#define MEM_CDR_2NDO_SDM_MODE_SHIFT 11
+
+#define PIPE3_PHY_RX_EQUALIZER 0x00000038
+#define MEM_EQLEV_MASK GENMASK(31, 16)
+#define MEM_EQLEV_SHIFT 16
+#define MEM_EQFTC_MASK GENMASK(15, 11)
+#define MEM_EQFTC_SHIFT 11
+#define MEM_EQCTL_MASK GENMASK(10, 7)
+#define MEM_EQCTL_SHIFT 7
+#define MEM_OVRD_EQLEV BIT(2)
+#define MEM_OVRD_EQLEV_SHIFT 2
+#define MEM_OVRD_EQFTC BIT(1)
+#define MEM_OVRD_EQFTC_SHIFT 1
+
+#define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44
+#define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9)
+#define MEM_CDR_LOS_SOURCE_SHIFT 9
#define PLL_IDLE_TIME 100 /* in milliseconds */
#define PLL_LOCK_TIME 100 /* in milliseconds */
+enum pipe3_mode { PIPE3_MODE_PCIE = 1,
+ PIPE3_MODE_SATA,
+ PIPE3_MODE_USBSS };
+
+struct pipe3_settings {
+ u8 ana_interface;
+ u8 ana_losd;
+ u8 dig_fastlock;
+ u8 dig_lbw;
+ u8 dig_stepcnt;
+ u8 dig_stl;
+ u8 dig_thr;
+ u8 dig_thr_mode;
+ u8 dig_2ndo_sdm_mode;
+ u8 dig_hs_rate;
+ u8 dig_ovrd_hs_rate;
+ u8 dll_trim_sel;
+ u8 dll_phint_rate;
+ u8 eq_lev;
+ u8 eq_ftc;
+ u8 eq_ctl;
+ u8 eq_ovrd_lev;
+ u8 eq_ovrd_ftc;
+};
+
struct omap_pipe3 {
void __iomem *pll_ctrl_base;
+ void __iomem *phy_rx;
void __iomem *power_reg;
void __iomem *pll_reset_reg;
struct pipe3_dpll_map *dpll_map;
+ enum pipe3_mode mode;
+ struct pipe3_settings settings;
};
-
struct pipe3_dpll_params {
u16 m;
u8 n;
@@ -75,6 +158,12 @@
struct pipe3_dpll_params params;
};
+struct pipe3_data {
+ enum pipe3_mode mode;
+ struct pipe3_dpll_map *dpll_map;
+ struct pipe3_settings settings;
+};
+
static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
{
return readl(addr + offset);
@@ -175,19 +264,75 @@
rate = rate/1000000;
if (on) {
- val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
- val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
- val |= rate <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
- } else {
- val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
- val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
- }
+ val &= ~(PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
+ PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
+ val |= rate << PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
+ writel(val, pipe3->power_reg);
- writel(val, pipe3->power_reg);
+ /* Power up TX before RX for SATA & USB */
+ val |= PIPE3_PHY_TX_POWERON;
+ writel(val, pipe3->power_reg);
+
+ val |= PIPE3_PHY_RX_POWERON;
+ writel(val, pipe3->power_reg);
+ } else {
+ val &= ~PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
+ writel(val, pipe3->power_reg);
+ }
+}
+
+static void ti_pipe3_calibrate(struct omap_pipe3 *phy)
+{
+ u32 val;
+ struct pipe3_settings *s = &phy->settings;
+
+ val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
+ val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
+ val = (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
+ omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
+
+ val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
+ val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
+ MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
+ MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
+ val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
+ s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
+ s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
+ s->dig_lbw << MEM_CDR_LBW_SHIFT |
+ s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
+ s->dig_stl << MEM_CDR_STL_SHIFT |
+ s->dig_thr << MEM_CDR_THR_SHIFT |
+ s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
+ s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
+ omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
+
+ val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
+ val &= ~MEM_DLL_TRIM_SEL_MASK;
+ val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
+ omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
+
+ val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
+ val &= ~MEM_DLL_PHINT_RATE_MASK;
+ val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
+ omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
+
+ val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
+ val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
+ MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
+ val |= s->eq_lev << MEM_EQLEV_SHIFT |
+ s->eq_ftc << MEM_EQFTC_SHIFT |
+ s->eq_ctl << MEM_EQCTL_SHIFT |
+ s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
+ s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
+ omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
+
+ if (phy->mode == PIPE3_MODE_SATA) {
+ val = omap_pipe3_readl(phy->phy_rx,
+ SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
+ val &= ~MEM_CDR_LOS_SOURCE_MASK;
+ omap_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
+ val);
+ }
}
static int pipe3_init(struct phy *phy)
@@ -202,6 +347,8 @@
ret = omap_pipe3_dpll_program(pipe3);
if (ret)
return ret;
+
+ ti_pipe3_calibrate(pipe3);
} else {
/* else just bring it out of IDLE mode */
val = omap_pipe3_readl(pipe3->pll_ctrl_base,
@@ -317,7 +464,22 @@
fdt_addr_t addr;
fdt_size_t sz;
struct omap_pipe3 *pipe3 = dev_get_priv(dev);
+ struct pipe3_data *data;
+ /* PHY_RX */
+ addr = devfdt_get_addr_size_index(dev, 0, &sz);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("missing phy_rx address\n");
+ return -EINVAL;
+ }
+
+ pipe3->phy_rx = map_physmem(addr, sz, MAP_NOCACHE);
+ if (!pipe3->phy_rx) {
+ pr_err("unable to remap phy_rx\n");
+ return -EINVAL;
+ }
+
+ /* PLLCTRL */
addr = devfdt_get_addr_size_index(dev, 2, &sz);
if (addr == FDT_ADDR_T_NONE) {
pr_err("missing pll ctrl address\n");
@@ -334,25 +496,28 @@
if (!pipe3->power_reg)
return -EINVAL;
- if (device_is_compatible(dev, "ti,phy-pipe3-sata")) {
+ data = (struct pipe3_data *)dev_get_driver_data(dev);
+ pipe3->mode = data->mode;
+ pipe3->dpll_map = data->dpll_map;
+ pipe3->settings = data->settings;
+
+ if (pipe3->mode == PIPE3_MODE_SATA) {
pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
if (!pipe3->pll_reset_reg)
return -EINVAL;
}
- pipe3->dpll_map = (struct pipe3_dpll_map *)dev_get_driver_data(dev);
-
return 0;
}
static struct pipe3_dpll_map dpll_map_sata[] = {
- {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
- {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
- {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
- {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
- {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
- {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
- { }, /* Terminator */
+ {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
+ {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
+ {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
+ {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
+ {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
+ {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
+ { }, /* Terminator */
};
static struct pipe3_dpll_map dpll_map_usb[] = {
@@ -365,9 +530,61 @@
{ }, /* Terminator */
};
+static struct pipe3_data data_usb = {
+ .mode = PIPE3_MODE_USBSS,
+ .dpll_map = dpll_map_usb,
+ .settings = {
+ /* DRA75x TRM Table 26-17. Preferred USB3_PHY_RX SCP Register Settings */
+ .ana_interface = INTERFACE_MODE_USBSS,
+ .ana_losd = 0xa,
+ .dig_fastlock = 1,
+ .dig_lbw = 3,
+ .dig_stepcnt = 0,
+ .dig_stl = 0x3,
+ .dig_thr = 1,
+ .dig_thr_mode = 1,
+ .dig_2ndo_sdm_mode = 0,
+ .dig_hs_rate = 0,
+ .dig_ovrd_hs_rate = 1,
+ .dll_trim_sel = 0x2,
+ .dll_phint_rate = 0x3,
+ .eq_lev = 0,
+ .eq_ftc = 0,
+ .eq_ctl = 0x9,
+ .eq_ovrd_lev = 0,
+ .eq_ovrd_ftc = 0,
+ },
+};
+
+static struct pipe3_data data_sata = {
+ .mode = PIPE3_MODE_SATA,
+ .dpll_map = dpll_map_sata,
+ .settings = {
+ /* DRA75x TRM Table 26-9. Preferred SATA_PHY_RX SCP Register Settings */
+ .ana_interface = INTERFACE_MODE_SATA_3P0,
+ .ana_losd = 0x5,
+ .dig_fastlock = 1,
+ .dig_lbw = 3,
+ .dig_stepcnt = 0,
+ .dig_stl = 0x3,
+ .dig_thr = 1,
+ .dig_thr_mode = 1,
+ .dig_2ndo_sdm_mode = 0,
+ .dig_hs_rate = 0, /* Not in TRM preferred settings */
+ .dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */
+ .dll_trim_sel = 0x1,
+ .dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */
+ .eq_lev = 0,
+ .eq_ftc = 0x1f,
+ .eq_ctl = 0,
+ .eq_ovrd_lev = 1,
+ .eq_ovrd_ftc = 1,
+ },
+};
+
static const struct udevice_id pipe3_phy_ids[] = {
- { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&dpll_map_sata },
- { .compatible = "ti,omap-usb3", .data = (ulong)&dpll_map_usb},
+ { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&data_sata },
+ { .compatible = "ti,omap-usb3", .data = (ulong)&data_usb},
{ }
};
diff --git a/drivers/rtc/rx8010sj.c b/drivers/rtc/rx8010sj.c
index 81560e1..82c5185 100644
--- a/drivers/rtc/rx8010sj.c
+++ b/drivers/rtc/rx8010sj.c
@@ -349,7 +349,7 @@
static int rx8010sj_probe(struct udevice *dev)
{
- rx8010sj_rtc_init(&dev);
+ rx8010sj_rtc_init(dev);
return 0;
}
@@ -364,6 +364,7 @@
static const struct udevice_id rx8010sj_rtc_ids[] = {
{ .compatible = "epson,rx8010sj-rtc" },
+ { .compatible = "epson,rx8010" },
{ }
};
diff --git a/drivers/rtc/s35392a.c b/drivers/rtc/s35392a.c
index 844f1b7..4f478cc 100644
--- a/drivers/rtc/s35392a.c
+++ b/drivers/rtc/s35392a.c
@@ -350,6 +350,8 @@
static const struct udevice_id s35392a_rtc_ids[] = {
{ .compatible = "sii,s35392a-rtc" },
+ { .compatible = "sii,s35392a" },
+ { .compatible = "s35392a" },
{ }
};
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index c04535a..95eeb83 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -27,6 +27,12 @@
/* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI 0
+/*
+ * ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However,
+ * the controller seems to hang when given 0x10000, so stick with this for now.
+ */
+#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
+
struct rockchip_spi_params {
/* RXFIFO overruns and TXFIFO underruns stop the master clock */
bool master_manages_fifo;
@@ -367,7 +373,7 @@
* represented in CTRLR1.
*/
if (data && data->master_manages_fifo)
- max_chunk_size = 0x10000;
+ max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN;
// rockchip_spi_configure(dev, mode, size)
rkspi_enable_chip(regs, false);
@@ -451,7 +457,7 @@
/* This is the original 8bit reader/writer code */
while (len > 0) {
- int todo = min(len, 0x10000);
+ int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN);
rkspi_enable_chip(regs, false);
writel(todo - 1, ®s->ctrlr1);
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index acbab05..991fe00 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -39,7 +39,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=Image.itb\0" \
- "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+ "console=ttymxc1,115200\0" \
"fdt_addr=0x43000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fit=try\0" \
diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
index 62037c7..ce73ca6 100644
--- a/include/configs/imx8mn_evk.h
+++ b/include/configs/imx8mn_evk.h
@@ -42,7 +42,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=Image.itb\0" \
- "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+ "console=ttymxc1,115200\0" \
"fdt_addr=0x43000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fit=try\0" \
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index b29989d..5d9ef70 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -103,7 +103,7 @@
CONFIG_MFG_ENV_SETTINGS \
"script=boot.scr\0" \
"image=Image\0" \
- "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
+ "console=ttymxc0,115200\0" \
"fdt_addr=0x43000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fdt=try\0" \
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 71ff789..10aa1bc 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -182,6 +182,19 @@
/*-----------------------------------------------------------------------
* environment organization
*/
+
+/*
+ * Environment starts at CONFIG_ENV_OFFSET=0xC0000 = 768k = 768 * 1024 = 786432
+ *
+ * Detect overlap between U-Boot image and environment area in build-time
+ *
+ * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset
+ * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
+ *
+ * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
+ * write the direct value here
+ */
+#define CONFIG_BOARD_SIZE_LIMIT 785408
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 704d9f3..55aace1 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -54,9 +54,9 @@
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \
- "mmcdev=2\0" \
+ "mmcdev=3\0" \
"mmcpart=1\0" \
- "finduuid=part uuid mmc 2:2 uuid\0" \
+ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=PARTUUID=${uuid} rootwait rw\0" \
"loadbootscript=" \
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 4157d76..bc8aa7a 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -37,7 +37,7 @@
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K
#define CONFIG_ENV_OVERWRITE
diff --git a/test/py/tests/test_env.py b/test/py/tests/test_env.py
index 9bdaef9..6ff38f1 100644
--- a/test/py/tests/test_env.py
+++ b/test/py/tests/test_env.py
@@ -49,7 +49,7 @@
for l in response.splitlines():
if not '=' in l:
continue
- (var, value) = l.strip().split('=', 1)
+ (var, value) = l.split('=', 1)
self.env[var] = value
def get_existent_var(self):
diff --git a/test/py/tests/test_handoff.py b/test/py/tests/test_handoff.py
index 0ee9722..038f030 100644
--- a/test/py/tests/test_handoff.py
+++ b/test/py/tests/test_handoff.py
@@ -6,7 +6,7 @@
# Magic number to check that SPL handoff is working
TEST_HANDOFF_MAGIC = 0x14f93c7b
-@pytest.mark.boardspec('sandbox')
+@pytest.mark.boardspec('sandbox_spl')
@pytest.mark.buildconfigspec('spl')
def test_handoff(u_boot_console):
"""Test that of-platdata can be generated and used in sandbox"""
diff --git a/tools/.gitignore b/tools/.gitignore
index d0176a7..82bdce2 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -1,3 +1,4 @@
+/asn1_compiler
/atmel_pmecc_params
/bin2header
/bmp_logo
diff --git a/tools/imximage.c b/tools/imximage.c
index d7c0b6e..d7edd3c 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -11,9 +11,13 @@
#include "imagetool.h"
#include <image.h>
#include "imximage.h"
+#include <generated/autoconf.h>
#define UNDEFINED 0xFFFFFFFF
+#if !defined(CONFIG_IMX_DCD_ADDR)
+#define CONFIG_IMX_DCD_ADDR 0x00910000
+#endif
/*
* Supported commands for configuration file
*/
@@ -524,8 +528,8 @@
printf("HAB Blocks: 0x%08x 0x%08x 0x%08x\n",
(uint32_t)fhdr_v2->self, 0,
(uint32_t)(fhdr_v2->csf - fhdr_v2->self));
- printf("DCD Blocks: 0x00910000 0x%08x 0x%08x\n",
- offs, be16_to_cpu(dcdlen));
+ printf("DCD Blocks: 0x%08x 0x%08x 0x%08x\n",
+ offs, CONFIG_IMX_DCD_ADDR, be16_to_cpu(dcdlen));
}
} else {
imx_header_v2_t *next_hdr_v2;