Merge git://git.denx.de/u-boot-mpc85xx
diff --git a/MAINTAINERS b/MAINTAINERS
index c8386ab..0cf2602 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -196,7 +196,8 @@
F: drivers/mtd/jedec_flash.c
COLDFIRE
-M: Jason Jin <jason.jin@freescale.com>
+M: Huan Wang <alison.wang@freescale.com>
+M: Angelo Dureghello <angelo@sysam.it>
S: Maintained
T: git git://git.denx.de/u-boot-coldfire.git
F: arch/m68k/
@@ -390,6 +391,7 @@
UBI
M: Kyungmin Park <kmpark@infradead.org>
+M: Heiko Schocher <hs@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-ubi.git
F: drivers/mtd/ubi/
diff --git a/Makefile b/Makefile
index 79cb45c..8a0de5c 100644
--- a/Makefile
+++ b/Makefile
@@ -503,6 +503,7 @@
-path ./include/config/auto.conf -newer $(KCONFIG_CONFIG)))
ifneq ($(autoconf_is_current),)
include $(srctree)/config.mk
+include $(srctree)/arch/$(ARCH)/Makefile
endif
# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
@@ -601,17 +602,11 @@
#########################################################################
# U-Boot objects....order is important (i.e. start must be first)
-head-y := $(CPUDIR)/start.o
-head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o
-head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o
-
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n)
libs-y += lib/
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
-libs-y += $(CPUDIR)/
libs-$(CONFIG_OF_EMBED) += dts/
-libs-y += arch/$(ARCH)/lib/
libs-y += fs/
libs-y += net/
libs-y += disk/
@@ -645,23 +640,11 @@
libs-y += drivers/usb/phy/
libs-y += drivers/usb/ulpi/
libs-y += common/
-libs-y += lib/libfdt/
libs-$(CONFIG_API) += api/
libs-$(CONFIG_HAS_POST) += post/
libs-y += test/
libs-y += test/dm/
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
-libs-y += arch/$(ARCH)/imx-common/
-endif
-
-ifneq (,$(filter $(SOC), armada-xp kirkwood))
-libs-y += arch/$(ARCH)/mvebu-common/
-endif
-
-libs-$(CONFIG_ARM) += arch/arm/cpu/
-libs-$(CONFIG_PPC) += arch/powerpc/cpu/
-
libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
libs-y := $(sort $(libs-y))
@@ -980,6 +963,9 @@
$(objtree)/tools/ifdtool -w \
$(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \
u-boot.tmp
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME) \
+ u-boot.tmp
mv u-boot.tmp $@
OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
diff --git a/README b/README
index 0c892d8..4ca04d0 100644
--- a/README
+++ b/README
@@ -3661,10 +3661,13 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION
- Address, size and partition on the MMC to load U-Boot from
+ Address and partition on the MMC to load U-Boot from
when the MMC is being used in raw mode.
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+ Partition on the MMC to load U-Boot from when the MMC is being
+ used in raw mode
+
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
Sector to load kernel uImage from when MMC is being
used in raw mode (for Falcon mode)
@@ -3675,6 +3678,10 @@
parameters from when MMC is being used in raw mode
(for falcon mode)
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
+ Partition on the MMC to load U-Boot from when the MMC is being
+ used in fs mode
+
CONFIG_SPL_FAT_SUPPORT
Support for fs/fat/libfat.o in SPL binary
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
new file mode 100644
index 0000000..de25cc9
--- /dev/null
+++ b/arch/arc/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/arc/cpu/$(CPU)/start.o
+
+libs-y += arch/arc/cpu/$(CPU)/
+libs-y += arch/arc/lib/
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b9ac59e..7a64b66 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -396,8 +396,8 @@
bool "Support mx35pdk"
select CPU_ARM1136
-config TARGET_RPI_B
- bool "Support rpi_b"
+config TARGET_RPI
+ bool "Support rpi"
select CPU_ARM1176
config TARGET_TNETV107X_EVM
@@ -793,6 +793,7 @@
bool "Panasonic UniPhier platform"
select CPU_V7
select SUPPORT_SPL
+ select OF_CONTROL if !SPL_BUILD
endchoice
@@ -930,7 +931,7 @@
source "board/phytec/pcm051/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/pxa255_idp/Kconfig"
-source "board/raspberrypi/rpi_b/Kconfig"
+source "board/raspberrypi/rpi/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
source "board/ronetix/pm9g45/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
new file mode 100644
index 0000000..ebb7dc3
--- /dev/null
+++ b/arch/arm/Makefile
@@ -0,0 +1,29 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/arm/cpu/$(CPU)/start.o
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_SPL_START_S_PATH),)
+head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
+endif
+endif
+
+libs-y += arch/arm/cpu/$(CPU)/
+libs-y += arch/arm/cpu/
+libs-y += arch/arm/lib/
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+libs-y += arch/arm/imx-common/
+endif
+else
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
+libs-y += arch/arm/imx-common/
+endif
+endif
+
+ifneq (,$(filter $(SOC), armada-xp kirkwood))
+libs-y += arch/arm/mvebu-common/
+endif
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index fb535eb..cb18908 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -33,8 +33,19 @@
* used. But it not correct to assume that romcode structure
* encoding would be same as u-boot. So use the defined offsets.
*/
- gd->arch.omap_boot_params.omap_bootdevice = boot_device =
- *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+ boot_device = *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+
+#if defined(BOOT_DEVICE_NAND_I2C)
+ /*
+ * Re-map NAND&I2C boot-device to the "normal" NAND boot-device.
+ * Otherwise the SPL boot IF can't handle this device correctly.
+ * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens
+ * Draco leads to this boot-device passed to SPL from the BootROM.
+ */
+ if (boot_device == BOOT_DEVICE_NAND_I2C)
+ boot_device = BOOT_DEVICE_NAND;
+#endif
+ gd->arch.omap_boot_params.omap_bootdevice = boot_device;
gd->arch.omap_boot_params.ch_flags =
*((u8 *)(rom_params + CH_FLAGS_OFFSET));
@@ -57,7 +68,7 @@
}
}
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
/*
* We get different values for QSPI_1 and QSPI_4 being used, but
* don't actually care about this difference. Rather than
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index c8e9bc8..e601ba1 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1226,13 +1226,14 @@
emif1_enabled = 1;
emif2_enabled = 1;
break;
- } else if (valid == 1) {
- emif1_enabled = 1;
- } else if (valid == 2) {
- emif2_enabled = 1;
}
- }
+ if (valid == 1)
+ emif1_enabled = 1;
+
+ if (valid == 2)
+ emif2_enabled = 1;
+ }
}
static void do_bug0039_workaround(u32 base)
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig
index 129982c..aca862d 100644
--- a/arch/arm/cpu/armv7/omap5/Kconfig
+++ b/arch/arm/cpu/armv7/omap5/Kconfig
@@ -12,6 +12,9 @@
config TARGET_DRA7XX_EVM
bool "TI DRA7XX"
+config TARGET_BEAGLE_X15
+ bool "BeagleBoard X15"
+
endchoice
config SYS_SOC
@@ -20,5 +23,6 @@
source "board/compulab/cm_t54/Kconfig"
source "board/ti/omap5_uevm/Kconfig"
source "board/ti/dra7xx/Kconfig"
+source "board/ti/beagle_x15/Kconfig"
endif
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 0257383..95f1686 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -365,31 +365,31 @@
.mpu.value = VDD_MPU_DRA752,
.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.eve.value = VDD_EVE_DRA752,
.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.gpu.value = VDD_GPU_DRA752,
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.core.value = VDD_CORE_DRA752,
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS659038_REG_ADDR_SMPS7_CORE,
+ .core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
.iva.value = VDD_IVA_DRA752,
.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA,
+ .iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
};
@@ -593,7 +593,7 @@
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
-void hw_data_init(void)
+void __weak hw_data_init(void)
{
u32 omap_rev = omap_revision();
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index ff08ef4..0745d42 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -376,6 +376,7 @@
struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_status = 0x4A002134,
+ .control_phy_power_usb = 0x4A002370,
.control_phy_power_sata = 0x4A002374,
.control_core_mac_id_0_lo = 0x4A002514,
.control_core_mac_id_0_hi = 0x4A002518,
@@ -800,6 +801,7 @@
.cm_clkmode_dpll_dsp = 0x4a005234,
.cm_shadow_freq_config1 = 0x4a005260,
.cm_clkmode_dpll_gmac = 0x4a0052a8,
+ .cm_coreaon_usb_phy_core_clkctrl = 0x4a008640,
.cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
/* cm1.mpu */
@@ -906,6 +908,7 @@
.cm_gmac_gmac_clkctrl = 0x4a0093d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
+ .cm_l3init_usb_otg_ss_clkctrl = 0x4a0093f0,
/* cm2.l4per */
.cm_l4per_clkstctrl = 0x4a009700,
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 065199b..7d8cec0 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -513,7 +513,7 @@
.mr16 = MR16_REF_FULL_ARRAY
};
-static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
+void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
const u32 **regs,
u32 *size)
{
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig
index 36b7f11..9760299 100644
--- a/arch/arm/cpu/armv7/uniphier/Kconfig
+++ b/arch/arm/cpu/armv7/uniphier/Kconfig
@@ -5,15 +5,17 @@
default "uniphier"
config SYS_CONFIG_NAME
- default "ph1_pro4" if MACH_PH1_PRO4
- default "ph1_ld4" if MACH_PH1_LD4
- default "ph1_sld8" if MACH_PH1_SLD8
+ default "uniphier"
+
+config UNIPHIER_SMP
+ bool
choice
prompt "UniPhier SoC select"
config MACH_PH1_PRO4
bool "PH1-Pro4"
+ select UNIPHIER_SMP
config MACH_PH1_LD4
bool "PH1-LD4"
@@ -23,6 +25,29 @@
endchoice
+choice
+ prompt "UniPhier Support Card select"
+ optional
+
+config PFC_MICRO_SUPPORT_CARD
+ bool "Support card with PFC CPLD"
+ help
+ This option provides support for the expansion board with PFC
+ original address mapping.
+
+ Say Y to use the on-board UART, Ether, LED devices.
+
+config DCC_MICRO_SUPPORT_CARD
+ bool "Support card with DCC CPLD"
+ help
+ This option provides support for the expansion board with DCC-
+ arranged address mapping that is compatible with legacy UniPhier
+ reference boards.
+
+ Say Y to use the on-board UART, Ether, LED devices.
+
+endchoice
+
config CMD_PINMON
bool "Enable boot mode pins monitor command"
depends on !SPL_BUILD
diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile
index 0f64d25..4a7b8a9 100644
--- a/arch/arm/cpu/armv7/uniphier/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/Makefile
@@ -11,6 +11,7 @@
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o
obj-y += dram_init.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
+obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-$(CONFIG_UNIPHIER_SMP) += smp.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
diff --git a/arch/arm/cpu/armv7/uniphier/board_early_init_r.c b/arch/arm/cpu/armv7/uniphier/board_early_init_r.c
new file mode 100644
index 0000000..cb7e04f
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/board_early_init_r.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/board.h>
+
+int board_early_init_r(void)
+{
+ uniphier_board_late_init();
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/uniphier/board_late_init.c b/arch/arm/cpu/armv7/uniphier/board_late_init.c
index 3730020..0622a1e 100644
--- a/arch/arm/cpu/armv7/uniphier/board_late_init.c
+++ b/arch/arm/cpu/armv7/uniphier/board_late_init.c
@@ -26,42 +26,6 @@
#endif
}
-static void nand_denali_fixup(void)
-{
-#if defined(CONFIG_NAND_DENALI) && \
- (defined(CONFIG_MACH_PH1_SLD8) || defined(CONFIG_MACH_PH1_PRO4))
- /*
- * The Denali NAND controller on some of UniPhier SoCs does not
- * automatically query the device parameters. For those SoCs,
- * some registers must be set after the device is probed.
- */
- void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
- struct mtd_info *mtd;
- struct nand_chip *chip;
-
- if (nand_curr_device < 0 ||
- nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE) {
- /* NAND was not detected. Just return. */
- return;
- }
-
- mtd = &nand_info[nand_curr_device];
- chip = mtd->priv;
-
- writel(mtd->erasesize / mtd->writesize, denali_reg + PAGES_PER_BLOCK);
- writel(0, denali_reg + DEVICE_WIDTH);
- writel(mtd->writesize, denali_reg + DEVICE_MAIN_AREA_SIZE);
- writel(mtd->oobsize, denali_reg + DEVICE_SPARE_AREA_SIZE);
- writel(1, denali_reg + DEVICES_CONNECTED);
-
- /*
- * chip->scan_bbt in nand_scan_tail() has been skipped.
- * It should be done in here.
- */
- chip->scan_bbt(mtd);
-#endif
-}
-
int board_late_init(void)
{
puts("MODE: ");
@@ -70,7 +34,6 @@
case BOOT_DEVICE_MMC1:
printf("eMMC Boot\n");
setenv("bootmode", "emmcboot");
- nand_denali_fixup();
break;
case BOOT_DEVICE_NAND:
printf("NAND Boot\n");
@@ -80,7 +43,6 @@
case BOOT_DEVICE_NOR:
printf("NOR Boot\n");
setenv("bootmode", "norboot");
- nand_denali_fixup();
break;
default:
printf("Unsupported Boot Mode\n");
diff --git a/arch/arm/cpu/armv7/uniphier/init_page_table.c b/arch/arm/cpu/armv7/uniphier/init_page_table.c
index d273835..a0d10a9 100644
--- a/arch/arm/cpu/armv7/uniphier/init_page_table.c
+++ b/arch/arm/cpu/armv7/uniphier/init_page_table.c
@@ -28,7 +28,12 @@
#define IS_SSC(x) ((IS_SPL_TEXT_AREA(x)) || \
(IS_INIT_STACK_AREA(x)))
#define IS_EXT(x) ((x) < 0x100)
-#define IS_REG(x) (0x500 <= (x) && (x) < 0x700)
+
+/* 0x20000000-0x2fffffff, 0xf0000000-0xffffffff are only used by PH1-sLD3 */
+#define IS_REG(x) (0x200 <= (x) && (x) < 0x300) || \
+ (0x500 <= (x) && (x) < 0x700) || \
+ (0xf00 <= (x))
+
#define IS_DDR(x) (0x800 <= (x) && (x) < 0xf00)
#define MMU_FLAGS(x) (IS_SSC(x)) ? SSC : \
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
index fba1cc7..5d682d3 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
@@ -3,7 +3,7 @@
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
-obj-y += platdevice.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
clkrst_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
index 62f5b01..9d51299 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
@@ -14,7 +14,6 @@
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
{
.base = 0x5a800100,
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
index 74129bc..fd1c432 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
@@ -3,7 +3,7 @@
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
-obj-y += platdevice.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
index 1843d04..31ee2a2 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
@@ -14,7 +14,6 @@
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
{
.base = 0x5a800100,
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
index f113db5..3c82a1a 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
@@ -22,16 +22,7 @@
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
- if (readl(SBBASE0) & 0x1) {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x00000000-0x01ffffff: mask ROM
- * 0x02000000-0x3effffff: memory bank (31MB)
- * 0x03f00000-0x3fffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- } else {
+ if (boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
@@ -40,6 +31,15 @@
* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
+ } else {
+ /*
+ * Boot Swap Off: boot from mask ROM
+ * 0x00000000-0x01ffffff: mask ROM
+ * 0x02000000-0x3effffff: memory bank (31MB)
+ * 0x03f00000-0x3fffffff: peripherals (1MB)
+ */
+ writel(0x0000be01, SBBASE0); /* dummy */
+ writel(0x0200be01, SBBASE1);
}
#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
#if !defined(CONFIG_SPL_BUILD)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
index fba1cc7..5d682d3 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
@@ -3,7 +3,7 @@
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
-obj-y += platdevice.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
clkrst_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
index 72ec599..ea0691d 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
@@ -14,7 +14,6 @@
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
{
.base = 0x5a800100,
diff --git a/arch/arm/cpu/armv7/uniphier/support_card.c b/arch/arm/cpu/armv7/uniphier/support_card.c
index 40d4940..419012e 100644
--- a/arch/arm/cpu/armv7/uniphier/support_card.c
+++ b/arch/arm/cpu/armv7/uniphier/support_card.c
@@ -83,6 +83,12 @@
}
#endif
+int check_support_card(void)
+{
+ printf("SC: Micro Support Card ");
+ return support_card_show_revision();
+}
+
void support_card_init(void)
{
/*
@@ -94,12 +100,6 @@
support_card_reset_deassert();
}
-int check_support_card(void)
-{
- printf("SC: Micro Support Card ");
- return support_card_show_revision();
-}
-
#if defined(CONFIG_SMC911X)
#include <netdev.h>
@@ -112,18 +112,14 @@
#if !defined(CONFIG_SYS_NO_FLASH)
#include <mtd/cfi_flash.h>
+#include <asm/arch/sbc-regs.h>
-#if CONFIG_SYS_MAX_FLASH_BANKS > 1
-static phys_addr_t flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS] =
- CONFIG_SYS_FLASH_BANKS_LIST;
+struct memory_bank {
+ phys_addr_t base;
+ unsigned long size;
+};
-phys_addr_t cfi_flash_bank_addr(int i)
-{
- return flash_banks_list[i];
-}
-#endif
-
-int mem_is_flash(phys_addr_t base)
+static int mem_is_flash(const struct memory_bank *mem)
{
const int loop = 128;
u32 *scratch_addr;
@@ -131,8 +127,9 @@
int ret = 1;
int i;
- scratch_addr = map_physmem(base + 0x01e00000,
- sizeof(u32) * loop, MAP_NOCACHE);
+ /* just in case, use the tail of the memory bank */
+ scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop,
+ sizeof(u32) * loop, MAP_NOCACHE);
for (i = 0; i < loop; i++, scratch_addr++) {
saved_value = readl(scratch_addr);
@@ -150,31 +147,79 @@
return ret;
}
-int board_flash_wp_on(void)
-{
- int i;
- int ret = 1;
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+ /* {address, size} */
+static const struct memory_bank memory_banks_boot_swap_off[] = {
+ {0x02000000, 0x01f00000},
+};
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- if (mem_is_flash(cfi_flash_bank_addr(i))) {
- /*
- * We found at least one flash.
- * We need to return 0 and call flash_init().
- */
- ret = 0;
- }
-#if CONFIG_SYS_MAX_FLASH_BANKS > 1
- else {
- /*
- * We might have a SRAM here.
- * To prevent SRAM data from being destroyed,
- * we set dummy address (SDRAM).
- */
- flash_banks_list[i] = 0x80000000 + 0x10000 * i;
- }
+static const struct memory_bank memory_banks_boot_swap_on[] = {
+ {0x00000000, 0x01f00000},
+};
#endif
+
+#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+static const struct memory_bank memory_banks_boot_swap_off[] = {
+ {0x04000000, 0x04000000},
+};
+
+static const struct memory_bank memory_banks_boot_swap_on[] = {
+ {0x00000000, 0x04000000},
+ {0x04000000, 0x04000000},
+};
+#endif
+
+static const struct memory_bank
+*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];
+
+phys_addr_t cfi_flash_bank_addr(int i)
+{
+ return flash_banks_list[i]->base;
+}
+
+unsigned long cfi_flash_bank_size(int i)
+{
+ return flash_banks_list[i]->size;
+}
+
+static void detect_num_flash_banks(void)
+{
+ const struct memory_bank *memory_bank, *end;
+
+ cfi_flash_num_flash_banks = 0;
+
+ if (boot_is_swapped()) {
+ memory_bank = memory_banks_boot_swap_on;
+ end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on);
+ } else {
+ memory_bank = memory_banks_boot_swap_off;
+ end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off);
}
- return ret;
+ for (; memory_bank < end; memory_bank++) {
+ if (cfi_flash_num_flash_banks >=
+ CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
+ break;
+
+ if (mem_is_flash(memory_bank)) {
+ flash_banks_list[cfi_flash_num_flash_banks] =
+ memory_bank;
+
+ debug("flash bank found: base = 0x%lx, size = 0x%lx\n",
+ memory_bank->base, memory_bank->size);
+ cfi_flash_num_flash_banks++;
+ }
+ }
+
+ debug("number of flash banks: %d\n", cfi_flash_num_flash_banks);
}
-#endif
+#else /* ONFIG_SYS_NO_FLASH */
+void detect_num_flash_banks(void)
+{
+};
+#endif /* ONFIG_SYS_NO_FLASH */
+
+void support_card_late_init(void)
+{
+ detect_num_flash_banks();
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e5846ea..187d58c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -32,6 +32,11 @@
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
tegra124-venice2.dtb
+dtb-$(CONFIG_ARCH_UNIPHIER) += \
+ uniphier-ph1-sld3-ref.dtb \
+ uniphier-ph1-pro4-ref.dtb \
+ uniphier-ph1-ld4-ref.dtb \
+ uniphier-ph1-sld8-ref.dtb
dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb \
diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
new file mode 100644
index 0000000..08bbd03
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
@@ -0,0 +1,61 @@
+/*
+ * Device Tree Source for UniPhier PH1-LD4 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-ld4.dtsi"
+
+/ {
+ model = "Panasonic UniPhier PH1-LD4 Reference Board";
+ compatible = "panasonic,ph1-ld4-ref", "panasonic,ph1-ld4";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ uart0 = &uart0;
+ uart1 = &uart1;
+ uart2 = &uart2;
+ uart3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ eeprom {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
new file mode 100644
index 0000000..2a3dd73
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -0,0 +1,120 @@
+/*
+ * Device Tree Source for UniPhier PH1-LD4 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "panasonic,ph1-ld4";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ uart0: serial@54006800 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart1: serial@54006900 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart2: serial@54006a00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart3: serial@54006b00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58400000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58480000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@58500000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58500000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58580000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ };
+
+ nand: nand@68000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
new file mode 100644
index 0000000..23add7c
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
@@ -0,0 +1,63 @@
+/*
+ * Device Tree Source for UniPhier PH1-Pro4 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-pro4.dtsi"
+
+/ {
+ model = "Panasonic UniPhier PH1-Pro4 Reference Board";
+ compatible = "panasonic,ph1-pro4-ref", "panasonic,ph1-pro4";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ uart0 = &uart0;
+ uart1 = &uart1;
+ uart2 = &uart2;
+ uart3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ eeprom {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
new file mode 100644
index 0000000..49e375e
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -0,0 +1,140 @@
+/*
+ * Device Tree Source for UniPhier PH1-Pro4 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "panasonic,ph1-pro4";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ uart0: serial@54006800 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x20>;
+ clock-frequency = <73728000>;
+ };
+
+ uart1: serial@54006900 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x20>;
+ clock-frequency = <73728000>;
+ };
+
+ uart2: serial@54006a00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x20>;
+ clock-frequency = <73728000>;
+ };
+
+ uart3: serial@54006b00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x20>;
+ clock-frequency = <73728000>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58780000 0x80>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58781000 0x80>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58782000 0x80>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58783000 0x80>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ /* i2c4 does not exist */
+
+ i2c5: i2c@58785000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58785000 0x80>;
+ clock-frequency = <400000>;
+ status = "ok";
+ };
+
+ i2c6: i2c@58786000 {
+ compatible = "panasonic,uniphier-fi2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58786000 0x80>;
+ clock-frequency = <400000>;
+ status = "ok";
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ };
+
+ nand: nand@68000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
new file mode 100644
index 0000000..91b4dbe
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
@@ -0,0 +1,60 @@
+/*
+ * Device Tree Source for UniPhier PH1-sLD3 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-sld3.dtsi"
+
+/ {
+ model = "Panasonic UniPhier PH1-sLD3 Reference Board";
+ compatible = "panasonic,ph1-sld3-ref", "panasonic,ph1-sld3";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ uart0 = &uart0;
+ uart1 = &uart1;
+ uart2 = &uart2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ eeprom {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
new file mode 100644
index 0000000..f5529d2
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -0,0 +1,125 @@
+/*
+ * Device Tree Source for UniPhier PH1-sLD3 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "panasonic,ph1-sld3";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ uart0: serial@54006800 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart1: serial@54006900 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ uart2: serial@54006a00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x20>;
+ clock-frequency = <36864000>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58400000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58480000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@58500000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58500000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58580000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ };
+
+ usb3: usb@5a830100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a830100 0x100>;
+ };
+
+ nand: nand@f8000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
new file mode 100644
index 0000000..a8ce049
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
@@ -0,0 +1,61 @@
+/*
+ * Device Tree Source for UniPhier PH1-sLD8 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-sld8.dtsi"
+
+/ {
+ model = "Panasonic UniPhier PH1-sLD8 Reference Board";
+ compatible = "panasonic,ph1-sld8-ref", "panasonic,ph1-sld8";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ uart0 = &uart0;
+ uart1 = &uart1;
+ uart2 = &uart2;
+ uart3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ eeprom {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
new file mode 100644
index 0000000..0ea76e5
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -0,0 +1,120 @@
+/*
+ * Device Tree Source for UniPhier PH1-sLD8 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "panasonic,ph1-sld8";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ uart0: serial@54006800 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x20>;
+ clock-frequency = <80000000>;
+ };
+
+ uart1: serial@54006900 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x20>;
+ clock-frequency = <80000000>;
+ };
+
+ uart2: serial@54006a00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x20>;
+ clock-frequency = <80000000>;
+ };
+
+ uart3: serial@54006b00 {
+ compatible = "panasonic,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x20>;
+ clock-frequency = <80000000>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58400000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58480000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@58500000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58500000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58580000 0x40>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "panasonic,uniphier-ehci", "usb-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ };
+
+ nand: nand@68000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 8543f43..e756418 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -25,6 +25,7 @@
#else
#define BOOT_DEVICE_XIP 2
#define BOOT_DEVICE_NAND 5
+#define BOOT_DEVICE_NAND_I2C 6
#if defined(CONFIG_AM33XX)
#define BOOT_DEVICE_MMC1 8
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h
index 61f427d..0289ba6 100644
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ b/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -119,6 +119,39 @@
* };
*/
+#define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002
+
+/*
+ * 0x2..0xf from:
+ * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/
+ * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733
+ * 0x10, 0x11 from swarren's testing
+ */
+#define BCM2835_BOARD_REV_B_I2C0_2 0x2
+#define BCM2835_BOARD_REV_B_I2C0_3 0x3
+#define BCM2835_BOARD_REV_B_I2C1_4 0x4
+#define BCM2835_BOARD_REV_B_I2C1_5 0x5
+#define BCM2835_BOARD_REV_B_I2C1_6 0x6
+#define BCM2835_BOARD_REV_A_7 0x7
+#define BCM2835_BOARD_REV_A_8 0x8
+#define BCM2835_BOARD_REV_A_9 0x9
+#define BCM2835_BOARD_REV_B_REV2_d 0xd
+#define BCM2835_BOARD_REV_B_REV2_e 0xe
+#define BCM2835_BOARD_REV_B_REV2_f 0xf
+#define BCM2835_BOARD_REV_B_PLUS 0x10
+#define BCM2835_BOARD_REV_CM 0x11
+
+struct bcm2835_mbox_tag_get_board_rev {
+ struct bcm2835_mbox_tag_hdr tag_hdr;
+ union {
+ struct {
+ } req;
+ struct {
+ u32 rev;
+ } resp;
+ } body;
+};
+
#define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003
struct bcm2835_mbox_tag_get_mac_address {
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 30d9de2..0dc584b 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -278,11 +278,11 @@
/* TPS659038 */
#define TPS659038_I2C_SLAVE_ADDR 0x58
-#define TPS659038_REG_ADDR_SMPS12_MPU 0x23
-#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B
-#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F
-#define TPS659038_REG_ADDR_SMPS7_CORE 0x33
-#define TPS659038_REG_ADDR_SMPS8_IVA 0x37
+#define TPS659038_REG_ADDR_SMPS12 0x23
+#define TPS659038_REG_ADDR_SMPS45 0x2B
+#define TPS659038_REG_ADDR_SMPS6 0x2F
+#define TPS659038_REG_ADDR_SMPS7 0x33
+#define TPS659038_REG_ADDR_SMPS8 0x37
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
@@ -314,7 +314,7 @@
*/
#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
#define V_OSCK 20000000 /* Clock output from T2 */
#else
#define V_OSCK 19200000 /* Clock output from T2 */
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index b9600cf..e218159 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -27,7 +27,7 @@
#define CONTROL_CORE_ID_CODE 0x4A002204
#define CONTROL_WKUP_ID_CODE 0x4AE0C204
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
#define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE
#else
#define CONTROL_ID_CODE CONTROL_CORE_ID_CODE
@@ -163,7 +163,7 @@
* much larger) and do not, at this time, make use of the additional
* space.
*/
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
#else
diff --git a/arch/arm/include/asm/arch-uniphier/board.h b/arch/arm/include/asm/arch-uniphier/board.h
index e6ba4e4..e3cba5b 100644
--- a/arch/arm/include/asm/arch-uniphier/board.h
+++ b/arch/arm/include/asm/arch-uniphier/board.h
@@ -12,10 +12,12 @@
defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
void support_card_reset(void);
void support_card_init(void);
+void support_card_late_init(void);
int check_support_card(void);
#else
#define support_card_reset() do {} while (0)
#define support_card_init() do {} while (0)
+#define support_card_late_init() do {} while (0)
static inline int check_support_card(void)
{
return 0;
@@ -32,4 +34,9 @@
support_card_init();
}
+static inline void uniphier_board_late_init(void)
+{
+ support_card_late_init();
+}
+
#endif /* ARCH_BOARD_H */
diff --git a/arch/arm/include/asm/arch-uniphier/gpio.h b/arch/arm/include/asm/arch-uniphier/gpio.h
new file mode 100644
index 0000000..1fc4e19
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/gpio.h
@@ -0,0 +1,6 @@
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h even if GPIO is not supported.
+ */
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 1838234..323952f 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -540,6 +540,7 @@
extern struct prcm_regs const omap4_prcm;
extern struct prcm_regs const dra7xx_prcm;
extern struct dplls const **dplls_data;
+extern struct dplls dra7xx_dplls;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
extern struct omap_sys_ctrl_regs const **ctrl;
@@ -547,6 +548,8 @@
extern struct omap_sys_ctrl_regs const omap5_ctrl;
extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
+extern struct pmic_data tps659038;
+
void hw_data_init(void);
const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
diff --git a/arch/avr32/Makefile b/arch/avr32/Makefile
new file mode 100644
index 0000000..e9b3184
--- /dev/null
+++ b/arch/avr32/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/avr32/cpu/start.o
+
+libs-y += arch/avr32/cpu/
+libs-y += arch/avr32/lib/
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
new file mode 100644
index 0000000..787475e
--- /dev/null
+++ b/arch/blackfin/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/blackfin/cpu/start.o
+
+libs-y += arch/blackfin/cpu/
+libs-y += arch/blackfin/lib/
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
index 69f08bc..aadb0d2 100644
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@@ -11,10 +11,9 @@
#ifdef __KERNEL__
+#include <linux/compiler.h>
#include <asm/blackfin.h>
-#define __iomem
-
static inline void sync(void)
{
SSYNC();
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
new file mode 100644
index 0000000..aa3d2fa
--- /dev/null
+++ b/arch/m68k/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/m68k/cpu/$(CPU)/start.o
+
+libs-y += arch/m68k/cpu/$(CPU)/
+libs-y += arch/m68k/lib/
diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile
new file mode 100644
index 0000000..ae4adc2
--- /dev/null
+++ b/arch/microblaze/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/microblaze/cpu/start.o
+
+libs-y += arch/microblaze/cpu/
+libs-y += arch/microblaze/lib/
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
new file mode 100644
index 0000000..1907b57
--- /dev/null
+++ b/arch/mips/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/mips/cpu/$(CPU)/start.o
+
+libs-y += arch/mips/cpu/$(CPU)/
+libs-y += arch/mips/lib/
diff --git a/arch/mips/include/asm/unaligned.h b/arch/mips/include/asm/unaligned.h
index 1d5112e..c25a846 100644
--- a/arch/mips/include/asm/unaligned.h
+++ b/arch/mips/include/asm/unaligned.h
@@ -8,7 +8,7 @@
#ifndef _ASM_MIPS_UNALIGNED_H
#define _ASM_MIPS_UNALIGNED_H
-#include <compiler.h>
+#include <linux/compiler.h>
#if defined(__MIPSEB__)
#define get_unaligned __get_unaligned_be
#define put_unaligned __put_unaligned_be
diff --git a/arch/nds32/Makefile b/arch/nds32/Makefile
new file mode 100644
index 0000000..e1eccba
--- /dev/null
+++ b/arch/nds32/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/nds32/cpu/$(CPU)/start.o
+
+libs-y += arch/nds32/cpu/$(CPU)/
+libs-y += arch/nds32/lib/
diff --git a/arch/nios2/Makefile b/arch/nios2/Makefile
new file mode 100644
index 0000000..18685a9
--- /dev/null
+++ b/arch/nios2/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/nios2/cpu/start.o
+
+libs-y += arch/nios2/cpu/
+libs-y += arch/nios2/lib/
diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile
new file mode 100644
index 0000000..c4da3ce
--- /dev/null
+++ b/arch/openrisc/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/openrisc/cpu/start.o
+
+libs-y += arch/openrisc/cpu/
+libs-y += arch/openrisc/lib/
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
new file mode 100644
index 0000000..8aa1d60
--- /dev/null
+++ b/arch/powerpc/Makefile
@@ -0,0 +1,11 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/powerpc/cpu/$(CPU)/start.o
+head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o
+head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o
+
+libs-y += arch/powerpc/cpu/$(CPU)/
+libs-y += arch/powerpc/cpu/
+libs-y += arch/powerpc/lib/
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index e447748e..99420ab 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -13,9 +13,6 @@
config TARGET_ESTEEM192E
bool "Support ESTEEM192E"
-config TARGET_HERMES
- bool "Support hermes"
-
config TARGET_IP860
bool "Support IP860"
@@ -112,7 +109,6 @@
source "board/RRvision/Kconfig"
source "board/cogent/Kconfig"
source "board/esteem192e/Kconfig"
-source "board/hermes/Kconfig"
source "board/ip860/Kconfig"
source "board/ivm/Kconfig"
source "board/kup/kup4k/Kconfig"
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 60c401e..6a1cd46 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -125,8 +125,7 @@
* I owe him a free beer. - wd]
*/
-#if defined(CONFIG_HERMES) || \
- defined(CONFIG_IP860) || \
+#if defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
defined(CONFIG_LWMON) || \
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 6eaab88..e6d5355 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -820,13 +820,6 @@
mac_read_from_eeprom();
#endif
-#ifdef CONFIG_HERMES
- if ((gd->board_type >> 16) == 2)
- bd->bi_ethspeed = gd->board_type & 0xFFFF;
- else
- bd->bi_ethspeed = 0xFFFF;
-#endif
-
#ifdef CONFIG_CMD_NET
/* kept around for legacy kernels only ... ignore the next section */
eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
@@ -876,11 +869,6 @@
misc_init_r();
#endif
-#ifdef CONFIG_HERMES
- if (bd->bi_ethspeed != 0xFFFF)
- hermes_start_lxt980((int) bd->bi_ethspeed);
-#endif
-
#if defined(CONFIG_CMD_KGDB)
WATCHDOG_RESET();
puts("KGDB: ");
diff --git a/arch/sandbox/Makefile b/arch/sandbox/Makefile
new file mode 100644
index 0000000..23fdcdb
--- /dev/null
+++ b/arch/sandbox/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/sandbox/cpu/start.o
+
+libs-y += arch/sandbox/cpu/
+libs-y += arch/sandbox/lib/
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 31c9344..4d5f805 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -367,6 +367,7 @@
done:
closedir(dir);
+ free(fname);
return ret;
}
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 0df7770..42353d8 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -130,7 +130,8 @@
state->write_ram_buf = true;
state->ram_buf_fname = arg;
- if (os_read_ram_buf(arg)) {
+ err = os_read_ram_buf(arg);
+ if (err) {
printf("Failed to read RAM buffer\n");
return err;
}
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
new file mode 100644
index 0000000..ca55fac
--- /dev/null
+++ b/arch/sh/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/sh/cpu/$(CPU)/start.o
+
+libs-y += arch/sh/cpu/$(CPU)/
+libs-y += arch/sh/lib/
diff --git a/arch/sh/include/asm/unaligned.h b/arch/sh/include/asm/unaligned.h
index 2e0d164..06096ee 100644
--- a/arch/sh/include/asm/unaligned.h
+++ b/arch/sh/include/asm/unaligned.h
@@ -8,7 +8,7 @@
#include <asm/unaligned-sh4a.h>
#else
/* Otherwise, SH can't handle unaligned accesses. */
-#include <compiler.h>
+#include <linux/compiler.h>
#if defined(__BIG_ENDIAN__)
#define get_unaligned __get_unaligned_be
#define put_unaligned __put_unaligned_be
diff --git a/arch/sparc/Makefile b/arch/sparc/Makefile
new file mode 100644
index 0000000..2d4c971
--- /dev/null
+++ b/arch/sparc/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/sparc/cpu/$(CPU)/start.o
+
+libs-y += arch/sparc/cpu/$(CPU)/
+libs-y += arch/sparc/lib/
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 6e29868..4f5ce38 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -83,6 +83,155 @@
to work correctly. It is not exhaustive but can save time by
detecting obvious failures.
+config MARK_GRAPHICS_MEM_WRCOMB
+ bool "Mark graphics memory as write-combining."
+ default n
+ help
+ The graphics performance may increase if the graphics
+ memory is set as write-combining cache type. This option
+ enables marking the graphics memory as write-combining.
+
+menu "Display"
+
+config FRAMEBUFFER_SET_VESA_MODE
+ prompt "Set framebuffer graphics resolution"
+ bool
+ help
+ Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
+
+choice
+ prompt "framebuffer graphics resolution"
+ default FRAMEBUFFER_VESA_MODE_117
+ depends on FRAMEBUFFER_SET_VESA_MODE
+ help
+ This option sets the resolution used for the coreboot framebuffer (and
+ bootsplash screen).
+
+config FRAMEBUFFER_VESA_MODE_100
+ bool "640x400 256-color"
+
+config FRAMEBUFFER_VESA_MODE_101
+ bool "640x480 256-color"
+
+config FRAMEBUFFER_VESA_MODE_102
+ bool "800x600 16-color"
+
+config FRAMEBUFFER_VESA_MODE_103
+ bool "800x600 256-color"
+
+config FRAMEBUFFER_VESA_MODE_104
+ bool "1024x768 16-color"
+
+config FRAMEBUFFER_VESA_MODE_105
+ bool "1024x7686 256-color"
+
+config FRAMEBUFFER_VESA_MODE_106
+ bool "1280x1024 16-color"
+
+config FRAMEBUFFER_VESA_MODE_107
+ bool "1280x1024 256-color"
+
+config FRAMEBUFFER_VESA_MODE_108
+ bool "80x60 text"
+
+config FRAMEBUFFER_VESA_MODE_109
+ bool "132x25 text"
+
+config FRAMEBUFFER_VESA_MODE_10A
+ bool "132x43 text"
+
+config FRAMEBUFFER_VESA_MODE_10B
+ bool "132x50 text"
+
+config FRAMEBUFFER_VESA_MODE_10C
+ bool "132x60 text"
+
+config FRAMEBUFFER_VESA_MODE_10D
+ bool "320x200 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_10E
+ bool "320x200 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_10F
+ bool "320x200 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_110
+ bool "640x480 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_111
+ bool "640x480 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_112
+ bool "640x480 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_113
+ bool "800x600 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_114
+ bool "800x600 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_115
+ bool "800x600 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_116
+ bool "1024x768 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_117
+ bool "1024x768 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_118
+ bool "1024x768 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_119
+ bool "1280x1024 32k-color (1:5:5:5)"
+
+config FRAMEBUFFER_VESA_MODE_11A
+ bool "1280x1024 64k-color (5:6:5)"
+
+config FRAMEBUFFER_VESA_MODE_11B
+ bool "1280x1024 16.8M-color (8:8:8)"
+
+config FRAMEBUFFER_VESA_MODE_USER
+ bool "Manually select VESA mode"
+
+endchoice
+
+# Map the config names to an integer (KB).
+config FRAMEBUFFER_VESA_MODE
+ prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
+ hex
+ default 0x100 if FRAMEBUFFER_VESA_MODE_100
+ default 0x101 if FRAMEBUFFER_VESA_MODE_101
+ default 0x102 if FRAMEBUFFER_VESA_MODE_102
+ default 0x103 if FRAMEBUFFER_VESA_MODE_103
+ default 0x104 if FRAMEBUFFER_VESA_MODE_104
+ default 0x105 if FRAMEBUFFER_VESA_MODE_105
+ default 0x106 if FRAMEBUFFER_VESA_MODE_106
+ default 0x107 if FRAMEBUFFER_VESA_MODE_107
+ default 0x108 if FRAMEBUFFER_VESA_MODE_108
+ default 0x109 if FRAMEBUFFER_VESA_MODE_109
+ default 0x10A if FRAMEBUFFER_VESA_MODE_10A
+ default 0x10B if FRAMEBUFFER_VESA_MODE_10B
+ default 0x10C if FRAMEBUFFER_VESA_MODE_10C
+ default 0x10D if FRAMEBUFFER_VESA_MODE_10D
+ default 0x10E if FRAMEBUFFER_VESA_MODE_10E
+ default 0x10F if FRAMEBUFFER_VESA_MODE_10F
+ default 0x110 if FRAMEBUFFER_VESA_MODE_110
+ default 0x111 if FRAMEBUFFER_VESA_MODE_111
+ default 0x112 if FRAMEBUFFER_VESA_MODE_112
+ default 0x113 if FRAMEBUFFER_VESA_MODE_113
+ default 0x114 if FRAMEBUFFER_VESA_MODE_114
+ default 0x115 if FRAMEBUFFER_VESA_MODE_115
+ default 0x116 if FRAMEBUFFER_VESA_MODE_116
+ default 0x117 if FRAMEBUFFER_VESA_MODE_117
+ default 0x118 if FRAMEBUFFER_VESA_MODE_118
+ default 0x119 if FRAMEBUFFER_VESA_MODE_119
+ default 0x11A if FRAMEBUFFER_VESA_MODE_11A
+ default 0x11B if FRAMEBUFFER_VESA_MODE_11B
+ default 0x117 if FRAMEBUFFER_VESA_MODE_USER
+
+endmenu
+
source "arch/x86/cpu/ivybridge/Kconfig"
source "board/coreboot/coreboot/Kconfig"
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
new file mode 100644
index 0000000..36a6018
--- /dev/null
+++ b/arch/x86/Makefile
@@ -0,0 +1,12 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+head-y := arch/x86/cpu/start.o
+ifeq ($(CONFIG_SPL_BUILD),y)
+head-y += arch/x86/cpu/start16.o
+head-y += arch/x86/cpu/resetvec.o
+endif
+
+libs-y += arch/x86/cpu/
+libs-y += arch/x86/lib/
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 2b9e9b9..7f09db5 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -13,4 +13,8 @@
obj-y += interrupts.o cpu.o call64.o
obj-$(CONFIG_SYS_COREBOOT) += coreboot/
+obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
+obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
+obj-y += lapic.o
obj-$(CONFIG_PCI) += pci.o
+obj-y += turbo.o
diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk
index f7b01d3..84aeaf3 100644
--- a/arch/x86/cpu/config.mk
+++ b/arch/x86/cpu/config.mk
@@ -12,5 +12,6 @@
# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
LDPPFLAGS += -DRESET_SEG_START=0xffff0000
LDPPFLAGS += -DRESET_SEG_SIZE=0x10000
-LDPPFLAGS += -DRESET_VEC_LOC=0xfff0
-LDPPFLAGS += -DSTART_16=0xf800
+LDPPFLAGS += -DRESET_VEC_LOC=0xfffffff0
+LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16)
+LDPPFLAGS += -DRESET_BASE="CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE)"
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 2df7288..cfacc05 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -39,17 +39,6 @@
return 0;
}
-int board_early_init_r(void)
-{
- /* CPU Speed to 100MHz */
- gd->cpu_clk = 100000000;
-
- /* Crystal is 33.000MHz */
- gd->bus_clk = 33000000;
-
- return 0;
-}
-
int print_cpuinfo(void)
{
return default_print_cpuinfo();
diff --git a/arch/x86/cpu/coreboot/ipchecksum.c b/arch/x86/cpu/coreboot/ipchecksum.c
index 5f6c009..3340872 100644
--- a/arch/x86/cpu/coreboot/ipchecksum.c
+++ b/arch/x86/cpu/coreboot/ipchecksum.c
@@ -29,7 +29,8 @@
* SUCH DAMAGE.
*/
-#include <compiler.h>
+#include <linux/types.h>
+#include <linux/compiler.h>
#include <asm/arch/ipchecksum.h>
unsigned short ipchksum(const void *vptr, unsigned long nbytes)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index b391b7a..30e5069 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -124,7 +124,7 @@
{
struct gdt_ptr gdt;
- gdt.len = (num_entries * 8) - 1;
+ gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
gdt.ptr = (u32)boot_gdt;
asm volatile("lgdtl %0\n" : : "m" (gdt));
@@ -144,10 +144,13 @@
(ulong)&id->arch.gd_addr, 0xfffff);
/* 16-bit CS: code, read/execute, 64 kB, base 0 */
- gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff);
+ gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
/* 16-bit DS: data, read/write, 64 kB, base 0 */
- gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff);
+ gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
+
+ gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
+ gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
load_ds(X86_GDT_ENTRY_32BIT_DS);
@@ -320,14 +323,6 @@
return 0;
}
-int x86_cpu_init_r(void)
-{
- /* Initialize core interrupt and exception functionality of CPU */
- cpu_init_interrupts();
- return 0;
-}
-int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
-
void x86_enable_caches(void)
{
unsigned long cr0;
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index 51e2c59..a21d2a6 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -20,6 +20,7 @@
#include <linux/compiler.h>
#include <asm/msr.h>
#include <asm/u-boot-x86.h>
+#include <asm/i8259.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -128,9 +129,6 @@
int irq_entry_size = irq_1 - irq_0;
void *irq_entry = (void *)irq_0;
- /* Just in case... */
- disable_interrupts();
-
/* Setup the IDT */
for (i = 0; i < 256; i++) {
idt[i].access = 0x8e;
@@ -146,9 +144,6 @@
load_idt(&idt_ptr);
- /* It is now safe to enable interrupts */
- enable_interrupts();
-
return 0;
}
@@ -172,6 +167,25 @@
return flags & X86_EFLAGS_IF;
}
+int interrupt_init(void)
+{
+ /* Just in case... */
+ disable_interrupts();
+
+#ifdef CONFIG_SYS_PCAT_INTERRUPTS
+ /* Initialize the master/slave i8259 pic */
+ i8259_init();
+#endif
+
+ /* Initialize core interrupt and exception functionality of CPU */
+ cpu_init_interrupts();
+
+ /* It is now safe to enable interrupts */
+ enable_interrupts();
+
+ return 0;
+}
+
/* IRQ Low-Level Service Routine */
void irq_llsr(struct irq_regs *regs)
{
@@ -603,31 +617,3 @@
DECLARE_INTERRUPT(253) \
DECLARE_INTERRUPT(254) \
DECLARE_INTERRUPT(255));
-
-#if defined(CONFIG_INTEL_CORE_ARCH)
-/*
- * Get the number of CPU time counter ticks since it was read first time after
- * restart. This yields a free running counter guaranteed to take almost 6
- * years to wrap around even at 100GHz clock rate.
- */
-u64 get_ticks(void)
-{
- u64 now_tick = rdtsc();
-
- if (!gd->arch.tsc_base)
- gd->arch.tsc_base = now_tick;
-
- return now_tick - gd->arch.tsc_base;
-}
-
-#define PLATFORM_INFO_MSR 0xce
-
-unsigned long get_tbclk(void)
-{
- u32 ratio;
- u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
-
- ratio = (platform_info >> 8) & 0xff;
- return 100 * 1000 * 1000 * ratio; /* 100MHz times Max Non Turbo ratio */
-}
-#endif
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 721b37e..0c7efae 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -4,13 +4,21 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += bd82x6x.o
obj-y += car.o
obj-y += cpu.o
obj-y += early_init.o
obj-y += early_me.o
+obj-y += gma.o
obj-y += lpc.o
obj-y += me_status.o
+obj-y += model_206ax.o
obj-y += microcode_intel.o
+obj-y += northbridge.o
+obj-y += pch.o
obj-y += pci.o
obj-y += report_platform.o
+obj-y += sata.o
obj-y += sdram.o
+obj-y += usb_ehci.o
+obj-y += usb_xhci.o
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
new file mode 100644
index 0000000..65a17d3
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/lapic.h>
+#include <asm/pci.h>
+#include <asm/arch/bd82x6x.h>
+#include <asm/arch/model_206ax.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/sandybridge.h>
+
+void bd82x6x_pci_init(pci_dev_t dev)
+{
+ u16 reg16;
+ u8 reg8;
+
+ debug("bd82x6x PCI init.\n");
+ /* Enable Bus Master */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MASTER;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ /* This device has no interrupt */
+ pci_write_config8(dev, INTR, 0xff);
+
+ /* disable parity error response and SERR */
+ reg16 = pci_read_config16(dev, BCTRL);
+ reg16 &= ~(1 << 0);
+ reg16 &= ~(1 << 1);
+ pci_write_config16(dev, BCTRL, reg16);
+
+ /* Master Latency Count must be set to 0x04! */
+ reg8 = pci_read_config8(dev, SMLT);
+ reg8 &= 0x07;
+ reg8 |= (0x04 << 3);
+ pci_write_config8(dev, SMLT, reg8);
+
+ /* Will this improve throughput of bus masters? */
+ pci_write_config8(dev, PCI_MIN_GNT, 0x06);
+
+ /* Clear errors in status registers */
+ reg16 = pci_read_config16(dev, PSTS);
+ /* reg16 |= 0xf900; */
+ pci_write_config16(dev, PSTS, reg16);
+
+ reg16 = pci_read_config16(dev, SECSTS);
+ /* reg16 |= 0xf900; */
+ pci_write_config16(dev, SECSTS, reg16);
+}
+
+#define PCI_BRIDGE_UPDATE_COMMAND
+void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
+{
+ uint16_t command;
+
+ command = pci_read_config16(dev, PCI_COMMAND);
+ command |= PCI_COMMAND_IO;
+#ifdef PCI_BRIDGE_UPDATE_COMMAND
+ /*
+ * If we write to PCI_COMMAND, on some systems this will cause the
+ * ROM and APICs to become invisible.
+ */
+ debug("%x cmd <- %02x\n", dev, command);
+ pci_write_config16(dev, PCI_COMMAND, command);
+#else
+ printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
+#endif
+}
+
+void bd82x6x_pci_bus_enable_resources(pci_dev_t dev)
+{
+ uint16_t ctrl;
+
+ ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ ctrl |= PCI_COMMAND_IO;
+ ctrl |= PCI_BRIDGE_CTL_VGA;
+ debug("%x bridge ctrl <- %04x\n", dev, ctrl);
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
+
+ bd82x6x_pci_dev_enable_resources(dev);
+}
+
+int bd82x6x_init_pci_devices(void)
+{
+ const void *blob = gd->fdt_blob;
+ struct pci_controller *hose;
+ struct x86_cpu_priv *cpu;
+ int sata_node, gma_node;
+ int ret;
+
+ hose = pci_bus_to_hose(0);
+ lpc_enable(PCH_LPC_DEV);
+ lpc_init(hose, PCH_LPC_DEV);
+ sata_node = fdtdec_next_compatible(blob, 0,
+ COMPAT_INTEL_PANTHERPOINT_AHCI);
+ if (sata_node < 0) {
+ debug("%s: Cannot find SATA node\n", __func__);
+ return -EINVAL;
+ }
+ bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node);
+ bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
+ bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
+
+ cpu = calloc(1, sizeof(*cpu));
+ if (!cpu)
+ return -ENOMEM;
+ model_206ax_init(cpu);
+
+ gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA);
+ if (gma_node < 0) {
+ debug("%s: Cannot find GMA node\n", __func__);
+ return -EINVAL;
+ }
+ ret = gma_func0_init(PCH_VIDEO_DEV, pci_bus_to_hose(0), blob,
+ gma_node);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int bd82x6x_init(void)
+{
+ const void *blob = gd->fdt_blob;
+ int sata_node;
+
+ sata_node = fdtdec_next_compatible(blob, 0,
+ COMPAT_INTEL_PANTHERPOINT_AHCI);
+ if (sata_node < 0) {
+ debug("%s: Cannot find SATA node\n", __func__);
+ return -EINVAL;
+ }
+
+ bd82x6x_pci_init(PCH_DEV);
+ bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node);
+ northbridge_enable(PCH_DEV);
+ northbridge_init(PCH_DEV);
+
+ return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
new file mode 100644
index 0000000..3d7f740
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -0,0 +1,756 @@
+/*
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2011 Chromium OS Authors
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <bios_emul.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pci_rom.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/sandybridge.h>
+
+struct gt_powermeter {
+ u16 reg;
+ u32 value;
+};
+
+static const struct gt_powermeter snb_pm_gt1[] = {
+ { 0xa200, 0xcc000000 },
+ { 0xa204, 0x07000040 },
+ { 0xa208, 0x0000fe00 },
+ { 0xa20c, 0x00000000 },
+ { 0xa210, 0x17000000 },
+ { 0xa214, 0x00000021 },
+ { 0xa218, 0x0817fe19 },
+ { 0xa21c, 0x00000000 },
+ { 0xa220, 0x00000000 },
+ { 0xa224, 0xcc000000 },
+ { 0xa228, 0x07000040 },
+ { 0xa22c, 0x0000fe00 },
+ { 0xa230, 0x00000000 },
+ { 0xa234, 0x17000000 },
+ { 0xa238, 0x00000021 },
+ { 0xa23c, 0x0817fe19 },
+ { 0xa240, 0x00000000 },
+ { 0xa244, 0x00000000 },
+ { 0xa248, 0x8000421e },
+ { 0 }
+};
+
+static const struct gt_powermeter snb_pm_gt2[] = {
+ { 0xa200, 0x330000a6 },
+ { 0xa204, 0x402d0031 },
+ { 0xa208, 0x00165f83 },
+ { 0xa20c, 0xf1000000 },
+ { 0xa210, 0x00000000 },
+ { 0xa214, 0x00160016 },
+ { 0xa218, 0x002a002b },
+ { 0xa21c, 0x00000000 },
+ { 0xa220, 0x00000000 },
+ { 0xa224, 0x330000a6 },
+ { 0xa228, 0x402d0031 },
+ { 0xa22c, 0x00165f83 },
+ { 0xa230, 0xf1000000 },
+ { 0xa234, 0x00000000 },
+ { 0xa238, 0x00160016 },
+ { 0xa23c, 0x002a002b },
+ { 0xa240, 0x00000000 },
+ { 0xa244, 0x00000000 },
+ { 0xa248, 0x8000421e },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt1[] = {
+ { 0xa800, 0x00000000 },
+ { 0xa804, 0x00021c00 },
+ { 0xa808, 0x00000403 },
+ { 0xa80c, 0x02001700 },
+ { 0xa810, 0x05000200 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00690500 },
+ { 0xa81c, 0x0000007f },
+ { 0xa820, 0x01002501 },
+ { 0xa824, 0x00000300 },
+ { 0xa828, 0x01000331 },
+ { 0xa82c, 0x0000000c },
+ { 0xa830, 0x00010016 },
+ { 0xa834, 0x01100101 },
+ { 0xa838, 0x00010103 },
+ { 0xa83c, 0x00041300 },
+ { 0xa840, 0x00000b30 },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0x7f000000 },
+ { 0xa84c, 0x05000008 },
+ { 0xa850, 0x00000001 },
+ { 0xa854, 0x00000004 },
+ { 0xa858, 0x00000007 },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00010000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00001c00 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x06000000 },
+ { 0xa910, 0x09000200 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00590000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x04002501 },
+ { 0xa924, 0x00000100 },
+ { 0xa928, 0x03000410 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00020000 },
+ { 0xa934, 0x02070106 },
+ { 0xa938, 0x00010100 },
+ { 0xa93c, 0x00401c00 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x10000e00 },
+ { 0xa94c, 0x02000004 },
+ { 0xa950, 0x00000001 },
+ { 0xa954, 0x00000004 },
+ { 0xa960, 0x00060000 },
+ { 0xaa3c, 0x00001c00 },
+ { 0xaa54, 0x00000004 },
+ { 0xaa60, 0x00060000 },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2[] = {
+ { 0xa800, 0x10000000 },
+ { 0xa804, 0x00033800 },
+ { 0xa808, 0x00000902 },
+ { 0xa80c, 0x0c002f00 },
+ { 0xa810, 0x12000400 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00d20800 },
+ { 0xa81c, 0x00000002 },
+ { 0xa820, 0x03004b02 },
+ { 0xa824, 0x00000600 },
+ { 0xa828, 0x07000773 },
+ { 0xa82c, 0x00000000 },
+ { 0xa830, 0x00010032 },
+ { 0xa834, 0x1520040d },
+ { 0xa838, 0x00020105 },
+ { 0xa83c, 0x00083700 },
+ { 0xa840, 0x0000151d },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0x20001b00 },
+ { 0xa84c, 0x0a000010 },
+ { 0xa850, 0x00000000 },
+ { 0xa854, 0x00000008 },
+ { 0xa858, 0x00000008 },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00020000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00003500 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x0c000000 },
+ { 0xa910, 0x12000500 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00b20000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x08004b02 },
+ { 0xa924, 0x00000200 },
+ { 0xa928, 0x07000820 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00030000 },
+ { 0xa934, 0x050f020d },
+ { 0xa938, 0x00020300 },
+ { 0xa93c, 0x00903900 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x20001b00 },
+ { 0xa94c, 0x0a000010 },
+ { 0xa950, 0x00000000 },
+ { 0xa954, 0x00000008 },
+ { 0xa960, 0x00110000 },
+ { 0xaa3c, 0x00003900 },
+ { 0xaa54, 0x00000008 },
+ { 0xaa60, 0x00110000 },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2_17w[] = {
+ { 0xa800, 0x20000000 },
+ { 0xa804, 0x000e3800 },
+ { 0xa808, 0x00000806 },
+ { 0xa80c, 0x0c002f00 },
+ { 0xa810, 0x0c000800 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00d20d00 },
+ { 0xa81c, 0x000000ff },
+ { 0xa820, 0x03004b02 },
+ { 0xa824, 0x00000600 },
+ { 0xa828, 0x07000773 },
+ { 0xa82c, 0x00000000 },
+ { 0xa830, 0x00020032 },
+ { 0xa834, 0x1520040d },
+ { 0xa838, 0x00020105 },
+ { 0xa83c, 0x00083700 },
+ { 0xa840, 0x000016ff },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0xff000000 },
+ { 0xa84c, 0x0a000010 },
+ { 0xa850, 0x00000002 },
+ { 0xa854, 0x00000008 },
+ { 0xa858, 0x0000000f },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00020000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00003800 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x0c000000 },
+ { 0xa910, 0x12000800 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00b20000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x08004b02 },
+ { 0xa924, 0x00000300 },
+ { 0xa928, 0x01000820 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00030000 },
+ { 0xa934, 0x15150406 },
+ { 0xa938, 0x00020300 },
+ { 0xa93c, 0x00903900 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x20001b00 },
+ { 0xa94c, 0x0a000010 },
+ { 0xa950, 0x00000000 },
+ { 0xa954, 0x00000008 },
+ { 0xa960, 0x00110000 },
+ { 0xaa3c, 0x00003900 },
+ { 0xaa54, 0x00000008 },
+ { 0xaa60, 0x00110000 },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2_35w[] = {
+ { 0xa800, 0x00000000 },
+ { 0xa804, 0x00030400 },
+ { 0xa808, 0x00000806 },
+ { 0xa80c, 0x0c002f00 },
+ { 0xa810, 0x0c000300 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00d20d00 },
+ { 0xa81c, 0x000000ff },
+ { 0xa820, 0x03004b02 },
+ { 0xa824, 0x00000600 },
+ { 0xa828, 0x07000773 },
+ { 0xa82c, 0x00000000 },
+ { 0xa830, 0x00020032 },
+ { 0xa834, 0x1520040d },
+ { 0xa838, 0x00020105 },
+ { 0xa83c, 0x00083700 },
+ { 0xa840, 0x000016ff },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0xff000000 },
+ { 0xa84c, 0x0a000010 },
+ { 0xa850, 0x00000001 },
+ { 0xa854, 0x00000008 },
+ { 0xa858, 0x00000008 },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00020000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00003800 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x0c000000 },
+ { 0xa910, 0x12000800 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00b20000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x08004b02 },
+ { 0xa924, 0x00000300 },
+ { 0xa928, 0x01000820 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00030000 },
+ { 0xa934, 0x15150406 },
+ { 0xa938, 0x00020300 },
+ { 0xa93c, 0x00903900 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x20001b00 },
+ { 0xa94c, 0x0a000010 },
+ { 0xa950, 0x00000000 },
+ { 0xa954, 0x00000008 },
+ { 0xa960, 0x00110000 },
+ { 0xaa3c, 0x00003900 },
+ { 0xaa54, 0x00000008 },
+ { 0xaa60, 0x00110000 },
+ { 0 }
+};
+
+/*
+ * Some vga option roms are used for several chipsets but they only have one
+ * PCI ID in their header. If we encounter such an option rom, we need to do
+ * the mapping ourselves.
+ */
+
+u32 map_oprom_vendev(u32 vendev)
+{
+ u32 new_vendev = vendev;
+
+ switch (vendev) {
+ case 0x80860102: /* GT1 Desktop */
+ case 0x8086010a: /* GT1 Server */
+ case 0x80860112: /* GT2 Desktop */
+ case 0x80860116: /* GT2 Mobile */
+ case 0x80860122: /* GT2 Desktop >=1.3GHz */
+ case 0x80860126: /* GT2 Mobile >=1.3GHz */
+ case 0x80860156: /* IVB */
+ case 0x80860166: /* IVB */
+ /* Set to GT1 Mobile */
+ new_vendev = 0x80860106;
+ break;
+ }
+
+ return new_vendev;
+}
+
+static inline u32 gtt_read(void *bar, u32 reg)
+{
+ return readl(bar + reg);
+}
+
+static inline void gtt_write(void *bar, u32 reg, u32 data)
+{
+ writel(data, bar + reg);
+}
+
+static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
+{
+ for (; pm && pm->reg; pm++)
+ gtt_write(bar, pm->reg, pm->value);
+}
+
+#define GTT_RETRY 1000
+static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
+{
+ unsigned try = GTT_RETRY;
+ u32 data;
+
+ while (try--) {
+ data = gtt_read(bar, reg);
+ if ((data & mask) == value)
+ return 1;
+ udelay(10);
+ }
+
+ printf("GT init timeout\n");
+ return 0;
+}
+
+static int gma_pm_init_pre_vbios(void *gtt_bar)
+{
+ u32 reg32;
+
+ debug("GT Power Management Init, silicon = %#x\n",
+ bridge_silicon_revision());
+
+ if (bridge_silicon_revision() < IVB_STEP_C0) {
+ /* 1: Enable force wake */
+ gtt_write(gtt_bar, 0xa18c, 0x00000001);
+ gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
+ } else {
+ gtt_write(gtt_bar, 0xa180, 1 << 5);
+ gtt_write(gtt_bar, 0xa188, 0xffff0001);
+ gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
+ }
+
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
+ reg32 = gtt_read(gtt_bar, 0x42004);
+ reg32 |= (1 << 14) | (1 << 15);
+ gtt_write(gtt_bar, 0x42004, reg32);
+ }
+
+ if (bridge_silicon_revision() >= IVB_STEP_A0) {
+ /* Display Reset Acknowledge Settings */
+ reg32 = gtt_read(gtt_bar, 0x45010);
+ reg32 |= (1 << 1) | (1 << 0);
+ gtt_write(gtt_bar, 0x45010, reg32);
+ }
+
+ /* 2: Get GT SKU from GTT+0x911c[13] */
+ reg32 = gtt_read(gtt_bar, 0x911c);
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ if (reg32 & (1 << 13)) {
+ debug("SNB GT1 Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, snb_pm_gt1);
+ } else {
+ debug("SNB GT2 Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, snb_pm_gt2);
+ }
+ } else {
+ u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
+
+ if (reg32 & (1 << 13)) {
+ /* GT1 SKU */
+ debug("IVB GT1 Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
+ } else {
+ /* GT2 SKU */
+ u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
+ tdp /= (1 << unit);
+
+ if (tdp <= 17) {
+ /* <=17W ULV */
+ debug("IVB GT2 17W Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
+ } else if ((tdp >= 25) && (tdp <= 35)) {
+ /* 25W-35W */
+ debug("IVB GT2 25W-35W Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
+ } else {
+ /* All others */
+ debug("IVB GT2 35W Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
+ }
+ }
+ }
+
+ /* 3: Gear ratio map */
+ gtt_write(gtt_bar, 0xa004, 0x00000010);
+
+ /* 4: GFXPAUSE */
+ gtt_write(gtt_bar, 0xa000, 0x00070020);
+
+ /* 5: Dynamic EU trip control */
+ gtt_write(gtt_bar, 0xa080, 0x00000004);
+
+ /* 6: ECO bits */
+ reg32 = gtt_read(gtt_bar, 0xa180);
+ reg32 |= (1 << 26) | (1 << 31);
+ /* (bit 20=1 for SNB step D1+ / IVB A0+) */
+ if (bridge_silicon_revision() >= SNB_STEP_D1)
+ reg32 |= (1 << 20);
+ gtt_write(gtt_bar, 0xa180, reg32);
+
+ /* 6a: for SnB step D2+ only */
+ if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&
+ (bridge_silicon_revision() >= SNB_STEP_D2)) {
+ reg32 = gtt_read(gtt_bar, 0x9400);
+ reg32 |= (1 << 7);
+ gtt_write(gtt_bar, 0x9400, reg32);
+
+ reg32 = gtt_read(gtt_bar, 0x941c);
+ reg32 &= 0xf;
+ reg32 |= (1 << 1);
+ gtt_write(gtt_bar, 0x941c, reg32);
+ gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
+ }
+
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ reg32 = gtt_read(gtt_bar, 0x907c);
+ reg32 |= (1 << 16);
+ gtt_write(gtt_bar, 0x907c, reg32);
+
+ /* 6b: Clocking reset controls */
+ gtt_write(gtt_bar, 0x9424, 0x00000001);
+ } else {
+ /* 6b: Clocking reset controls */
+ gtt_write(gtt_bar, 0x9424, 0x00000000);
+ }
+
+ /* 7 */
+ if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
+ gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
+ /* Mailbox Cmd for RC6 VID */
+ gtt_write(gtt_bar, 0x138124, 0x80000004);
+ if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
+ gtt_write(gtt_bar, 0x138124, 0x8000000a);
+ gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
+ }
+
+ /* 8 */
+ gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
+ gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
+ gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
+ gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
+ gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
+ gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
+
+ /* 9 */
+ gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
+ gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
+ gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
+
+ /* 10 */
+ gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
+ gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
+ gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
+ gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
+ gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
+
+ /* 11 */
+ gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
+ gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
+ gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
+ gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
+ gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
+ gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
+ gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
+
+ /* 11a: Enable Render Standby (RC6) */
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ /*
+ * IvyBridge should also support DeepRenderStandby.
+ *
+ * Unfortunately it does not work reliably on all SKUs so
+ * disable it here and it can be enabled by the kernel.
+ */
+ gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
+ } else {
+ gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
+ }
+
+ /* 12: Normal Frequency Request */
+ /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
+ reg32 = readl(MCHBAR_REG(0x5998));
+ reg32 >>= 16;
+ reg32 &= 0xef;
+ reg32 <<= 25;
+ gtt_write(gtt_bar, 0xa008, reg32);
+
+ /* 13: RP Control */
+ gtt_write(gtt_bar, 0xa024, 0x00000592);
+
+ /* 14: Enable PM Interrupts */
+ gtt_write(gtt_bar, 0x4402c, 0x03000076);
+
+ /* Clear 0x6c024 [8:6] */
+ reg32 = gtt_read(gtt_bar, 0x6c024);
+ reg32 &= ~0x000001c0;
+ gtt_write(gtt_bar, 0x6c024, reg32);
+
+ return 0;
+}
+
+int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node)
+{
+ u32 reg32, cycle_delay;
+
+ debug("GT Power Management Init (post VBIOS)\n");
+
+ /* 15: Deassert Force Wake */
+ if (bridge_silicon_revision() < IVB_STEP_C0) {
+ gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
+ gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
+ } else {
+ gtt_write(gtt_bar, 0xa188, 0x1fffe);
+ if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
+ gtt_write(gtt_bar, 0xa188,
+ gtt_read(gtt_bar, 0xa188) | 1);
+ }
+ }
+
+ /* 16: SW RC Control */
+ gtt_write(gtt_bar, 0xa094, 0x00060000);
+
+ /* Setup Digital Port Hotplug */
+ reg32 = gtt_read(gtt_bar, 0xc4030);
+ if (!reg32) {
+ u32 dp_hotplug[3];
+
+ if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
+ dp_hotplug, ARRAY_SIZE(dp_hotplug)))
+ return -EINVAL;
+
+ reg32 = (dp_hotplug[0] & 0x7) << 2;
+ reg32 |= (dp_hotplug[0] & 0x7) << 10;
+ reg32 |= (dp_hotplug[0] & 0x7) << 18;
+ gtt_write(gtt_bar, 0xc4030, reg32);
+ }
+
+ /* Setup Panel Power On Delays */
+ reg32 = gtt_read(gtt_bar, 0xc7208);
+ if (!reg32) {
+ reg32 = (unsigned)fdtdec_get_int(blob, node,
+ "panel-port-select", 0) << 30;
+ reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
+ << 16;
+ reg32 |= fdtdec_get_int(blob, node,
+ "panel-power-backlight-on-delay", 0);
+ gtt_write(gtt_bar, 0xc7208, reg32);
+ }
+
+ /* Setup Panel Power Off Delays */
+ reg32 = gtt_read(gtt_bar, 0xc720c);
+ if (!reg32) {
+ reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
+ << 16;
+ reg32 |= fdtdec_get_int(blob, node,
+ "panel-power-backlight-off-delay", 0);
+ gtt_write(gtt_bar, 0xc720c, reg32);
+ }
+
+ /* Setup Panel Power Cycle Delay */
+ cycle_delay = fdtdec_get_int(blob, node,
+ "intel,panel-power-cycle-delay", 0);
+ if (cycle_delay) {
+ reg32 = gtt_read(gtt_bar, 0xc7210);
+ reg32 &= ~0xff;
+ reg32 |= cycle_delay;
+ gtt_write(gtt_bar, 0xc7210, reg32);
+ }
+
+ /* Enable Backlight if needed */
+ reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
+ if (reg32) {
+ gtt_write(gtt_bar, 0x48250, (1 << 31));
+ gtt_write(gtt_bar, 0x48254, reg32);
+ }
+ reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
+ if (reg32) {
+ gtt_write(gtt_bar, 0xc8250, (1 << 31));
+ gtt_write(gtt_bar, 0xc8254, reg32);
+ }
+
+ return 0;
+}
+
+/*
+ * Some vga option roms are used for several chipsets but they only have one
+ * PCI ID in their header. If we encounter such an option rom, we need to do
+ * the mapping ourselves.
+ */
+
+uint32_t board_map_oprom_vendev(uint32_t vendev)
+{
+ switch (vendev) {
+ case 0x80860102: /* GT1 Desktop */
+ case 0x8086010a: /* GT1 Server */
+ case 0x80860112: /* GT2 Desktop */
+ case 0x80860116: /* GT2 Mobile */
+ case 0x80860122: /* GT2 Desktop >=1.3GHz */
+ case 0x80860126: /* GT2 Mobile >=1.3GHz */
+ case 0x80860156: /* IVB */
+ case 0x80860166: /* IVB */
+ return 0x80860106; /* GT1 Mobile */
+ }
+
+ return vendev;
+}
+
+static int int15_handler(void)
+{
+ int res = 0;
+
+ debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CL = 0x00; /* Use video bios default */
+ res = 1;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000; /* Use video bios default */
+ res = 1;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0003; /* eDP */
+ res = 1;
+ break;
+ case 0x5f70:
+ switch (M.x86.R_CH) {
+ case 0:
+ /* Get Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ res = 1;
+ break;
+ case 1:
+ /* Set Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ res = 1;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ res = 1;
+ break;
+ default:
+ /* Interrupt was not handled */
+ debug("Unknown INT15 5f70 function: 0x%02x\n",
+ M.x86.R_CH);
+ break;
+ }
+ break;
+ case 0x5fac:
+ res = 1;
+ break;
+ default:
+ debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
+ break;
+ }
+ return res;
+}
+
+int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
+ const void *blob, int node)
+{
+ void *gtt_bar;
+ u32 reg32;
+ int ret;
+
+ /* IGD needs to be Bus Master */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0);
+ debug("GT bar %p\n", gtt_bar);
+ ret = gma_pm_init_pre_vbios(gtt_bar);
+ if (ret)
+ return ret;
+
+ ret = pci_run_vga_bios(dev, int15_handler, false);
+
+ /* Post VBIOS init */
+ ret = gma_pm_init_post_vbios(gtt_bar, blob, node);
+ if (ret)
+ return ret;
+
+ return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/gma.h b/arch/x86/cpu/ivybridge/gma.h
new file mode 100644
index 0000000..e7ec649
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/gma.h
@@ -0,0 +1,156 @@
+/*
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2012 Chromium OS Authors
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/* mailbox 0: header */
+__packed struct opregion_header {
+ u8 signature[16];
+ u32 size;
+ u32 version;
+ u8 sbios_version[32];
+ u8 vbios_version[16];
+ u8 driver_version[16];
+ u32 mailboxes;
+ u8 reserved[164];
+};
+
+#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
+#define IGD_OPREGION_VERSION 2
+
+#define IGD_MBOX1 (1 << 0)
+#define IGD_MBOX2 (1 << 1)
+#define IGD_MBOX3 (1 << 2)
+#define IGD_MBOX4 (1 << 3)
+#define IGD_MBOX5 (1 << 4)
+
+#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
+ IGD_MBOX4 | IGD_MBOX5)
+#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
+
+#define SBIOS_VERSION_SIZE 32
+
+/* mailbox 1: public acpi methods */
+__packed struct opregion_mailbox1 {
+ u32 drdy;
+ u32 csts;
+ u32 cevt;
+ u8 reserved1[20];
+ u32 didl[8];
+ u32 cpdl[8];
+ u32 cadl[8];
+ u32 nadl[8];
+ u32 aslp;
+ u32 tidx;
+ u32 chpd;
+ u32 clid;
+ u32 cdck;
+ u32 sxsw;
+ u32 evts;
+ u32 cnot;
+ u32 nrdy;
+ u8 reserved2[60];
+};
+
+/* mailbox 2: software sci interface */
+__packed struct opregion_mailbox2 {
+ u32 scic;
+ u32 parm;
+ u32 dslp;
+ u8 reserved[244];
+};
+
+/* mailbox 3: power conservation */
+__packed struct opregion_mailbox3 {
+ u32 ardy;
+ u32 aslc;
+ u32 tche;
+ u32 alsi;
+ u32 bclp;
+ u32 pfit;
+ u32 cblv;
+ u16 bclm[20];
+ u32 cpfm;
+ u32 epfm;
+ u8 plut[74];
+ u32 pfmb;
+ u32 ccdv;
+ u32 pcft;
+ u8 reserved[94];
+};
+
+#define IGD_BACKLIGHT_BRIGHTNESS 0xff
+#define IGD_INITIAL_BRIGHTNESS 0x64
+
+#define IGD_FIELD_VALID (1 << 31)
+#define IGD_WORD_FIELD_VALID (1 << 15)
+#define IGD_PFIT_STRETCH 6
+
+/* mailbox 4: vbt */
+__packed struct {
+ u8 gvd1[7168];
+} opregion_vbt_t;
+
+/* IGD OpRegion */
+__packed struct igd_opregion {
+ opregion_header_t header;
+ opregion_mailbox1_t mailbox1;
+ opregion_mailbox2_t mailbox2;
+ opregion_mailbox3_t mailbox3;
+ opregion_vbt_t vbt;
+};
+
+/* Intel Video BIOS (Option ROM) */
+__packed struct optionrom_header {
+ u16 signature;
+ u8 size;
+ u8 reserved[21];
+ u16 pcir_offset;
+ u16 vbt_offset;
+};
+
+#define OPROM_SIGNATURE 0xaa55
+
+__packed struct optionrom_pcir {
+ u32 signature;
+ u16 vendor;
+ u16 device;
+ u16 reserved1;
+ u16 length;
+ u8 revision;
+ u8 classcode[3];
+ u16 imagelength;
+ u16 coderevision;
+ u8 codetype;
+ u8 indicator;
+ u16 reserved2;
+};
+
+__packed struct optionrom_vbt {
+ u8 hdr_signature[20];
+ u16 hdr_version;
+ u16 hdr_size;
+ u16 hdr_vbt_size;
+ u8 hdr_vbt_checksum;
+ u8 hdr_reserved;
+ u32 hdr_vbt_datablock;
+ u32 hdr_aim[4];
+ u8 datahdr_signature[16];
+ u16 datahdr_version;
+ u16 datahdr_size;
+ u16 datahdr_datablocksize;
+ u8 coreblock_id;
+ u16 coreblock_size;
+ u16 coreblock_biossize;
+ u8 coreblock_biostype;
+ u8 coreblock_releasestatus;
+ u8 coreblock_hwsupported;
+ u8 coreblock_integratedhw;
+ u8 coreblock_biosbuild[4];
+ u8 coreblock_biossignon[155];
+};
+
+#define VBT_SIGNATURE 0x54425624
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 621ef2c..43fdd314 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -9,10 +9,460 @@
#include <common.h>
#include <errno.h>
#include <fdtdec.h>
+#include <rtc.h>
#include <pci.h>
+#include <asm/acpi.h>
+#include <asm/interrupt.h>
+#include <asm/io.h>
+#include <asm/ioapic.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>
+#define NMI_OFF 0
+
+#define ENABLE_ACPI_MODE_IN_COREBOOT 0
+#define TEST_SMM_FLASH_LOCKDOWN 0
+
+static int pch_enable_apic(pci_dev_t dev)
+{
+ u32 reg32;
+ int i;
+
+ /* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
+ pci_write_config8(dev, ACPI_CNTL, 0x80);
+
+ writel(0, IO_APIC_INDEX);
+ writel(1 << 25, IO_APIC_DATA);
+
+ /* affirm full set of redirection table entries ("write once") */
+ writel(1, IO_APIC_INDEX);
+ reg32 = readl(IO_APIC_DATA);
+ writel(1, IO_APIC_INDEX);
+ writel(reg32, IO_APIC_DATA);
+
+ writel(0, IO_APIC_INDEX);
+ reg32 = readl(IO_APIC_DATA);
+ debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f);
+ if (reg32 != (1 << 25)) {
+ printf("APIC Error - cannot write to registers\n");
+ return -EPERM;
+ }
+
+ debug("Dumping IOAPIC registers\n");
+ for (i = 0; i < 3; i++) {
+ writel(i, IO_APIC_INDEX);
+ debug(" reg 0x%04x:", i);
+ reg32 = readl(IO_APIC_DATA);
+ debug(" 0x%08x\n", reg32);
+ }
+
+ /* Select Boot Configuration register. */
+ writel(3, IO_APIC_INDEX);
+
+ /* Use Processor System Bus to deliver interrupts. */
+ writel(1, IO_APIC_DATA);
+
+ return 0;
+}
+
+static void pch_enable_serial_irqs(pci_dev_t dev)
+{
+ u32 value;
+
+ /* Set packet length and toggle silent mode bit for one frame. */
+ value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
+#ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
+ pci_write_config8(dev, SERIRQ_CNTL, value);
+#else
+ pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
+#endif
+}
+
+static int pch_pirq_init(const void *blob, int node, pci_dev_t dev)
+{
+ uint8_t route[8], *ptr;
+
+ if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route,
+ sizeof(route)))
+ return -EINVAL;
+ ptr = route;
+ pci_write_config8(dev, PIRQA_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQB_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQC_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQD_ROUT, *ptr++);
+
+ pci_write_config8(dev, PIRQE_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQF_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQG_ROUT, *ptr++);
+ pci_write_config8(dev, PIRQH_ROUT, *ptr++);
+
+ /*
+ * TODO(sjg@chromium.org): U-Boot does not set up the interrupts
+ * here. It's unclear if it is needed
+ */
+ return 0;
+}
+
+static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev)
+{
+ u8 route[16];
+ u32 reg;
+ int gpi;
+
+ if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route,
+ sizeof(route)))
+ return -EINVAL;
+
+ for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
+ reg |= route[gpi] << (gpi * 2);
+
+ pci_write_config32(dev, 0xb8, reg);
+
+ return 0;
+}
+
+static int pch_power_options(const void *blob, int node, pci_dev_t dev)
+{
+ u8 reg8;
+ u16 reg16, pmbase;
+ u32 reg32;
+ const char *state;
+ int pwr_on;
+ int nmi_option;
+ int ret;
+
+ /*
+ * Which state do we want to goto after g3 (power restored)?
+ * 0 == S0 Full On
+ * 1 == S5 Soft Off
+ *
+ * If the option is not existent (Laptops), use Kconfig setting.
+ * TODO(sjg@chromium.org): Make this configurable
+ */
+ pwr_on = MAINBOARD_POWER_ON;
+
+ reg16 = pci_read_config16(dev, GEN_PMCON_3);
+ reg16 &= 0xfffe;
+ switch (pwr_on) {
+ case MAINBOARD_POWER_OFF:
+ reg16 |= 1;
+ state = "off";
+ break;
+ case MAINBOARD_POWER_ON:
+ reg16 &= ~1;
+ state = "on";
+ break;
+ case MAINBOARD_POWER_KEEP:
+ reg16 &= ~1;
+ state = "state keep";
+ break;
+ default:
+ state = "undefined";
+ }
+
+ reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
+ reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
+
+ reg16 &= ~(1 << 10);
+ reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
+
+ reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
+
+ pci_write_config16(dev, GEN_PMCON_3, reg16);
+ debug("Set power %s after power failure.\n", state);
+
+ /* Set up NMI on errors. */
+ reg8 = inb(0x61);
+ reg8 &= 0x0f; /* Higher Nibble must be 0 */
+ reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
+ reg8 |= (1 << 2); /* PCI SERR# Disable for now */
+ outb(reg8, 0x61);
+
+ reg8 = inb(0x70);
+ /* TODO(sjg@chromium.org): Make this configurable */
+ nmi_option = NMI_OFF;
+ if (nmi_option) {
+ debug("NMI sources enabled.\n");
+ reg8 &= ~(1 << 7); /* Set NMI. */
+ } else {
+ debug("NMI sources disabled.\n");
+ /* Can't mask NMI from PCI-E and NMI_NOW */
+ reg8 |= (1 << 7);
+ }
+ outb(reg8, 0x70);
+
+ /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
+ reg16 = pci_read_config16(dev, GEN_PMCON_1);
+ reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
+ reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
+#if DEBUG_PERIODIC_SMIS
+ /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
+ reg16 |= (3 << 0); /* Periodic SMI every 8s */
+#endif
+ pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+ /* Set the board's GPI routing. */
+ ret = pch_gpi_routing(blob, node, dev);
+ if (ret)
+ return ret;
+
+ pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
+
+ writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
+ "intel,gpe0-enable", 0));
+ writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
+ "intel,alt-gp-smi-enable", 0));
+
+ /* Set up power management block and determine sleep mode */
+ reg32 = inl(pmbase + 0x04); /* PM1_CNT */
+ reg32 &= ~(7 << 10); /* SLP_TYP */
+ reg32 |= (1 << 0); /* SCI_EN */
+ outl(reg32, pmbase + 0x04);
+
+ /* Clear magic status bits to prevent unexpected wake */
+ setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0));
+ clrbits_le32(RCB_REG(0x3f02), 0xf);
+
+ return 0;
+}
+
+static void pch_rtc_init(pci_dev_t dev)
+{
+ int rtc_failed;
+ u8 reg8;
+
+ reg8 = pci_read_config8(dev, GEN_PMCON_3);
+ rtc_failed = reg8 & RTC_BATTERY_DEAD;
+ if (rtc_failed) {
+ reg8 &= ~RTC_BATTERY_DEAD;
+ pci_write_config8(dev, GEN_PMCON_3, reg8);
+ }
+ debug("rtc_failed = 0x%x\n", rtc_failed);
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* Avoid clearing pending interrupts and resetting the RTC control
+ * register in the resume path because the Linux kernel relies on
+ * this to know if it should restart the RTC timerqueue if the wake
+ * was due to the RTC alarm.
+ */
+ if (acpi_get_slp_type() == 3)
+ return;
+#endif
+ /* TODO: Handle power failure */
+ if (rtc_failed)
+ printf("RTC power failed\n");
+ rtc_init();
+}
+
+/* CougarPoint PCH Power Management init */
+static void cpt_pm_init(pci_dev_t dev)
+{
+ debug("CougarPoint PM init\n");
+ pci_write_config8(dev, 0xa9, 0x47);
+ setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
+
+ setbits_le32(RCB_REG(0x228c), 1 << 0);
+ setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14));
+ setbits_le32(RCB_REG(0x0900), 1 << 14);
+ writel(0xc0388400, RCB_REG(0x2304));
+ setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
+ setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
+ clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf);
+ writel(0x050f0000, RCB_REG(0x3318));
+ writel(0x04000000, RCB_REG(0x3324));
+ setbits_le32(RCB_REG(0x3340), 0xfffff);
+ setbits_le32(RCB_REG(0x3344), 1 << 1);
+
+ writel(0x0001c000, RCB_REG(0x3360));
+ writel(0x00061100, RCB_REG(0x3368));
+ writel(0x7f8fdfff, RCB_REG(0x3378));
+ writel(0x000003fc, RCB_REG(0x337c));
+ writel(0x00001000, RCB_REG(0x3388));
+ writel(0x0001c000, RCB_REG(0x3390));
+ writel(0x00000800, RCB_REG(0x33a0));
+ writel(0x00001000, RCB_REG(0x33b0));
+ writel(0x00093900, RCB_REG(0x33c0));
+ writel(0x24653002, RCB_REG(0x33cc));
+ writel(0x062108fe, RCB_REG(0x33d0));
+ clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
+ writel(0x01010000, RCB_REG(0x3a28));
+ writel(0x01010404, RCB_REG(0x3a2c));
+ writel(0x01041041, RCB_REG(0x3a80));
+ clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
+ setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */
+ setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */
+ writel(0x00000001, RCB_REG(0x3a6c));
+ clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c);
+ clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
+ writel(0, RCB_REG(0x33c8));
+ setbits_le32(RCB_REG(0x21b0), 0xf);
+}
+
+/* PantherPoint PCH Power Management init */
+static void ppt_pm_init(pci_dev_t dev)
+{
+ debug("PantherPoint PM init\n");
+ pci_write_config8(dev, 0xa9, 0x47);
+ setbits_le32(RCB_REG(0x2238), 1 << 0);
+ setbits_le32(RCB_REG(0x228c), 1 << 0);
+ setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
+ setbits_le16(RCB_REG(0x0900), 1 << 14);
+ writel(0xc03b8400, RCB_REG(0x2304));
+ setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
+ setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
+ clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf);
+ writel(0x054f0000, RCB_REG(0x3318));
+ writel(0x04000000, RCB_REG(0x3324));
+ setbits_le32(RCB_REG(0x3340), 0xfffff);
+ setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0));
+ writel(0x0001c000, RCB_REG(0x3360));
+ writel(0x00061100, RCB_REG(0x3368));
+ writel(0x7f8fdfff, RCB_REG(0x3378));
+ writel(0x000003fd, RCB_REG(0x337c));
+ writel(0x00001000, RCB_REG(0x3388));
+ writel(0x0001c000, RCB_REG(0x3390));
+ writel(0x00000800, RCB_REG(0x33a0));
+ writel(0x00001000, RCB_REG(0x33b0));
+ writel(0x00093900, RCB_REG(0x33c0));
+ writel(0x24653002, RCB_REG(0x33cc));
+ writel(0x067388fe, RCB_REG(0x33d0));
+ clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
+ writel(0x01010000, RCB_REG(0x3a28));
+ writel(0x01010404, RCB_REG(0x3a2c));
+ writel(0x01040000, RCB_REG(0x3a80));
+ clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
+ /* SATA 2/3 disabled */
+ setbits_le32(RCB_REG(0x3a84), 1 << 24);
+ /* SATA 4/5 disabled */
+ setbits_le32(RCB_REG(0x3a88), 1 << 0);
+ writel(0x00000001, RCB_REG(0x3a6c));
+ clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c);
+ clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
+ setbits_le32(RCB_REG(0x33a4), (1 << 0));
+ writel(0, RCB_REG(0x33c8));
+ setbits_le32(RCB_REG(0x21b0), 0xf);
+}
+
+static void enable_hpet(void)
+{
+ /* Move HPET to default address 0xfed00000 and enable it */
+ clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7);
+}
+
+static void enable_clock_gating(pci_dev_t dev)
+{
+ u32 reg32;
+ u16 reg16;
+
+ setbits_le32(RCB_REG(0x2234), 0xf);
+
+ reg16 = pci_read_config16(dev, GEN_PMCON_1);
+ reg16 |= (1 << 2) | (1 << 11);
+ pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+ pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
+ pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
+ pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
+ pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
+
+ reg32 = readl(RCB_REG(CG));
+ reg32 |= (1 << 31);
+ reg32 |= (1 << 29) | (1 << 28);
+ reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
+ reg32 |= (1 << 16);
+ reg32 |= (1 << 17);
+ reg32 |= (1 << 18);
+ reg32 |= (1 << 22);
+ reg32 |= (1 << 23);
+ reg32 &= ~(1 << 20);
+ reg32 |= (1 << 19);
+ reg32 |= (1 << 0);
+ reg32 |= (0xf << 1);
+ writel(reg32, RCB_REG(CG));
+
+ setbits_le32(RCB_REG(0x38c0), 0x7);
+ setbits_le32(RCB_REG(0x36d4), 0x6680c004);
+ setbits_le32(RCB_REG(0x3564), 0x3);
+}
+
+#if CONFIG_HAVE_SMI_HANDLER
+static void pch_lock_smm(pci_dev_t dev)
+{
+#if TEST_SMM_FLASH_LOCKDOWN
+ u8 reg8;
+#endif
+
+ if (acpi_slp_type != 3) {
+#if ENABLE_ACPI_MODE_IN_COREBOOT
+ debug("Enabling ACPI via APMC:\n");
+ outb(0xe1, 0xb2); /* Enable ACPI mode */
+ debug("done.\n");
+#else
+ debug("Disabling ACPI via APMC:\n");
+ outb(0x1e, 0xb2); /* Disable ACPI mode */
+ debug("done.\n");
+#endif
+ }
+
+ /* Don't allow evil boot loaders, kernels, or
+ * userspace applications to deceive us:
+ */
+ smm_lock();
+
+#if TEST_SMM_FLASH_LOCKDOWN
+ /* Now try this: */
+ debug("Locking BIOS to RO... ");
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
+ (reg8 & 1) ? "rw" : "ro");
+ reg8 &= ~(1 << 0); /* clear BIOSWE */
+ pci_write_config8(dev, 0xdc, reg8);
+ reg8 |= (1 << 1); /* set BLE */
+ pci_write_config8(dev, 0xdc, reg8);
+ debug("ok.\n");
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
+ (reg8 & 1) ? "rw" : "ro");
+
+ debug("Writing:\n");
+ writeb(0, 0xfff00000);
+ debug("Testing:\n");
+ reg8 |= (1 << 0); /* set BIOSWE */
+ pci_write_config8(dev, 0xdc, reg8);
+
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
+ (reg8 & 1) ? "rw" : "ro");
+ debug("Done.\n");
+#endif
+}
+#endif
+
+static void pch_disable_smm_only_flashing(pci_dev_t dev)
+{
+ u8 reg8;
+
+ debug("Enabling BIOS updates outside of SMM... ");
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 &= ~(1 << 5);
+ pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void pch_fixups(pci_dev_t dev)
+{
+ u8 gen_pmcon_2;
+
+ /* Indicate DRAM init done for MRC S3 to know it can resume */
+ gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2);
+ gen_pmcon_2 |= (1 << 7);
+ pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
+
+ /* Enable DMI ASPM in the PCH */
+ clrbits_le32(RCB_REG(0x2304), 1 << 10);
+ setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10));
+ setbits_le32(RCB_REG(0x21a8), 0x3);
+}
+
int lpc_early_init(const void *blob, int node, pci_dev_t dev)
{
struct reg_info {
@@ -22,7 +472,7 @@
int count;
int i;
- count = fdtdec_get_int_array_count(blob, node, "gen-dec",
+ count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec",
(u32 *)values, sizeof(values) / sizeof(u32));
if (count < 0)
return -EINVAL;
@@ -46,3 +496,74 @@
return 0;
}
+
+int lpc_init(struct pci_controller *hose, pci_dev_t dev)
+{
+ const void *blob = gd->fdt_blob;
+ int node;
+
+ debug("pch: lpc_init\n");
+ pci_write_bar32(hose, dev, 0, 0);
+ pci_write_bar32(hose, dev, 1, 0xff800000);
+ pci_write_bar32(hose, dev, 2, 0xfec00000);
+ pci_write_bar32(hose, dev, 3, 0x800);
+ pci_write_bar32(hose, dev, 4, 0x900);
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
+ if (node < 0)
+ return -ENOENT;
+
+ /* Set the value for PCI command register. */
+ pci_write_config16(dev, PCI_COMMAND, 0x000f);
+
+ /* IO APIC initialization. */
+ pch_enable_apic(dev);
+
+ pch_enable_serial_irqs(dev);
+
+ /* Setup the PIRQ. */
+ pch_pirq_init(blob, node, dev);
+
+ /* Setup power options. */
+ pch_power_options(blob, node, dev);
+
+ /* Initialize power management */
+ switch (pch_silicon_type()) {
+ case PCH_TYPE_CPT: /* CougarPoint */
+ cpt_pm_init(dev);
+ break;
+ case PCH_TYPE_PPT: /* PantherPoint */
+ ppt_pm_init(dev);
+ break;
+ default:
+ printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev),
+ PCI_FUNC(dev));
+ return -ENOSYS;
+ }
+
+ /* Initialize the real time clock. */
+ pch_rtc_init(dev);
+
+ /* Initialize the High Precision Event Timers, if present. */
+ enable_hpet();
+
+ /* Initialize Clock Gating */
+ enable_clock_gating(dev);
+
+ pch_disable_smm_only_flashing(dev);
+
+#if CONFIG_HAVE_SMI_HANDLER
+ pch_lock_smm(dev);
+#endif
+
+ pch_fixups(dev);
+
+ return 0;
+}
+
+void lpc_enable(pci_dev_t dev)
+{
+ /* Enable PCH Display Port */
+ writew(0x0010, RCB_REG(DISPBDF));
+ setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
+}
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
new file mode 100644
index 0000000..11dc625
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -0,0 +1,514 @@
+/*
+ * From Coreboot file of same name
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium Authors
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/acpi.h>
+#include <asm/cpu.h>
+#include <asm/lapic.h>
+#include <asm/lapic_def.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
+#include <asm/processor.h>
+#include <asm/speedstep.h>
+#include <asm/turbo.h>
+#include <asm/arch/model_206ax.h>
+
+static void enable_vmx(void)
+{
+ struct cpuid_result regs;
+#ifdef CONFIG_ENABLE_VMX
+ int enable = true;
+#else
+ int enable = false;
+#endif
+ msr_t msr;
+
+ regs = cpuid(1);
+ /* Check that the VMX is supported before reading or writing the MSR. */
+ if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX)))
+ return;
+
+ msr = msr_read(MSR_IA32_FEATURE_CONTROL);
+
+ if (msr.lo & (1 << 0)) {
+ debug("VMX is locked, so %s will do nothing\n", __func__);
+ /* VMX locked. If we set it again we get an illegal
+ * instruction
+ */
+ return;
+ }
+
+ /* The IA32_FEATURE_CONTROL MSR may initialize with random values.
+ * It must be cleared regardless of VMX config setting.
+ */
+ msr.hi = 0;
+ msr.lo = 0;
+
+ debug("%s VMX\n", enable ? "Enabling" : "Disabling");
+
+ /*
+ * Even though the Intel manual says you must set the lock bit in
+ * addition to the VMX bit in order for VMX to work, it is incorrect.
+ * Thus we leave it unlocked for the OS to manage things itself.
+ * This is good for a few reasons:
+ * - No need to reflash the bios just to toggle the lock bit.
+ * - The VMX bits really really should match each other across cores,
+ * so hard locking it on one while another has the opposite setting
+ * can easily lead to crashes as code using VMX migrates between
+ * them.
+ * - Vendors that want to "upsell" from a bios that disables+locks to
+ * one that doesn't is sleazy.
+ * By leaving this to the OS (e.g. Linux), people can do exactly what
+ * they want on the fly, and do it correctly (e.g. across multiple
+ * cores).
+ */
+ if (enable) {
+ msr.lo |= (1 << 2);
+ if (regs.ecx & CPUID_SMX)
+ msr.lo |= (1 << 1);
+ }
+
+ msr_write(MSR_IA32_FEATURE_CONTROL, msr);
+}
+
+/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
+static const u8 power_limit_time_sec_to_msr[] = {
+ [0] = 0x00,
+ [1] = 0x0a,
+ [2] = 0x0b,
+ [3] = 0x4b,
+ [4] = 0x0c,
+ [5] = 0x2c,
+ [6] = 0x4c,
+ [7] = 0x6c,
+ [8] = 0x0d,
+ [10] = 0x2d,
+ [12] = 0x4d,
+ [14] = 0x6d,
+ [16] = 0x0e,
+ [20] = 0x2e,
+ [24] = 0x4e,
+ [28] = 0x6e,
+ [32] = 0x0f,
+ [40] = 0x2f,
+ [48] = 0x4f,
+ [56] = 0x6f,
+ [64] = 0x10,
+ [80] = 0x30,
+ [96] = 0x50,
+ [112] = 0x70,
+ [128] = 0x11,
+};
+
+/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
+static const u8 power_limit_time_msr_to_sec[] = {
+ [0x00] = 0,
+ [0x0a] = 1,
+ [0x0b] = 2,
+ [0x4b] = 3,
+ [0x0c] = 4,
+ [0x2c] = 5,
+ [0x4c] = 6,
+ [0x6c] = 7,
+ [0x0d] = 8,
+ [0x2d] = 10,
+ [0x4d] = 12,
+ [0x6d] = 14,
+ [0x0e] = 16,
+ [0x2e] = 20,
+ [0x4e] = 24,
+ [0x6e] = 28,
+ [0x0f] = 32,
+ [0x2f] = 40,
+ [0x4f] = 48,
+ [0x6f] = 56,
+ [0x10] = 64,
+ [0x30] = 80,
+ [0x50] = 96,
+ [0x70] = 112,
+ [0x11] = 128,
+};
+
+int cpu_config_tdp_levels(void)
+{
+ struct cpuid_result result;
+ msr_t platform_info;
+
+ /* Minimum CPU revision */
+ result = cpuid(1);
+ if (result.eax < IVB_CONFIG_TDP_MIN_CPUID)
+ return 0;
+
+ /* Bits 34:33 indicate how many levels supported */
+ platform_info = msr_read(MSR_PLATFORM_INFO);
+ return (platform_info.hi >> 1) & 3;
+}
+
+/*
+ * Configure processor power limits if possible
+ * This must be done AFTER set of BIOS_RESET_CPL
+ */
+void set_power_limits(u8 power_limit_1_time)
+{
+ msr_t msr = msr_read(MSR_PLATFORM_INFO);
+ msr_t limit;
+ unsigned power_unit;
+ unsigned tdp, min_power, max_power, max_time;
+ u8 power_limit_1_val;
+
+ if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
+ return;
+
+ if (!(msr.lo & PLATFORM_INFO_SET_TDP))
+ return;
+
+ /* Get units */
+ msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
+ power_unit = 2 << ((msr.lo & 0xf) - 1);
+
+ /* Get power defaults for this SKU */
+ msr = msr_read(MSR_PKG_POWER_SKU);
+ tdp = msr.lo & 0x7fff;
+ min_power = (msr.lo >> 16) & 0x7fff;
+ max_power = msr.hi & 0x7fff;
+ max_time = (msr.hi >> 16) & 0x7f;
+
+ debug("CPU TDP: %u Watts\n", tdp / power_unit);
+
+ if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
+ power_limit_1_time = power_limit_time_msr_to_sec[max_time];
+
+ if (min_power > 0 && tdp < min_power)
+ tdp = min_power;
+
+ if (max_power > 0 && tdp > max_power)
+ tdp = max_power;
+
+ power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
+
+ /* Set long term power limit to TDP */
+ limit.lo = 0;
+ limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
+ limit.lo |= PKG_POWER_LIMIT_EN;
+ limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
+ PKG_POWER_LIMIT_TIME_SHIFT;
+
+ /* Set short term power limit to 1.25 * TDP */
+ limit.hi = 0;
+ limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
+ limit.hi |= PKG_POWER_LIMIT_EN;
+ /* Power limit 2 time is only programmable on SNB EP/EX */
+
+ msr_write(MSR_PKG_POWER_LIMIT, limit);
+
+ /* Use nominal TDP values for CPUs with configurable TDP */
+ if (cpu_config_tdp_levels()) {
+ msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+ limit.hi = 0;
+ limit.lo = msr.lo & 0xff;
+ msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
+ }
+}
+
+static void configure_c_states(void)
+{
+ struct cpuid_result result;
+ msr_t msr;
+
+ msr = msr_read(MSR_PMG_CST_CONFIG_CTL);
+ msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
+ msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
+ msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
+ msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
+ msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
+ msr.lo |= 7; /* No package C-state limit */
+ msr_write(MSR_PMG_CST_CONFIG_CTL, msr);
+
+ msr = msr_read(MSR_PMG_IO_CAPTURE_ADR);
+ msr.lo &= ~0x7ffff;
+ msr.lo |= (PMB0_BASE + 4); /* LVL_2 base address */
+ msr.lo |= (2 << 16); /* CST Range: C7 is max C-state */
+ msr_write(MSR_PMG_IO_CAPTURE_ADR, msr);
+
+ msr = msr_read(MSR_MISC_PWR_MGMT);
+ msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
+ msr_write(MSR_MISC_PWR_MGMT, msr);
+
+ msr = msr_read(MSR_POWER_CTL);
+ msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
+ msr.lo |= (1 << 1); /* C1E Enable */
+ msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
+ msr_write(MSR_POWER_CTL, msr);
+
+ /* C3 Interrupt Response Time Limit */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
+ msr_write(MSR_PKGC3_IRTL, msr);
+
+ /* C6 Interrupt Response Time Limit */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
+ msr_write(MSR_PKGC6_IRTL, msr);
+
+ /* C7 Interrupt Response Time Limit */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
+ msr_write(MSR_PKGC7_IRTL, msr);
+
+ /* Primary Plane Current Limit */
+ msr = msr_read(MSR_PP0_CURRENT_CONFIG);
+ msr.lo &= ~0x1fff;
+ msr.lo |= PP0_CURRENT_LIMIT;
+ msr_write(MSR_PP0_CURRENT_CONFIG, msr);
+
+ /* Secondary Plane Current Limit */
+ msr = msr_read(MSR_PP1_CURRENT_CONFIG);
+ msr.lo &= ~0x1fff;
+ result = cpuid(1);
+ if (result.eax >= 0x30600)
+ msr.lo |= PP1_CURRENT_LIMIT_IVB;
+ else
+ msr.lo |= PP1_CURRENT_LIMIT_SNB;
+ msr_write(MSR_PP1_CURRENT_CONFIG, msr);
+}
+
+static int configure_thermal_target(void)
+{
+ int tcc_offset;
+ msr_t msr;
+ int node;
+
+ /* Find pointer to CPU configuration */
+ node = fdtdec_next_compatible(gd->fdt_blob, 0,
+ COMPAT_INTEL_MODEL_206AX);
+ if (node < 0)
+ return -ENOENT;
+ tcc_offset = fdtdec_get_int(gd->fdt_blob, node, "tcc-offset", 0);
+
+ /* Set TCC activaiton offset if supported */
+ msr = msr_read(MSR_PLATFORM_INFO);
+ if ((msr.lo & (1 << 30)) && tcc_offset) {
+ msr = msr_read(MSR_TEMPERATURE_TARGET);
+ msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+ msr.lo |= (tcc_offset & 0xf) << 24;
+ msr_write(MSR_TEMPERATURE_TARGET, msr);
+ }
+
+ return 0;
+}
+
+static void configure_misc(void)
+{
+ msr_t msr;
+
+ msr = msr_read(IA32_MISC_ENABLE);
+ msr.lo |= (1 << 0); /* Fast String enable */
+ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr_write(IA32_MISC_ENABLE, msr);
+
+ /* Disable Thermal interrupts */
+ msr.lo = 0;
+ msr.hi = 0;
+ msr_write(IA32_THERM_INTERRUPT, msr);
+
+ /* Enable package critical interrupt only */
+ msr.lo = 1 << 4;
+ msr.hi = 0;
+ msr_write(IA32_PACKAGE_THERM_INTERRUPT, msr);
+}
+
+static void enable_lapic_tpr(void)
+{
+ msr_t msr;
+
+ msr = msr_read(MSR_PIC_MSG_CONTROL);
+ msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
+ msr_write(MSR_PIC_MSG_CONTROL, msr);
+}
+
+static void configure_dca_cap(void)
+{
+ struct cpuid_result cpuid_regs;
+ msr_t msr;
+
+ /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+ cpuid_regs = cpuid(1);
+ if (cpuid_regs.ecx & (1 << 18)) {
+ msr = msr_read(IA32_PLATFORM_DCA_CAP);
+ msr.lo |= 1;
+ msr_write(IA32_PLATFORM_DCA_CAP, msr);
+ }
+}
+
+static void set_max_ratio(void)
+{
+ msr_t msr, perf_ctl;
+
+ perf_ctl.hi = 0;
+
+ /* Check for configurable TDP option */
+ if (cpu_config_tdp_levels()) {
+ /* Set to nominal TDP ratio */
+ msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+ perf_ctl.lo = (msr.lo & 0xff) << 8;
+ } else {
+ /* Platform Info bits 15:8 give max ratio */
+ msr = msr_read(MSR_PLATFORM_INFO);
+ perf_ctl.lo = msr.lo & 0xff00;
+ }
+ msr_write(IA32_PERF_CTL, perf_ctl);
+
+ debug("model_x06ax: frequency set to %d\n",
+ ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
+}
+
+static void set_energy_perf_bias(u8 policy)
+{
+ msr_t msr;
+
+ /* Energy Policy is bits 3:0 */
+ msr = msr_read(IA32_ENERGY_PERFORMANCE_BIAS);
+ msr.lo &= ~0xf;
+ msr.lo |= policy & 0xf;
+ msr_write(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+
+ debug("model_x06ax: energy policy set to %u\n", policy);
+}
+
+static void configure_mca(void)
+{
+ msr_t msr;
+ int i;
+
+ msr.lo = 0;
+ msr.hi = 0;
+ /* This should only be done on a cold boot */
+ for (i = 0; i < 7; i++)
+ msr_write(IA32_MC0_STATUS + (i * 4), msr);
+}
+
+#if CONFIG_USBDEBUG
+static unsigned ehci_debug_addr;
+#endif
+
+/*
+ * Initialize any extra cores/threads in this package.
+ */
+static int intel_cores_init(struct x86_cpu_priv *cpu)
+{
+ struct cpuid_result result;
+ unsigned threads_per_package, threads_per_core, i;
+
+ /* Logical processors (threads) per core */
+ result = cpuid_ext(0xb, 0);
+ threads_per_core = result.ebx & 0xffff;
+
+ /* Logical processors (threads) per package */
+ result = cpuid_ext(0xb, 1);
+ threads_per_package = result.ebx & 0xffff;
+
+ debug("CPU: %u has %u cores, %u threads per core\n",
+ cpu->apic_id, threads_per_package / threads_per_core,
+ threads_per_core);
+
+ for (i = 1; i < threads_per_package; ++i) {
+ struct x86_cpu_priv *new_cpu;
+
+ new_cpu = calloc(1, sizeof(*new_cpu));
+ if (!new_cpu)
+ return -ENOMEM;
+
+ new_cpu->apic_id = cpu->apic_id + i;
+
+ /* Update APIC ID if no hyperthreading */
+ if (threads_per_core == 1)
+ new_cpu->apic_id <<= 1;
+
+ debug("CPU: %u has core %u\n", cpu->apic_id, new_cpu->apic_id);
+
+#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+ /* Start the new cpu */
+ if (!start_cpu(new_cpu)) {
+ /* Record the error in cpu? */
+ printk(BIOS_ERR, "CPU %u would not start!\n",
+ new_cpu->apic_id);
+ new_cpu->start_err = 1;
+ }
+#endif
+ }
+
+ return 0;
+}
+
+int model_206ax_init(struct x86_cpu_priv *cpu)
+{
+ int ret;
+
+ /* Clear out pending MCEs */
+ configure_mca();
+
+#if CONFIG_USBDEBUG
+ /* Is this caution really needed? */
+ if (!ehci_debug_addr)
+ ehci_debug_addr = get_ehci_debug();
+ set_ehci_debug(0);
+#endif
+
+ /* Setup MTRRs based on physical address size */
+#if 0 /* TODO: Implement this */
+ struct cpuid_result cpuid_regs;
+
+ cpuid_regs = cpuid(0x80000008);
+ x86_setup_fixed_mtrrs();
+ x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2);
+ x86_mtrr_check();
+#endif
+
+#if CONFIG_USBDEBUG
+ set_ehci_debug(ehci_debug_addr);
+#endif
+
+ /* Enable the local cpu apics */
+ enable_lapic_tpr();
+ lapic_setup();
+
+ /* Enable virtualization if enabled in CMOS */
+ enable_vmx();
+
+ /* Configure C States */
+ configure_c_states();
+
+ /* Configure Enhanced SpeedStep and Thermal Sensors */
+ configure_misc();
+
+ /* Thermal throttle activation offset */
+ ret = configure_thermal_target();
+ if (ret)
+ return ret;
+
+ /* Enable Direct Cache Access */
+ configure_dca_cap();
+
+ /* Set energy policy */
+ set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+ /* Set Max Ratio */
+ set_max_ratio();
+
+ /* Enable Turbo */
+ turbo_enable();
+
+ /* Start up extra cores */
+ intel_cores_init(cpu);
+
+ return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
new file mode 100644
index 0000000..c50b5de
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -0,0 +1,188 @@
+/*
+ * From Coreboot northbridge/intel/sandybridge/northbridge.c
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium Authors
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/msr.h>
+#include <asm/acpi.h>
+#include <asm/cpu.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/processor.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/model_206ax.h>
+#include <asm/arch/sandybridge.h>
+
+static int bridge_revision_id = -1;
+
+int bridge_silicon_revision(void)
+{
+ if (bridge_revision_id < 0) {
+ struct cpuid_result result;
+ uint8_t stepping, bridge_id;
+ pci_dev_t dev;
+
+ result = cpuid(1);
+ stepping = result.eax & 0xf;
+ dev = PCI_BDF(0, 0, 0);
+ bridge_id = pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
+ bridge_revision_id = bridge_id | stepping;
+ }
+
+ return bridge_revision_id;
+}
+
+/*
+ * Reserve everything between A segment and 1MB:
+ *
+ * 0xa0000 - 0xbffff: legacy VGA
+ * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
+ * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
+ */
+static const int legacy_hole_base_k = 0xa0000 / 1024;
+static const int legacy_hole_size_k = 384;
+
+static int get_pcie_bar(u32 *base, u32 *len)
+{
+ pci_dev_t dev = PCI_BDF(0, 0, 0);
+ u32 pciexbar_reg;
+
+ *base = 0;
+ *len = 0;
+
+ pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+
+ if (!(pciexbar_reg & (1 << 0)))
+ return 0;
+
+ switch ((pciexbar_reg >> 1) & 3) {
+ case 0: /* 256MB */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28));
+ *len = 256 * 1024 * 1024;
+ return 1;
+ case 1: /* 128M */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28) | (1 << 27));
+ *len = 128 * 1024 * 1024;
+ return 1;
+ case 2: /* 64M */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28) | (1 << 27) | (1 << 26));
+ *len = 64 * 1024 * 1024;
+ return 1;
+ }
+
+ return 0;
+}
+
+static void add_fixed_resources(pci_dev_t dev, int index)
+{
+ u32 pcie_config_base, pcie_config_size;
+
+ if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
+ debug("Adding PCIe config bar base=0x%08x size=0x%x\n",
+ pcie_config_base, pcie_config_size);
+ }
+}
+
+static void northbridge_dmi_init(pci_dev_t dev)
+{
+ /* Clear error status bits */
+ writel(0xffffffff, DMIBAR_REG(0x1c4));
+ writel(0xffffffff, DMIBAR_REG(0x1d0));
+
+ /* Steps prior to DMI ASPM */
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20),
+ 1 << 21);
+ }
+
+ setbits_le32(DMIBAR_REG(0x238), 1 << 29);
+
+ if (bridge_silicon_revision() >= SNB_STEP_D0) {
+ setbits_le32(DMIBAR_REG(0x1f8), 1 << 16);
+ } else if (bridge_silicon_revision() >= SNB_STEP_D1) {
+ clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16);
+ setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23));
+ }
+
+ /* Enable ASPM on SNB link, should happen before PCH link */
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB)
+ setbits_le32(DMIBAR_REG(0xd04), 1 << 4);
+
+ setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0));
+}
+
+void northbridge_init(pci_dev_t dev)
+{
+ u32 bridge_type;
+
+ add_fixed_resources(dev, 6);
+ northbridge_dmi_init(dev);
+
+ bridge_type = readl(MCHBAR_REG(0x5f10));
+ bridge_type &= ~0xff;
+
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ /* Enable Power Aware Interrupt Routing - fixed priority */
+ clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4);
+
+ /* 30h for IvyBridge */
+ bridge_type |= 0x30;
+ } else {
+ /* 20h for Sandybridge */
+ bridge_type |= 0x20;
+ }
+ writel(bridge_type, MCHBAR_REG(0x5f10));
+
+ /*
+ * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
+ * that BIOS has initialized memory and power management
+ */
+ setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1);
+ debug("Set BIOS_RESET_CPL\n");
+
+ /* Configure turbo power limits 1ms after reset complete bit */
+ mdelay(1);
+ set_power_limits(28);
+
+ /*
+ * CPUs with configurable TDP also need power limits set
+ * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT.
+ */
+ if (cpu_config_tdp_levels()) {
+ msr_t msr = msr_read(MSR_PKG_POWER_LIMIT);
+
+ writel(msr.lo, MCHBAR_REG(0x59A0));
+ writel(msr.hi, MCHBAR_REG(0x59A4));
+ }
+
+ /* Set here before graphics PM init */
+ writel(0x00100001, MCHBAR_REG(0x5500));
+}
+
+void northbridge_enable(pci_dev_t dev)
+{
+#if CONFIG_HAVE_ACPI_RESUME
+ switch (pci_read_config32(dev, SKPAD)) {
+ case 0xcafebabe:
+ debug("Normal boot.\n");
+ apci_set_slp_type(0);
+ break;
+ case 0xcafed00d:
+ debug("S3 Resume.\n");
+ apci_set_slp_type(3);
+ break;
+ default:
+ debug("Unknown boot method, assuming normal.\n");
+ apci_set_slp_type(0);
+ break;
+ }
+#endif
+}
diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c
new file mode 100644
index 0000000..fa04d48
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/pch.c
@@ -0,0 +1,123 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+static int pch_revision_id = -1;
+static int pch_type = -1;
+
+int pch_silicon_revision(void)
+{
+ pci_dev_t dev;
+
+ dev = PCH_LPC_DEV;
+
+ if (pch_revision_id < 0)
+ pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID);
+ return pch_revision_id;
+}
+
+int pch_silicon_type(void)
+{
+ pci_dev_t dev;
+
+ dev = PCH_LPC_DEV;
+
+ if (pch_type < 0)
+ pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1);
+ return pch_type;
+}
+
+int pch_silicon_supported(int type, int rev)
+{
+ int cur_type = pch_silicon_type();
+ int cur_rev = pch_silicon_revision();
+
+ switch (type) {
+ case PCH_TYPE_CPT:
+ /* CougarPoint minimum revision */
+ if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
+ return 1;
+ /* PantherPoint any revision */
+ if (cur_type == PCH_TYPE_PPT)
+ return 1;
+ break;
+
+ case PCH_TYPE_PPT:
+ /* PantherPoint minimum revision */
+ if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
+ return 1;
+ break;
+ }
+
+ return 0;
+}
+
+#define IOBP_RETRY 1000
+static inline int iobp_poll(void)
+{
+ unsigned try = IOBP_RETRY;
+ u32 data;
+
+ while (try--) {
+ data = readl(RCB_REG(IOBPS));
+ if ((data & 1) == 0)
+ return 1;
+ udelay(10);
+ }
+
+ printf("IOBP timeout\n");
+ return 0;
+}
+
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+{
+ u32 data;
+
+ /* Set the address */
+ writel(address, RCB_REG(IOBPIRI));
+
+ /* READ OPCODE */
+ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
+ writel(IOBPS_RW_BX, RCB_REG(IOBPS));
+ else
+ writel(IOBPS_READ_AX, RCB_REG(IOBPS));
+ if (!iobp_poll())
+ return;
+
+ /* Read IOBP data */
+ data = readl(RCB_REG(IOBPD));
+ if (!iobp_poll())
+ return;
+
+ /* Check for successful transaction */
+ if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) {
+ printf("IOBP read 0x%08x failed\n", address);
+ return;
+ }
+
+ /* Update the data */
+ data &= andvalue;
+ data |= orvalue;
+
+ /* WRITE OPCODE */
+ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
+ writel(IOBPS_RW_BX, RCB_REG(IOBPS));
+ else
+ writel(IOBPS_WRITE_AX, RCB_REG(IOBPS));
+ if (!iobp_poll())
+ return;
+
+ /* Write IOBP data */
+ writel(data, RCB_REG(IOBPD));
+ if (!iobp_poll())
+ return;
+}
diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
index c1ae658..452d1c3 100644
--- a/arch/x86/cpu/ivybridge/pci.c
+++ b/arch/x86/cpu/ivybridge/pci.c
@@ -12,6 +12,8 @@
#include <common.h>
#include <pci.h>
#include <asm/pci.h>
+#include <asm/arch/bd82x6x.h>
+#include <asm/arch/pch.h>
static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *table)
@@ -58,3 +60,41 @@
hose->region_count = 3;
}
+
+int board_pci_pre_scan(struct pci_controller *hose)
+{
+ pci_dev_t dev;
+ u16 reg16;
+
+ bd82x6x_init();
+
+ reg16 = 0xff;
+ dev = PCH_DEV;
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+ pci_write_bar32(hose, dev, 0, 0xf0000000);
+
+ return 0;
+}
+
+int board_pci_post_scan(struct pci_controller *hose)
+{
+ int ret;
+
+ ret = bd82x6x_init_pci_devices();
+ if (ret) {
+ printf("bd82x6x_init_pci_devices() failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
new file mode 100644
index 0000000..bbcd47d
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -0,0 +1,225 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/bd82x6x.h>
+
+static inline u32 sir_read(pci_dev_t dev, int idx)
+{
+ pci_write_config32(dev, SATA_SIRI, idx);
+ return pci_read_config32(dev, SATA_SIRD);
+}
+
+static inline void sir_write(pci_dev_t dev, int idx, u32 value)
+{
+ pci_write_config32(dev, SATA_SIRI, idx);
+ pci_write_config32(dev, SATA_SIRD, value);
+}
+
+static void common_sata_init(pci_dev_t dev, unsigned int port_map)
+{
+ u32 reg32;
+ u16 reg16;
+
+ /* Set IDE I/O Configuration */
+ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+ pci_write_config32(dev, IDE_CONFIG, reg32);
+
+ /* Port enable */
+ reg16 = pci_read_config16(dev, 0x92);
+ reg16 &= ~0x3f;
+ reg16 |= port_map;
+ pci_write_config16(dev, 0x92, reg16);
+
+ /* SATA Initialization register */
+ port_map &= 0xff;
+ pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
+}
+
+void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
+{
+ unsigned int port_map, speed_support, port_tx;
+ struct pci_controller *hose = pci_bus_to_hose(0);
+ const char *mode;
+ u32 reg32;
+ u16 reg16;
+
+ debug("SATA: Initializing...\n");
+
+ /* SATA configuration */
+ port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
+ speed_support = fdtdec_get_int(blob, node,
+ "sata_interface_speed_support", 0);
+
+ /* Enable BARs */
+ pci_write_config16(dev, PCI_COMMAND, 0x0007);
+
+ mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
+ if (!mode || !strcmp(mode, "ahci")) {
+ u32 abar;
+
+ debug("SATA: Controller in AHCI mode\n");
+
+ /* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */
+ pci_write_config8(dev, INTR_LN, 0x0a);
+
+ /* Set timings */
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+ IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+
+ /* Sync DMA */
+ pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
+
+ common_sata_init(dev, 0x8000 | port_map);
+
+ /* Initialize AHCI memory-mapped space */
+ abar = pci_read_bar32(hose, dev, 5);
+ debug("ABAR: %08X\n", abar);
+ /* CAP (HBA Capabilities) : enable power management */
+ reg32 = readl(abar + 0x00);
+ reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */
+ reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
+ /* Set ISS, if available */
+ if (speed_support) {
+ reg32 &= ~0x00f00000;
+ reg32 |= (speed_support & 0x03) << 20;
+ }
+ writel(reg32, abar + 0x00);
+ /* PI (Ports implemented) */
+ writel(port_map, abar + 0x0c);
+ (void) readl(abar + 0x0c); /* Read back 1 */
+ (void) readl(abar + 0x0c); /* Read back 2 */
+ /* CAP2 (HBA Capabilities Extended)*/
+ reg32 = readl(abar + 0x24);
+ reg32 &= ~0x00000002;
+ writel(reg32, abar + 0x24);
+ /* VSP (Vendor Specific Register */
+ reg32 = readl(abar + 0xa0);
+ reg32 &= ~0x00000005;
+ writel(reg32, abar + 0xa0);
+ } else if (!strcmp(mode, "combined")) {
+ debug("SATA: Controller in combined mode\n");
+
+ /* No AHCI: clear AHCI base */
+ pci_write_bar32(hose, dev, 5, 0x00000000);
+ /* And without AHCI BAR no memory decoding */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 &= ~PCI_COMMAND_MEMORY;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ pci_write_config8(dev, 0x09, 0x80);
+
+ /* Set timings */
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+ IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+
+ /* Sync DMA */
+ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
+
+ common_sata_init(dev, port_map);
+ } else {
+ debug("SATA: Controller in plain-ide mode\n");
+
+ /* No AHCI: clear AHCI base */
+ pci_write_bar32(hose, dev, 5, 0x00000000);
+
+ /* And without AHCI BAR no memory decoding */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 &= ~PCI_COMMAND_MEMORY;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ /*
+ * Native mode capable on both primary and secondary (0xa)
+ * OR'ed with enabled (0x50) = 0xf
+ */
+ pci_write_config8(dev, 0x09, 0x8f);
+
+ /* Set Interrupt Line */
+ /* Interrupt Pin is set by D31IP.PIP */
+ pci_write_config8(dev, INTR_LN, 0xff);
+
+ /* Set timings */
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+ IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_SITRE | IDE_ISP_3_CLOCKS |
+ IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
+
+ /* Sync DMA */
+ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
+
+ common_sata_init(dev, port_map);
+ }
+
+ /* Set Gen3 Transmitter settings if needed */
+ port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
+ if (port_tx)
+ pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx);
+
+ port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
+ if (port_tx)
+ pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx);
+
+ /* Additional Programming Requirements */
+ sir_write(dev, 0x04, 0x00001600);
+ sir_write(dev, 0x28, 0xa0000033);
+ reg32 = sir_read(dev, 0x54);
+ reg32 &= 0xff000000;
+ reg32 |= 0x5555aa;
+ sir_write(dev, 0x54, reg32);
+ sir_write(dev, 0x64, 0xcccc8484);
+ reg32 = sir_read(dev, 0x68);
+ reg32 &= 0xffff0000;
+ reg32 |= 0xcccc;
+ sir_write(dev, 0x68, reg32);
+ reg32 = sir_read(dev, 0x78);
+ reg32 &= 0x0000ffff;
+ reg32 |= 0x88880000;
+ sir_write(dev, 0x78, reg32);
+ sir_write(dev, 0x84, 0x001c7000);
+ sir_write(dev, 0x88, 0x88338822);
+ sir_write(dev, 0xa0, 0x001c7000);
+ sir_write(dev, 0xc4, 0x0c0c0c0c);
+ sir_write(dev, 0xc8, 0x0c0c0c0c);
+ sir_write(dev, 0xd4, 0x10000000);
+
+ pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
+ pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
+}
+
+void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
+{
+ unsigned port_map;
+ const char *mode;
+ u16 map = 0;
+
+ /*
+ * Set SATA controller mode early so the resource allocator can
+ * properly assign IO/Memory resources for the controller.
+ */
+ mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
+ if (mode && !strcmp(mode, "ahci"))
+ map = 0x0060;
+ port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
+
+ map |= (port_map ^ 0x3f) << 8;
+ pci_write_config16(dev, 0x90, map);
+}
diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c
new file mode 100644
index 0000000..291c971
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/usb_ehci.c
@@ -0,0 +1,29 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+void bd82x6x_usb_ehci_init(pci_dev_t dev)
+{
+ u32 reg32;
+
+ /* Disable Wake on Disconnect in RMH */
+ reg32 = readl(RCB_REG(0x35b0));
+ reg32 |= 0x22;
+ writel(reg32, RCB_REG(0x35b0));
+
+ debug("EHCI: Setting up controller.. ");
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER;
+ /* reg32 |= PCI_COMMAND_SERR; */
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ debug("done.\n");
+}
diff --git a/arch/x86/cpu/ivybridge/usb_xhci.c b/arch/x86/cpu/ivybridge/usb_xhci.c
new file mode 100644
index 0000000..4a32a7e
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/usb_xhci.c
@@ -0,0 +1,32 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+void bd82x6x_usb_xhci_init(pci_dev_t dev)
+{
+ u32 reg32;
+
+ debug("XHCI: Setting up controller.. ");
+
+ /* lock overcurrent map */
+ reg32 = pci_read_config32(dev, 0x44);
+ reg32 |= 1;
+ pci_write_config32(dev, 0x44, reg32);
+
+ /* Enable clock gating */
+ reg32 = pci_read_config32(dev, 0x40);
+ reg32 &= ~((1 << 20) | (1 << 21));
+ reg32 |= (1 << 19) | (1 << 18) | (1 << 17);
+ reg32 |= (1 << 10) | (1 << 9) | (1 << 8);
+ reg32 |= (1 << 31); /* lock */
+ pci_write_config32(dev, 0x40, reg32);
+
+ debug("done.\n");
+}
diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c
new file mode 100644
index 0000000..4690603
--- /dev/null
+++ b/arch/x86/cpu/lapic.c
@@ -0,0 +1,57 @@
+/*
+ * From coreboot file of same name
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/msr.h>
+#include <asm/io.h>
+#include <asm/lapic.h>
+#include <asm/post.h>
+
+void lapic_setup(void)
+{
+#if NEED_LAPIC == 1
+ /* Only Pentium Pro and later have those MSR stuff */
+ debug("Setting up local apic: ");
+
+ /* Enable the local apic */
+ enable_lapic();
+
+ /*
+ * Set Task Priority to 'accept all'.
+ */
+ lapic_write_around(LAPIC_TASKPRI,
+ lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
+
+ /* Put the local apic in virtual wire mode */
+ lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) &
+ ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
+ lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) &
+ ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+ LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+ LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+ LAPIC_DELIVERY_MODE_MASK)) |
+ (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+ LAPIC_DELIVERY_MODE_EXTINT));
+ lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) &
+ ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+ LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+ LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+ LAPIC_DELIVERY_MODE_MASK)) |
+ (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+ LAPIC_DELIVERY_MODE_NMI));
+
+ debug("apic_id: 0x%02lx, ", lapicid());
+#else /* !NEED_LLAPIC */
+ /* Only Pentium Pro and later have those MSR stuff */
+ debug("Disabling local apic: ");
+ disable_lapic();
+#endif /* !NEED_LAPIC */
+ debug("done.\n");
+ post_code(POST_LAPIC);
+}
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index e399388..f3492c3 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -33,6 +33,16 @@
return 0;
}
+__weak int board_pci_pre_scan(struct pci_controller *hose)
+{
+ return 0;
+}
+
+__weak int board_pci_post_scan(struct pci_controller *hose)
+{
+ return 0;
+}
+
void pci_init_board(void)
{
struct pci_controller *hose = &x86_hose;
@@ -44,7 +54,9 @@
pci_setup_type1(hose);
pci_register_hose(hose);
+ board_pci_pre_scan(hose);
hose->last_busno = pci_hose_scan(hose);
+ board_pci_post_scan(hose);
}
static struct pci_controller *get_hose(void)
diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c
new file mode 100644
index 0000000..254d0de
--- /dev/null
+++ b/arch/x86/cpu/turbo.c
@@ -0,0 +1,98 @@
+/*
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2011 The Chromium Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/cpu.h>
+#include <asm/msr.h>
+#include <asm/processor.h>
+#include <asm/turbo.h>
+
+#if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+static inline int get_global_turbo_state(void)
+{
+ return TURBO_UNKNOWN;
+}
+
+static inline void set_global_turbo_state(int state)
+{
+}
+#else
+static int g_turbo_state = TURBO_UNKNOWN;
+
+static inline int get_global_turbo_state(void)
+{
+ return g_turbo_state;
+}
+
+static inline void set_global_turbo_state(int state)
+{
+ g_turbo_state = state;
+}
+#endif
+
+static const char *const turbo_state_desc[] = {
+ [TURBO_UNKNOWN] = "unknown",
+ [TURBO_UNAVAILABLE] = "unavailable",
+ [TURBO_DISABLED] = "available but hidden",
+ [TURBO_ENABLED] = "available and visible"
+};
+
+/*
+ * Determine the current state of Turbo and cache it for later.
+ * Turbo is a package level config so it does not need to be
+ * enabled on every core.
+ */
+int turbo_get_state(void)
+{
+ struct cpuid_result cpuid_regs;
+ int turbo_en, turbo_cap;
+ msr_t msr;
+ int turbo_state = get_global_turbo_state();
+
+ /* Return cached state if available */
+ if (turbo_state != TURBO_UNKNOWN)
+ return turbo_state;
+
+ cpuid_regs = cpuid(CPUID_LEAF_PM);
+ turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE);
+
+ msr = msr_read(MSR_IA32_MISC_ENABLES);
+ turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO);
+
+ if (!turbo_cap && turbo_en) {
+ /* Unavailable */
+ turbo_state = TURBO_UNAVAILABLE;
+ } else if (!turbo_cap && !turbo_en) {
+ /* Available but disabled */
+ turbo_state = TURBO_DISABLED;
+ } else if (turbo_cap && turbo_en) {
+ /* Available */
+ turbo_state = TURBO_ENABLED;
+ }
+
+ set_global_turbo_state(turbo_state);
+ debug("Turbo is %s\n", turbo_state_desc[turbo_state]);
+ return turbo_state;
+}
+
+void turbo_enable(void)
+{
+ msr_t msr;
+
+ /* Only possible if turbo is available but hidden */
+ if (turbo_get_state() == TURBO_DISABLED) {
+ /* Clear Turbo Disable bit in Misc Enables */
+ msr = msr_read(MSR_IA32_MISC_ENABLES);
+ msr.hi &= ~H_MISC_DISABLE_TURBO;
+ msr_write(MSR_IA32_MISC_ENABLES, msr);
+
+ /* Update cached turbo state */
+ set_global_turbo_state(TURBO_ENABLED);
+ debug("Turbo has been enabled\n");
+ }
+}
diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds
index f48bff5..b0d8531 100644
--- a/arch/x86/cpu/u-boot.lds
+++ b/arch/x86/cpu/u-boot.lds
@@ -44,7 +44,9 @@
. = ALIGN(4);
__rel_dyn_start = .;
- .rel.dyn : { *(.rel.dyn) }
+ .rel.dyn : {
+ *(.rel*)
+ }
__rel_dyn_end = .;
. = ALIGN(4);
_end = .;
@@ -64,15 +66,19 @@
/DISCARD/ : { *(.gnu*) }
#ifdef CONFIG_X86_RESET_VECTOR
-
/*
* The following expressions place the 16-bit Real-Mode code and
* Reset Vector at the end of the Flash ROM
*/
- . = START_16;
- .start16 : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + START_16)) { KEEP(*(.start16)); }
+ . = START_16 - RESET_SEG_START;
+ .start16 : AT (START_16) {
+ KEEP(*(.start16));
+ }
- . = RESET_VEC_LOC;
- .resetvec : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); }
+ . = RESET_VEC_LOC - RESET_SEG_START;
+ .resetvec : AT (RESET_VEC_LOC) {
+ KEEP(*(.resetvec));
+ }
#endif
+
}
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index 9329916..592af16 100644
--- a/arch/x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
@@ -163,21 +163,51 @@
};
};
- lpc {
- compatible = "intel,lpc";
- #address-cells = <1>;
- #size-cells = <1>;
- gen-dec = <0x800 0xfc 0x900 0xfc>;
- cros-ec@200 {
- compatible = "google,cros-ec";
- reg = <0x204 1 0x200 1 0x880 0x80>;
+ pci {
+ sata {
+ compatible = "intel,pantherpoint-ahci";
+ intel,sata-mode = "ahci";
+ intel,sata-port-map = <1>;
+ intel,sata-port0-gen3-tx = <0x00880a7f>;
+ };
- /* This describes the flash memory within the EC */
+ gma {
+ compatible = "intel,gma";
+ intel,dp_hotplug = <0 0 0x06>;
+ intel,panel-port-select = <1>;
+ intel,panel-power-cycle-delay = <6>;
+ intel,panel-power-up-delay = <2000>;
+ intel,panel-power-down-delay = <500>;
+ intel,panel-power-backlight-on-delay = <2000>;
+ intel,panel-power-backlight-off-delay = <2000>;
+ intel,cpu-backlight = <0x00000200>;
+ intel,pch-backlight = <0x04000000>;
+ };
+
+ lpc {
+ compatible = "intel,lpc";
#address-cells = <1>;
#size-cells = <1>;
- flash@8000000 {
- reg = <0x08000000 0x20000>;
- erase-value = <0xff>;
+ gen-dec = <0x800 0xfc 0x900 0xfc>;
+ intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
+ intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
+ 0x80 0x80 0x80 0x80>;
+ intel,gpi-routing = <0 0 0 0 0 0 0 2
+ 1 0 0 0 0 0 0 0>;
+ /* Enable EC SMI source */
+ intel,alt-gp-smi-enable = <0x0100>;
+
+ cros-ec@200 {
+ compatible = "google,cros-ec";
+ reg = <0x204 1 0x200 1 0x880 0x80>;
+
+ /* Describes the flash memory within the EC */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ flash@8000000 {
+ reg = <0x08000000 0x20000>;
+ erase-value = <0xff>;
+ };
};
};
};
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
new file mode 100644
index 0000000..4872b92
--- /dev/null
+++ b/arch/x86/include/asm/acpi.h
@@ -0,0 +1,24 @@
+/*
+ * From coreboot
+ *
+ * Copyright (C) 2004 SUSE LINUX AG
+ * Copyright (C) 2004 Nick Barker
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * (Written by Stefan Reinauer <stepan@coresystems.de>)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_ACPI_H
+#define __ASM_ACPI_H
+
+#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */
+#define ACPI_TABLE_CREATOR "U-BootAC" /* Must be exactly 8 bytes long! */
+#define OEM_ID "U-Boot" /* Must be exactly 6 bytes long! */
+#define ASLC "U-Bo" /* Must be exactly 4 bytes long! */
+
+/* 0 = S0, 1 = S1 ...*/
+int acpi_get_slp_type(void);
+void apci_set_slp_type(int type);
+
+#endif
diff --git a/arch/x86/include/asm/arch-coreboot/sysinfo.h b/arch/x86/include/asm/arch-coreboot/sysinfo.h
index 8e4a61d..832c50a 100644
--- a/arch/x86/include/asm/arch-coreboot/sysinfo.h
+++ b/arch/x86/include/asm/arch-coreboot/sysinfo.h
@@ -10,7 +10,7 @@
#define _COREBOOT_SYSINFO_H
#include <common.h>
-#include <compiler.h>
+#include <linux/compiler.h>
#include <libfdt.h>
#include <asm/arch/tables.h>
diff --git a/arch/x86/include/asm/arch-coreboot/tables.h b/arch/x86/include/asm/arch-coreboot/tables.h
index 0d02fe0..e254484 100644
--- a/arch/x86/include/asm/arch-coreboot/tables.h
+++ b/arch/x86/include/asm/arch-coreboot/tables.h
@@ -9,7 +9,7 @@
#ifndef _COREBOOT_TABLES_H
#define _COREBOOT_TABLES_H
-#include <compiler.h>
+#include <linux/compiler.h>
struct cbuint64 {
u32 lo;
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
new file mode 100644
index 0000000..e1d9a9b
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_BD82X6X_H
+#define _ASM_ARCH_BD82X6X_H
+
+void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node);
+void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
+void bd82x6x_pci_init(pci_dev_t dev);
+void bd82x6x_usb_ehci_init(pci_dev_t dev);
+void bd82x6x_usb_xhci_init(pci_dev_t dev);
+int bd82x6x_init_pci_devices(void);
+int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
+ const void *blob, int node);
+int bd82x6x_init(void);
+
+struct x86_cpu_priv;
+int model_206ax_init(struct x86_cpu_priv *cpu);
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
index 8281d7a..7b4f2e7 100644
--- a/arch/x86/include/asm/arch-ivybridge/model_206ax.h
+++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
@@ -79,4 +79,8 @@
#define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10
+/* Configure power limits for turbo mode */
+void set_power_limits(u8 power_limit_1_time);
+int cpu_config_tdp_levels(void);
+
#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index c6efdb8..21df083 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -14,11 +14,41 @@
#include <pci.h>
+/* PCH types */
+#define PCH_TYPE_CPT 0x1c /* CougarPoint */
+#define PCH_TYPE_PPT 0x1e /* IvyBridge */
+
+/* PCH stepping values for LPC device */
+#define PCH_STEP_A0 0
+#define PCH_STEP_A1 1
+#define PCH_STEP_B0 2
+#define PCH_STEP_B1 3
+#define PCH_STEP_B2 4
+#define PCH_STEP_B3 5
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
#define SMBUS_IO_BASE 0x0400
+int pch_silicon_revision(void);
+int pch_silicon_type(void);
+int pch_silicon_supported(int type, int rev);
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
+
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON 1
+#define MAINBOARD_POWER_KEEP 2
+
+/* PCI Configuration Space (D30:F0): PCI2PCI */
+#define PSTS 0x06
+#define SMLT 0x1b
+#define SECSTS 0x1e
+#define INTR 0x3c
+#define BCTRL 0x3e
+#define SBR (1 << 6)
+#define SEE (1 << 1)
+#define PERE (1 << 0)
+
#define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
#define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
@@ -30,6 +60,35 @@
/* PCI Configuration Space (D31:F0): LPC */
#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
+#define SERIRQ_CNTL 0x64
+
+#define GEN_PMCON_1 0xa0
+#define GEN_PMCON_2 0xa2
+#define GEN_PMCON_3 0xa4
+#define ETR3 0xac
+#define ETR3_CWORWRE (1 << 18)
+#define ETR3_CF9GR (1 << 20)
+
+/* GEN_PMCON_3 bits */
+#define RTC_BATTERY_DEAD (1 << 2)
+#define RTC_POWER_FAILED (1 << 1)
+#define SLEEP_AFTER_POWER_FAIL (1 << 0)
+
+#define PMBASE 0x40
+#define ACPI_CNTL 0x44
+#define BIOS_CNTL 0xDC
+#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
+#define GPIO_ROUT 0xb8
+
+#define PIRQA_ROUT 0x60
+#define PIRQB_ROUT 0x61
+#define PIRQC_ROUT 0x62
+#define PIRQD_ROUT 0x63
+#define PIRQE_ROUT 0x68
+#define PIRQF_ROUT 0x69
+#define PIRQG_ROUT 0x6A
+#define PIRQH_ROUT 0x6B
#define GEN_PMCON_1 0xa0
#define GEN_PMCON_2 0xa2
@@ -63,6 +122,64 @@
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
#define LPC_GENX_DEC(x) (0x84 + 4 * (x))
+/* PCI Configuration Space (D31:F1): IDE */
+#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
+#define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2)
+#define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5)
+
+#define INTR_LN 0x3c
+#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
+#define IDE_DECODE_ENABLE (1 << 15)
+#define IDE_SITRE (1 << 14)
+#define IDE_ISP_5_CLOCKS (0 << 12)
+#define IDE_ISP_4_CLOCKS (1 << 12)
+#define IDE_ISP_3_CLOCKS (2 << 12)
+#define IDE_RCT_4_CLOCKS (0 << 8)
+#define IDE_RCT_3_CLOCKS (1 << 8)
+#define IDE_RCT_2_CLOCKS (2 << 8)
+#define IDE_RCT_1_CLOCKS (3 << 8)
+#define IDE_DTE1 (1 << 7)
+#define IDE_PPE1 (1 << 6)
+#define IDE_IE1 (1 << 5)
+#define IDE_TIME1 (1 << 4)
+#define IDE_DTE0 (1 << 3)
+#define IDE_PPE0 (1 << 2)
+#define IDE_IE0 (1 << 1)
+#define IDE_TIME0 (1 << 0)
+#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
+
+#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
+#define IDE_SSDE1 (1 << 3)
+#define IDE_SSDE0 (1 << 2)
+#define IDE_PSDE1 (1 << 1)
+#define IDE_PSDE0 (1 << 0)
+
+#define IDE_SDMA_TIM 0x4a
+
+#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
+#define SIG_MODE_SEC_NORMAL (0 << 18)
+#define SIG_MODE_SEC_TRISTATE (1 << 18)
+#define SIG_MODE_SEC_DRIVELOW (2 << 18)
+#define SIG_MODE_PRI_NORMAL (0 << 16)
+#define SIG_MODE_PRI_TRISTATE (1 << 16)
+#define SIG_MODE_PRI_DRIVELOW (2 << 16)
+#define FAST_SCB1 (1 << 15)
+#define FAST_SCB0 (1 << 14)
+#define FAST_PCB1 (1 << 13)
+#define FAST_PCB0 (1 << 12)
+#define SCB1 (1 << 3)
+#define SCB0 (1 << 2)
+#define PCB1 (1 << 1)
+#define PCB0 (1 << 0)
+
+#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
+#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
+#define SATA_SP 0xd0 /* Scratchpad */
+
+/* SATA IOBP Registers */
+#define SATA_IOBP_SP0G3IR 0xea000151
+#define SATA_IOBP_SP1G3IR 0xea000051
+
/* PCI Configuration Space (D31:F3): SMBus */
#define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3)
#define SMB_BASE 0x20
@@ -343,6 +460,9 @@
#define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66
+int lpc_init(struct pci_controller *hose, pci_dev_t dev);
+void lpc_enable(pci_dev_t dev);
+
/**
* lpc_early_init() - set up LPC serial ports and other early things
*
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index 114ee19..cf7457f 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -97,11 +97,22 @@
/*
* MCHBAR
*/
-#define MCHBAR_REG(reg) (DEFAULT_RCBA + (reg))
+#define MCHBAR_REG(reg) (DEFAULT_MCHBAR + (reg))
#define SSKPD 0x5d14 /* 16bit (scratchpad) */
#define BIOS_RESET_CPL 0x5da8 /* 8bit */
+/*
+ * DMIBAR
+ */
+
+#define DMIBAR_REG(x) (DEFAULT_DMIBAR + x)
+
+int bridge_silicon_revision(void);
+
+void northbridge_enable(pci_dev_t dev);
+void northbridge_init(pci_dev_t dev);
+
void report_platform_info(void);
void sandybridge_early_init(int chipset_type);
diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h
index 73113f9..bc4033b 100644
--- a/arch/x86/include/asm/i8259.h
+++ b/arch/x86/include/asm/i8259.h
@@ -69,4 +69,6 @@
#define ICW4_AEOI 0x02 /* Automatic EOI Mode */
#define ICW4_PM 0x01 /* Microprocessor Mode */
+int i8259_init(void);
+
#endif
diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h
index 3f46e09..25abde7 100644
--- a/arch/x86/include/asm/interrupt.h
+++ b/arch/x86/include/asm/interrupt.h
@@ -27,4 +27,15 @@
extern char exception_stack[];
+/**
+ * configure_irq_trigger() - Configure IRQ triggering
+ *
+ * Switch the given interrupt to be level / edge triggered
+ *
+ * @param int_num legacy interrupt number (3-7, 9-15)
+ * @param is_level_triggered true for level triggered interrupt, false for
+ * edge triggered interrupt
+ */
+void configure_irq_trigger(int int_num, bool is_level_triggered);
+
#endif
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index fcd9aa9..e0b2561 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -1,7 +1,7 @@
#ifndef _ASM_IO_H
#define _ASM_IO_H
-#include <compiler.h>
+#include <linux/compiler.h>
/*
* This file contains the definitions for the x86 IO instructions
diff --git a/arch/x86/include/asm/ioapic.h b/arch/x86/include/asm/ioapic.h
new file mode 100644
index 0000000..699160f
--- /dev/null
+++ b/arch/x86/include/asm/ioapic.h
@@ -0,0 +1,38 @@
+/*
+ * From coreboot file of the same name
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_IOAPIC_H
+#define __ASM_IOAPIC_H
+
+#define IO_APIC_ADDR 0xfec00000
+#define IO_APIC_INDEX IO_APIC_ADDR
+#define IO_APIC_DATA (IO_APIC_ADDR + 0x10)
+#define IO_APIC_INTERRUPTS 24
+
+#define ALL (0xff << 24)
+#define NONE 0
+#define DISABLED (1 << 16)
+#define ENABLED (0 << 16)
+#define TRIGGER_EDGE (0 << 15)
+#define TRIGGER_LEVEL (1 << 15)
+#define POLARITY_HIGH (0 << 13)
+#define POLARITY_LOW (1 << 13)
+#define PHYSICAL_DEST (0 << 11)
+#define LOGICAL_DEST (1 << 11)
+#define ExtINT (7 << 8)
+#define NMI (4 << 8)
+#define SMI (2 << 8)
+#define INT (1 << 8)
+
+u32 io_apic_read(u32 ioapic_base, u32 reg);
+void io_apic_write(u32 ioapic_base, u32 reg, u32 value);
+void set_ioapic_id(u32 ioapic_base, u8 ioapic_id);
+void setup_ioapic(u32 ioapic_base, u8 ioapic_id);
+void clear_ioapic(u32 ioapic_base);
+
+#endif
diff --git a/arch/x86/include/asm/lapic.h b/arch/x86/include/asm/lapic.h
index 948e643..0a7f443 100644
--- a/arch/x86/include/asm/lapic.h
+++ b/arch/x86/include/asm/lapic.h
@@ -14,6 +14,13 @@
#include <asm/msr.h>
#include <asm/processor.h>
+/* See if I need to initialize the local apic */
+#if CONFIG_SMP || CONFIG_IOAPIC
+# define NEED_LAPIC 1
+#else
+# define NEED_LAPIC 0
+#endif
+
static inline __attribute__((always_inline))
unsigned long lapic_read(unsigned long reg)
{
@@ -37,8 +44,9 @@
msr = msr_read(LAPIC_BASE_MSR);
msr.hi &= 0xffffff00;
- msr.lo &= 0x000007ff;
- msr.lo |= LAPIC_DEFAULT_BASE | (1 << 11);
+ msr.lo |= LAPIC_BASE_MSR_ENABLE;
+ msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK;
+ msr.lo |= LAPIC_DEFAULT_BASE;
msr_write(LAPIC_BASE_MSR, msr);
}
@@ -56,4 +64,116 @@
return lapic_read(LAPIC_ID) >> 24;
}
+#if !CONFIG_AP_IN_SIPI_WAIT
+/* If we need to go back to sipi wait, we use the long non-inlined version of
+ * this function in lapic_cpu_init.c
+ */
+static inline __attribute__((always_inline)) void stop_this_cpu(void)
+{
+ /* Called by an AP when it is ready to halt and wait for a new task */
+ for (;;)
+ cpu_hlt();
+}
+#else
+void stop_this_cpu(void);
+#endif
+
+#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
+ sizeof(*(ptr))))
+
+struct __xchg_dummy { unsigned long a[100]; };
+#define __xg(x) ((struct __xchg_dummy *)(x))
+
+/*
+ * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
+ * Note 2: xchg has side effect, so that attribute volatile is necessary,
+ * but generally the primitive is invalid, *ptr is output argument. --ANK
+ */
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+ int size)
+{
+ switch (size) {
+ case 1:
+ __asm__ __volatile__("xchgb %b0,%1"
+ : "=q" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ case 2:
+ __asm__ __volatile__("xchgw %w0,%1"
+ : "=r" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ case 4:
+ __asm__ __volatile__("xchgl %0,%1"
+ : "=r" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ }
+
+ return x;
+}
+
+static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
+{
+ (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
+}
+
+
+#ifdef X86_GOOD_APIC
+# define FORCE_READ_AROUND_WRITE 0
+# define lapic_read_around(x) lapic_read(x)
+# define lapic_write_around(x, y) lapic_write((x), (y))
+#else
+# define FORCE_READ_AROUND_WRITE 1
+# define lapic_read_around(x) lapic_read(x)
+# define lapic_write_around(x, y) lapic_write_atomic((x), (y))
+#endif
+
+static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
+{
+ int timeout;
+ unsigned long status;
+ int result;
+ lapic_wait_icr_idle();
+ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
+ lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
+ timeout = 0;
+ do {
+ status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
+ } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
+
+ result = -1;
+ if (status == LAPIC_ICR_RR_VALID) {
+ *pvalue = lapic_read(LAPIC_RRR);
+ result = 0;
+ }
+ return result;
+}
+
+
+void lapic_setup(void);
+
+#if CONFIG_SMP
+struct device;
+int start_cpu(struct device *cpu);
+#endif /* CONFIG_SMP */
+
+int boot_cpu(void);
+
+/**
+ * struct x86_cpu_priv - Information about a single CPU
+ *
+ * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
+ * just a number representing the CPU core
+ *
+ * TODO: Move this to driver model once lifecycle is understood
+ */
+struct x86_cpu_priv {
+ int apic_id;
+ int start_err;
+};
+
#endif
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 6027d59..2cbb270 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -326,6 +326,8 @@
#define MSR_AMD_PERF_STATUS 0xc0010063
#define MSR_AMD_PERF_CTL 0xc0010062
+#define MSR_PMG_CST_CONFIG_CTL 0x000000e2
+#define MSR_PMG_IO_CAPTURE_ADR 0x000000e4
#define MSR_IA32_MPERF 0x000000e7
#define MSR_IA32_APERF 0x000000e8
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index df43983..1955a75 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -229,17 +229,6 @@
struct msr *msrs_alloc(void);
void msrs_free(struct msr *msrs);
-#ifdef CONFIG_SMP
-int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
-void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
-void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
-int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
-int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
-int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
-
-#endif /* CONFIG_SMP */
#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_X86_MSR_H */
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index 98817aa..ac1a808 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -34,6 +34,9 @@
*/
int pci_early_init_hose(struct pci_controller **hosep);
+int board_pci_pre_scan(struct pci_controller *hose);
+int board_pci_post_scan(struct pci_controller *hose);
+
/*
* Simple PCI access routines - these work from either the early PCI hose
* or the 'real' one, created after U-Boot has memory available
diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h
index ce68839..6d2ae5d 100644
--- a/arch/x86/include/asm/post.h
+++ b/arch/x86/include/asm/post.h
@@ -30,6 +30,7 @@
#define POST_PRE_MRC 0x2e
#define POST_MRC 0x2f
#define POST_DRAM 0x2f
+#define POST_LAPIC 0x30
#define POST_RAM_FAILURE 0xea
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index b9317cb..3e26202 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -8,25 +8,18 @@
#ifndef __ASM_PROCESSOR_H_
#define __ASM_PROCESSOR_H_ 1
-#define X86_GDT_ENTRY_SIZE 8
+#define X86_GDT_ENTRY_SIZE 8
-#ifndef __ASSEMBLY__
-
-enum {
- X86_GDT_ENTRY_NULL = 0,
- X86_GDT_ENTRY_UNUSED,
- X86_GDT_ENTRY_32BIT_CS,
- X86_GDT_ENTRY_32BIT_DS,
- X86_GDT_ENTRY_32BIT_FS,
- X86_GDT_ENTRY_16BIT_CS,
- X86_GDT_ENTRY_16BIT_DS,
- X86_GDT_NUM_ENTRIES
-};
-#else
-/* NOTE: If the above enum is modified, this define must be checked */
-#define X86_GDT_ENTRY_32BIT_DS 3
-#define X86_GDT_NUM_ENTRIES 7
-#endif
+#define X86_GDT_ENTRY_NULL 0
+#define X86_GDT_ENTRY_UNUSED 1
+#define X86_GDT_ENTRY_32BIT_CS 2
+#define X86_GDT_ENTRY_32BIT_DS 3
+#define X86_GDT_ENTRY_32BIT_FS 4
+#define X86_GDT_ENTRY_16BIT_CS 5
+#define X86_GDT_ENTRY_16BIT_DS 6
+#define X86_GDT_ENTRY_16BIT_FLAT_CS 7
+#define X86_GDT_ENTRY_16BIT_FLAT_DS 8
+#define X86_GDT_NUM_ENTRIES 9
#define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)
diff --git a/arch/x86/include/asm/speedstep.h b/arch/x86/include/asm/speedstep.h
new file mode 100644
index 0000000..b938b86
--- /dev/null
+++ b/arch/x86/include/asm/speedstep.h
@@ -0,0 +1,89 @@
+/*
+ * From Coreboot file of same name
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * 2012 secunet Security Networks AG
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_SPEEDSTEP_H
+#define _ASM_SPEEDSTEP_H
+
+/* Magic value used to locate speedstep configuration in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
+/* MWAIT coordination I/O base address. This must match
+ * the \_PR_.CPU0 PM base address.
+ */
+#define PMB0_BASE 0x510
+
+/* PMB1: I/O port that triggers SMI once cores are in the same state.
+ * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
+ */
+#define PMB1_BASE 0x800
+
+struct sst_state {
+ uint8_t dynfsb:1; /* whether this is SLFM */
+ uint8_t nonint:1; /* add .5 to ratio */
+ uint8_t ratio:6;
+ uint8_t vid;
+ uint8_t is_turbo;
+ uint8_t is_slfm;
+ uint32_t power;
+};
+#define SPEEDSTEP_RATIO_SHIFT 8
+#define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT)
+#define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT)
+#define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT)
+#define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT)
+#define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT)
+#define SPEEDSTEP_VID_MASK 0x3f
+#define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((struct sst_state){ \
+ 0, /* dynfsb won't be read. */ \
+ ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \
+ (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \
+ >> SPEEDSTEP_RATIO_SHIFT), \
+ (val & mask) & SPEEDSTEP_VID_MASK, \
+ 0, /* not turbo by default */ \
+ 0, /* not slfm by default */ \
+ 0 /* power is hardcoded in software. */ \
+ })
+#define SPEEDSTEP_ENCODE_STATE(state) ( \
+ ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \
+ ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \
+ ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \
+ ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK))
+#define SPEEDSTEP_DOUBLE_RATIO(state) ( \
+ ((uint8_t)(state).ratio * 2) + (state).nonint)
+
+struct sst_params {
+ struct sst_state slfm;
+ struct sst_state min;
+ struct sst_state max;
+ struct sst_state turbo;
+};
+
+/* Looking at core2's spec, the highest normal bus ratio for an eist enabled
+ processor is 14, the lowest is always 6. This makes 5 states with the
+ minimal step width of 2. With turbo mode and super LFM we have at most 7. */
+#define SPEEDSTEP_MAX_NORMAL_STATES 5
+#define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2)
+struct sst_table {
+ /* Table of p-states for EMTTM and ACPI by decreasing performance. */
+ struct sst_state states[SPEEDSTEP_MAX_STATES];
+ int num_states;
+};
+
+void speedstep_gen_pstates(struct sst_table *);
+
+#define SPEEDSTEP_MAX_POWER_YONAH 31000
+#define SPEEDSTEP_MIN_POWER_YONAH 13100
+#define SPEEDSTEP_MAX_POWER_MEROM 35000
+#define SPEEDSTEP_MIN_POWER_MEROM 25000
+#define SPEEDSTEP_SLFM_POWER_MEROM 12000
+#define SPEEDSTEP_MAX_POWER_PENRYN 35000
+#define SPEEDSTEP_MIN_POWER_PENRYN 15000
+#define SPEEDSTEP_SLFM_POWER_PENRYN 12000
+
+#endif
diff --git a/arch/x86/include/asm/turbo.h b/arch/x86/include/asm/turbo.h
new file mode 100644
index 0000000..bb0d4b4
--- /dev/null
+++ b/arch/x86/include/asm/turbo.h
@@ -0,0 +1,31 @@
+/*
+ * From coreboot file of the same name
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_TURBO_H
+#define _ASM_TURBO_H
+
+#define CPUID_LEAF_PM 6
+#define PM_CAP_TURBO_MODE (1 << 1)
+
+#define MSR_IA32_MISC_ENABLES 0x1a0
+#define H_MISC_DISABLE_TURBO (1 << 6)
+
+enum {
+ TURBO_UNKNOWN,
+ TURBO_UNAVAILABLE,
+ TURBO_DISABLED,
+ TURBO_ENABLED,
+};
+
+/* Return current turbo state */
+int turbo_get_state(void);
+
+/* Enable turbo */
+void turbo_enable(void);
+
+#endif
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 98217dd..36145cb 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -10,8 +10,6 @@
/* cpu/.../cpu.c */
int arch_cpu_init(void);
-int x86_cpu_init_r(void);
-int cpu_init_r(void);
int x86_cpu_init_f(void);
int cpu_init_f(void);
void init_gd(gd_t *id, u64 *gdt_addr);
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index e146e64..55de788 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -5,6 +5,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += bios.o
+obj-y += bios_asm.o
+obj-y += bios_interrupts.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cmd_boot.o
obj-y += gcc.o
diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c
new file mode 100644
index 0000000..298fca6
--- /dev/null
+++ b/arch/x86/lib/bios.c
@@ -0,0 +1,347 @@
+/*
+ * From Coreboot file device/oprom/realmode/x86.c
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009-2010 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <common.h>
+#include <bios_emul.h>
+#include <vbe.h>
+#include <asm/cache.h>
+#include <asm/processor.h>
+#include <asm/i8259.h>
+#include <asm/io.h>
+#include <asm/post.h>
+#include "bios.h"
+
+/* Interrupt handlers for each interrupt the ROM can call */
+static int (*int_handler[256])(void);
+
+/* to have a common register file for interrupt handlers */
+X86EMU_sysEnv _X86EMU_env;
+
+asmlinkage void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
+ u32 esi, u32 edi);
+
+asmlinkage void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx,
+ u32 edx, u32 esi, u32 edi);
+
+static void setup_realmode_code(void)
+{
+ memcpy((void *)REALMODE_BASE, &asm_realmode_code,
+ asm_realmode_code_size);
+
+ /* Ensure the global pointers are relocated properly. */
+ realmode_call = PTR_TO_REAL_MODE(asm_realmode_call);
+ realmode_interrupt = PTR_TO_REAL_MODE(__realmode_interrupt);
+
+ debug("Real mode stub @%x: %d bytes\n", REALMODE_BASE,
+ asm_realmode_code_size);
+}
+
+static void setup_rombios(void)
+{
+ const char date[] = "06/11/99";
+ memcpy((void *)0xffff5, &date, 8);
+
+ const char ident[] = "PCI_ISA";
+ memcpy((void *)0xfffd9, &ident, 7);
+
+ /* system model: IBM-AT */
+ writeb(0xfc, 0xffffe);
+}
+
+static int int_exception_handler(void)
+{
+ /* compatibility shim */
+ struct eregs reg_info = {
+ .eax = M.x86.R_EAX,
+ .ecx = M.x86.R_ECX,
+ .edx = M.x86.R_EDX,
+ .ebx = M.x86.R_EBX,
+ .esp = M.x86.R_ESP,
+ .ebp = M.x86.R_EBP,
+ .esi = M.x86.R_ESI,
+ .edi = M.x86.R_EDI,
+ .vector = M.x86.intno,
+ .error_code = 0,
+ .eip = M.x86.R_EIP,
+ .cs = M.x86.R_CS,
+ .eflags = M.x86.R_EFLG
+ };
+ struct eregs *regs = ®_info;
+
+ debug("Oops, exception %d while executing option rom\n", regs->vector);
+ cpu_hlt();
+
+ return 0;
+}
+
+static int int_unknown_handler(void)
+{
+ debug("Unsupported software interrupt #0x%x eax 0x%x\n",
+ M.x86.intno, M.x86.R_EAX);
+
+ return -1;
+}
+
+/* setup interrupt handlers for mainboard */
+void bios_set_interrupt_handler(int intnum, int (*int_func)(void))
+{
+ int_handler[intnum] = int_func;
+}
+
+static void setup_interrupt_handlers(void)
+{
+ int i;
+
+ /*
+ * The first 16 int_handler functions are not BIOS services,
+ * but the CPU-generated exceptions ("hardware interrupts")
+ */
+ for (i = 0; i < 0x10; i++)
+ int_handler[i] = &int_exception_handler;
+
+ /* Mark all other int_handler calls as unknown first */
+ for (i = 0x10; i < 0x100; i++) {
+ /* Skip if bios_set_interrupt_handler() isn't called first */
+ if (int_handler[i])
+ continue;
+
+ /*
+ * Now set the default functions that are actually needed
+ * to initialize the option roms. The board may override
+ * these with bios_set_interrupt_handler()
+ */
+ switch (i) {
+ case 0x10:
+ int_handler[0x10] = &int10_handler;
+ break;
+ case 0x12:
+ int_handler[0x12] = &int12_handler;
+ break;
+ case 0x16:
+ int_handler[0x16] = &int16_handler;
+ break;
+ case 0x1a:
+ int_handler[0x1a] = &int1a_handler;
+ break;
+ default:
+ int_handler[i] = &int_unknown_handler;
+ break;
+ }
+ }
+}
+
+static void write_idt_stub(void *target, u8 intnum)
+{
+ unsigned char *codeptr;
+
+ codeptr = (unsigned char *)target;
+ memcpy(codeptr, &__idt_handler, __idt_handler_size);
+ codeptr[3] = intnum; /* modify int# in the code stub. */
+}
+
+static void setup_realmode_idt(void)
+{
+ struct realmode_idt *idts = NULL;
+ int i;
+
+ /*
+ * Copy IDT stub code for each interrupt. This might seem wasteful
+ * but it is really simple
+ */
+ for (i = 0; i < 256; i++) {
+ idts[i].cs = 0;
+ idts[i].offset = 0x1000 + (i * __idt_handler_size);
+ write_idt_stub((void *)((u32)idts[i].offset), i);
+ }
+
+ /*
+ * Many option ROMs use the hard coded interrupt entry points in the
+ * system bios. So install them at the known locations.
+ */
+
+ /* int42 is the relocated int10 */
+ write_idt_stub((void *)0xff065, 0x42);
+ /* BIOS Int 11 Handler F000:F84D */
+ write_idt_stub((void *)0xff84d, 0x11);
+ /* BIOS Int 12 Handler F000:F841 */
+ write_idt_stub((void *)0xff841, 0x12);
+ /* BIOS Int 13 Handler F000:EC59 */
+ write_idt_stub((void *)0xfec59, 0x13);
+ /* BIOS Int 14 Handler F000:E739 */
+ write_idt_stub((void *)0xfe739, 0x14);
+ /* BIOS Int 15 Handler F000:F859 */
+ write_idt_stub((void *)0xff859, 0x15);
+ /* BIOS Int 16 Handler F000:E82E */
+ write_idt_stub((void *)0xfe82e, 0x16);
+ /* BIOS Int 17 Handler F000:EFD2 */
+ write_idt_stub((void *)0xfefd2, 0x17);
+ /* ROM BIOS Int 1A Handler F000:FE6E */
+ write_idt_stub((void *)0xffe6e, 0x1a);
+}
+
+static u8 vbe_get_mode_info(struct vbe_mode_info *mi)
+{
+ u16 buffer_seg;
+ u16 buffer_adr;
+ char *buffer;
+
+ debug("VBE: Getting information about VESA mode %04x\n",
+ mi->video_mode);
+ buffer = PTR_TO_REAL_MODE(asm_realmode_buffer);
+ buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00;
+ buffer_adr = ((unsigned long)buffer) & 0xffff;
+
+ realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, mi->video_mode,
+ 0x0000, buffer_seg, buffer_adr);
+ memcpy(mi->mode_info_block, buffer, sizeof(struct vbe_mode_info));
+ mi->valid = true;
+
+ return 0;
+}
+
+static u8 vbe_set_mode(struct vbe_mode_info *mi)
+{
+ debug("VBE: Setting VESA mode %#04x\n", mi->video_mode);
+ /* request linear framebuffer mode */
+ mi->video_mode |= (1 << 14);
+ /* request clearing of framebuffer */
+ mi->video_mode &= ~(1 << 15);
+ realmode_interrupt(0x10, VESA_SET_MODE, mi->video_mode,
+ 0x0000, 0x0000, 0x0000, 0x0000);
+
+ return 0;
+}
+
+static void vbe_set_graphics(int vesa_mode, struct vbe_mode_info *mode_info)
+{
+ unsigned char *framebuffer;
+
+ mode_info->video_mode = (1 << 14) | vesa_mode;
+ vbe_get_mode_info(mode_info);
+
+ framebuffer = (unsigned char *)mode_info->vesa.phys_base_ptr;
+ debug("VBE: resolution: %dx%d@%d\n",
+ le16_to_cpu(mode_info->vesa.x_resolution),
+ le16_to_cpu(mode_info->vesa.y_resolution),
+ mode_info->vesa.bits_per_pixel);
+ debug("VBE: framebuffer: %p\n", framebuffer);
+ if (!framebuffer) {
+ debug("VBE: Mode does not support linear framebuffer\n");
+ return;
+ }
+
+ vbe_set_mode(mode_info);
+}
+
+void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode,
+ struct vbe_mode_info *mode_info)
+{
+ u32 num_dev;
+
+ num_dev = PCI_BUS(pcidev) << 8 | PCI_DEV(pcidev) << 3 |
+ PCI_FUNC(pcidev);
+
+ /* Needed to avoid exceptions in some ROMs */
+ interrupt_init();
+
+ /* Set up some legacy information in the F segment */
+ setup_rombios();
+
+ /* Set up C interrupt handlers */
+ setup_interrupt_handlers();
+
+ /* Set up real-mode IDT */
+ setup_realmode_idt();
+
+ /* Make sure the code is placed. */
+ setup_realmode_code();
+
+ disable_caches();
+ debug("Calling Option ROM at %lx, pci device %#x...", addr, num_dev);
+
+ /* Option ROM entry point is at OPROM start + 3 */
+ realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0,
+ 0x0);
+ debug("done\n");
+
+ if (vesa_mode != -1)
+ vbe_set_graphics(vesa_mode, mode_info);
+}
+
+asmlinkage int interrupt_handler(u32 intnumber, u32 gsfs, u32 dses,
+ u32 edi, u32 esi, u32 ebp, u32 esp,
+ u32 ebx, u32 edx, u32 ecx, u32 eax,
+ u32 cs_ip, u16 stackflags)
+{
+ u32 ip;
+ u32 cs;
+ u32 flags;
+ int ret = 0;
+
+ ip = cs_ip & 0xffff;
+ cs = cs_ip >> 16;
+ flags = stackflags;
+
+#ifdef CONFIG_REALMODE_DEBUG
+ debug("oprom: INT# 0x%x\n", intnumber);
+ debug("oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n",
+ eax, ebx, ecx, edx);
+ debug("oprom: ebp: %08x esp: %08x edi: %08x esi: %08x\n",
+ ebp, esp, edi, esi);
+ debug("oprom: ip: %04x cs: %04x flags: %08x\n",
+ ip, cs, flags);
+ debug("oprom: stackflags = %04x\n", stackflags);
+#endif
+
+ /*
+ * Fetch arguments from the stack and put them to a place
+ * suitable for the interrupt handlers
+ */
+ M.x86.R_EAX = eax;
+ M.x86.R_ECX = ecx;
+ M.x86.R_EDX = edx;
+ M.x86.R_EBX = ebx;
+ M.x86.R_ESP = esp;
+ M.x86.R_EBP = ebp;
+ M.x86.R_ESI = esi;
+ M.x86.R_EDI = edi;
+ M.x86.intno = intnumber;
+ M.x86.R_EIP = ip;
+ M.x86.R_CS = cs;
+ M.x86.R_EFLG = flags;
+
+ /* Call the interrupt handler for this interrupt number */
+ ret = int_handler[intnumber]();
+
+ /*
+ * This code is quite strange...
+ *
+ * Put registers back on the stack. The assembler code will pop them
+ * later. We force (volatile!) changing the values of the parameters
+ * of this function. We know that they stay alive on the stack after
+ * we leave this function.
+ */
+ *(volatile u32 *)&eax = M.x86.R_EAX;
+ *(volatile u32 *)&ecx = M.x86.R_ECX;
+ *(volatile u32 *)&edx = M.x86.R_EDX;
+ *(volatile u32 *)&ebx = M.x86.R_EBX;
+ *(volatile u32 *)&esi = M.x86.R_ESI;
+ *(volatile u32 *)&edi = M.x86.R_EDI;
+ flags = M.x86.R_EFLG;
+
+ /* Pass success or error back to our caller via the CARRY flag */
+ if (ret) {
+ flags &= ~1; /* no error: clear carry */
+ } else {
+ debug("int%02x call returned error\n", intnumber);
+ flags |= 1; /* error: set carry */
+ }
+ *(volatile u16 *)&stackflags = flags;
+
+ return ret;
+}
diff --git a/arch/x86/lib/bios.h b/arch/x86/lib/bios.h
new file mode 100644
index 0000000..8491b4a
--- /dev/null
+++ b/arch/x86/lib/bios.h
@@ -0,0 +1,98 @@
+/*
+ * From Coreboot file device/oprom/realmode/x86.h
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009-2010 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _X86_LIB_BIOS_H
+#define _X86_LIB_BIOS_H
+
+#define REALMODE_BASE 0x600
+
+#ifdef __ASSEMBLY__
+
+#define PTR_TO_REAL_MODE(x) (x - asm_realmode_code + REALMODE_BASE)
+
+#else
+
+/* Convert a symbol address to our real mode area */
+#define PTR_TO_REAL_MODE(sym)\
+ (void *)(REALMODE_BASE + ((char *)&(sym) - (char *)&asm_realmode_code))
+
+/*
+ * The following symbols cannot be used directly. They need to be fixed up
+ * to point to the correct address location after the code has been copied
+ * to REALMODE_BASE. Absolute symbols are not used because those symbols are
+ * relocated by U-Boot.
+ */
+extern unsigned char asm_realmode_call, __realmode_interrupt;
+extern unsigned char asm_realmode_buffer;
+
+#define DOWNTO8(A) \
+ union { \
+ struct { \
+ union { \
+ struct { \
+ uint8_t A##l; \
+ uint8_t A##h; \
+ } __packed; \
+ uint16_t A##x; \
+ } __packed; \
+ uint16_t h##A##x; \
+ } __packed; \
+ uint32_t e##A##x; \
+ } __packed;
+
+#define DOWNTO16(A) \
+ union { \
+ struct { \
+ uint16_t A; \
+ uint16_t h##A; \
+ } __packed; \
+ uint32_t e##A; \
+ } __packed;
+
+struct eregs {
+ DOWNTO8(a);
+ DOWNTO8(c);
+ DOWNTO8(d);
+ DOWNTO8(b);
+ DOWNTO16(sp);
+ DOWNTO16(bp);
+ DOWNTO16(si);
+ DOWNTO16(di);
+ uint32_t vector;
+ uint32_t error_code;
+ uint32_t eip;
+ uint32_t cs;
+ uint32_t eflags;
+};
+
+struct realmode_idt {
+ u16 offset, cs;
+};
+
+void x86_exception(struct eregs *info);
+
+/* From x86_asm.S */
+extern unsigned char __idt_handler;
+extern unsigned int __idt_handler_size;
+extern unsigned char asm_realmode_code;
+extern unsigned int asm_realmode_code_size;
+
+asmlinkage void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
+ u32 esi, u32 edi);
+
+asmlinkage void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx,
+ u32 edx, u32 esi, u32 edi);
+
+int int10_handler(void);
+int int12_handler(void);
+int int16_handler(void);
+int int1a_handler(void);
+#endif /*__ASSEMBLY__ */
+
+#endif
diff --git a/arch/x86/lib/bios_asm.S b/arch/x86/lib/bios_asm.S
new file mode 100644
index 0000000..4faa70e
--- /dev/null
+++ b/arch/x86/lib/bios_asm.S
@@ -0,0 +1,281 @@
+/*
+ * From coreboot x86_asm.S, cleaned up substantially
+ *
+ * Copyright (C) 2009-2010 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <asm/processor.h>
+#include <asm/processor-flags.h>
+#include "bios.h"
+
+#define SEG(segment) $segment * X86_GDT_ENTRY_SIZE
+
+/*
+ * This is the interrupt handler stub code. It gets copied to the IDT and
+ * to some fixed addresses in the F segment. Before the code can used,
+ * it gets patched up by the C function copying it: byte 3 (the $0 in
+ * movb $0, %al) is overwritten with the interrupt numbers.
+ */
+
+ .code16
+ .globl __idt_handler
+__idt_handler:
+ pushal
+ movb $0, %al /* This instruction gets modified */
+ ljmp $0, $__interrupt_handler_16bit
+ .globl __idt_handler_size
+__idt_handler_size:
+ .long . - __idt_handler
+
+.macro setup_registers
+ /* initial register values */
+ movl 44(%ebp), %eax
+ movl %eax, __registers + 0 /* eax */
+ movl 48(%ebp), %eax
+ movl %eax, __registers + 4 /* ebx */
+ movl 52(%ebp), %eax
+ movl %eax, __registers + 8 /* ecx */
+ movl 56(%ebp), %eax
+ movl %eax, __registers + 12 /* edx */
+ movl 60(%ebp), %eax
+ movl %eax, __registers + 16 /* esi */
+ movl 64(%ebp), %eax
+ movl %eax, __registers + 20 /* edi */
+.endm
+
+.macro enter_real_mode
+ /* Activate the right segment descriptor real mode. */
+ ljmp SEG(X86_GDT_ENTRY_16BIT_CS), $PTR_TO_REAL_MODE(1f)
+1:
+.code16
+ /*
+ * Load the segment registers with properly configured segment
+ * descriptors. They will retain these configurations (limits,
+ * writability, etc.) once protected mode is turned off.
+ */
+ mov SEG(X86_GDT_ENTRY_16BIT_DS), %ax
+ mov %ax, %ds
+ mov %ax, %es
+ mov %ax, %fs
+ mov %ax, %gs
+ mov %ax, %ss
+
+ /* Turn off protection */
+ movl %cr0, %eax
+ andl $~X86_CR0_PE, %eax
+ movl %eax, %cr0
+
+ /* Now really going into real mode */
+ ljmp $0, $PTR_TO_REAL_MODE(1f)
+1:
+ /*
+ * Set up a stack: Put the stack at the end of page zero. That way
+ * we can easily share it between real and protected, since the
+ * 16-bit ESP at segment 0 will work for any case.
+ */
+ mov $0x0, %ax
+ mov %ax, %ss
+
+ /* Load 16 bit IDT */
+ xor %ax, %ax
+ mov %ax, %ds
+ lidt __realmode_idt
+
+.endm
+
+.macro prepare_for_irom
+ movl $0x1000, %eax
+ movl %eax, %esp
+
+ /* Initialise registers for option rom lcall */
+ movl __registers + 0, %eax
+ movl __registers + 4, %ebx
+ movl __registers + 8, %ecx
+ movl __registers + 12, %edx
+ movl __registers + 16, %esi
+ movl __registers + 20, %edi
+
+ /* Set all segments to 0x0000, ds to 0x0040 */
+ push %ax
+ xor %ax, %ax
+ mov %ax, %es
+ mov %ax, %fs
+ mov %ax, %gs
+ mov SEG(X86_GDT_ENTRY_16BIT_FLAT_DS), %ax
+ mov %ax, %ds
+ pop %ax
+
+.endm
+
+.macro enter_protected_mode
+ /* Go back to protected mode */
+ movl %cr0, %eax
+ orl $X86_CR0_PE, %eax
+ movl %eax, %cr0
+
+ /* Now that we are in protected mode jump to a 32 bit code segment */
+ data32 ljmp SEG(X86_GDT_ENTRY_32BIT_CS), $PTR_TO_REAL_MODE(1f)
+1:
+ .code32
+ mov SEG(X86_GDT_ENTRY_32BIT_DS), %ax
+ mov %ax, %ds
+ mov %ax, %es
+ mov %ax, %gs
+ mov %ax, %ss
+ mov SEG(X86_GDT_ENTRY_32BIT_FS), %ax
+ mov %ax, %fs
+
+ /* restore proper idt */
+ lidt idt_ptr
+.endm
+
+/*
+ * In order to be independent of U-Boot's position in RAM we relocate a part
+ * of the code to the first megabyte of RAM, so the CPU can use it in
+ * real-mode. This code lives at asm_realmode_code.
+ */
+ .globl asm_realmode_code
+asm_realmode_code:
+
+/* Realmode IDT pointer structure. */
+__realmode_idt = PTR_TO_REAL_MODE(.)
+ .word 1023 /* 16 bit limit */
+ .long 0 /* 24 bit base */
+ .word 0
+
+/* Preserve old stack */
+__stack = PTR_TO_REAL_MODE(.)
+ .long 0
+
+/* Register store for realmode_call and realmode_interrupt */
+__registers = PTR_TO_REAL_MODE(.)
+ .long 0 /* 0 - EAX */
+ .long 0 /* 4 - EBX */
+ .long 0 /* 8 - ECX */
+ .long 0 /* 12 - EDX */
+ .long 0 /* 16 - ESI */
+ .long 0 /* 20 - EDI */
+
+/* 256 byte buffer, used by int10 */
+ .globl asm_realmode_buffer
+asm_realmode_buffer:
+ .skip 256
+
+ .code32
+ .globl asm_realmode_call
+asm_realmode_call:
+ /* save all registers to the stack */
+ pusha
+ pushf
+ movl %esp, __stack
+ movl %esp, %ebp
+
+ /*
+ * This function is called with regparm=0 and we have to skip the
+ * 36 bytes from pushf+pusha. Hence start at 40.
+ * Set up our call instruction.
+ */
+ movl 40(%ebp), %eax
+ mov %ax, __lcall_instr + 1
+ andl $0xffff0000, %eax
+ shrl $4, %eax
+ mov %ax, __lcall_instr + 3
+
+ wbinvd
+
+ setup_registers
+ enter_real_mode
+ prepare_for_irom
+
+__lcall_instr = PTR_TO_REAL_MODE(.)
+ .byte 0x9a
+ .word 0x0000, 0x0000
+
+ enter_protected_mode
+
+ /* restore stack pointer, eflags and register values and exit */
+ movl __stack, %esp
+ popf
+ popa
+ ret
+
+ .globl __realmode_interrupt
+__realmode_interrupt:
+ /* save all registers to the stack and store the stack pointer */
+ pusha
+ pushf
+ movl %esp, __stack
+ movl %esp, %ebp
+
+ /*
+ * This function is called with regparm=0 and we have to skip the
+ * 36 bytes from pushf+pusha. Hence start at 40.
+ * Prepare interrupt calling code.
+ */
+ movl 40(%ebp), %eax
+ movb %al, __intXX_instr + 1 /* intno */
+
+ setup_registers
+ enter_real_mode
+ prepare_for_irom
+
+__intXX_instr = PTR_TO_REAL_MODE(.)
+ .byte 0xcd, 0x00 /* This becomes intXX */
+
+ enter_protected_mode
+
+ /* restore stack pointer, eflags and register values and exit */
+ movl __stack, %esp
+ popf
+ popa
+ ret
+
+/*
+ * This is the 16-bit interrupt entry point called by the IDT stub code.
+ *
+ * Before this code code is called, %eax is pushed to the stack, and the
+ * interrupt number is loaded into %al. On return this function cleans up
+ * for its caller.
+ */
+ .code16
+__interrupt_handler_16bit = PTR_TO_REAL_MODE(.)
+ push %ds
+ push %es
+ push %fs
+ push %gs
+
+ /* Clear DF to not break ABI assumptions */
+ cld
+
+ /*
+ * Clean up the interrupt number. We could do this in the stub, but
+ * it would cost two more bytes per stub entry.
+ */
+ andl $0xff, %eax
+ pushl %eax /* ... and make it the first parameter */
+
+ enter_protected_mode
+
+ /* Call the C interrupt handler */
+ movl $interrupt_handler, %eax
+ call *%eax
+
+ enter_real_mode
+
+ /*
+ * Restore all registers, including those manipulated by the C
+ * handler
+ */
+ popl %eax
+ pop %gs
+ pop %fs
+ pop %es
+ pop %ds
+ popal
+ iret
+
+ .globl asm_realmode_code_size
+asm_realmode_code_size:
+ .long . - asm_realmode_code
diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c
new file mode 100644
index 0000000..b0e2ecb
--- /dev/null
+++ b/arch/x86/lib/bios_interrupts.c
@@ -0,0 +1,217 @@
+/*
+ * From Coreboot
+ *
+ * Copyright (C) 2001 Ronald G. Minnich
+ * Copyright (C) 2005 Nick.Barker9@btinternet.com
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/pci.h>
+#include "bios_emul.h"
+
+/* errors go in AH. Just set these up so that word assigns will work */
+enum {
+ PCIBIOS_SUCCESSFUL = 0x0000,
+ PCIBIOS_UNSUPPORTED = 0x8100,
+ PCIBIOS_BADVENDOR = 0x8300,
+ PCIBIOS_NODEV = 0x8600,
+ PCIBIOS_BADREG = 0x8700
+};
+
+int int10_handler(void)
+{
+ static u8 cursor_row, cursor_col;
+ int res = 0;
+
+ switch ((M.x86.R_EAX & 0xff00) >> 8) {
+ case 0x01: /* Set cursor shape */
+ res = 1;
+ break;
+ case 0x02: /* Set cursor position */
+ if (cursor_row != ((M.x86.R_EDX >> 8) & 0xff) ||
+ cursor_col >= (M.x86.R_EDX & 0xff)) {
+ debug("\n");
+ }
+ cursor_row = (M.x86.R_EDX >> 8) & 0xff;
+ cursor_col = M.x86.R_EDX & 0xff;
+ res = 1;
+ break;
+ case 0x03: /* Get cursor position */
+ M.x86.R_EAX &= 0x00ff;
+ M.x86.R_ECX = 0x0607;
+ M.x86.R_EDX = (cursor_row << 8) | cursor_col;
+ res = 1;
+ break;
+ case 0x06: /* Scroll up */
+ debug("\n");
+ res = 1;
+ break;
+ case 0x08: /* Get Character and Mode at Cursor Position */
+ M.x86.R_EAX = 0x0f00 | 'A'; /* White on black 'A' */
+ res = 1;
+ break;
+ case 0x09: /* Write Character and attribute */
+ case 0x0e: /* Write Character */
+ debug("%c", M.x86.R_EAX & 0xff);
+ res = 1;
+ break;
+ case 0x0f: /* Get video mode */
+ M.x86.R_EAX = 0x5002; /*80 x 25 */
+ M.x86.R_EBX &= 0x00ff;
+ res = 1;
+ break;
+ default:
+ printf("Unknown INT10 function %04x\n", M.x86.R_EAX & 0xffff);
+ break;
+ }
+ return res;
+}
+
+int int12_handler(void)
+{
+ M.x86.R_EAX = 64 * 1024;
+ return 1;
+}
+
+int int16_handler(void)
+{
+ int res = 0;
+
+ switch ((M.x86.R_EAX & 0xff00) >> 8) {
+ case 0x00: /* Check for Keystroke */
+ M.x86.R_EAX = 0x6120; /* Space Bar, Space */
+ res = 1;
+ break;
+ case 0x01: /* Check for Keystroke */
+ M.x86.R_EFLG |= 1 << 6; /* Zero Flag set (no key available) */
+ res = 1;
+ break;
+ default:
+ printf("Unknown INT16 function %04x\n", M.x86.R_EAX & 0xffff);
+
+break;
+ }
+ return res;
+}
+
+#define PCI_CONFIG_SPACE_TYPE1 (1 << 0)
+#define PCI_SPECIAL_CYCLE_TYPE1 (1 << 4)
+
+int int1a_handler(void)
+{
+ unsigned short func = (unsigned short)M.x86.R_EAX;
+ int retval = 1;
+ unsigned short devid, vendorid, devfn;
+ /* Use short to get rid of gabage in upper half of 32-bit register */
+ short devindex;
+ unsigned char bus;
+ pci_dev_t dev;
+ u32 dword;
+ u16 word;
+ u8 byte, reg;
+
+ switch (func) {
+ case 0xb101: /* PCIBIOS Check */
+ M.x86.R_EDX = 0x20494350; /* ' ICP' */
+ M.x86.R_EAX &= 0xffff0000; /* Clear AH / AL */
+ M.x86.R_EAX |= PCI_CONFIG_SPACE_TYPE1 |
+ PCI_SPECIAL_CYCLE_TYPE1;
+ /*
+ * last bus in the system. Hard code to 255 for now.
+ * dev_enumerate() does not seem to tell us (publically)
+ */
+ M.x86.R_ECX = 0xff;
+ M.x86.R_EDI = 0x00000000; /* protected mode entry */
+ retval = 1;
+ break;
+ case 0xb102: /* Find Device */
+ devid = M.x86.R_ECX;
+ vendorid = M.x86.R_EDX;
+ devindex = M.x86.R_ESI;
+ dev = pci_find_device(vendorid, devid, devindex);
+ if (dev != -1) {
+ unsigned short busdevfn;
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_SUCCESSFUL;
+ /*
+ * busnum is an unsigned char;
+ * devfn is an int, so we mask it off.
+ */
+ busdevfn = (PCI_BUS(dev) << 8) | PCI_DEV(dev) << 3 |
+ PCI_FUNC(dev);
+ debug("0x%x: return 0x%x\n", func, busdevfn);
+ M.x86.R_EBX = busdevfn;
+ retval = 1;
+ } else {
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_NODEV;
+ retval = 0;
+ }
+ break;
+ case 0xb10a: /* Read Config Dword */
+ case 0xb109: /* Read Config Word */
+ case 0xb108: /* Read Config Byte */
+ case 0xb10d: /* Write Config Dword */
+ case 0xb10c: /* Write Config Word */
+ case 0xb10b: /* Write Config Byte */
+ devfn = M.x86.R_EBX & 0xff;
+ bus = M.x86.R_EBX >> 8;
+ reg = M.x86.R_EDI;
+ dev = PCI_BDF(bus, devfn >> 3, devfn & 7);
+ if (!dev) {
+ debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func,
+ bus, devfn);
+ /* Or are we supposed to return PCIBIOS_NODEV? */
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_BADREG;
+ retval = 0;
+ return retval;
+ }
+ switch (func) {
+ case 0xb108: /* Read Config Byte */
+ byte = pci_read_config8(dev, reg);
+ M.x86.R_ECX = byte;
+ break;
+ case 0xb109: /* Read Config Word */
+ word = pci_read_config16(dev, reg);
+ M.x86.R_ECX = word;
+ break;
+ case 0xb10a: /* Read Config Dword */
+ dword = pci_read_config32(dev, reg);
+ M.x86.R_ECX = dword;
+ break;
+ case 0xb10b: /* Write Config Byte */
+ byte = M.x86.R_ECX;
+ pci_write_config8(dev, reg, byte);
+ break;
+ case 0xb10c: /* Write Config Word */
+ word = M.x86.R_ECX;
+ pci_write_config16(dev, reg, word);
+ break;
+ case 0xb10d: /* Write Config Dword */
+ dword = M.x86.R_ECX;
+ pci_write_config32(dev, reg, dword);
+ break;
+ }
+
+#ifdef CONFIG_REALMODE_DEBUG
+ debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func,
+ bus, devfn, reg, M.x86.R_ECX);
+#endif
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_SUCCESSFUL;
+ retval = 1;
+ break;
+ default:
+ printf("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
+ M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
+ M.x86.R_EAX |= PCIBIOS_UNSUPPORTED;
+ retval = 0;
+ break;
+ }
+
+ return retval;
+}
diff --git a/arch/x86/lib/pcat_interrupts.c b/arch/x86/lib/pcat_interrupts.c
index 4c86f7f..a9af87e 100644
--- a/arch/x86/lib/pcat_interrupts.c
+++ b/arch/x86/lib/pcat_interrupts.c
@@ -24,12 +24,10 @@
#error "CONFIG_SYS_NUM_IRQS must equal 16 if CONFIG_SYS_NUM_IRQS is defined"
#endif
-int interrupt_init(void)
+int i8259_init(void)
{
u8 i;
- disable_interrupts();
-
/* Mask all interrupts */
outb(0xff, MASTER_PIC + IMR);
outb(0xff, SLAVE_PIC + IMR);
@@ -62,7 +60,8 @@
*/
unmask_irq(2);
- enable_interrupts();
+ /* Interrupt 9 should be level triggered (SCI). The OS might do this */
+ configure_irq_trigger(9, true);
return 0;
}
@@ -114,3 +113,38 @@
outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);
}
+
+#define ELCR1 0x4d0
+#define ELCR2 0x4d1
+
+void configure_irq_trigger(int int_num, bool is_level_triggered)
+{
+ u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
+
+ debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
+ if (is_level_triggered)
+ int_bits |= (1 << int_num);
+ else
+ int_bits &= ~(1 << int_num);
+
+ /* Write new values */
+ debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
+ outb((u8)(int_bits & 0xff), ELCR1);
+ outb((u8)(int_bits >> 8), ELCR2);
+
+#ifdef PARANOID_IRQ_TRIGGERS
+ /*
+ * Try reading back the new values. This seems like an error but is
+ * not
+ */
+ if (inb(ELCR1) != (int_bits & 0xff)) {
+ printf("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
+ __func__, (int_bits & 0xff), inb(ELCR1));
+ }
+
+ if (inb(ELCR2) != (int_bits >> 8)) {
+ printf("%s: higher order bits are wrong: want 0x%x, got 0x%x\n",
+ __func__, (int_bits>>8), inb(ELCR2));
+ }
+#endif
+}
diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c
index faca38f..b33586b 100644
--- a/arch/x86/lib/relocate.c
+++ b/arch/x86/lib/relocate.c
@@ -76,6 +76,9 @@
/* The size of the region of u-boot that runs out of RAM. */
uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;
+ if (re_src == re_end)
+ panic("No relocation data");
+
do {
/* Get the location from the relocation entry */
offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
diff --git a/arch/x86/lib/string.c b/arch/x86/lib/string.c
index a1656cc..6c66431 100644
--- a/arch/x86/lib/string.c
+++ b/arch/x86/lib/string.c
@@ -8,9 +8,9 @@
/* From glibc-2.14, sysdeps/i386/memset.c */
-#include <compiler.h>
-#include <asm/string.h>
#include <linux/types.h>
+#include <linux/compiler.h>
+#include <asm/string.h>
typedef uint32_t op_t;
diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c
index 2b826df..9d4c41b 100644
--- a/board/comelit/dig297/dig297.c
+++ b/board/comelit/dig297/dig297.c
@@ -133,6 +133,11 @@
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
#endif
#ifdef CONFIG_CMD_NET
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index 886c723..43463d5 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -382,6 +382,13 @@
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#ifdef CONFIG_SYS_I2C_OMAP34XX
/*
* Routine: reset_net_chip
diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c
index 9e81bf3..0fddf45 100644
--- a/board/corscience/tricorder/tricorder.c
+++ b/board/corscience/tricorder/tricorder.c
@@ -147,6 +147,13 @@
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index 88cee05..1822237 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -5,15 +5,14 @@
*/
#include <common.h>
+#include <cros_ec.h>
#include <asm/gpio.h>
int arch_early_init_r(void)
{
- return 0;
-}
+ if (cros_ec_board_init())
+ return -1;
-int board_early_init_r(void)
-{
return 0;
}
diff --git a/board/hermes/Kconfig b/board/hermes/Kconfig
deleted file mode 100644
index deb37fd..0000000
--- a/board/hermes/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_HERMES
-
-config SYS_BOARD
- default "hermes"
-
-config SYS_CONFIG_NAME
- default "hermes"
-
-endif
diff --git a/board/hermes/MAINTAINERS b/board/hermes/MAINTAINERS
deleted file mode 100644
index a596dad..0000000
--- a/board/hermes/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-HERMES BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/hermes/
-F: include/configs/hermes.h
-F: configs/hermes_defconfig
diff --git a/board/hermes/Makefile b/board/hermes/Makefile
deleted file mode 100644
index ccca520..0000000
--- a/board/hermes/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = hermes.o flash.o
diff --git a/board/hermes/flash.c b/board/hermes/flash.c
deleted file mode 100644
index 38d3cd3..0000000
--- a/board/hermes/flash.c
+++ /dev/null
@@ -1,444 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_byte (flash_info_t *info, ulong dest, uchar data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
- (memctl->memc_br0 & ~(BR_BA_MSK));
-
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size;
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- uchar value;
- vu_char *caddr = (vu_char *)addr;
- ulong base = (ulong)addr;
-
-
- /* Write auto select command: read Manufacturer ID */
- caddr[0x0AAA] = 0xAA;
- caddr[0x0555] = 0x55;
- caddr[0x0AAA] = 0x90;
-
- value = caddr[0];
- switch (value) {
- case (AMD_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = caddr[2]; /* device ID */
-
- switch (value) {
- case (AMD_ID_LV400T & 0xFF):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case (AMD_ID_LV400B & 0xFF):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case (AMD_ID_LV800T & 0xFF):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV800B & 0xFF):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV160T & 0xFF):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV160B & 0xFF):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-#if 0 /* enable when device IDs are available */
- case (AMD_ID_LV320T & 0xFF):
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV320B & 0xFF):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection: D0 = 1 if protected */
- caddr = (volatile unsigned char *)(info->start[i]);
- info->protect[i] = caddr[4] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- caddr = (vu_char *)info->start[0];
-
- *caddr = 0xF0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_char *addr = (vu_char*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0AAA] = 0xAA;
- addr[0x0555] = 0x55;
- addr[0x0AAA] = 0x80;
- addr[0x0AAA] = 0xAA;
- addr[0x0555] = 0x55;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_char*)(info->start[sect]);
- addr[0] = 0x30;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_char*)(info->start[l_sect]);
- while ((addr[0] & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (vu_char *)info->start[0];
- addr[0] = 0xF0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- int rc;
-
- while (cnt > 0) {
- if ((rc = write_byte(info, addr++, *src++)) != 0) {
- return (rc);
- }
- --cnt;
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_byte (flash_info_t *info, ulong dest, uchar data)
-{
- vu_char *addr = (vu_char*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_char *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0AAA] = 0xAA;
- addr[0x0555] = 0x55;
- addr[0x0AAA] = 0xA0;
-
- *((vu_char *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c
deleted file mode 100644
index 6126b73..0000000
--- a/board/hermes/hermes.c
+++ /dev/null
@@ -1,590 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <commproc.h>
-#include <mpc8xx.h>
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# include <status_led.h>
-# define SHOW_BOOT_PROGRESS(arg) bootstage_mark(arg)
-#else
-# define SHOW_BOOT_PROGRESS(arg)
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-static ulong board_init (void);
-static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
- uchar * msg);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
- 0x1ff77c47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1fe77c35, 0xffaffc34, 0x1fa57c35, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaebc00, 0x10ad4c00, 0xf0afcc00,
- 0xf0afcc00, 0xe1bb8c06, 0x1ff77c47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x7ffffc07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Test ID string (HERMES...)
- *
- * Return code for board revision and network speed
- */
-
-int checkboard (void)
-{
- char buf[64];
- int i;
- int l = getenv_f("serial#", buf, sizeof(buf));
-
- puts ("Board: ");
-
- if (l < 0 || strncmp(buf, "HERMES", 6)) {
- puts ("### No HW ID - assuming HERMES-PRO");
- } else {
- for (i = 0; i < l; i++) {
- if (buf[i] == ' ')
- break;
- putc (buf[i]);
- }
- }
-
- gd->board_type = board_init ();
-
- printf (" Rev. %ld.x\n", (gd->board_type >> 16));
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size, size8, size9;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /*
- * Preliminary prescaler for refresh
- */
- memctl->memc_mptpr = 0x0400;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller banks 1 to the SDRAM banks at preliminary address
- */
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-
- /* HERMES-PRO boards have only one bank SDRAM */
-
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mamr = 0xD0802114;
- memctl->memc_mcr = 0x80002105;
- udelay (1);
- memctl->memc_mamr = 0xD0802118;
- memctl->memc_mcr = 0x80002130;
- udelay (1);
- memctl->memc_mamr = 0xD0802114;
- memctl->memc_mcr = 0x80002106;
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE_PRELIM,
- SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
- SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration at 9 columns */
- size = size9;
-/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
- } else { /* back to 8 columns */
- size = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
- udelay (500);
-/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
- }
-
- udelay (1000);
-
- memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
- memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- udelay (10000);
-
- return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#define PB_LED_3 0x00020000 /* Status LED's */
-#define PB_LED_2 0x00010000
-#define PB_LED_1 0x00008000
-#define PB_LED_0 0x00004000
-
-#define PB_LED_ALL (PB_LED_0 | PB_LED_1 | PB_LED_2 | PB_LED_3)
-
-#define PC_REP_SPD1 0x00000800
-#define PC_REP_SPD0 0x00000400
-
-#define PB_RESET_2081 0x00000020 /* Reset PEB2081 */
-
-#define PB_MAI_4 0x00000010 /* Configuration */
-#define PB_MAI_3 0x00000008
-#define PB_MAI_2 0x00000004
-#define PB_MAI_1 0x00000002
-#define PB_MAI_0 0x00000001
-
-#define PB_MAI_ALL (PB_MAI_0 | PB_MAI_1 | PB_MAI_2 | PB_MAI_3 | PB_MAI_4)
-
-
-#define PC_REP_MGRPRS 0x0200
-#define PC_REP_SPD 0x0040 /* Select 100 Mbps */
-#define PC_REP_RES 0x0004
-#define PC_BIT14 0x0002 /* ??? */
-#define PC_BIT15 0x0001 /* ??? ENDSL ?? */
-
-/* ------------------------------------------------------------------------- */
-
-static ulong board_init (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- ulong reg, revision, speed = 100;
- int ethspeed;
- char *s;
-
- if ((s = getenv ("ethspeed")) != NULL) {
- if (strcmp (s, "100") == 0) {
- ethspeed = 100;
- } else if (strcmp (s, "10") == 0) {
- ethspeed = 10;
- } else {
- ethspeed = 0;
- }
- } else {
- ethspeed = 0;
- }
-
- /* Configure Port B Output Pins => 0x0003cc3F */
- reg = PB_LED_ALL | PC_REP_SPD1 | PC_REP_SPD0 | PB_RESET_2081 |
- PB_MAI_ALL;
- immr->im_cpm.cp_pbpar &= ~reg;
- immr->im_cpm.cp_pbodr &= ~reg;
- immr->im_cpm.cp_pbdat &= ~reg; /* all 0 */
- immr->im_cpm.cp_pbdir |= reg;
-
- /* Check hardware revision */
- if ((immr->im_ioport.iop_pcdat & 0x0003) == 0x0003) {
- /*
- * Revision 3.x hardware
- */
- revision = 3;
-
- immr->im_ioport.iop_pcdat = 0x0240;
- immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14); /* = 0x0246 */
- immr->im_ioport.iop_pcdat |= PC_REP_RES;
- } else {
- immr->im_ioport.iop_pcdat = 0x0002;
- immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0207 */
-
- if ((immr->im_ioport.iop_pcdat & PC_REP_SPD) == 0) {
- /*
- * Revision 2.x hardware: PC9 connected to PB21
- */
- revision = 2;
-
- if (ethspeed == 0) {
- /* both 10 and 100 Mbps allowed:
- * select 10 Mbps and autonegotiation
- */
- puts (" [10+100]");
- immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
- speed = 10;
- } else if (ethspeed == 10) {
- /* we are asked for 10 Mbps,
- * so select 10 Mbps
- */
- puts (" [10]");
- immr->im_cpm.cp_pbdat = 0; /* ??? */
- speed = 10;
- } else {
- /* anything else:
- * select 100 Mbps
- */
- puts (" [100]");
- immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
- /* SPD1:SPD0 = 1:1 - 100 Mbps */
- speed = 100;
- }
- immr->im_ioport.iop_pcdat |= (PC_REP_RES | PC_BIT14);
-
- /* must be run from RAM */
- /* start_lxt980 (speed); */
- /*************************/
- } else {
- /*
- * Revision 1.x hardware
- */
- revision = 1;
-
- immr->im_ioport.iop_pcdat = PC_REP_MGRPRS | PC_BIT14; /* = 0x0202 */
- immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0247 */
-
- if (ethspeed == 0) {
- /* both 10 and 100 Mbps allowed:
- * select 100 Mbps and autonegotiation
- */
- puts (" [10+100]");
- immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
- immr->im_ioport.iop_pcdat |= PC_REP_SPD;
- } else if (ethspeed == 10) {
- /* we are asked for 10 Mbps,
- * so select 10 Mbps
- */
- puts (" [10]");
- immr->im_cpm.cp_pbdat = PC_REP_SPD0; /* SPD1:SPD0 = 0:1 - 10 Mbps */
- } else {
- /* anything else:
- * select 100 Mbps
- */
- puts (" [100]");
- immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
- /* SPD1:SPD0 = 1:1 - 100 Mbps */
- immr->im_ioport.iop_pcdat |= PC_REP_SPD;
- }
-
- immr->im_ioport.iop_pcdat |= PC_REP_RES;
- }
- }
- SHOW_BOOT_PROGRESS(BOOTSTAGE_ID_CHECK_MAGIC);
-
- return ((revision << 16) | (speed & 0xFFFF));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#define SCC_SM 1 /* Index => SCC2 */
-#define PROFF PROFF_SCC2
-
-#define SMI_MSGLEN 8 /* Length of SMI Messages */
-
-#define PHYGPCR_ADDR 0x109 /* Port Enable */
-#define PHYPCR_ADDR 0x132 /* PHY Port Control Reg. (port 1) */
-#define LEDPCR_ADDR 0x141 /* LED Port Control Reg. */
-#define RPRESET_ADDR 0x144 /* Repeater Reset */
-
-#define PHYPCR_SPEED 0x2000 /* on for 100 Mbps, off for 10 Mbps */
-#define PHYPCR_AN 0x1000 /* on to enable Auto-Negotiation */
-#define PHYPCR_REST_AN 0x0200 /* on to restart Auto-Negotiation */
-#define PHYPCR_FDX 0x0100 /* on for Full Duplex, off for HDX */
-#define PHYPCR_COLT 0x0080 /* on to enable COL signal test */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Must run from RAM:
- * uses parameter RAM area which is used for stack while running from ROM
- */
-void hermes_start_lxt980 (int speed)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm);
- volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]);
- volatile cbd_t *bd;
- volatile hdlc_pram_t *hp;
- uchar smimsg[SMI_MSGLEN];
- ushort phypcrval;
- uint bd_off;
- int pnr;
-
- printf ("LXT9880: %3d Mbps\n", speed);
-
- immr->im_ioport.iop_paodr |= 0x0008; /* init PAODR: PA12 (TXD2) open drain */
- immr->im_ioport.iop_papar |= 0x400c; /* init PAPAR: TXD2, RXD2, BRGO4 */
- immr->im_ioport.iop_padir &= 0xbff3; /* init PADIR: BRGO4 */
- immr->im_ioport.iop_padir |= 0x4000;
-
- /* get temporary BD; no need for permanent alloc */
- bd_off = dpram_base_align (8);
-
- bd = (cbd_t *) (immr->im_cpm.cp_dpmem + bd_off);
-
- bd->cbd_bufaddr = 0;
- bd->cbd_datlen = 0;
- bd->cbd_sc = BD_SC_WRAP | BD_SC_LAST | BD_SC_INTRPT | BD_SC_TC;
-
- /* init. baudrate generator BRG4 */
- cp->cp_brgc4 = (0x00010000 | (50 << 1)); /* output 1 MHz */
-
- cp->cp_sicr &= 0xFFFF00FF; /* SICR: mask SCC2 */
- cp->cp_sicr |= 0x00001B00; /* SICR: SCC2 clk BRG4 */
-
- /* init SCC_SM register */
- sp->scc_psmr = 0x0000; /* init PSMR: no additional flags */
- sp->scc_todr = 0x0000;
- sp->scc_dsr = 0x7e7e;
-
- /* init. SCC_SM parameter area */
- hp = (hdlc_pram_t *) & cp->cp_dparam[PROFF];
-
- hp->tbase = bd_off; /* offset from beginning of DPRAM */
-
- hp->rfcr = 0x18;
- hp->tfcr = 0x18;
- hp->mrblr = 10;
-
- hp->c_mask = 0x0000f0b8;
- hp->c_pres = 0x0000ffff;
-
- hp->disfc = 0;
- hp->crcec = 0;
- hp->abtsc = 0;
- hp->nmarc = 0;
- hp->retrc = 0;
-
- hp->mflr = 10;
-
- hp->rfthr = 1;
-
- hp->hmask = 0;
- hp->haddr1 = 0;
- hp->haddr2 = 0;
- hp->haddr3 = 0;
- hp->haddr4 = 0;
-
- cp->cp_cpcr = SCC_SM << 6 | 0x0001; /* SCC_SM: init TX/RX params */
- while (cp->cp_cpcr & CPM_CR_FLG);
-
- /* clear all outstanding SCC events */
- sp->scc_scce = ~0;
-
- /* enable transmitter: GSMR_L: TPL=2(16bits), TPP=3(all ones), ENT */
- sp->scc_gsmrh = 0;
- sp->scc_gsmrl |= SCC_GSMRL_TPL_16 | SCC_GSMRL_TPP_ALL1 |
- SCC_GSMRL_ENT | SCC_GSMRL_MODE_HDLC;
-
-#if 0
- smimsg[0] = 0x00; /* CHIP/HUB ID */
- smimsg[1] = 0x38; /* WRITE CMD */
- smimsg[2] = (RPRESET_ADDR << 4) & 0xf0;
- smimsg[3] = RPRESET_ADDR >> 4;
- smimsg[4] = 0x01;
- smimsg[5] = 0x00;
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-#endif
-
- smimsg[0] = 0x7f; /* BROADCAST */
- smimsg[1] = 0x34; /* ASSIGN HUB ID */
- smimsg[2] = 0x00;
- smimsg[3] = 0x00;
- smimsg[4] = 0x00; /* HUB ID = 0 */
- smimsg[5] = 0x00;
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-
- smimsg[0] = 0x7f; /* BROADCAST */
- smimsg[1] = 0x3c; /* SET ARBOUT TO 0 */
- smimsg[2] = 0x00; /* ADDRESS = 0 */
- smimsg[3] = 0x00;
- smimsg[4] = 0x00; /* DATA = 0 */
- smimsg[5] = 0x00;
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-
- if (speed == 100) {
- phypcrval = PHYPCR_SPEED; /* 100 MBIT, disable autoneg. */
- } else {
- phypcrval = 0; /* 10 MBIT, disable autoneg. */
- }
-
- /* send MSGs */
- for (pnr = 0; pnr < 8; pnr++) {
- smimsg[0] = 0x00; /* CHIP/HUB ID */
- smimsg[1] = 0x38; /* WRITE CMD */
- smimsg[2] = ((PHYPCR_ADDR + pnr) << 4) & 0xf0;
- smimsg[3] = (PHYPCR_ADDR + pnr) >> 4;
- smimsg[4] = (unsigned char) (phypcrval & 0xff);
- smimsg[5] = (unsigned char) (phypcrval >> 8);
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
- }
-
- smimsg[0] = 0x00; /* CHIP/HUB ID */
- smimsg[1] = 0x38; /* WRITE CMD */
- smimsg[2] = (PHYGPCR_ADDR << 4) & 0xf0;
- smimsg[3] = PHYGPCR_ADDR >> 4;
- smimsg[4] = 0xff; /* enable port 1-8 */
- smimsg[5] = 0x01; /* enable MII1 (0x01) */
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-
- smimsg[0] = 0x00; /* CHIP/HUB ID */
- smimsg[1] = 0x38; /* WRITE CMD */
- smimsg[2] = (LEDPCR_ADDR << 4) & 0xf0;
- smimsg[3] = LEDPCR_ADDR >> 4;
- smimsg[4] = 0xaa; /* Port 1-8 Conf.bits = 10 (Hardware control) */
- smimsg[5] = 0xaa;
- smimsg[6] = 0x00;
- smimsg[7] = 0x00;
-
- send_smi_frame (sp, bd, smimsg);
-
- /*
- * Disable Transmitter (so that we can free the BD, too)
- */
- sp->scc_gsmrl &= ~SCC_GSMRL_ENT;
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
- uchar * msg)
-{
-#ifdef DEBUG
- unsigned hub, chip, cmd, length, addr;
-
- hub = msg[0] & 0x1F;
- chip = msg[0] >> 5;
- cmd = msg[1] & 0x1F;
- length = (msg[1] >> 5) | ((msg[2] & 0x0F) << 3);
- addr = (msg[2] >> 4) | (msg[3] << 4);
-
- printf ("SMI send: Hub %02x Chip %x Cmd %02x Len %d Addr %03x: "
- "%02x %02x %02x %02x\n",
- hub, chip, cmd, length, addr, msg[4], msg[5], msg[6], msg[7]);
-#endif /* DEBUG */
-
- bd->cbd_bufaddr = (uint) msg;
- bd->cbd_datlen = SMI_MSGLEN;
- bd->cbd_sc |= BD_SC_READY;
-
- /* wait for msg transmitted */
- while ((sp->scc_scce & 0x0002) == 0);
- /* clear all events */
- sp->scc_scce = ~0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-void show_boot_progress (int status)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- /* let things compatible */
- if (status < -BOOTSTAGE_ID_POST_FAIL_R)
- status = -1;
- status ^= 0x0F;
- status = (status & 0x0F) << 14;
- immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status;
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds
deleted file mode 100644
index 0309860..0000000
--- a/board/hermes/u-boot.lds
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- board/hermes/built-in.o (.text*)
-
- . = env_offset;
- common/env_embedded.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug
deleted file mode 100644
index f34c07b..0000000
--- a/board/hermes/u-boot.lds.debug
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
- arch/powerpc/lib/time.o (.text)
- arch/powerpc/lib/ticks.o (.text)
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 7b87cc2..47522f8 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -150,6 +150,13 @@
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
void set_fdt(void)
{
switch (gd->bd->bi_arch_number) {
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
index 1fd9f2c..609edf1 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -128,6 +128,13 @@
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#ifdef CONFIG_SMC911X
/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
static const u32 gpmc_lan92xx_config[] = {
diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c
index 9ef0026..d39203a 100644
--- a/board/logicpd/zoom1/zoom1.c
+++ b/board/logicpd/zoom1/zoom1.c
@@ -109,6 +109,11 @@
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
#endif
#ifdef CONFIG_CMD_NET
diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c
index a69359f..c9d615b 100644
--- a/board/matrix_vision/mvblx/mvblx.c
+++ b/board/matrix_vision/mvblx/mvblx.c
@@ -94,6 +94,12 @@
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+ twl4030_power_mmc_init(1);
+}
#endif
#if defined(CONFIG_CMD_NET)
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index c2e07db..b6b8ad6 100644
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@@ -659,3 +659,9 @@
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+ twl4030_power_mmc_init(1);
+}
diff --git a/board/overo/overo.c b/board/overo/overo.c
index dfb8602..b7f85e7 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -493,6 +493,13 @@
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c
index 146dcea..59b5a7e 100644
--- a/board/pandora/pandora.c
+++ b/board/pandora/pandora.c
@@ -126,4 +126,9 @@
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
#endif
diff --git a/board/raspberrypi/rpi_b/Kconfig b/board/raspberrypi/rpi/Kconfig
similarity index 71%
rename from board/raspberrypi/rpi_b/Kconfig
rename to board/raspberrypi/rpi/Kconfig
index 501d511..6a538cf 100644
--- a/board/raspberrypi/rpi_b/Kconfig
+++ b/board/raspberrypi/rpi/Kconfig
@@ -1,7 +1,7 @@
-if TARGET_RPI_B
+if TARGET_RPI
config SYS_BOARD
- default "rpi_b"
+ default "rpi"
config SYS_VENDOR
default "raspberrypi"
@@ -10,6 +10,6 @@
default "bcm2835"
config SYS_CONFIG_NAME
- default "rpi_b"
+ default "rpi"
endif
diff --git a/board/raspberrypi/rpi/MAINTAINERS b/board/raspberrypi/rpi/MAINTAINERS
new file mode 100644
index 0000000..6dcb7bd
--- /dev/null
+++ b/board/raspberrypi/rpi/MAINTAINERS
@@ -0,0 +1,6 @@
+RPI BOARD
+M: Stephen Warren <swarren@wwwdotorg.org>
+S: Maintained
+F: board/raspberrypi/rpi/
+F: include/configs/rpi.h
+F: configs/rpi_defconfig
diff --git a/board/raspberrypi/rpi_b/Makefile b/board/raspberrypi/rpi/Makefile
similarity index 96%
rename from board/raspberrypi/rpi_b/Makefile
rename to board/raspberrypi/rpi/Makefile
index 7e9bfbf..c53c92b 100644
--- a/board/raspberrypi/rpi_b/Makefile
+++ b/board/raspberrypi/rpi/Makefile
@@ -12,4 +12,4 @@
# GNU General Public License for more details.
#
-obj-y := rpi_b.o
+obj-y := rpi.o
diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi/rpi.c
similarity index 63%
rename from board/raspberrypi/rpi_b/rpi_b.c
rename to board/raspberrypi/rpi/rpi.c
index db904a4..51a4fa1 100644
--- a/board/raspberrypi/rpi_b/rpi_b.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -42,6 +42,12 @@
u32 end_tag;
};
+struct msg_get_board_rev {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_board_rev get_board_rev;
+ u32 end_tag;
+};
+
struct msg_get_mac_address {
struct bcm2835_mbox_hdr hdr;
struct bcm2835_mbox_tag_get_mac_address get_mac_address;
@@ -60,6 +66,67 @@
u32 end_tag;
};
+/* See comments in mbox.h for data source */
+static const struct {
+ const char *name;
+ const char *fdtfile;
+} models[] = {
+ [BCM2835_BOARD_REV_B_I2C0_2] = {
+ "Model B (no P5)",
+ "bcm2835-rpi-b-i2c0.dtb",
+ },
+ [BCM2835_BOARD_REV_B_I2C0_3] = {
+ "Model B (no P5)",
+ "bcm2835-rpi-b-i2c0.dtb",
+ },
+ [BCM2835_BOARD_REV_B_I2C1_4] = {
+ "Model B",
+ "bcm2835-rpi-b.dtb",
+ },
+ [BCM2835_BOARD_REV_B_I2C1_5] = {
+ "Model B",
+ "bcm2835-rpi-b.dtb",
+ },
+ [BCM2835_BOARD_REV_B_I2C1_6] = {
+ "Model B",
+ "bcm2835-rpi-b.dtb",
+ },
+ [BCM2835_BOARD_REV_A_7] = {
+ "Model A",
+ "bcm2835-rpi-a.dtb",
+ },
+ [BCM2835_BOARD_REV_A_8] = {
+ "Model A",
+ "bcm2835-rpi-a.dtb",
+ },
+ [BCM2835_BOARD_REV_A_9] = {
+ "Model A",
+ "bcm2835-rpi-a.dtb",
+ },
+ [BCM2835_BOARD_REV_B_REV2_d] = {
+ "Model B rev2",
+ "bcm2835-rpi-b-rev2.dtb",
+ },
+ [BCM2835_BOARD_REV_B_REV2_e] = {
+ "Model B rev2",
+ "bcm2835-rpi-b-rev2.dtb",
+ },
+ [BCM2835_BOARD_REV_B_REV2_f] = {
+ "Model B rev2",
+ "bcm2835-rpi-b-rev2.dtb",
+ },
+ [BCM2835_BOARD_REV_B_PLUS] = {
+ "Model B+",
+ "bcm2835-rpi-b-plus.dtb",
+ },
+ [BCM2835_BOARD_REV_CM] = {
+ "Compute Module",
+ "bcm2835-rpi-cm.dtb",
+ },
+};
+
+u32 rpi_board_rev = 0;
+
int dram_init(void)
{
ALLOC_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1, 16);
@@ -79,13 +146,27 @@
return 0;
}
-int misc_init_r(void)
+static void set_fdtfile(void)
+{
+ const char *fdtfile;
+
+ if (getenv("fdtfile"))
+ return;
+
+ fdtfile = models[rpi_board_rev].fdtfile;
+ if (!fdtfile)
+ fdtfile = "bcm2835-rpi-other.dtb";
+
+ setenv("fdtfile", fdtfile);
+}
+
+static void set_usbethaddr(void)
{
ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16);
int ret;
if (getenv("usbethaddr"))
- return 0;
+ return;
BCM2835_MBOX_INIT_HDR(msg);
BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS);
@@ -94,11 +175,18 @@
if (ret) {
printf("bcm2835: Could not query MAC address\n");
/* Ignore error; not critical */
- return 0;
+ return;
}
eth_setenv_enetaddr("usbethaddr", msg->get_mac_address.body.resp.mac);
+ return;
+}
+
+int misc_init_r(void)
+{
+ set_fdtfile();
+ set_usbethaddr();
return 0;
}
@@ -126,8 +214,36 @@
return 0;
}
+static void get_board_rev(void)
+{
+ ALLOC_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1, 16);
+ int ret;
+ const char *name;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret) {
+ printf("bcm2835: Could not query board revision\n");
+ /* Ignore error; not critical */
+ return;
+ }
+
+ rpi_board_rev = msg->get_board_rev.body.resp.rev;
+ if (rpi_board_rev >= ARRAY_SIZE(models))
+ rpi_board_rev = 0;
+
+ name = models[rpi_board_rev].name;
+ if (!name)
+ name = "Unknown model";
+ printf("RPI model: %s\n", name);
+}
+
int board_init(void)
{
+ get_board_rev();
+
gd->bd->bi_boot_params = 0x100;
return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
diff --git a/board/raspberrypi/rpi_b/MAINTAINERS b/board/raspberrypi/rpi_b/MAINTAINERS
deleted file mode 100644
index 14f3948..0000000
--- a/board/raspberrypi/rpi_b/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-RPI_B BOARD
-M: Stephen Warren <swarren@wwwdotorg.org>
-S: Maintained
-F: board/raspberrypi/rpi_b/
-F: include/configs/rpi_b.h
-F: configs/rpi_b_defconfig
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 2782bcc..cc0ac6b 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -96,15 +96,6 @@
return &dpll_ddr;
}
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- omap_nand_switch_ecc(1, 8);
-
- return 0;
-}
-#endif
-
#ifndef CONFIG_SPL_BUILD
#if defined(BOARD_DFU_BUTTON_GPIO)
/*
diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c
index 266dbbb..7baac3d 100644
--- a/board/siemens/common/factoryset.c
+++ b/board/siemens/common/factoryset.c
@@ -86,6 +86,7 @@
int i, nxt = 0;
int c;
unsigned char end = 0xff;
+ unsigned char tmp;
for (i = 0; fact_get_char(i) != end; i = nxt) {
nxt = i + 1;
@@ -93,6 +94,7 @@
int pos;
int endpos;
int z;
+ int level = 0;
c = strncmp((char *)&eeprom_buf[i + 1], (char *)record,
strlen((char *)record));
@@ -103,22 +105,30 @@
/* search for "<" */
c = -1;
for (z = pos; fact_get_char(z) != end; z++) {
- if ((fact_get_char(z) == '<') ||
- (fact_get_char(z) == '>')) {
- endpos = z;
- nxt = endpos;
- c = 0;
- break;
+ if (fact_get_char(z) == '<') {
+ if (level == 0) {
+ endpos = z;
+ nxt = endpos;
+ c = 0;
+ break;
+ } else {
+ level--;
+ }
}
+ if (fact_get_char(z) == '>')
+ level++;
}
+ } else {
+ continue;
}
if (c == 0) {
/* end found -> call get_factory_val */
+ tmp = eeprom_buf[endpos];
eeprom_buf[endpos] = end;
ret = get_factory_val(&eeprom_buf[pos],
- size - pos, name, buf, len);
+ endpos - pos, name, buf, len);
/* fix buffer */
- eeprom_buf[endpos] = '<';
+ eeprom_buf[endpos] = tmp;
debug("%s: %s.%s = %s\n",
__func__, record, name, buf);
return ret;
@@ -210,15 +220,6 @@
printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id,
factory_dat.usb_product_id);
#endif
- if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
- (uchar *)"id", buf,
- MAX_STRING_LENGTH)) {
- if (strncmp((const char *)buf, "PXM50", 5) == 0)
- factory_dat.pxm50 = 1;
- else
- factory_dat.pxm50 = 0;
- }
- debug("PXM50: %d\n", factory_dat.pxm50);
#if defined(CONFIG_VIDEO)
if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1",
(uchar *)"name", factory_dat.disp_name,
@@ -238,6 +239,23 @@
NULL, 16);
debug("version number: %d\n", factory_dat.version);
}
+ /* Get ASN from factory set if available */
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+ (uchar *)"id", factory_dat.asn,
+ MAX_STRING_LENGTH)) {
+ debug("factoryset asn: %s\n", factory_dat.asn);
+ } else {
+ factory_dat.asn[0] = 0;
+ }
+ /* Get COMP/ver from factory set if available */
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"COMP",
+ (uchar *)"ver",
+ factory_dat.comp_version,
+ MAX_STRING_LENGTH)) {
+ debug("factoryset COMP/ver: %s\n", factory_dat.comp_version);
+ } else {
+ strcpy((char *)factory_dat.comp_version, "1.0");
+ }
return 0;
diff --git a/board/siemens/common/factoryset.h b/board/siemens/common/factoryset.h
index 4d6de10..3f23d5e 100644
--- a/board/siemens/common/factoryset.h
+++ b/board/siemens/common/factoryset.h
@@ -20,6 +20,8 @@
#endif
unsigned char serial[MAX_STRING_LENGTH];
int version;
+ uchar asn[MAX_STRING_LENGTH];
+ uchar comp_version[MAX_STRING_LENGTH];
};
int factoryset_read_eeprom(int i2c_addr);
diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index 9be2e34..ede73ba 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -280,4 +280,13 @@
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ omap_nand_switch_ecc(1, 8);
+
+ return 0;
+}
+#endif
+
#include "../common/board.c"
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index 559af0e..264ba02 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -428,4 +428,38 @@
return 0;
}
#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+
+ omap_nand_switch_ecc(1, 8);
+
+#ifdef CONFIG_FACTORYSET
+ if (factory_dat.asn[0] != 0) {
+ char tmp[2 * MAX_STRING_LENGTH + 2];
+
+ if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
+ factory_dat.pxm50 = 1;
+ else
+ factory_dat.pxm50 = 0;
+ sprintf(tmp, "%s_%s", factory_dat.asn,
+ factory_dat.comp_version);
+ ret = setenv("boardid", tmp);
+ if (ret)
+ printf("error setting board id\n");
+ } else {
+ factory_dat.pxm50 = 1;
+ ret = setenv("boardid", "PXM50_1.0");
+ if (ret)
+ printf("error setting board id\n");
+ }
+ debug("PXM50: %d\n", factory_dat.pxm50);
+#endif
+
+ return 0;
+}
+#endif
+
#include "../common/board.c"
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index 1752df2..fb840f7 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -467,4 +467,27 @@
return 0;
}
#endif /* ifdef CONFIG_VIDEO */
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+ char tmp[2 * MAX_STRING_LENGTH + 2];
+
+ omap_nand_switch_ecc(1, 8);
+
+ if (factory_dat.asn[0] != 0)
+ sprintf(tmp, "%s_%s", factory_dat.asn,
+ factory_dat.comp_version);
+ else
+ sprintf(tmp, "QMX7.E38_4.0");
+
+ ret = setenv("boardid", tmp);
+ if (ret)
+ printf("error setting board id\n");
+
+ return 0;
+}
+#endif
+
#include "../common/board.c"
diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c
index 44a8240..744ff44 100644
--- a/board/technexion/tao3530/tao3530.c
+++ b/board/technexion/tao3530/tao3530.c
@@ -188,6 +188,13 @@
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
/* Call usb_stop() before starting the kernel */
void show_boot_progress(int val)
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 4c5e381..7b37fbe 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -534,6 +534,13 @@
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
/* Call usb_stop() before starting the kernel */
void show_boot_progress(int val)
diff --git a/board/ti/beagle_x15/Kconfig b/board/ti/beagle_x15/Kconfig
new file mode 100644
index 0000000..a305ff1
--- /dev/null
+++ b/board/ti/beagle_x15/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BEAGLE_X15
+
+config SYS_BOARD
+ default "beagle_x15"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "beagle_x15"
+
+endif
diff --git a/board/ti/beagle_x15/Makefile b/board/ti/beagle_x15/Makefile
new file mode 100644
index 0000000..5cd6873
--- /dev/null
+++ b/board/ti/beagle_x15/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014
+# Texas Instruments, <www.ti.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c
new file mode 100644
index 0000000..db96e34
--- /dev/null
+++ b/board/ti/beagle_x15/board.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Felipe Balbi <balbi@ti.com>
+ *
+ * Based on board/ti/dra7xx/evm.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <palmas.h>
+#include <sata.h>
+#include <usb.h>
+#include <asm/omap_common.h>
+#include <asm/emif.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sata.h>
+#include <asm/arch/gpio.h>
+#include <environment.h>
+
+#include "mux_data.h"
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+#include <cpsw.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: BeagleBoard x15\n"
+};
+
+static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
+ .dmm_lisa_map_3 = 0x80740300,
+ .is_ma_present = 0x1
+};
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+{
+ *dmm_lisa_regs = &beagle_x15_lisa_regs;
+}
+
+static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
+ .sdram_config_init = 0x61851b32,
+ .sdram_config = 0x61851b32,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xceef266b,
+ .sdram_tim2 = 0x328f7fda,
+ .sdram_tim3 = 0x027f88a8,
+ .read_idle_ctrl = 0x00050001,
+ .zq_config = 0x0007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400a,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
+ .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
+ .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
+static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x00800080,
+ 0x00360036,
+ 0x00340034,
+ 0x00360036,
+ 0x00350035,
+ 0x00350035,
+
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+
+ 0x00430043,
+ 0x003e003e,
+ 0x004a004a,
+ 0x00470047,
+ 0x00400040,
+
+ 0x00000000,
+ 0x00600020,
+ 0x40010080,
+ 0x08102040,
+
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040
+};
+
+static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
+ .sdram_config_init = 0x61851b32,
+ .sdram_config = 0x61851b32,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xceef266b,
+ .sdram_tim2 = 0x328f7fda,
+ .sdram_tim3 = 0x027f88a8,
+ .read_idle_ctrl = 0x00050001,
+ .zq_config = 0x0007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400a,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
+ .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
+ .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
+static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x00800080,
+ 0x00370037,
+ 0x00390039,
+ 0x00360036,
+ 0x00370037,
+ 0x00350035,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x00540054,
+ 0x00540054,
+ 0x004e004e,
+ 0x004c004c,
+ 0x00400040,
+
+ 0x00000000,
+ 0x00600020,
+ 0x40010080,
+ 0x08102040,
+
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040
+};
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+ switch (emif_nr) {
+ case 1:
+ *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
+ break;
+ case 2:
+ *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
+ break;
+ }
+}
+
+void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
+{
+ switch (emif_nr) {
+ case 1:
+ *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
+ *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
+ break;
+ case 2:
+ *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
+ *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
+ break;
+ }
+}
+
+struct vcores_data beagle_x15_volts = {
+ .mpu.value = VDD_MPU_DRA752,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12,
+ .mpu.pmic = &tps659038,
+
+ .eve.value = VDD_EVE_DRA752,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45,
+ .eve.pmic = &tps659038,
+
+ .gpu.value = VDD_GPU_DRA752,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS45,
+ .gpu.pmic = &tps659038,
+
+ .core.value = VDD_CORE_DRA752,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS659038_REG_ADDR_SMPS6,
+ .core.pmic = &tps659038,
+
+ .iva.value = VDD_IVA_DRA752,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS659038_REG_ADDR_SMPS45,
+ .iva.pmic = &tps659038,
+};
+
+void hw_data_init(void)
+{
+ *prcm = &dra7xx_prcm;
+ *dplls_data = &dra7xx_dplls;
+ *omap_vcores = &beagle_x15_volts;
+ *ctrl = &dra7xx_ctrl;
+}
+
+int board_init(void)
+{
+ gpmc_init();
+ gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ init_sata(0);
+ /*
+ * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
+ * This is the POWERHOLD-in-Low behavior.
+ */
+ palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
+ return 0;
+}
+
+static void do_set_mux32(u32 base,
+ struct pad_conf_entry const *array, int size)
+{
+ int i;
+ struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
+
+ for (i = 0; i < size; i++, pad++)
+ writel(pad->val, base + pad->offset);
+}
+
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ if (getenv_yesno("boot_os") != 1)
+ return 1;
+#endif
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+/* Delay value to add to calibrated value */
+#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
+#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
+#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
+#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
+#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
+#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
+#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
+#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
+#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
+#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
+
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 1,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 2,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+ uint32_t ctrl_val;
+
+ /* try reading mac address from efuse */
+ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
+ mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
+ mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = mac_hi & 0xFF;
+ mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+ mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+ mac_addr[5] = mac_lo & 0xFF;
+
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
+ mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
+ mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = mac_hi & 0xFF;
+ mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+ mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+ mac_addr[5] = mac_lo & 0xFF;
+
+ if (!getenv("eth1addr")) {
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("eth1addr", mac_addr);
+ }
+
+ ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
+ ctrl_val |= 0x22;
+ writel(ctrl_val, (*ctrl)->control_core_control_io1);
+
+ ret = cpsw_register(&cpsw_data);
+ if (ret < 0)
+ printf("Error %d registering CPSW switch\n", ret);
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_OMAP
+int board_usb_init(int index, enum usb_init_type init)
+{
+ setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
+ OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);
+
+ return 0;
+}
+#endif
diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h
new file mode 100644
index 0000000..2294abe
--- /dev/null
+++ b/board/ti/beagle_x15/mux_data.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Felipe Balbi <balbi@ti.com>
+ *
+ * Based on board/ti/dra7xx/evm.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _MUX_DATA_BEAGLE_X15_H_
+#define _MUX_DATA_BEAGLE_X15_H_
+
+#include <asm/arch/mux_dra7xx.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+ {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
+ {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
+ {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
+ {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
+ {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
+ {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
+ {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
+ {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
+ {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
+ {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
+ {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
+ {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
+ {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
+ {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
+ {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
+ {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
+ {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
+ {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
+ {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
+ {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
+ {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
+ {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
+ {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
+ {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
+ {RGMII0_TXC, (M0) },
+ {RGMII0_TXCTL, (M0) },
+ {RGMII0_TXD3, (M0) },
+ {RGMII0_TXD2, (M0) },
+ {RGMII0_TXD1, (M0) },
+ {RGMII0_TXD0, (M0) },
+ {RGMII0_RXC, (IEN | M0) },
+ {RGMII0_RXCTL, (IEN | M0) },
+ {RGMII0_RXD3, (IEN | M0) },
+ {RGMII0_RXD2, (IEN | M0) },
+ {RGMII0_RXD1, (IEN | M0) },
+ {RGMII0_RXD0, (IEN | M0) },
+ {USB1_DRVVBUS, (M0 | FSC) },
+ {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */
+};
+#endif /* _MUX_DATA_BEAGLE_X15_H_ */
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 37df7b2..6522241 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -96,18 +96,6 @@
return 0;
}
-/**
- * @brief misc_init_r - Configure EVM board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * @return 0
- */
-int misc_init_r(void)
-{
- return 0;
-}
-
static void do_set_mux32(u32 base,
struct pad_conf_entry const *array, int size)
{
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 7276014..4824077 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -130,8 +130,8 @@
{GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
{GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
{GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
- {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
- {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
+ {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
+ {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
{GPMC_A18, (M1)}, /* QSPI1_SCLK */
{GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
{GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index 81dd081..3f93d9c 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -20,6 +20,7 @@
#include <asm/arch/mmc_host_def.h>
#include <asm/gpio.h>
#include <i2c.h>
+#include <twl4030.h>
#include <asm/mach-types.h>
#include <linux/mtd/nand.h>
#include "evm.h"
@@ -264,3 +265,10 @@
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
+
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c
index 957940d..7171363 100644
--- a/board/ti/sdp3430/sdp.c
+++ b/board/ti/sdp3430/sdp.c
@@ -195,4 +195,9 @@
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
#endif
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index bcbee73..b978044 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -124,6 +124,13 @@
}
#endif
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
#if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
/*
* Routine: board_eth_init
diff --git a/common/board_r.c b/common/board_r.c
index 19c6427..4eb7a02 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -291,26 +291,14 @@
{
ulong flash_size = 0;
bd_t *bd = gd->bd;
- int ok;
puts("Flash: ");
- if (board_flash_wp_on()) {
+ if (board_flash_wp_on())
printf("Uninitialized - Write Protect On\n");
- /* Since WP is on, we can't find real size. Set to 0 */
- ok = 1;
- } else {
+ else
flash_size = flash_init();
- ok = flash_size > 0;
- }
- if (!ok) {
- puts("*** failed ***\n");
-#ifdef CONFIG_PPC
- /* Why does PPC do this? */
- hang();
-#endif
- return -1;
- }
+
print_size(flash_size, "");
#ifdef CONFIG_SYS_FLASH_CHECKSUM
/*
@@ -454,24 +442,6 @@
return 0;
}
-#ifdef CONFIG_HERMES
-static int initr_hermes(void)
-{
- if ((gd->board_type >> 16) == 2)
- gd->bd->bi_ethspeed = gd->board_type & 0xFFFF;
- else
- gd->bd->bi_ethspeed = 0xFFFF;
- return 0;
-}
-
-static int initr_hermes_start(void)
-{
- if (gd->bd->bi_ethspeed != 0xFFFF)
- hermes_start_lxt980((int) gd->bd->bi_ethspeed);
- return 0;
-}
-#endif
-
#ifdef CONFIG_SC3
/* TODO: with new initcalls, move this into the driver */
extern void sc3_read_eeprom(void);
@@ -775,7 +745,7 @@
initr_flash,
#endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_PPC) || defined(CONFIG_X86)
+#if defined(CONFIG_PPC)
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r,
#endif
@@ -803,9 +773,6 @@
#ifdef CONFIG_SC3
initr_sc3_read_eeprom,
#endif
-#ifdef CONFIG_HERMES
- initr_hermes,
-#endif
#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
mac_read_from_eeprom,
#endif
@@ -831,18 +798,12 @@
#ifdef CONFIG_MISC_INIT_R
misc_init_r, /* miscellaneous platform-dependent init */
#endif
-#ifdef CONFIG_HERMES
- initr_hermes_start,
-#endif
INIT_FUNC_WATCHDOG_RESET
#ifdef CONFIG_CMD_KGDB
initr_kgdb,
#endif
-#ifdef CONFIG_X86
- board_early_init_r,
-#endif
interrupt_init,
-#if defined(CONFIG_ARM) || defined(CONFIG_x86)
+#if defined(CONFIG_ARM)
initr_enable_interrupts,
#endif
#ifdef CONFIG_X86
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 3d37a86..f0b713c 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -144,9 +144,6 @@
print_eth(5);
#endif
-#ifdef CONFIG_HERMES
- print_mhz("ethspeed", bd->bi_ethspeed);
-#endif
printf("IP addr = %s\n", getenv("ipaddr"));
printf("baudrate = %6u bps\n", gd->baudrate);
print_num("relocaddr", gd->relocaddr);
diff --git a/common/cmd_fuse.c b/common/cmd_fuse.c
index abab978..d4bc0f6 100644
--- a/common/cmd_fuse.c
+++ b/common/cmd_fuse.c
@@ -128,7 +128,7 @@
err:
puts("ERROR\n");
- return ret;
+ return CMD_RET_FAILURE;
}
U_BOOT_CMD(
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index 0d50dcf..bcb3ee3 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -19,6 +19,7 @@
#include <dataflash.h>
#endif
#include <hash.h>
+#include <inttypes.h>
#include <watchdog.h>
#include <asm/io.h>
#include <linux/compiler.h>
@@ -338,7 +339,8 @@
if (word1 != word2) {
ulong offset = buf1 - base;
#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
- printf("%s at 0x%p (%#0*llx) != %s at 0x%p (%#0*llx)\n",
+ printf("%s at 0x%p (%#0*"PRIx64") != %s at 0x%p (%#0*"
+ PRIx64 ")\n",
type, (void *)(addr1 + offset), size, word1,
type, (void *)(addr2 + offset), size, word2);
#else
@@ -1146,7 +1148,7 @@
printf(" %08x", *((u32 *)ptr));
#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
else if (size == 8)
- printf(" %016llx", *((u64 *)ptr));
+ printf(" %016" PRIx64, *((u64 *)ptr));
#endif
else if (size == 2)
printf(" %04x", *((u16 *)ptr));
diff --git a/common/console.c b/common/console.c
index 4695386..29560c3 100644
--- a/common/console.c
+++ b/common/console.c
@@ -125,12 +125,12 @@
*/
switch (file) {
case stdin:
- gd->jt[XF_getc] = dev->getc;
- gd->jt[XF_tstc] = dev->tstc;
+ gd->jt[XF_getc] = getc;
+ gd->jt[XF_tstc] = tstc;
break;
case stdout:
- gd->jt[XF_putc] = dev->putc;
- gd->jt[XF_puts] = dev->puts;
+ gd->jt[XF_putc] = putc;
+ gd->jt[XF_puts] = puts;
gd->jt[XF_printf] = printf;
break;
}
diff --git a/common/fdt_support.c b/common/fdt_support.c
index ea42c63..8266bca 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <inttypes.h>
#include <stdio_dev.h>
#include <linux/ctype.h>
#include <linux/types.h>
@@ -370,22 +371,22 @@
int n)
{
int i;
- int address_len = fdt_address_cells(fdt, 0);
- int size_len = fdt_size_cells(fdt, 0);
+ int address_cells = fdt_address_cells(fdt, 0);
+ int size_cells = fdt_size_cells(fdt, 0);
char *p = buf;
for (i = 0; i < n; i++) {
- if (address_len == 2)
+ if (address_cells == 2)
*(fdt64_t *)p = cpu_to_fdt64(address[i]);
else
*(fdt32_t *)p = cpu_to_fdt32(address[i]);
- p += address_len;
+ p += 4 * address_cells;
- if (size_len == 2)
+ if (size_cells == 2)
*(fdt64_t *)p = cpu_to_fdt64(size[i]);
else
*(fdt32_t *)p = cpu_to_fdt32(size[i]);
- p += size_len;
+ p += 4 * size_cells;
}
return p - (char *)buf;
@@ -914,8 +915,6 @@
fdt_delprop(blob, off, alias);
}
-#define PRu64 "%llx"
-
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
#define OF_BAD_ADDR ((u64)-1)
@@ -973,8 +972,8 @@
s = of_read_number(range + na + pna, ns);
da = of_read_number(addr, na);
- debug("OF: default map, cp="PRu64", s="PRu64", da="PRu64"\n",
- cp, s, da);
+ debug("OF: default map, cp=%" PRIu64 ", s=%" PRIu64
+ ", da=%" PRIu64 "\n", cp, s, da);
if (da < cp || da >= (cp + s))
return OF_BAD_ADDR;
@@ -1052,7 +1051,7 @@
finish:
of_dump_addr("OF: parent translation for:", addr, pna);
- debug("OF: with offset: "PRu64"\n", offset);
+ debug("OF: with offset: %" PRIu64 "\n", offset);
/* Translate it into parent bus space */
return pbus->translate(addr, offset, pna);
@@ -1381,9 +1380,9 @@
dt_addr = fdt_translate_address(fdt, node, reg);
if (addr != dt_addr) {
- printf("Warning: U-Boot configured device %s at address %llx,\n"
- " but the device tree has it address %llx.\n",
- alias, addr, dt_addr);
+ printf("Warning: U-Boot configured device %s at address %"
+ PRIx64 ",\n but the device tree has it address %"
+ PRIx64 ".\n", alias, addr, dt_addr);
return 0;
}
diff --git a/common/image-fdt.c b/common/image-fdt.c
index 1d76bd6..e3f06cd 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -237,6 +237,7 @@
int fdt_noffset;
#endif
const char *select = NULL;
+ int ok_no_fdt = 0;
*of_flat_tree = NULL;
*of_size = 0;
@@ -309,7 +310,7 @@
fdt_addr);
fdt_hdr = image_get_fdt(fdt_addr);
if (!fdt_hdr)
- goto error;
+ goto no_fdt;
/*
* move image data to the load address,
@@ -379,7 +380,7 @@
break;
default:
puts("ERROR: Did not find a cmdline Flattened Device Tree\n");
- goto error;
+ goto no_fdt;
}
printf(" Booting using the fdt blob at %#08lx\n", fdt_addr);
@@ -413,11 +414,11 @@
}
} else {
debug("## No Flattened Device Tree\n");
- goto error;
+ goto no_fdt;
}
} else {
debug("## No Flattened Device Tree\n");
- goto error;
+ goto no_fdt;
}
*of_flat_tree = fdt_blob;
@@ -427,9 +428,15 @@
return 0;
+no_fdt:
+ ok_no_fdt = 1;
error:
*of_flat_tree = NULL;
*of_size = 0;
+ if (!select && ok_no_fdt) {
+ debug("Continuing to boot without FDT\n");
+ return 0;
+ }
return 1;
}
diff --git a/common/lcd.c b/common/lcd.c
index 28b3fe7..3ed504d 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -530,7 +530,7 @@
lcd_ctrl_init(lcdbase);
/*
- * lcd_ctrl_init() of some drivers (i.e. bcm2835 on rpi_b) ignores
+ * lcd_ctrl_init() of some drivers (i.e. bcm2835 on rpi) ignores
* the 'lcdbase' argument and uses custom lcd base address
* by setting up gd->fb_base. Check for this condition and fixup
* 'lcd_base' address.
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index ee71f79..7bae16b 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -15,7 +15,7 @@
DECLARE_GLOBAL_DATA_PTR;
-static int mmc_load_image_raw(struct mmc *mmc, unsigned long sector)
+static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
{
unsigned long err;
u32 image_size_sectors;
@@ -51,6 +51,22 @@
return (err == 0);
}
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+static int mmc_load_image_raw_partition(struct mmc *mmc, int partition)
+{
+ disk_partition_t info;
+
+ if (get_partition_info(&mmc->block_dev, partition, &info)) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ printf("spl: partition error\n");
+#endif
+ return -1;
+ }
+
+ return mmc_load_image_raw_sector(mmc, info.start);
+}
+#endif
+
#ifdef CONFIG_SPL_OS_BOOT
static int mmc_load_image_raw_os(struct mmc *mmc)
{
@@ -64,7 +80,8 @@
return -1;
}
- return mmc_load_image_raw(mmc, CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR);
+ return mmc_load_image_raw_sector(mmc,
+ CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR);
}
#endif
@@ -98,18 +115,24 @@
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || mmc_load_image_raw_os(mmc))
#endif
- err = mmc_load_image_raw(mmc,
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+ err = mmc_load_image_raw_partition(mmc,
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
+#else
+ err = mmc_load_image_raw_sector(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
+#endif
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
- } else if (boot_mode == MMCSD_MODE_FS) {
+ }
+ if (err || boot_mode == MMCSD_MODE_FS) {
debug("boot mode - FS\n");
#ifdef CONFIG_SPL_FAT_SUPPORT
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || spl_load_image_fat_os(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION))
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION))
#endif
err = spl_load_image_fat(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION,
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
if(err)
#endif /* CONFIG_SPL_FAT_SUPPORT */
@@ -117,10 +140,10 @@
#ifdef CONFIG_SPL_EXT_SUPPORT
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || spl_load_image_ext_os(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION))
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION))
#endif
err = spl_load_image_ext(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION,
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
#endif /* CONFIG_SPL_EXT_SUPPORT */
}
@@ -146,7 +169,7 @@
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || mmc_load_image_raw_os(mmc))
#endif
- err = mmc_load_image_raw(mmc,
+ err = mmc_load_image_raw_sector(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
#endif
} else {
diff --git a/common/usb.c b/common/usb.c
index 7d33a0f..736cd9f 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -33,7 +33,6 @@
#include <linux/ctype.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
-#include <compiler.h>
#include <errno.h>
#include <usb.h>
#ifdef CONFIG_4xx
diff --git a/configs/beagle_x15_defconfig b/configs/beagle_x15_defconfig
new file mode 100644
index 0000000..872ab63
--- /dev/null
+++ b/configs/beagle_x15_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3"
++S:CONFIG_ARM=y
++S:CONFIG_OMAP54XX=y
++S:CONFIG_TARGET_BEAGLE_X15=y
diff --git a/configs/hermes_defconfig b/configs/hermes_defconfig
deleted file mode 100644
index a923a61..0000000
--- a/configs/hermes_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_HERMES=y
diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig
index f54b15f..3155340 100644
--- a/configs/ph1_ld4_defconfig
+++ b/configs/ph1_ld4_defconfig
@@ -1,7 +1,34 @@
CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_LD4=y
++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_EDITENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig
index e795752..7ea4e6e 100644
--- a/configs/ph1_pro4_defconfig
+++ b/configs/ph1_pro4_defconfig
@@ -1,7 +1,34 @@
CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_PRO4=y
++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_EDITENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig
index 6510937..ddf210c 100644
--- a/configs/ph1_sld8_defconfig
+++ b/configs/ph1_sld8_defconfig
@@ -1,7 +1,34 @@
CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_SLD8=y
++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_EDITENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
diff --git a/configs/rpi_b_defconfig b/configs/rpi_b_defconfig
deleted file mode 100644
index 9a4705e..0000000
--- a/configs/rpi_b_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_RPI_B=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
new file mode 100644
index 0000000..9379cf0
--- /dev/null
+++ b/configs/rpi_defconfig
@@ -0,0 +1,2 @@
+CONFIG_ARM=y
+CONFIG_TARGET_RPI=y
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 612f092..efed58f 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -14,6 +14,7 @@
#include <common.h>
#include <command.h>
#include <ide.h>
+#include <inttypes.h>
#include <malloc.h>
#include <part_efi.h>
#include <linux/ctype.h>
@@ -553,28 +554,28 @@
/* Check that the my_lba entry points to the LBA that contains the GPT */
if (le64_to_cpu(pgpt_head->my_lba) != lba) {
- printf("GPT: my_lba incorrect: %llX != %llX\n",
- le64_to_cpu(pgpt_head->my_lba),
- lba);
+ printf("GPT: my_lba incorrect: %llX != %" PRIX64 "\n",
+ le64_to_cpu(pgpt_head->my_lba),
+ lba);
return 0;
}
/* Check the first_usable_lba and last_usable_lba are within the disk. */
lastlba = (u64)dev_desc->lba;
if (le64_to_cpu(pgpt_head->first_usable_lba) > lastlba) {
- printf("GPT: first_usable_lba incorrect: %llX > %llX\n",
- le64_to_cpu(pgpt_head->first_usable_lba), lastlba);
+ printf("GPT: first_usable_lba incorrect: %llX > %" PRIX64 "\n",
+ le64_to_cpu(pgpt_head->first_usable_lba), lastlba);
return 0;
}
if (le64_to_cpu(pgpt_head->last_usable_lba) > lastlba) {
- printf("GPT: last_usable_lba incorrect: %llX > %llX\n",
- le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
+ printf("GPT: last_usable_lba incorrect: %llX > %" PRIX64 "\n",
+ le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
return 0;
}
- debug("GPT: first_usable_lba: %llX last_usable_lba %llX last lba %llX\n",
- le64_to_cpu(pgpt_head->first_usable_lba),
- le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
+ debug("GPT: first_usable_lba: %llX last_usable_lba %llX last lba %"
+ PRIX64 "\n", le64_to_cpu(pgpt_head->first_usable_lba),
+ le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
/* Read and allocate Partition Table Entries */
*pgpt_pte = alloc_read_gpt_entries(dev_desc, pgpt_head);
diff --git a/doc/README.clang b/doc/README.clang
index 52495d3..fe36909 100644
--- a/doc/README.clang
+++ b/doc/README.clang
@@ -28,7 +28,7 @@
To compile U-Boot with clang on linux without IAS use e.g.:
export TRIPLET=arm-linux-gnueabi && export CROSS_COMPILE="$TRIPLET-"
-make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" rpi_b_defconfig
+make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" rpi_defconfig
make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" all V=1 -j8
FreeBSD 11 (Current):
@@ -42,7 +42,7 @@
# The following commands compile U-Boot using the clang xdev toolchain.
# NOTE: CROSS_COMPILE and target differ on purpose!
export CROSS_COMPILE=arm-gnueabi-freebsd-
-gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" rpi_b_defconfig
+gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" rpi_defconfig
gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" -j8
Given that u-boot will default to gcc, above commands can be
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 8ba6e0a..deb4af4 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,8 +12,9 @@
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-PRS200 powerpc mpc5200 - -
-MCC200 powerpc mpc5200 - -
+hermes powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
+PRS200 powerpc mpc5200 ecfdcee 2014-11-12
+MCC200 powerpc mpc5200 ecfdcee 2014-11-12
TOP5200 powerpc mpc5200 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TOP860 powerpc mpc860 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TOP9000 arm at91sam9xeXXX d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
diff --git a/doc/device-tree-bindings/ata/intel-sata.txt b/doc/device-tree-bindings/ata/intel-sata.txt
new file mode 100644
index 0000000..5e4da83
--- /dev/null
+++ b/doc/device-tree-bindings/ata/intel-sata.txt
@@ -0,0 +1,26 @@
+Intel Pantherpoint SATA Device Binding
+======================================
+
+The device tree node which describes the operation of the Intel Pantherpoint
+SATA device is as follows:
+
+Required properties :
+- compatible = "intel,pantherpoint-ahci"
+- intel,sata-mode : string, one of:
+ "ahci" : Use AHCI mode (default)
+ "combined" : Use combined IDE + legacy mode
+ "plain-ide" : Use plain IDE mode
+- intel,sata-port-map : Which SATA ports are enabled, bit 0=enable first port,
+ bit 1=enable second port, etc.
+- intel,sata-port0-gen3-tx : Value for the IOBP_SP0G3IR register
+- intel,sata-port1-gen3-tx : Value for the IOBP_SP1G3IR register
+
+Example
+-------
+
+sata {
+ compatible = "intel,pantherpoint-ahci";
+ intel,sata-mode = "ahci";
+ intel,sata-port-map = <1>;
+ intel,sata-port0-gen3-tx = <0x00880a7f>;
+};
diff --git a/doc/device-tree-bindings/misc/intel-lpc.txt b/doc/device-tree-bindings/misc/intel-lpc.txt
index 7e1b389..ba6ca9d 100644
--- a/doc/device-tree-bindings/misc/intel-lpc.txt
+++ b/doc/device-tree-bindings/misc/intel-lpc.txt
@@ -6,10 +6,37 @@
Required properties :
- compatible = "intel,lpc"
-- gen-dec : Specifies the values for the gen-dec registers. Up to four cell
- pairs can be provided - the first of each pair is the base address and
+- intel,alt-gp-smi-enable : Enable SMI sources. This cell is written to the
+ ALT_GP_SMI_EN register
+- intel,gen-dec : Specifies the values for the gen-dec registers. Up to four
+ cell pairs can be provided - the first of each pair is the base address and
the second is the size. These are written into the GENx_DEC registers of
the LPC device
+- intel,gpi-routing : Specifies the GPI routing. There are 16 cells, valid
+ values are:
+ 0 No effect (default)
+ 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ 2 SCI (if corresponding GPIO_EN bit is also set)
+- intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H,
+ one cell for each.
+ 0x00 - 0000 = Reserved
+ 0x01 - 0001 = Reserved
+ 0x02 - 0010 = Reserved
+ 0x03 - 0011 = IRQ3
+ 0x04 - 0100 = IRQ4
+ 0x05 - 0101 = IRQ5
+ 0x06 - 0110 = IRQ6
+ 0x07 - 0111 = IRQ7
+ 0x08 - 1000 = Reserved
+ 0x09 - 1001 = IRQ9
+ 0x0A - 1010 = IRQ10
+ 0x0B - 1011 = IRQ11
+ 0x0C - 1100 = IRQ12
+ 0x0D - 1101 = Reserved
+ 0x0E - 1110 = IRQ14
+ 0x0F - 1111 = IRQ15
+ PIRQ[n]_ROUT[7] - PIRQ Routing Control
+ 0x80 - The PIRQ is not routed.
Example
@@ -19,5 +46,19 @@
compatible = "intel,lpc";
#address-cells = <1>;
#size-cells = <1>;
- gen-dec = <0x800 0xfc 0x900 0xfc>;
+ intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
+
+ intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
+ 0x80 0x80 0x80 0x80>;
+ /*
+ * GPI routing
+ * 0 No effect (default)
+ * 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is
+ * also set)
+ * 2 SCI (if corresponding GPIO_EN bit is also set)
+ */
+ intel,gpi-routing = <0 0 0 0 0 0 0 2
+ 1 0 0 0 0 0 0 0>;
+ /* Enable EC SMI source */
+ intel,alt-gp-smi-enable = <0x0100>;
};
diff --git a/doc/device-tree-bindings/video/intel-gma.txt b/doc/device-tree-bindings/video/intel-gma.txt
new file mode 100644
index 0000000..914be4f
--- /dev/null
+++ b/doc/device-tree-bindings/video/intel-gma.txt
@@ -0,0 +1,40 @@
+Intel GMA Bindings
+==================
+
+This is the Intel Graphics Media Accelerator. This binding supports selection
+of display parameters only.
+
+
+Required properties:
+ - compatible : "intel,gma";
+
+Optional properties:
+ - intel,dp-hotplug : values for digital port hotplug, one cell per value for
+ ports B, C and D
+ - intel,panel-port-select : output port to use: 0=LVDS 1=DP_B 2=DP_C 3=DP_D
+ - intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms)
+
+ The following delays are in units of 0.1ms:
+ - intel,panel-power-up-delay : T1+T2 time sequence
+ - intel,panel-power-down-delay : T3 time sequence
+ - intel,panel-power-backlight-on-delay : T5 time sequence
+ - intel,panel-power-backlight-off-delay : Tx time sequence
+
+ - intel,cpu-backlight : Value for CPU Backlight PWM
+ - intel,pch-backlight : Value for PCH Backlight PWM
+
+Example
+-------
+
+gma {
+ compatible = "intel,gma";
+ intel,dp_hotplug = <0 0 0x06>;
+ intel,panel-port-select = <1>;
+ intel,panel-power-cycle-delay = <6>;
+ intel,panel-power-up-delay = <2000>;
+ intel,panel-power-down-delay = <500>;
+ intel,panel-power-backlight-on-delay = <2000>;
+ intel,panel-power-backlight-off-delay = <2000>;
+ intel,cpu-backlight = <0x00000200>;
+ intel,pch-backlight = <0x04000000>;
+};
diff --git a/doc/git-mailrc b/doc/git-mailrc
index ad22763..6c79a6d 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -14,6 +14,9 @@
alias abiessmann Andreas Bießmann <andreas.devel@googlemail.com>
alias afleming Andy Fleming <afleming@gmail.com>
alias ag Anatolij Gustschin <agust@denx.de>
+alias alisonwang Alison Wang <alison.wang@freescale.com>
+alias angelo_ts Angelo Dureghello <angelo@sysam.it>
+alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
alias galak Kumar Gala <galak@kernel.crashing.org>
alias gruss Graeme Russ <graeme.russ@gmail.com>
alias hs Heiko Schocher <hs@denx.de>
@@ -72,13 +75,13 @@
alias bfin uboot, vapier, sonic
alias blackfin bfin
-alias m68k uboot, jasonjin
+alias m68k uboot, alisonwang, angelo_ts
alias coldfire m68k
alias microblaze uboot, monstr
alias mb microblaze
-alias mips uboot, Shinya Kuribayashi <skuribay@pobox.com>
+alias mips uboot, danielschwierzeck
alias nds32 uboot, macpaul
@@ -119,6 +122,7 @@
alias nand uboot, scottwood
alias net uboot, jhersh
alias spi uboot, jagan
+alias ubi uboot, hs
alias usb uboot, marex
alias video uboot, ag
alias patman uboot, sjg
diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile
index e56356e..2ba43ac 100644
--- a/drivers/bios_emulator/Makefile
+++ b/drivers/bios_emulator/Makefile
@@ -9,4 +9,4 @@
$(X86DIR)/debug.o
ccflags-y := -I$(srctree)/$(src) -I$(srctree)/$(src)/include \
- -D__PPC__ -D__BIG_ENDIAN__
+ $(if $(CONFIG_PPC),-D__PPC__ -D__BIG_ENDIAN__)
diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c
index 3b2ed6e..93b815c 100644
--- a/drivers/bios_emulator/atibios.c
+++ b/drivers/bios_emulator/atibios.c
@@ -46,8 +46,11 @@
* BIOS in u-boot.
****************************************************************************/
#include <common.h>
-#include "biosemui.h"
+#include <bios_emul.h>
+#include <errno.h>
#include <malloc.h>
+#include <vbe.h>
+#include "biosemui.h"
/* Length of the BIOS image */
#define MAX_BIOSLEN (128 * 1024L)
@@ -59,17 +62,54 @@
static u32 saveBaseAddress18;
static u32 saveBaseAddress20;
+static void atibios_set_vesa_mode(RMREGS *regs, int vesa_mode,
+ struct vbe_mode_info *mode_info)
+{
+ debug("VBE: Setting VESA mode %#04x\n", vesa_mode);
+ /* request linear framebuffer mode */
+ vesa_mode |= (1 << 14);
+ /* request clearing of framebuffer */
+ vesa_mode &= ~(1 << 15);
+ regs->e.eax = VESA_SET_MODE;
+ regs->e.ebx = vesa_mode;
+ BE_int86(0x10, regs, regs);
+
+ int offset = 0x2000;
+ void *buffer = (void *)(M.mem_base + offset);
+
+ u16 buffer_seg = (((unsigned long)offset) >> 4) & 0xff00;
+ u16 buffer_adr = ((unsigned long)offset) & 0xffff;
+ regs->e.eax = VESA_GET_MODE_INFO;
+ regs->e.ebx = 0;
+ regs->e.ecx = vesa_mode;
+ regs->e.edx = 0;
+ regs->e.esi = buffer_seg;
+ regs->e.edi = buffer_adr;
+ BE_int86(0x10, regs, regs);
+ memcpy(mode_info->mode_info_block, buffer,
+ sizeof(struct vbe_mode_info));
+ mode_info->valid = true;
+
+ vesa_mode |= (1 << 14);
+ /* request clearing of framebuffer */
+ vesa_mode &= ~(1 << 15);
+ regs->e.eax = VESA_SET_MODE;
+ regs->e.ebx = vesa_mode;
+ BE_int86(0x10, regs, regs);
+}
+
/****************************************************************************
PARAMETERS:
pcidev - PCI device info for the video card on the bus to boot
-VGAInfo - BIOS emulator VGA info structure
+vga_info - BIOS emulator VGA info structure
REMARKS:
This function executes the BIOS POST code on the controller. We assume that
at this stage the controller has its I/O and memory space enabled and
that all other controllers are in a disabled state.
****************************************************************************/
-static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo * VGAInfo)
+static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info,
+ int vesa_mode, struct vbe_mode_info *mode_info)
{
RMREGS regs;
RMSREGS sregs;
@@ -84,13 +124,16 @@
((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev);
/*Setup the X86 emulator for the VGA BIOS*/
- BE_setVGA(VGAInfo);
+ BE_setVGA(vga_info);
/*Execute the BIOS POST code*/
BE_callRealMode(0xC000, 0x0003, ®s, &sregs);
/*Cleanup and exit*/
- BE_getVGA(VGAInfo);
+ BE_getVGA(vga_info);
+
+ if (vesa_mode != -1)
+ atibios_set_vesa_mode(®s, vesa_mode, mode_info);
}
/****************************************************************************
@@ -244,49 +287,109 @@
Loads and POST's the display controllers BIOS, directly from the BIOS
image we can extract over the PCI bus.
****************************************************************************/
-static int PCI_postController(pci_dev_t pcidev, BE_VGAInfo * VGAInfo)
+static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
+ BE_VGAInfo *vga_info, int vesa_mode,
+ struct vbe_mode_info *mode_info)
{
- u32 BIOSImageLen;
- uchar *mappedBIOS;
- uchar *copyOfBIOS;
+ u32 bios_image_len;
+ uchar *mapped_bios;
+ uchar *copy_of_bios;
- /*Allocate memory to store copy of BIOS from display controller*/
- if ((mappedBIOS = PCI_mapBIOSImage(pcidev)) == NULL) {
- printf("videoboot: Video ROM failed to map!\n");
- return false;
+ if (bios_rom) {
+ copy_of_bios = bios_rom;
+ bios_image_len = bios_len;
+ } else {
+ /*
+ * Allocate memory to store copy of BIOS from display
+ * controller
+ */
+ mapped_bios = PCI_mapBIOSImage(pcidev);
+ if (mapped_bios == NULL) {
+ printf("videoboot: Video ROM failed to map!\n");
+ return false;
+ }
+
+ bios_image_len = mapped_bios[2] * 512;
+
+ copy_of_bios = malloc(bios_image_len);
+ if (copy_of_bios == NULL) {
+ printf("videoboot: Out of memory!\n");
+ return false;
+ }
+ memcpy(copy_of_bios, mapped_bios, bios_image_len);
+ PCI_unmapBIOSImage(pcidev, mapped_bios);
}
- BIOSImageLen = mappedBIOS[2] * 512;
-
- if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL) {
- printf("videoboot: Out of memory!\n");
- return false;
- }
- memcpy(copyOfBIOS, mappedBIOS, BIOSImageLen);
-
- PCI_unmapBIOSImage(pcidev, mappedBIOS);
-
- /*Save information in VGAInfo structure*/
- VGAInfo->function = PCI_FUNC(pcidev);
- VGAInfo->device = PCI_DEV(pcidev);
- VGAInfo->bus = PCI_BUS(pcidev);
- VGAInfo->pcidev = pcidev;
- VGAInfo->BIOSImage = copyOfBIOS;
- VGAInfo->BIOSImageLen = BIOSImageLen;
+ /*Save information in vga_info structure*/
+ vga_info->function = PCI_FUNC(pcidev);
+ vga_info->device = PCI_DEV(pcidev);
+ vga_info->bus = PCI_BUS(pcidev);
+ vga_info->pcidev = pcidev;
+ vga_info->BIOSImage = copy_of_bios;
+ vga_info->BIOSImageLen = bios_image_len;
/*Now execute the BIOS POST for the device*/
- if (copyOfBIOS[0] != 0x55 || copyOfBIOS[1] != 0xAA) {
+ if (copy_of_bios[0] != 0x55 || copy_of_bios[1] != 0xAA) {
printf("videoboot: Video ROM image is invalid!\n");
return false;
}
- PCI_doBIOSPOST(pcidev, VGAInfo);
+ PCI_doBIOSPOST(pcidev, vga_info, vesa_mode, mode_info);
/*Reset the size of the BIOS image to the final size*/
- VGAInfo->BIOSImageLen = copyOfBIOS[2] * 512;
+ vga_info->BIOSImageLen = copy_of_bios[2] * 512;
return true;
}
+int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **vga_infop)
+{
+ BE_VGAInfo *VGAInfo;
+
+ printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n",
+ PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev));
+
+ /*Initialise the x86 BIOS emulator*/
+ if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) {
+ printf("videoboot: Out of memory!\n");
+ return -ENOMEM;
+ }
+ memset(VGAInfo, 0, sizeof(*VGAInfo));
+ BE_init(0, 65536, VGAInfo, 0);
+ *vga_infop = VGAInfo;
+
+ return 0;
+}
+
+void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void))
+{
+ X86EMU_setupIntrFunc(intnum, (X86EMU_intrFuncs)int_func);
+}
+
+int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
+ BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
+ struct vbe_mode_info *mode_info)
+{
+ /*Post all the display controller BIOS'es*/
+ if (!PCI_postController(pcidev, bios_rom, bios_len, vga_info,
+ vesa_mode, mode_info))
+ return -EINVAL;
+
+ /*
+ * Cleanup and exit the emulator if requested. If the BIOS emulator
+ * is needed after booting the card, we will not call BE_exit and
+ * leave it enabled for further use (ie: VESA driver etc).
+ */
+ if (clean_up) {
+ BE_exit();
+ if (vga_info->BIOSImage)
+ free(vga_info->BIOSImage);
+ free(vga_info);
+ vga_info = NULL;
+ }
+
+ return 0;
+}
+
/****************************************************************************
PARAMETERS:
pcidev - PCI device info for the video card on the bus to boot
@@ -297,38 +400,21 @@
Boots the PCI/AGP video card on the bus using the Video ROM BIOS image
and the X86 BIOS emulator module.
****************************************************************************/
-int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp)
+int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up)
{
BE_VGAInfo *VGAInfo;
+ int ret;
- printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n",
- PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev));
-
- /*Initialise the x86 BIOS emulator*/
- if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) {
- printf("videoboot: Out of memory!\n");
+ ret = biosemu_setup(pcidev, &VGAInfo);
+ if (ret)
return false;
- }
- memset(VGAInfo, 0, sizeof(*VGAInfo));
- BE_init(0, 65536, VGAInfo, 0);
-
- /*Post all the display controller BIOS'es*/
- if (!PCI_postController(pcidev, VGAInfo))
+ ret = biosemu_run(pcidev, NULL, 0, VGAInfo, clean_up, -1, NULL);
+ if (ret)
return false;
- /*Cleanup and exit the emulator if requested. If the BIOS emulator
- is needed after booting the card, we will not call BE_exit and
- leave it enabled for further use (ie: VESA driver etc).
- */
- if (cleanUp) {
- BE_exit();
- if (VGAInfo->BIOSImage)
- free(VGAInfo->BIOSImage);
- free(VGAInfo);
- VGAInfo = NULL;
- }
- /*Return VGA info pointer if the caller requested it*/
+ /* Return VGA info pointer if the caller requested it*/
if (pVGAInfo)
*pVGAInfo = VGAInfo;
+
return true;
}
diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c
index ad88a53..752a928 100644
--- a/drivers/bios_emulator/besys.c
+++ b/drivers/bios_emulator/besys.c
@@ -54,12 +54,20 @@
/*------------------------- Global Variables ------------------------------*/
-#ifndef __i386__
+#ifndef CONFIG_X86EMU_RAW_IO
static char *BE_biosDate = "08/14/99";
static u8 BE_model = 0xFC;
static u8 BE_submodel = 0x00;
#endif
+#undef DEBUG_IO_ACCESS
+
+#ifdef DEBUG_IO_ACCESS
+#define debug_io(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+#define debug_io(x, b...)
+#endif
+
/*----------------------------- Implementation ----------------------------*/
/****************************************************************************
@@ -80,38 +88,40 @@
if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) {
return (u8*)(_BE_env.biosmem_base + addr - 0xC0000);
} else if (addr > _BE_env.biosmem_limit && addr < 0xD0000) {
- DB(printf("BE_memaddr: address %#lx may be invalid!\n", addr);)
- return M.mem_base;
+ DB(printf("BE_memaddr: address %#lx may be invalid!\n",
+ (ulong)addr);)
+ return (u8 *)M.mem_base;
} else if (addr >= 0xA0000 && addr <= 0xBFFFF) {
return (u8*)(_BE_env.busmem_base + addr - 0xA0000);
}
-#ifdef __i386__
+#ifdef CONFIG_X86EMU_RAW_IO
else if (addr >= 0xD0000 && addr <= 0xFFFFF) {
/* We map the real System BIOS directly on real PC's */
- DB(printf("BE_memaddr: System BIOS address %#lx\n", addr);)
- return _BE_env.busmem_base + addr - 0xA0000;
+ DB(printf("BE_memaddr: System BIOS address %#lx\n",
+ (ulong)addr);)
+ return (u8 *)_BE_env.busmem_base + addr - 0xA0000;
}
#else
else if (addr >= 0xFFFF5 && addr < 0xFFFFE) {
/* Return a faked BIOS date string for non-x86 machines */
- DB(printf("BE_memaddr - Returning BIOS date\n");)
+ debug_io("BE_memaddr - Returning BIOS date\n");
return (u8 *)(BE_biosDate + addr - 0xFFFF5);
} else if (addr == 0xFFFFE) {
/* Return system model identifier for non-x86 machines */
- DB(printf("BE_memaddr - Returning model\n");)
+ debug_io("BE_memaddr - Returning model\n");
return &BE_model;
} else if (addr == 0xFFFFF) {
/* Return system submodel identifier for non-x86 machines */
- DB(printf("BE_memaddr - Returning submodel\n");)
+ debug_io("BE_memaddr - Returning submodel\n");
return &BE_submodel;
}
#endif
else if (addr > M.mem_size - 1) {
HALT_SYS();
- return M.mem_base;
+ return (u8 *)M.mem_base;
}
- return M.mem_base + addr;
+ return (u8 *)(M.mem_base + addr);
}
/****************************************************************************
@@ -230,7 +240,7 @@
}
}
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
/* For Non-Intel machines we may need to emulate some I/O port accesses that
* the BIOS may try to access, such as the PCI config registers.
@@ -258,6 +268,7 @@
{
u8 val = 0xff;
+ debug_io("vga_inb.%04X -> ", (u16) port);
switch (port) {
case 0x3C0:
/* 3C0 has funky characteristics because it can act as either
@@ -560,7 +571,7 @@
{
u8 val = 0;
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
if (IS_VGA_PORT(port)){
/*seems reading port 0x3c3 return the high 16 bit of io port*/
if(port == 0x3c3)
@@ -581,7 +592,12 @@
val = LOG_inpb(port);
} else
#endif
+ {
+ debug_io("inb.%04X -> ", (u16) port);
val = LOG_inpb(port);
+ debug_io("%02X\n", val);
+ }
+
return val;
}
@@ -601,7 +617,7 @@
{
u16 val = 0;
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
if (IS_PCI_PORT(port))
val = PCI_inp(port, REG_READ_WORD);
else if (port < 0x100) {
@@ -609,7 +625,12 @@
val = LOG_inpw(port);
} else
#endif
+ {
+ debug_io("inw.%04X -> ", (u16) port);
val = LOG_inpw(port);
+ debug_io("%04X\n", val);
+ }
+
return val;
}
@@ -629,14 +650,19 @@
{
u32 val = 0;
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
if (IS_PCI_PORT(port))
val = PCI_inp(port, REG_READ_DWORD);
else if (port < 0x100) {
val = LOG_inpd(port);
} else
#endif
+ {
+ debug_io("inl.%04X -> ", (u16) port);
val = LOG_inpd(port);
+ debug_io("%08X\n", val);
+ }
+
return val;
}
@@ -652,7 +678,7 @@
****************************************************************************/
void X86API BE_outb(X86EMU_pioAddr port, u8 val)
{
-#if defined(DEBUG) || !defined(__i386__)
+#if !defined(CONFIG_X86EMU_RAW_IO)
if (IS_VGA_PORT(port))
VGA_outpb(port, val);
else if (IS_TIMER_PORT(port))
@@ -668,7 +694,11 @@
LOG_outpb(port, val);
} else
#endif
+ {
+ debug_io("outb.%04X <- %02X", (u16) port, val);
LOG_outpb(port, val);
+ debug_io("\n");
+ }
}
/****************************************************************************
@@ -683,19 +713,23 @@
****************************************************************************/
void X86API BE_outw(X86EMU_pioAddr port, u16 val)
{
-#if defined(DEBUG) || !defined(__i386__)
- if (IS_VGA_PORT(port)) {
- VGA_outpb(port, val);
- VGA_outpb(port + 1, val >> 8);
- } else if (IS_PCI_PORT(port))
- PCI_outp(port, val, REG_WRITE_WORD);
- else if (port < 0x100) {
- DB(printf("WARN: MAybe INVALID outw.%04X <- %04X\n", (u16) port,
- val);)
- LOG_outpw(port, val);
- } else
+#if !defined(CONFIG_X86EMU_RAW_IO)
+ if (IS_VGA_PORT(port)) {
+ VGA_outpb(port, val);
+ VGA_outpb(port + 1, val >> 8);
+ } else if (IS_PCI_PORT(port)) {
+ PCI_outp(port, val, REG_WRITE_WORD);
+ } else if (port < 0x100) {
+ DB(printf("WARN: MAybe INVALID outw.%04X <- %04X\n", (u16)port,
+ val);)
+ LOG_outpw(port, val);
+ } else
#endif
- LOG_outpw(port, val);
+ {
+ debug_io("outw.%04X <- %04X", (u16) port, val);
+ LOG_outpw(port, val);
+ debug_io("\n");
+ }
}
/****************************************************************************
@@ -710,13 +744,17 @@
****************************************************************************/
void X86API BE_outl(X86EMU_pioAddr port, u32 val)
{
-#if defined(DEBUG) || !defined(__i386__)
- if (IS_PCI_PORT(port))
+#if !defined(CONFIG_X86EMU_RAW_IO)
+ if (IS_PCI_PORT(port)) {
PCI_outp(port, val, REG_WRITE_DWORD);
- else if (port < 0x100) {
+ } else if (port < 0x100) {
DB(printf("WARN: INVALID outl.%04X <- %08X\n", (u16) port,val);)
LOG_outpd(port, val);
} else
#endif
+ {
+ debug_io("outl.%04X <- %08X", (u16) port, val);
LOG_outpd(port, val);
+ debug_io("\n");
+ }
}
diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c
index bcc192f..152d70a 100644
--- a/drivers/bios_emulator/bios.c
+++ b/drivers/bios_emulator/bios.c
@@ -84,14 +84,14 @@
PM_outpb(0x3c2, PM_inpb(0x3cc) & (u8) ~ 0x02);
return;
}
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
else {
printf("int42: unknown function AH=0x12, BL=0x32, AL=%#02x\n",
M.x86.R_AL);
}
#endif
}
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
else {
printf("int42: unknown function AH=%#02x, AL=%#02x, BL=%#02x\n",
M.x86.R_AH, M.x86.R_AL, M.x86.R_BL);
diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h
index 8c1f111..7853015 100644
--- a/drivers/bios_emulator/biosemui.h
+++ b/drivers/bios_emulator/biosemui.h
@@ -48,7 +48,7 @@
#include <asm/io.h>
/*---------------------- Macros and type definitions ----------------------*/
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
#define DB(x) x
#else
#define DB(x) do{}while(0);
diff --git a/drivers/bios_emulator/include/biosemu.h b/drivers/bios_emulator/include/biosemu.h
index e92e96e..124d79d 100644
--- a/drivers/bios_emulator/include/biosemu.h
+++ b/drivers/bios_emulator/include/biosemu.h
@@ -43,6 +43,8 @@
#ifndef __BIOSEMU_H
#define __BIOSEMU_H
+#include <bios_emul.h>
+
#ifdef __KERNEL__
#include "x86emu.h"
#else
@@ -55,57 +57,6 @@
#pragma pack(1)
-#ifndef __KERNEL__
-/****************************************************************************
-REMARKS:
-Data structure used to describe the details specific to a particular VGA
-controller. This information is used to allow the VGA controller to be
-swapped on the fly within the BIOS emulator.
-
-HEADER:
-biosemu.h
-
-MEMBERS:
-pciInfo - PCI device information block for the controller
-BIOSImage - Pointer to a read/write copy of the BIOS image
-BIOSImageLen - Length of the BIOS image
-LowMem - Copy of key low memory areas
-****************************************************************************/
-typedef struct {
- PCIDeviceInfo *pciInfo;
- void *BIOSImage;
- ulong BIOSImageLen;
- uchar LowMem[1536];
-} BE_VGAInfo;
-#else
-/****************************************************************************
-REMARKS:
-Data structure used to describe the details for the BIOS emulator system
-environment as used by the X86 emulator library.
-
-HEADER:
-biosemu.h
-
-MEMBERS:
-vgaInfo - VGA BIOS information structure
-biosmem_base - Base of the BIOS image
-biosmem_limit - Limit of the BIOS image
-busmem_base - Base of the VGA bus memory
-****************************************************************************/
-typedef struct {
- int function;
- int device;
- int bus;
- u32 VendorID;
- u32 DeviceID;
- pci_dev_t pcidev;
- void *BIOSImage;
- u32 BIOSImageLen;
- u8 LowMem[1536];
-} BE_VGAInfo;
-
-#endif /* __KERNEL__ */
-
#define CRT_C 24 /* 24 CRT Controller Registers */
#define ATT_C 21 /* 21 Attribute Controller Registers */
#define GRA_C 9 /* 9 Graphics Controller Registers */
diff --git a/drivers/bios_emulator/include/x86emu.h b/drivers/bios_emulator/include/x86emu.h
index a70a768..b28cdc6 100644
--- a/drivers/bios_emulator/include/x86emu.h
+++ b/drivers/bios_emulator/include/x86emu.h
@@ -53,9 +53,9 @@
/*---------------------- Macros and type definitions ----------------------*/
-#if defined (CONFIG_ARM)
+#if defined(CONFIG_ARM)
#define GAS_LINE_COMMENT "@"
-#elif defined(CONFIG_MIPS) || defined(CONFIG_PPC)
+#elif defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_X86)
#define GAS_LINE_COMMENT "#"
#elif defined (CONFIG_SH)
#define GAS_LINE_COMMENT "!"
@@ -153,6 +153,7 @@
void X86EMU_setupMemFuncs(X86EMU_memFuncs * funcs);
void X86EMU_setupPioFuncs(X86EMU_pioFuncs * funcs);
void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]);
+ void X86EMU_setupIntrFunc(int intnum, X86EMU_intrFuncs func);
void X86EMU_prepareForInt(int num);
/* decode.c */
@@ -160,7 +161,7 @@
void X86EMU_exec(void);
void X86EMU_halt_sys(void);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
#define HALT_SYS() \
printf("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \
X86EMU_halt_sys()
diff --git a/drivers/bios_emulator/include/x86emu/debug.h b/drivers/bios_emulator/include/x86emu/debug.h
index 268c9d3..304b2bf 100644
--- a/drivers/bios_emulator/include/x86emu/debug.h
+++ b/drivers/bios_emulator/include/x86emu/debug.h
@@ -48,7 +48,7 @@
#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */
#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset */
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F)
# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F)
# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F)
@@ -60,7 +60,7 @@
# define CHECK_DATA_ACCESS()
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F)
# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F)
# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F)
@@ -99,7 +99,11 @@
# define DEBUG_DECODE_NOPRINT() 0
#endif
-#ifdef DEBUG
+# define ERR_PRINTF(x) printf(x)
+# define ERR_PRINTF2(x, y) printf(x, y)
+
+#ifdef CONFIG_X86EMU_DEBUG103
+
# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \
x86emu_decode_printf(x)
@@ -129,7 +133,7 @@
# define SAVE_IP_CS(x,y)
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
#define TRACE_REGS() \
if (DEBUG_DISASSEMBLE()) { \
x86emu_just_disassemble(); \
@@ -140,7 +144,7 @@
# define TRACE_REGS()
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step()
#else
# define SINGLE_STEP()
@@ -150,7 +154,7 @@
TRACE_REGS(); \
SINGLE_STEP()
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define START_OF_INSTR()
# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr();
# define END_OF_INSTR_NO_TRACE() x86emu_end_instr();
@@ -160,7 +164,7 @@
# define END_OF_INSTR_NO_TRACE()
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
# define CALL_TRACE(u,v,w,x,s) \
if (DEBUG_TRACECALLREGS()) \
x86emu_dump_regs(); \
@@ -176,7 +180,7 @@
# define RETURN_TRACE(n,u,v)
#endif
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
#define DB(x) x
#else
#define DB(x)
diff --git a/drivers/bios_emulator/include/x86emu/regs.h b/drivers/bios_emulator/include/x86emu/regs.h
index a7fedd2..2934129 100644
--- a/drivers/bios_emulator/include/x86emu/regs.h
+++ b/drivers/bios_emulator/include/x86emu/regs.h
@@ -282,7 +282,7 @@
u8 intno;
volatile int intr; /* mask of pending interrupts */
int debug;
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
int check;
u16 saved_ip;
u16 saved_cs;
diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c
index 2fa8050..27e90e4 100644
--- a/drivers/bios_emulator/x86emu/debug.c
+++ b/drivers/bios_emulator/x86emu/debug.c
@@ -44,7 +44,7 @@
/*----------------------------- Implementation ----------------------------*/
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
static void print_encoded_bytes(u16 s, u16 o);
static void print_decoded_instruction(void);
@@ -211,9 +211,7 @@
u32 start = off & 0xfffffff0;
u32 end = (off + 16) & 0xfffffff0;
u32 i;
- u32 current;
- current = start;
while (end <= off + amt) {
printk("%04x:%04x ", seg, start);
for (i = start; i < off; i++)
@@ -229,7 +227,7 @@
void x86emu_single_step(void)
{
char s[1024];
- int ps[10];
+ int ps[10];
int ntok;
int cmd;
int done;
@@ -238,8 +236,6 @@
static int breakpoint;
static int noDecode = 1;
- char *p;
-
if (DEBUG_BREAK()) {
if (M.x86.saved_ip != breakpoint) {
return;
@@ -255,6 +251,8 @@
offset = M.x86.saved_ip;
while (!done) {
printk("-");
+ ps[1] = 0; /* Avoid dodgy compiler warnings */
+ ps[2] = 0;
cmd = x86emu_parse_line(s, ps, &ntok);
switch (cmd) {
case 'u':
diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c
index a782b81..da44c3d 100644
--- a/drivers/bios_emulator/x86emu/decode.c
+++ b/drivers/bios_emulator/x86emu/decode.c
@@ -303,7 +303,7 @@
u8 fetch_data_byte(
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
@@ -322,7 +322,7 @@
u16 fetch_data_word(
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
@@ -341,7 +341,7 @@
u32 fetch_data_long(
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
@@ -362,7 +362,7 @@
uint segment,
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
@@ -383,7 +383,7 @@
uint segment,
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
@@ -404,7 +404,7 @@
uint segment,
uint offset)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
@@ -426,7 +426,7 @@
uint offset,
u8 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
@@ -448,7 +448,7 @@
uint offset,
u16 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
@@ -470,7 +470,7 @@
uint offset,
u32 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
@@ -493,7 +493,7 @@
uint offset,
u8 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
@@ -516,7 +516,7 @@
uint offset,
u16 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
@@ -539,7 +539,7 @@
uint offset,
u32 val)
{
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c
index f8e093d..2bb5e2d 100644
--- a/drivers/bios_emulator/x86emu/ops.c
+++ b/drivers/bios_emulator/x86emu/ops.c
@@ -79,7 +79,7 @@
/* constant arrays to do several instructions in just one function */
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
static char *x86emu_GenOpName[8] = {
"ADD", "OR", "ADC", "SBB", "AND", "SUB", "XOR", "CMP"};
#endif
@@ -160,7 +160,7 @@
sar_long,
};
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
static char *opF6_names[8] =
{ "TEST\t", "", "NOT\t", "NEG\t", "MUL\t", "IMUL\t", "DIV\t", "IDIV\t" };
@@ -179,7 +179,7 @@
{
START_OF_INSTR();
if (M.x86.R_SP != 0) {
- DECODE_PRINTF("ILLEGAL X86 OPCODE\n");
+ ERR_PRINTF("ILLEGAL X86 OPCODE\n");
TRACE_REGS();
DB( printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n",
M.x86.R_CS, M.x86.R_IP-1,op1));
@@ -1281,7 +1281,7 @@
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -1359,7 +1359,7 @@
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -1475,7 +1475,7 @@
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -1551,7 +1551,7 @@
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -2148,7 +2148,7 @@
DECODE_PRINTF("POP\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (rh != 0) {
- DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
+ ERR_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
HALT_SYS();
}
if (mod < 3) {
@@ -3083,7 +3083,7 @@
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -3158,7 +3158,7 @@
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -3347,7 +3347,7 @@
DECODE_PRINTF("MOV\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (rh != 0) {
- DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n");
+ ERR_PRINTF("ILLEGAL DECODE OF OPCODE c6\n");
HALT_SYS();
}
if (mod < 3) {
@@ -3381,7 +3381,7 @@
DECODE_PRINTF("MOV\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (rh != 0) {
- DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
+ ERR_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
HALT_SYS();
}
if (mod < 3) {
@@ -3630,7 +3630,7 @@
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -3701,7 +3701,7 @@
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -3803,7 +3803,7 @@
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -3876,7 +3876,7 @@
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -3968,7 +3968,7 @@
DECODE_PRINTF("AAM\n");
a = fetch_byte_imm(); /* this is a stupid encoding. */
if (a != 10) {
- DECODE_PRINTF("ERROR DECODING AAM\n");
+ ERR_PRINTF("ERROR DECODING AAM\n");
TRACE_REGS();
HALT_SYS();
}
@@ -4443,7 +4443,7 @@
test_byte(destval, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
@@ -4490,7 +4490,7 @@
test_byte(*destreg, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
@@ -4559,7 +4559,7 @@
test_long(destval, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
HALT_SYS();
break;
case 2:
@@ -4611,7 +4611,7 @@
test_word(destval, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
HALT_SYS();
break;
case 2:
@@ -4666,7 +4666,7 @@
test_long(*destreg, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
@@ -4715,7 +4715,7 @@
test_word(*destreg, srcval);
break;
case 1:
- DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+ ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
@@ -4859,7 +4859,7 @@
/* Yet another special case instruction. */
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -4879,7 +4879,7 @@
case 5:
case 6:
case 7:
- DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod);
+ ERR_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x\n", mod);
HALT_SYS();
break;
}
@@ -4923,7 +4923,7 @@
/* Yet another special case instruction. */
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
-#ifdef DEBUG
+#ifdef CONFIG_X86EMU_DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
@@ -4961,7 +4961,7 @@
DECODE_PRINTF("PUSH\t");
break;
case 7:
- DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t");
+ ERR_PRINTF("ILLEGAL DECODING OF OPCODE FF\t");
HALT_SYS();
break;
}
@@ -5092,7 +5092,7 @@
M.x86.R_IP = *destreg;
break;
case 3: /* jmp far ptr ... */
- DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
+ ERR_PRINTF("OPERATION UNDEFINED 0XFF\n");
TRACE_AND_STEP();
HALT_SYS();
break;
@@ -5104,7 +5104,7 @@
M.x86.R_IP = (u16) (*destreg);
break;
case 5: /* jmp far ptr ... */
- DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
+ ERR_PRINTF("OPERATION UNDEFINED 0XFF\n");
TRACE_AND_STEP();
HALT_SYS();
break;
diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c
index 59dbb42..be4ef36 100644
--- a/drivers/bios_emulator/x86emu/ops2.c
+++ b/drivers/bios_emulator/x86emu/ops2.c
@@ -58,7 +58,7 @@
u8 op2)
{
START_OF_INSTR();
- DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
+ ERR_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
TRACE_REGS();
printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n",
M.x86.R_CS, M.x86.R_IP-2,op2);
@@ -1089,7 +1089,7 @@
DECODE_PRINTF("BTC\t");
break;
default:
- DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
+ ERR_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
TRACE_REGS();
printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n",
M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl);
diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c
index 21f9730..0ba9c0c 100644
--- a/drivers/bios_emulator/x86emu/sys.c
+++ b/drivers/bios_emulator/x86emu/sys.c
@@ -273,6 +273,11 @@
sys_outl = funcs->outl;
}
+void X86EMU_setupIntrFunc(int intnum, X86EMU_intrFuncs func)
+{
+ _X86EMU_intrTab[intnum] = func;
+}
+
/****************************************************************************
PARAMETERS:
funcs - New interrupt vector table to make active
diff --git a/drivers/block/pata_bfin.h b/drivers/block/pata_bfin.h
index 2093cf0..b678f60 100644
--- a/drivers/block/pata_bfin.h
+++ b/drivers/block/pata_bfin.h
@@ -43,7 +43,6 @@
#define DRV_NAME "pata-bfin"
#define DRV_VERSION "0.9"
-#define __iomem
#define ATA_REG_CTRL 0x0E
#define ATA_REG_ALTSTATUS ATA_REG_CTRL
diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index d34b749..41cc3b8 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -174,11 +174,11 @@
return 0;
}
-static int i2c_mux_disconnet_all(void)
+static int i2c_mux_disconnect_all(void)
{
struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS];
int i;
- uint8_t buf;
+ uint8_t buf = 0;
if (I2C_ADAP->init_done == 0)
return 0;
@@ -197,7 +197,7 @@
ret = I2C_ADAP->write(I2C_ADAP, chip, 0, 0, &buf, 1);
if (ret != 0) {
- printf("i2c: mux diconnect error\n");
+ printf("i2c: mux disconnect error\n");
return ret;
}
} while (i > 0);
@@ -293,7 +293,7 @@
}
#ifndef CONFIG_SYS_I2C_DIRECT_BUS
- i2c_mux_disconnet_all();
+ i2c_mux_disconnect_all();
#endif
gd->cur_i2c_bus = bus;
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 44a4feb..8436bc7 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1277,6 +1277,11 @@
}
#endif
+/* board-specific MMC power initializations. */
+__weak void board_mmc_power_init(void)
+{
+}
+
int mmc_start_init(struct mmc *mmc)
{
int err;
@@ -1293,6 +1298,8 @@
if (mmc->has_init)
return 0;
+ board_mmc_power_init();
+
/* made sure it's not NULL earlier */
err = mmc->cfg->ops->init(mmc);
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index ffb5284..c880ced 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -135,12 +135,7 @@
pbias_lite = readl(&t2_base->pbias_lite);
pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
writel(pbias_lite, &t2_base->pbias_lite);
-#endif
-#if defined(CONFIG_TWL4030_POWER)
- twl4030_power_mmc_init();
- mdelay(100); /* ramp-up delay from Linux code */
-#endif
-#if defined(CONFIG_OMAP34XX)
+
writel(pbias_lite | PBIASLITEPWRDNZ1 |
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
&t2_base->pbias_lite);
@@ -663,7 +658,8 @@
case 1:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
- defined(CONFIG_DRA7XX)) && defined(CONFIG_HSMMC2_8BIT)
+ defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && \
+ defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
@@ -672,7 +668,7 @@
#ifdef OMAP_HSMMC3_BASE
case 2:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
-#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
+#if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
/* Enable 8-bit interface for eMMC on DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c
index ed83a14..76ba93b 100644
--- a/drivers/mmc/sh_mmcif.c
+++ b/drivers/mmc/sh_mmcif.c
@@ -103,20 +103,18 @@
static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
{
- int i;
-
sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
if (!clk)
return;
- if (clk == CLKDEV_EMMC_DATA) {
+
+ if (clk == CLKDEV_EMMC_DATA)
sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
- } else {
- for (i = 1; (unsigned int)host->clk / (1 << i) >= clk; i++)
- ;
- sh_mmcif_bitset((i - 1) << 16, &host->regs->ce_clk_ctrl);
- }
+ else
+ sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk,
+ clk) - 1) - 1) << 16,
+ &host->regs->ce_clk_ctrl);
sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
}
@@ -581,8 +579,6 @@
.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
MMC_MODE_8BIT | MMC_MODE_HC,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .f_min = CLKDEV_MMC_INIT,
- .f_max = CLKDEV_EMMC_DATA,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};
@@ -599,6 +595,9 @@
host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
host->clk = CONFIG_SH_MMCIF_CLK;
+ sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
+ sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
+
mmc = mmc_create(&sh_mmcif_cfg, host);
if (mmc == NULL) {
free(host);
diff --git a/drivers/mmc/sh_mmcif.h b/drivers/mmc/sh_mmcif.h
index bd6fbf7..4b6752f 100644
--- a/drivers/mmc/sh_mmcif.h
+++ b/drivers/mmc/sh_mmcif.h
@@ -199,7 +199,13 @@
#define SOFT_RST_OFF (0 << 31)
#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
-#define CLKDEV_MMC_INIT 400000 /* 100 - 400 KHz */
+#ifdef CONFIG_RMOBILE
+#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 9))
+#define MMC_CLK_DIV_MAX(clk) (clk / (1 << 1))
+#else
+#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 8))
+#define MMC_CLK_DIV_MAX(clk) CLKDEV_EMMC_DATA
+#endif
#define MMC_BUS_WIDTH_1 0
#define MMC_BUS_WIDTH_4 2
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 40d6705..93829a4 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -73,14 +73,11 @@
writeb(cmd, this->IO_ADDR_W);
}
-#ifdef CONFIG_SPL_BUILD
/* Check wait pin as dev ready indicator */
-static int omap_spl_dev_ready(struct mtd_info *mtd)
+static int omap_dev_ready(struct mtd_info *mtd)
{
return gpmc_cfg->status & (1 << 8);
}
-#endif
-
/*
* gen_true_ecc - This function will generate true ECC value, which
@@ -887,7 +884,9 @@
nand->read_buf = nand_read_buf16;
else
nand->read_buf = nand_read_buf;
- nand->dev_ready = omap_spl_dev_ready;
#endif
+
+ nand->dev_ready = omap_dev_ready;
+
return 0;
}
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index e73a4986..55d6a9b 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -6,7 +6,7 @@
#
obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
-obj-$(CONFIG_PCI) += pci.o pci_auto.o
+obj-$(CONFIG_PCI) += pci.o pci_auto.o pci_rom.o
obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 7ee21d1..3daf73c 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -366,9 +366,27 @@
return phys_addr;
}
-/*
- *
- */
+void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
+ u32 addr_and_ctrl)
+{
+ int bar;
+
+ bar = PCI_BASE_ADDRESS_0 + barnum * 4;
+ pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
+}
+
+u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
+{
+ u32 addr;
+ int bar;
+
+ bar = PCI_BASE_ADDRESS_0 + barnum * 4;
+ pci_hose_read_config_dword(hose, dev, bar, &addr);
+ if (addr & PCI_BASE_ADDRESS_SPACE_IO)
+ return addr & PCI_BASE_ADDRESS_IO_MASK;
+ else
+ return addr & PCI_BASE_ADDRESS_MEM_MASK;
+}
int pci_hose_config_device(struct pci_controller *hose,
pci_dev_t dev,
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
new file mode 100644
index 0000000..af6a3ae
--- /dev/null
+++ b/drivers/pci/pci_rom.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * From coreboot, originally based on the Linux kernel (drivers/pci/pci.c).
+ *
+ * Modifications are:
+ * Copyright (C) 2003-2004 Linux Networx
+ * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
+ * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
+ * Copyright (C) 2005-2006 Tyan
+ * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
+ * Copyright (C) 2005-2009 coresystems GmbH
+ * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
+ *
+ * PCI Bus Services, see include/linux/pci.h for further explanation.
+ *
+ * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
+ * David Mosberger-Tang
+ *
+ * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
+
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <bios_emul.h>
+#include <errno.h>
+#include <malloc.h>
+#include <pci.h>
+#include <pci_rom.h>
+#include <vbe.h>
+#include <video_fb.h>
+
+#ifdef CONFIG_HAVE_ACPI_RESUME
+#include <asm/acpi.h>
+#endif
+
+__weak bool board_should_run_oprom(pci_dev_t dev)
+{
+ return true;
+}
+
+static bool should_load_oprom(pci_dev_t dev)
+{
+#ifdef CONFIG_HAVE_ACPI_RESUME
+ if (acpi_get_slp_type() == 3)
+ return false;
+#endif
+ if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM))
+ return 1;
+ if (board_should_run_oprom(dev))
+ return 1;
+
+ return 0;
+}
+
+__weak uint32_t board_map_oprom_vendev(uint32_t vendev)
+{
+ return vendev;
+}
+
+static int pci_rom_probe(pci_dev_t dev, uint class,
+ struct pci_rom_header **hdrp)
+{
+ struct pci_rom_header *rom_header;
+ struct pci_rom_data *rom_data;
+ u16 vendor, device;
+ u32 vendev;
+ u32 mapped_vendev;
+ u32 rom_address;
+
+ pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
+ pci_read_config_word(dev, PCI_DEVICE_ID, &device);
+ vendev = vendor << 16 | device;
+ mapped_vendev = board_map_oprom_vendev(vendev);
+ if (vendev != mapped_vendev)
+ debug("Device ID mapped to %#08x\n", mapped_vendev);
+
+#ifdef CONFIG_X86_OPTION_ROM_ADDR
+ rom_address = CONFIG_X86_OPTION_ROM_ADDR;
+#else
+ pci_write_config_dword(dev, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK);
+ pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address);
+ if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
+ debug("%s: rom_address=%x\n", __func__, rom_address);
+ return -ENOENT;
+ }
+
+ /* Enable expansion ROM address decoding. */
+ pci_write_config_dword(dev, PCI_ROM_ADDRESS,
+ rom_address | PCI_ROM_ADDRESS_ENABLE);
+#endif
+ debug("Option ROM address %x\n", rom_address);
+ rom_header = (struct pci_rom_header *)rom_address;
+
+ debug("PCI expansion ROM, signature %#04x, INIT size %#04x, data ptr %#04x\n",
+ le32_to_cpu(rom_header->signature),
+ rom_header->size * 512, le32_to_cpu(rom_header->data));
+
+ if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
+ printf("Incorrect expansion ROM header signature %04x\n",
+ le32_to_cpu(rom_header->signature));
+ return -EINVAL;
+ }
+
+ rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data));
+
+ debug("PCI ROM image, vendor ID %04x, device ID %04x,\n",
+ rom_data->vendor, rom_data->device);
+
+ /* If the device id is mapped, a mismatch is expected */
+ if ((vendor != rom_data->vendor || device != rom_data->device) &&
+ (vendev == mapped_vendev)) {
+ printf("ID mismatch: vendor ID %04x, device ID %04x\n",
+ rom_data->vendor, rom_data->device);
+ return -EPERM;
+ }
+
+ debug("PCI ROM image, Class Code %04x%02x, Code Type %02x\n",
+ rom_data->class_hi, rom_data->class_lo, rom_data->type);
+
+ if (class != ((rom_data->class_hi << 8) | rom_data->class_lo)) {
+ debug("Class Code mismatch ROM %08x, dev %08x\n",
+ (rom_data->class_hi << 8) | rom_data->class_lo,
+ class);
+ }
+ *hdrp = rom_header;
+
+ return 0;
+}
+
+int pci_rom_load(uint16_t class, struct pci_rom_header *rom_header,
+ struct pci_rom_header **ram_headerp)
+{
+ struct pci_rom_data *rom_data;
+ unsigned int rom_size;
+ unsigned int image_size = 0;
+ void *target;
+
+ do {
+ /* Get next image, until we see an x86 version */
+ rom_header = (struct pci_rom_header *)((void *)rom_header +
+ image_size);
+
+ rom_data = (struct pci_rom_data *)((void *)rom_header +
+ le32_to_cpu(rom_header->data));
+
+ image_size = le32_to_cpu(rom_data->ilen) * 512;
+ } while ((rom_data->type != 0) && (rom_data->indicator != 0));
+
+ if (rom_data->type != 0)
+ return -EACCES;
+
+ rom_size = rom_header->size * 512;
+
+ target = (void *)PCI_VGA_RAM_IMAGE_START;
+ if (target != rom_header) {
+ debug("Copying VGA ROM Image from %p to %p, 0x%x bytes\n",
+ rom_header, target, rom_size);
+ memcpy(target, rom_header, rom_size);
+ if (memcmp(target, rom_header, rom_size)) {
+ printf("VGA ROM copy failed\n");
+ return -EFAULT;
+ }
+ }
+ *ram_headerp = target;
+
+ return 0;
+}
+
+static struct vbe_mode_info mode_info;
+
+int vbe_get_video_info(struct graphic_device *gdev)
+{
+#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE
+ struct vesa_mode_info *vesa = &mode_info.vesa;
+
+ gdev->winSizeX = vesa->x_resolution;
+ gdev->winSizeY = vesa->y_resolution;
+
+ gdev->plnSizeX = vesa->x_resolution;
+ gdev->plnSizeY = vesa->y_resolution;
+
+ gdev->gdfBytesPP = vesa->bits_per_pixel / 8;
+
+ switch (vesa->bits_per_pixel) {
+ case 24:
+ gdev->gdfIndex = GDF_32BIT_X888RGB;
+ break;
+ case 16:
+ gdev->gdfIndex = GDF_16BIT_565RGB;
+ break;
+ default:
+ gdev->gdfIndex = GDF__8BIT_INDEX;
+ break;
+ }
+
+ gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
+ gdev->pciBase = vesa->phys_base_ptr;
+
+ gdev->frameAdrs = vesa->phys_base_ptr;
+ gdev->memSize = vesa->bytes_per_scanline * vesa->y_resolution;
+
+ gdev->vprBase = vesa->phys_base_ptr;
+ gdev->cprBase = vesa->phys_base_ptr;
+
+ return 0;
+#else
+ return -ENOSYS;
+#endif
+}
+
+int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate)
+{
+ struct pci_rom_header *rom, *ram;
+ int vesa_mode = -1;
+ uint16_t class;
+ int ret;
+
+ /* Only execute VGA ROMs */
+ pci_read_config_word(dev, PCI_CLASS_DEVICE, &class);
+ if ((class ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
+ debug("%s: Class %#x, should be %#x\n", __func__, class,
+ PCI_CLASS_DISPLAY_VGA);
+ return -ENODEV;
+ }
+
+ if (!should_load_oprom(dev))
+ return -ENXIO;
+
+ ret = pci_rom_probe(dev, class, &rom);
+ if (ret)
+ return ret;
+
+ ret = pci_rom_load(class, rom, &ram);
+ if (ret)
+ return ret;
+
+ if (!board_should_run_oprom(dev))
+ return -ENXIO;
+
+#if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \
+ defined(CONFIG_FRAMEBUFFER_VESA_MODE)
+ vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
+#endif
+ debug("Selected vesa mode %d\b", vesa_mode);
+ if (emulate) {
+#ifdef CONFIG_BIOSEMU
+ BE_VGAInfo *info;
+
+ ret = biosemu_setup(dev, &info);
+ if (ret)
+ return ret;
+ biosemu_set_interrupt_handler(0x15, int15_handler);
+ ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, true,
+ vesa_mode, &mode_info);
+ if (ret)
+ return ret;
+#else
+ printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
+ return -ENOSYS;
+#endif
+ } else {
+#ifdef CONFIG_X86
+ bios_set_interrupt_handler(0x15, int15_handler);
+
+ bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
+ &mode_info);
+#else
+ printf("BIOS native execution is only available on x86\n");
+ return -ENOSYS;
+#endif
+ }
+ debug("Final vesa mode %d\n", mode_info.video_mode);
+
+ return 0;
+}
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c
index cfbc9dc..6430fe0 100644
--- a/drivers/power/palmas.c
+++ b/drivers/power/palmas.c
@@ -27,7 +27,7 @@
{
u8 val = 0;
-#if defined(CONFIG_DRA7XX)
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
/*
* Currently valid for the dra7xx_evm board:
* Set TPS659038 LDO1 to 3.0 V
diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c
index 594cd11..0dcf9fe 100644
--- a/drivers/power/power_i2c.c
+++ b/drivers/power/power_i2c.c
@@ -14,7 +14,7 @@
#include <linux/types.h>
#include <power/pmic.h>
#include <i2c.h>
-#include <compiler.h>
+#include <linux/compiler.h>
int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
{
diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c
index e578ae6..7f1fdd1 100644
--- a/drivers/power/twl4030.c
+++ b/drivers/power/twl4030.c
@@ -91,17 +91,23 @@
TWL4030_PM_RECEIVER_DEV_GRP_P1);
}
-void twl4030_power_mmc_init(void)
+void twl4030_power_mmc_init(int dev_index)
{
- /* Set VMMC1 to 3.15 Volts */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
- TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
- TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ if (dev_index == 0) {
+ /* Set VMMC1 to 3.15 Volts */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
+ TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
+ TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
- /* Set VMMC2 to 3.15 Volts */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
- TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
- TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ mdelay(100); /* ramp-up delay from Linux code */
+ } else if (dev_index == 1) {
+ /* Set VMMC2 to 3.15 Volts */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
+ TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
+ TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+ mdelay(100); /* ramp-up delay from Linux code */
+ }
}
diff --git a/drivers/rtc/bfin_rtc.c b/drivers/rtc/bfin_rtc.c
index 21a2189..4cf2d83 100644
--- a/drivers/rtc/bfin_rtc.c
+++ b/drivers/rtc/bfin_rtc.c
@@ -27,7 +27,7 @@
#define NUM_SECS_IN_DAY DAYS_TO_SECS(1)
/* Enable the RTC prescaler enable register */
-static void rtc_init(void)
+void rtc_init(void)
{
if (!(bfin_read_RTC_PREN() & 0x1))
bfin_write_RTC_PREN(0x1);
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index f7cf106..39e6041 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -14,6 +14,7 @@
#include <common.h>
#include <command.h>
#include <rtc.h>
+#include <version.h>
#if defined(__I386__) || defined(CONFIG_MALTA)
#include <asm/io.h>
@@ -23,6 +24,9 @@
#if defined(CONFIG_CMD_DATE)
+/* Set this to 1 to clear the CMOS RAM */
+#define CLEAR_CMOS 0
+
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
@@ -41,7 +45,14 @@
#define RTC_CONFIG_B 0x0B
#define RTC_CONFIG_C 0x0C
#define RTC_CONFIG_D 0x0D
+#define RTC_REG_SIZE 0x80
+#define RTC_CONFIG_A_REF_CLCK_32KHZ (1 << 5)
+#define RTC_CONFIG_A_RATE_1024HZ 6
+
+#define RTC_CONFIG_B_24H (1 << 1)
+
+#define RTC_CONFIG_D_VALID_RAM_AND_TIME 0x80
/* ------------------------------------------------------------------------- */
@@ -128,25 +139,49 @@
*/
static uchar rtc_read (uchar reg)
{
- return(in8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg));
+ return in8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg);
}
static void rtc_write (uchar reg, uchar val)
{
- out8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg, val);
+ out8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg, val);
}
#else
static uchar rtc_read (uchar reg)
{
out8(RTC_PORT_MC146818,reg);
- return(in8(RTC_PORT_MC146818+1));
+ return in8(RTC_PORT_MC146818 + 1);
}
static void rtc_write (uchar reg, uchar val)
{
out8(RTC_PORT_MC146818,reg);
- out8(RTC_PORT_MC146818+1,val);
+ out8(RTC_PORT_MC146818+1, val);
}
#endif
+void rtc_init(void)
+{
+#if CLEAR_CMOS
+ int i;
+
+ rtc_write(RTC_SECONDS_ALARM, 0);
+ rtc_write(RTC_MINUTES_ALARM, 0);
+ rtc_write(RTC_HOURS_ALARM, 0);
+ for (i = RTC_CONFIG_A; i < RTC_REG_SIZE; i++)
+ rtc_write(i, 0);
+ printf("RTC: zeroing CMOS RAM\n");
+#endif
+
+ /* Setup the real time clock */
+ rtc_write(RTC_CONFIG_B, RTC_CONFIG_B_24H);
+ /* Setup the frequency it operates at */
+ rtc_write(RTC_CONFIG_A, RTC_CONFIG_A_REF_CLCK_32KHZ |
+ RTC_CONFIG_A_RATE_1024HZ);
+ /* Ensure all reserved bits are 0 in register D */
+ rtc_write(RTC_CONFIG_D, RTC_CONFIG_D_VALID_RAM_AND_TIME);
+
+ /* Clear any pending interrupts */
+ rtc_read(RTC_CONFIG_C);
+}
#endif
diff --git a/drivers/rtc/mvrtc.h b/drivers/rtc/mvrtc.h
index ebddc12..424743c 100644
--- a/drivers/rtc/mvrtc.h
+++ b/drivers/rtc/mvrtc.h
@@ -13,7 +13,7 @@
#define _MVRTC_H_
#include <asm/arch/soc.h>
-#include <compiler.h>
+#include <linux/compiler.h>
/* RTC registers */
struct mvrtc_registers {
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 8f05191..af5beba 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -132,11 +132,12 @@
void NS16550_init(NS16550_t com_port, int baud_divisor)
{
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX))
+#if (defined(CONFIG_SPL_BUILD) && \
+ (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX)))
/*
- * On some OMAP3 devices when UART3 is configured for boot mode before
- * SPL starts only THRE bit is set. We have to empty the transmitter
- * before initialization starts.
+ * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode
+ * before SPL starts only THRE bit is set. We have to empty the
+ * transmitter before initialization starts.
*/
if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
== UART_LSR_THRE) {
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index b09053f..d1b5777 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -39,7 +39,7 @@
/* Check for a chosen console */
node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path");
if (node < 0)
- node = fdtdec_get_alias_node(gd->fdt_blob, "console");
+ node = fdt_path_offset(gd->fdt_blob, "console");
if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &dev)) {
gd->cur_serial_dev = dev;
return;
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 38dda91..e1bf496 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -72,30 +72,39 @@
static int pl01x_generic_serial_init(struct pl01x_regs *regs,
enum pl01x_type type)
{
- unsigned int lcr;
-
+ switch (type) {
+ case TYPE_PL010:
+ /* disable everything */
+ writel(0, ®s->pl010_cr);
+ break;
+ case TYPE_PL011:
#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
- if (type == TYPE_PL011) {
/* Empty RX fifo if necessary */
if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) {
while (!(readl(®s->fr) & UART_PL01x_FR_RXFE))
readl(®s->dr);
}
- }
#endif
-
- /* First, disable everything */
- writel(0, ®s->pl010_cr);
-
- /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
- lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
- writel(lcr, ®s->pl011_lcrh);
-
- switch (type) {
- case TYPE_PL010:
+ /* disable everything */
+ writel(0, ®s->pl011_cr);
break;
- case TYPE_PL011: {
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int set_line_control(struct pl01x_regs *regs)
+{
+ unsigned int lcr;
+ /*
+ * Internal update of baud rate register require line
+ * control register write
+ */
+ lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
#ifdef CONFIG_PL011_SERIAL_RLCR
+ {
int i;
/*
@@ -107,15 +116,9 @@
writel(lcr, ®s->fr);
writel(lcr, ®s->pl011_rlcr);
- /* lcrh needs to be set again for change to be effective */
- writel(lcr, ®s->pl011_lcrh);
+ }
#endif
- break;
- }
- default:
- return -EINVAL;
- }
-
+ writel(lcr, ®s->pl011_lcrh);
return 0;
}
@@ -175,6 +178,7 @@
writel(divider, ®s->pl011_ibrd);
writel(fraction, ®s->pl011_fbrd);
+ set_line_control(regs);
/* Finally, enable the UART */
writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr);
@@ -201,7 +205,7 @@
base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
pl01x_generic_serial_init(base_regs, pl01x_type);
- pl01x_generic_setbrg(base_regs, TYPE_PL010, clock, baudrate);
+ pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
}
/*
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
index 6046efb..e8a1608 100644
--- a/drivers/serial/serial_uniphier.c
+++ b/drivers/serial/serial_uniphier.c
@@ -11,6 +11,7 @@
#include <dm/device.h>
#include <dm/platform_data/serial-uniphier.h>
#include <serial.h>
+#include <fdtdec.h>
#define UART_REG(x) \
u8 x; \
@@ -113,19 +114,21 @@
}
#ifdef CONFIG_OF_CONTROL
-static const struct udevice_id uniphier_uart_of_match = {
- { .compatible = "panasonic,uniphier-uart"},
+static const struct udevice_id uniphier_uart_of_match[] = {
+ { .compatible = "panasonic,uniphier-uart" },
{},
};
static int uniphier_serial_ofdata_to_platdata(struct udevice *dev)
{
- /*
- * TODO: Masahiro Yamada (yamada.m@jp.panasonic.com)
- *
- * Implement conversion code from DTB to platform data
- * when supporting CONFIG_OF_CONTROL on UniPhir platform.
- */
+ struct uniphier_serial_platform_data *plat = dev_get_platdata(dev);
+ DECLARE_GLOBAL_DATA_PTR;
+
+ plat->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "clock-frequency", 0);
+
+ return 0;
}
#endif
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index fd7fea8..857b604 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -102,7 +102,7 @@
struct spi_slave *slave = &qslave->slave;
u32 memval = 0;
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
slave->memory_map = (void *)MMAP_START_ADDR_DRA;
#else
slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
@@ -244,7 +244,7 @@
uint status;
int timeout;
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
int val;
#endif
@@ -254,7 +254,7 @@
/* Setup mmap flags */
if (flags & SPI_XFER_MMAP) {
writel(MM_SWITCH, &qslave->base->memswitch);
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
val = readl(CORE_CTRL_IO);
val |= MEM_CS;
writel(val, CORE_CTRL_IO);
@@ -262,7 +262,7 @@
return 0;
} else if (flags & SPI_XFER_MMAP_END) {
writel(~MM_SWITCH, &qslave->base->memswitch);
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
val = readl(CORE_CTRL_IO);
val &= MEM_CS_UNSELECT;
writel(val, CORE_CTRL_IO);
diff --git a/drivers/tpm/tpm.c b/drivers/tpm/tpm.c
index bc0f964..31761ec 100644
--- a/drivers/tpm/tpm.c
+++ b/drivers/tpm/tpm.c
@@ -34,7 +34,7 @@
#include <config.h>
#include <common.h>
-#include <compiler.h>
+#include <linux/compiler.h>
#include <fdtdec.h>
#include <i2c.h>
#include <tpm.h>
diff --git a/drivers/tpm/tpm_tis_i2c.c b/drivers/tpm/tpm_tis_i2c.c
index 2dd8501..c1bbed4 100644
--- a/drivers/tpm/tpm_tis_i2c.c
+++ b/drivers/tpm/tpm_tis_i2c.c
@@ -38,7 +38,7 @@
#include <common.h>
#include <fdtdec.h>
-#include <compiler.h>
+#include <linux/compiler.h>
#include <i2c.h>
#include <tpm.h>
#include <asm-generic/errno.h>
diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c
index 77f6c9d..32a4375 100644
--- a/drivers/usb/host/ehci-uniphier.c
+++ b/drivers/usb/host/ehci-uniphier.c
@@ -6,10 +6,43 @@
*/
#include <common.h>
+#include <linux/err.h>
#include <usb.h>
#include <asm/arch/ehci-uniphier.h>
#include "ehci.h"
+#ifdef CONFIG_OF_CONTROL
+#include <fdtdec.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FDT gd->fdt_blob
+#define COMPAT "panasonic,uniphier-ehci"
+
+static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
+{
+ int offset;
+
+ for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
+ offset >= 0;
+ offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
+ if (index == 0) {
+ *base = (struct ehci_hccr *)
+ fdtdec_get_addr(FDT, offset, "reg");
+ return 0;
+ }
+ index--;
+ }
+
+ return -ENODEV; /* not found */
+}
+#else
+static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
+{
+ *base = (struct ehci_hccr *)uniphier_ehci_platdata[index].base;
+ return 0;
+}
+#endif
+
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
@@ -17,12 +50,15 @@
int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
struct ehci_hcor **hcor)
{
+ int ret;
struct ehci_hccr *cr;
struct ehci_hcor *or;
uniphier_ehci_reset(index, 0);
- cr = (struct ehci_hccr *)(uniphier_ehci_platdata[index].base);
+ ret = get_uniphier_ehci_base(index, &cr);
+ if (ret < 0)
+ return ret;
or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase));
*hccr = cr;
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index f78d532..52a3664 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -118,7 +118,6 @@
void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
{
omap_usb_dpll_lock(phy_regs);
-
usb3_phy_partial_powerup(phy_regs);
/*
* Give enough time for the PHY to partially power-up before
@@ -126,7 +125,6 @@
* team.
*/
mdelay(100);
- usb3_phy_power(1);
}
static void omap_enable_usb3_phy(struct omap_xhci *omap)
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 7301be3..00b563f 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -42,6 +42,7 @@
obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o
obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
+obj-$(CONFIG_VIDEO_X86) += x86_fb.o
obj-$(CONFIG_FORMIKE) += formike.o
obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
obj-$(CONFIG_VIDEO_PARADE) += parade.o
diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c
index 618f5d9..5748951 100644
--- a/drivers/video/ati_radeon_fb.c
+++ b/drivers/video/ati_radeon_fb.c
@@ -19,6 +19,7 @@
#include <common.h>
#include <command.h>
+#include <bios_emul.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/errno.h>
@@ -544,7 +545,6 @@
}
#include "../bios_emulator/include/biosemu.h"
-extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp);
int radeon_probe(struct radeonfb_info *rinfo)
{
diff --git a/drivers/video/x86_fb.c b/drivers/video/x86_fb.c
new file mode 100644
index 0000000..8743a8c
--- /dev/null
+++ b/drivers/video/x86_fb.c
@@ -0,0 +1,37 @@
+/*
+ *
+ * Vesa frame buffer driver for x86
+ *
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <video_fb.h>
+#include <vbe.h>
+#include "videomodes.h"
+
+/*
+ * The Graphic Device
+ */
+GraphicDevice ctfb;
+
+void *video_hw_init(void)
+{
+ GraphicDevice *gdev = &ctfb;
+ int bits_per_pixel;
+
+ printf("Video: ");
+ if (vbe_get_video_info(gdev)) {
+ printf("No video mode configured\n");
+ return NULL;
+ }
+
+ bits_per_pixel = gdev->gdfBytesPP * 8;
+ sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
+ bits_per_pixel);
+ printf("%s\n", gdev->modeIdent);
+
+ return (void *)gdev;
+}
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index 943b5bc..258b937 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -25,6 +25,7 @@
#include <ext_common.h>
#include <ext4fs.h>
#include "ext4_common.h"
+#include <div64.h>
int ext4fs_symlinknest;
struct ext_filesystem ext_fs;
@@ -67,11 +68,11 @@
if (len > filesize)
len = filesize;
- blockcnt = ((len + pos) + blocksize - 1) / blocksize;
+ blockcnt = lldiv(((len + pos) + blocksize - 1), blocksize);
- for (i = pos / blocksize; i < blockcnt; i++) {
+ for (i = lldiv(pos, blocksize); i < blockcnt; i++) {
lbaint_t blknr;
- int blockoff = pos % blocksize;
+ int blockoff = pos - (blocksize * i);
int blockend = blocksize;
int skipfirst = 0;
blknr = read_allocated_block(&(node->inode), i);
@@ -82,7 +83,7 @@
/* Last block. */
if (i == blockcnt - 1) {
- blockend = (len + pos) % blocksize;
+ blockend = (len + pos) - (blocksize * i);
/* The last portion is exactly blocksize. */
if (!blockend)
@@ -90,7 +91,7 @@
}
/* First block. */
- if (i == pos / blocksize) {
+ if (i == lldiv(pos, blocksize)) {
skipfirst = blockoff;
blockend -= skipfirst;
}
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index 88dd495..98b88ad 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -13,6 +13,8 @@
#include <asm/byteorder.h>
#include <part.h>
#include <linux/ctype.h>
+#include <div64.h>
+#include <linux/math64.h>
#include "fat.c"
static void uppercase(char *str, int len)
@@ -770,7 +772,7 @@
*/
static int check_overflow(fsdata *mydata, __u32 clustnum, loff_t size)
{
- __u32 startsect, sect_num;
+ __u32 startsect, sect_num, offset;
if (clustnum > 0) {
startsect = mydata->data_begin +
@@ -779,13 +781,13 @@
startsect = mydata->rootdir_sect;
}
- sect_num = size / mydata->sect_size;
- if (size % mydata->sect_size)
+ sect_num = div_u64_rem(size, mydata->sect_size, &offset);
+
+ if (offset != 0)
sect_num++;
if (startsect + sect_num > cur_part_info.start + total_sector)
return -1;
-
return 0;
}
diff --git a/fs/fs.c b/fs/fs.c
index 3da7860..ddd751c 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -23,6 +23,8 @@
#include <fs.h>
#include <sandboxfs.h>
#include <asm/io.h>
+#include <div64.h>
+#include <linux/math64.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -399,7 +401,7 @@
printf("%llu bytes read in %lu ms", len_read, time);
if (time > 0) {
puts(" (");
- print_size(len_read / time * 1000, "/s");
+ print_size(div_u64(len_read, time) * 1000, "/s");
puts(")");
}
puts("\n");
@@ -469,7 +471,7 @@
printf("%llu bytes written in %lu ms", len, time);
if (time > 0) {
puts(" (");
- print_size(len / time * 1000, "/s");
+ print_size(div_u64(len, time) * 1000, "/s");
puts(")");
}
puts("\n");
diff --git a/include/bios_emul.h b/include/bios_emul.h
new file mode 100644
index 0000000..3643b82
--- /dev/null
+++ b/include/bios_emul.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 1996-1999 SciTech Software, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _BIOS_EMUL_H
+#define _BIOS_EMUL_H
+
+/* Include the register header directly here */
+#include "../drivers/bios_emulator/include/x86emu/regs.h"
+#include <pci.h>
+
+/****************************************************************************
+REMARKS:
+Data structure used to describe the details for the BIOS emulator system
+environment as used by the X86 emulator library.
+
+HEADER:
+biosemu.h
+
+MEMBERS:
+vgaInfo - VGA BIOS information structure
+biosmem_base - Base of the BIOS image
+biosmem_limit - Limit of the BIOS image
+busmem_base - Base of the VGA bus memory
+****************************************************************************/
+typedef struct {
+ int function;
+ int device;
+ int bus;
+ u32 VendorID;
+ u32 DeviceID;
+ pci_dev_t pcidev;
+ void *BIOSImage;
+ u32 BIOSImageLen;
+ u8 LowMem[1536];
+} BE_VGAInfo;
+
+struct vbe_mode_info;
+
+int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int cleanUp);
+
+/* Run a BIOS ROM natively (only supported on x86 machines) */
+void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode,
+ struct vbe_mode_info *mode_info);
+
+/**
+ * bios_set_interrupt_handler() - Install an interrupt handler for the BIOS
+ *
+ * This installs an interrupt handler that the BIOS will call when needed.
+ *
+ * @intnum: Interrupt number to install a handler for
+ * @int_handler_func: Function to call to handle interrupt
+ */
+void bios_set_interrupt_handler(int intnum, int (*int_handler_func)(void));
+
+void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void));
+
+int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo);
+
+int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
+ BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
+ struct vbe_mode_info *mode_info);
+
+#endif
diff --git a/include/common.h b/include/common.h
index f1ab2cf..46f07fe 100644
--- a/include/common.h
+++ b/include/common.h
@@ -73,6 +73,9 @@
#ifdef CONFIG_ARM
#define asmlinkage /* nothing */
#endif
+#ifdef CONFIG_X86
+#define asmlinkage __attribute__((regparm(0)))
+#endif
#ifdef CONFIG_BLACKFIN
#include <asm/blackfin.h>
#endif
@@ -442,11 +445,6 @@
extern ssize_t spi_write (uchar *, int, uchar *, int);
#endif
-#ifdef CONFIG_HERMES
-/* $(BOARD)/hermes.c */
-void hermes_start_lxt980 (int speed);
-#endif
-
#ifdef CONFIG_EVB64260
void evb64260_init(void);
void debug_led(int, int);
diff --git a/include/commproc.h b/include/commproc.h
index d78ab00..6875c4c 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -535,34 +535,6 @@
#define SICR_ENET_CLKRT ((uint)0x00002600)
#endif /* CONFIG_FPS850L, CONFIG_FPS860L */
-/*** HERMES-PRO ******************************************************/
-
-/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
-
-#ifdef CONFIG_HERMES
-
-#define FEC_ENET /* use FEC for EThernet */
-#undef SCC_ENET
-
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-#endif /* CONFIG_HERMES */
-
/*** IP860 **********************************************************/
#if defined(CONFIG_IP860)
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index 120fdc6..d23d2c4 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -418,8 +418,6 @@
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NOR_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0xfc000000
-#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx"
-#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
#define CONFIG_SPL_SERIAL_SUPPORT
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 0fbfa3f..09ee10c 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -304,7 +304,7 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 8719f76..190ef0e 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -313,7 +313,7 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h
new file mode 100644
index 0000000..cc36330
--- /dev/null
+++ b/include/configs/beagle_x15.h
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated.
+ * Felipe Balbi <balbi@ti.com>
+ *
+ * Configuration settings for the TI Beagle x15 board.
+ * See ti_omap5_common.h for omap5 common settings.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_BEAGLE_X15_H
+#define __CONFIG_BEAGLE_X15_H
+
+#define CONFIG_AM57XX
+
+#define CONFIG_NR_DRAM_BANKS 2
+
+#define CONFIG_ENV_SIZE (64 << 10)
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE "mmc"
+#define FAT_ENV_DEVICE_AND_PART "0:1"
+#define FAT_ENV_FILE "uboot.env"
+
+#define CONFIG_CMD_SAVEENV
+
+#define CONSOLEDEV "ttyO2"
+#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_OMAP_ABE_SYSCK
+
+/* Define the default GPT table for eMMC */
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
+
+#include <configs/ti_omap5_common.h>
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+/* CPSW Ethernet */
+#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
+#define CONFIG_MII /* Required in net/eth.c */
+#define CONFIG_PHY_GIGE /* per-board part of CPSW */
+#define CONFIG_PHYLIB
+
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* USB xHCI HOST */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_OMAP_USB3PHY1_HOST
+
+/* SATA */
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
+#endif /* __CONFIG_BEAGLE_X5_H */
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index 8caeca6..645b31c 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -21,7 +21,6 @@
#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000
#define CONFIG_SYS_X86_START16 0xfffff800
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_X86_RESET_VECTOR
@@ -40,20 +39,9 @@
{PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-/*
- * These common x86 features are not yet supported, but are added in
- * follow-on patches in this series. Add undefs here to avoid every patch
- * having to put things back into x86-common.h
- */
-#undef CONFIG_VIDEO
-#undef CONFIG_CFB_CONSOLE
-#undef CONFIG_ICH_SPI
-#undef CONFIG_SPI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_SF
-#undef CONFIG_USB_EHCI
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_SCSI
+#define CONFIG_X86_OPTION_ROM_FILENAME pci8086,0166.bin
+#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
+#define CONFIG_VIDEO_X86
#define CONFIG_PCI_MEM_BUS 0xe0000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
@@ -67,6 +55,18 @@
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0xefff
+#define CONFIG_SYS_EARLY_PCI_INIT
+#define CONFIG_PCI_PNP
+
+#define CONFIG_BIOSEMU
+#define VIDEO_IO_OFFSET 0
+#define CONFIG_X86EMU_RAW_IO
+
+#define CONFIG_CROS_EC
+#define CONFIG_CROS_EC_LPC
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_ARCH_EARLY_INIT_R
+
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial\0" \
"stderr=vga,serial\0"
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 1919cde..ccd9b88 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -321,7 +321,7 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_BOARD_INIT
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index 641ab48..92ce1e1 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -16,7 +16,6 @@
#include <configs/ti_omap5_common.h>
-#undef CONFIG_MISC_INIT_R
#undef CONFIG_SPL_OS_BOOT
/* Enable Generic board */
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index ca62461..930b08e 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -299,7 +299,7 @@
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 2eaabde..174a711 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -50,6 +50,7 @@
#define CONFIG_EFI_PARTITION
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
+#define CONFIG_HSMMC2_8BIT
/* CPSW Ethernet */
#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
diff --git a/include/configs/hermes.h b/include/configs/hermes.h
deleted file mode 100644
index 736ffb61..0000000
--- a/include/configs/hermes.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
-#define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 9600
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-
-#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000 /* Non-Standard value! */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#ifdef DEBUG
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- * +0x0004
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * +0x0000 => 0x000000C0
- */
-#define CONFIG_SYS_SIUMCR 0
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- * +0x0200 => 0x00C2
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- * +0x0240 => 0x0082
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* +0x0286 => 0x00B0D0C0 */
-#define CONFIG_SYS_PLPRCR \
- ( (11 << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
- /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
- PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
- )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-/* +0x0282 => 0x03800000 */
-#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \
- SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
- SCCR_EBDF00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | \
- SCCR_DFNH000)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-/* +0x0220 => 0x00C3 */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register 19-4
- *-----------------------------------------------------------------------
- */
-/* +0x09C4 => TIMEP=1 */
-#define CONFIG_SYS_RCCR 0x0100
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-/* allow for max 4 MB of Flash */
-#define CONFIG_SYS_REMAP_OR_AM 0xFFC00000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */
-#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
- OR_SCY_5_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-/* 8 bit, bank valid */
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR1/OR1 - SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
-#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
-
-#define CONFIG_SYS_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide
- */
-#define HPRO2_BASE 0xE0000000
-#define HPRO2_OR_AM 0xFFFF8000
-#define HPRO2_TIMING 0x00000934
-
-#define CONFIG_SYS_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
-#define CONFIG_SYS_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3/OR3: not used
- * BR4/OR4: not used
- * BR5/OR5: not used
- * BR6/OR6: not used
- * BR7/OR7: not used
- */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-#endif /* __CONFIG_H */
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 5a5f940..1b9c277 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -28,7 +28,6 @@
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x00908000
#define CONFIG_SPL_MAX_SIZE 0x10000
-#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7"
#define CONFIG_SPL_STACK 0x0091FFB8
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
@@ -46,7 +45,7 @@
#if defined(CONFIG_SPL_MMC_SUPPORT)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 138 /* offset 69KB */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024)
#endif
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 58e7295..d43db52 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -671,8 +671,6 @@
#define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */
#define CONFIG_SYS_SPL_MAX_LEN (64 << 10)
#define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */
-#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/ppc4xx"
-#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/ppc4xx/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
#define CONFIG_SPL_SERIAL_SUPPORT
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index b775ebd..26eb220 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -369,7 +369,7 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
/* NAND boot config */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 27bf89c..8bdc08f 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -75,7 +75,7 @@
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
/* Partition tables */
diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h
index 2daf13c..1185f42 100644
--- a/include/configs/omap3_evm_quick_mmc.h
+++ b/include/configs/omap3_evm_quick_mmc.h
@@ -87,7 +87,7 @@
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif /* __OMAP3_EVM_QUICK_MMC_H */
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index e8dc462..e07795f 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -23,6 +23,7 @@
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
#define CONFIG_BAUDRATE 115200
+#define CONFIG_MISC_INIT_R
/* MMC ENV related defines */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
diff --git a/include/configs/ph1_ld4.h b/include/configs/ph1_ld4.h
deleted file mode 100644
index 73a95e6..0000000
--- a/include/configs/ph1_ld4.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PH1_XXX_H
-#define __PH1_XXX_H
-
-/*
- * Support Card Select
- *
- * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
- * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
- * CPLD is re-programmed for ARIMA board compatibility.
- * No define - No support card.
- */
-
-#if 0
-#define CONFIG_PFC_MICRO_SUPPORT_CARD
-#else
-#define CONFIG_DCC_MICRO_SUPPORT_CARD
-#endif
-
-/*
- * Serial Configuration
- * SoC UART : enable CONFIG_UNIPHIER_SERIAL
- * On-board UART: enable CONFIG_SYS_NS16550_SERIAL
- */
-#if 0
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
-#define CONFIG_SMC911X
-
-#define CONFIG_DDR_NUM_CH0 1
-#define CONFIG_DDR_NUM_CH1 1
-
-/*
- * Memory Size & Mapping
- */
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE 0x80000000
-#define CONFIG_SDRAM0_SIZE 0x10000000
-#define CONFIG_SDRAM1_BASE 0x90000000
-#define CONFIG_SDRAM1_SIZE 0x10000000
-
-#define CONFIG_SPL_TEXT_BASE 0x40000
-
-#include "uniphier-common.h"
-
-#endif /* __PH1_XXX_H */
diff --git a/include/configs/ph1_pro4.h b/include/configs/ph1_pro4.h
deleted file mode 100644
index fc5132d..0000000
--- a/include/configs/ph1_pro4.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PH1_XXX_H
-#define __PH1_XXX_H
-
-/*
- * Support Card Select
- *
- * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
- * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
- * CPLD is re-programmed for ARIMA board compatibility.
- * No define - No support card.
- */
-
-#if 0
-#define CONFIG_PFC_MICRO_SUPPORT_CARD
-#else
-#define CONFIG_DCC_MICRO_SUPPORT_CARD
-#endif
-
-/*
- * Serial Configuration
- * SoC UART : enable CONFIG_UNIPHIER_SERIAL
- * On-board UART: enable CONFIG_SYS_NS16550_SERIAL
- */
-#if 0
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
-#define CONFIG_SMC911X
-
-#define CONFIG_DDR_NUM_CH0 2
-#define CONFIG_DDR_NUM_CH1 2
-
-#define CONFIG_UNIPHIER_SMP
-
-/*
- * Memory Size & Mapping
- */
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE 0x80000000
-#define CONFIG_SDRAM0_SIZE 0x20000000
-#define CONFIG_SDRAM1_BASE 0xa0000000
-#define CONFIG_SDRAM1_SIZE 0x20000000
-
-#define CONFIG_SPL_TEXT_BASE 0x100000
-
-#include "uniphier-common.h"
-
-#endif /* __PH1_XXX_H */
diff --git a/include/configs/ph1_sld8.h b/include/configs/ph1_sld8.h
deleted file mode 100644
index e2f1102..0000000
--- a/include/configs/ph1_sld8.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PH1_XXX_H
-#define __PH1_XXX_H
-
-/*
- * Support Card Select
- *
- * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
- * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
- * CPLD is re-programmed for ARIMA board compatibility.
- * No define - No support card.
- */
-
-#if 0
-#define CONFIG_PFC_MICRO_SUPPORT_CARD
-#else
-#define CONFIG_DCC_MICRO_SUPPORT_CARD
-#endif
-
-/*
- * Serial Configuration
- * SoC UART : enable CONFIG_UNIPHIER_SERIAL
- * On-board UART: enable CONFIG_SYS_NS16550_SERIAL
- */
-#if 0
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
-#define CONFIG_SMC911X
-
-#define CONFIG_DDR_NUM_CH0 1
-#define CONFIG_DDR_NUM_CH1 1
-
-/* #define CONFIG_DDR_STANDARD */
-
-/*
- * Memory Size & Mapping
- */
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE 0x80000000
-#define CONFIG_SDRAM0_SIZE 0x10000000
-#define CONFIG_SDRAM1_BASE 0x90000000
-#define CONFIG_SDRAM1_SIZE 0x10000000
-
-#define CONFIG_SPL_TEXT_BASE 0x40000
-
-#include "uniphier-common.h"
-
-#endif /* __PH1_XXX_H */
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index d75d562..946b2c8 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -150,4 +150,8 @@
#define CONFIG_SYS_CONSOLE_FG_COL 0x00
#endif
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FIT
+#endif
+
#endif /* ! __CONFIG_PXM2_H */
diff --git a/include/configs/rpi_b.h b/include/configs/rpi.h
similarity index 95%
rename from include/configs/rpi_b.h
rename to include/configs/rpi.h
index 41e975f..4d5426e 100644
--- a/include/configs/rpi_b.h
+++ b/include/configs/rpi.h
@@ -105,15 +105,15 @@
/* Environment */
#define CONFIG_ENV_SIZE SZ_16K
-#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE "mmc"
+#define FAT_ENV_DEVICE_AND_PART "0:1"
+#define FAT_ENV_FILE "uboot.env"
+#define CONFIG_FAT_WRITE
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_SYS_LOAD_ADDR 0x1000000
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_PREBOOT \
- "if load mmc 0:1 ${loadaddr} /uEnv.txt; then " \
- "env import -t -r ${loadaddr} ${filesize}; " \
- "fi"
/* Shell */
#define CONFIG_SYS_MAXARGS 8
@@ -138,7 +138,6 @@
/* Some things don't make sense on this HW or yet */
#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SAVEENV
/* Environment */
#define ENV_DEVICE_SETTINGS \
@@ -175,7 +174,6 @@
"pxefile_addr_r=0x00100000\0" \
"kernel_addr_r=0x01000000\0" \
"fdt_addr_r=0x02000000\0" \
- "fdtfile=bcm2835-rpi-b.dtb\0" \
"ramdisk_addr_r=0x02100000\0" \
#define BOOT_TARGET_DEVICES(func) \
diff --git a/include/configs/rut.h b/include/configs/rut.h
index 6bddede..0067ea4 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -154,4 +154,8 @@
#define CONFIG_SYS_CONSOLE_FG_COL 0x00
#endif
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FIT
+#endif
+
#endif /* ! __CONFIG_RUT_H */
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
index 5b77db2..d5588b1 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -230,7 +230,7 @@
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index dfbf3cb..f2849d7 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -276,7 +276,7 @@
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 0d5dba1..21e13e5 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -148,7 +148,7 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index a160329..7d2c0d2 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -304,7 +304,7 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_BOARD_INIT
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 2fddef3..deb6bb2 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -178,7 +178,7 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index aeabb1b..87a4efc 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -144,7 +144,7 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index a8790c2..bc75172 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -233,7 +233,7 @@
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
/* FAT sd card locations. */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#ifdef CONFIG_SPL_OS_BOOT
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 3166392..c47651d 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -19,7 +19,6 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_MISC_INIT_R
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_CACHELINE_SIZE 64
@@ -79,7 +78,7 @@
"partitions=" PARTS_DEFAULT "\0" \
"optargs=\0" \
"mmcdev=0\0" \
- "mmcroot=/dev/mmcblk1p2 rw\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext4 rootwait\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
@@ -118,6 +117,8 @@
"setenv fdtfile dra7-evm.dtb; fi;" \
"if test $board_name = dra72x; then " \
"setenv fdtfile dra72-evm.dtb; fi;" \
+ "if test $board_name = beagle_x15; then " \
+ "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 6e7a7fb..36621a5 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -349,7 +349,7 @@
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
diff --git a/include/configs/uniphier-common.h b/include/configs/uniphier.h
similarity index 84%
rename from include/configs/uniphier-common.h
rename to include/configs/uniphier.h
index 7c4dba0..dd022fb 100644
--- a/include/configs/uniphier-common.h
+++ b/include/configs/uniphier.h
@@ -10,10 +10,37 @@
#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) && \
- defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-# error "Both CONFIG_PFC_MICRO_SUPPORT_CARD and CONFIG_DCC_MICRO_SUPPORT_CARD \
-are defined. Select only one of them."
+#if defined(CONFIG_MACH_PH1_PRO4)
+#define CONFIG_DDR_NUM_CH0 2
+#define CONFIG_DDR_NUM_CH1 2
+
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE 0x80000000
+#define CONFIG_SDRAM0_SIZE 0x20000000
+#define CONFIG_SDRAM1_BASE 0xa0000000
+#define CONFIG_SDRAM1_SIZE 0x20000000
+#endif
+
+#if defined(CONFIG_MACH_PH1_LD4)
+#define CONFIG_DDR_NUM_CH0 1
+#define CONFIG_DDR_NUM_CH1 1
+
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE 0x80000000
+#define CONFIG_SDRAM0_SIZE 0x10000000
+#define CONFIG_SDRAM1_BASE 0x90000000
+#define CONFIG_SDRAM1_SIZE 0x10000000
+#endif
+
+#if defined(CONFIG_MACH_PH1_SLD8)
+#define CONFIG_DDR_NUM_CH0 1
+#define CONFIG_DDR_NUM_CH1 1
+
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE 0x80000000
+#define CONFIG_SDRAM0_SIZE 0x10000000
+#define CONFIG_SDRAM1_BASE 0x90000000
+#define CONFIG_SDRAM1_SIZE 0x10000000
#endif
/*
@@ -40,6 +67,13 @@
#define CONFIG_SYS_NS16550_REG_SIZE -2
#endif
+/* TODO: move to Kconfig and device tree */
+#if 0
+#define CONFIG_SYS_NS16550_SERIAL
+#endif
+
+#define CONFIG_SMC911X
+
#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
#define CONFIG_SMC911X_32_BIT
@@ -58,6 +92,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
@@ -87,17 +122,7 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
-# define CONFIG_SYS_MAX_FLASH_BANKS 1
-# define CONFIG_SYS_FLASH_BANKS_LIST {0x00000000}
-# define CONFIG_SYS_FLASH_BANKS_SIZES {0x02000000}
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-# define CONFIG_SYS_MAX_FLASH_BANKS 1
-# define CONFIG_SYS_FLASH_BANKS_LIST {0x04000000}
-# define CONFIG_SYS_FLASH_BANKS_SIZES {0x04000000}
-#endif
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
/* serial console configuration */
#define CONFIG_BAUDRATE 115200
@@ -112,7 +137,6 @@
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* add command line history */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
@@ -143,15 +167,6 @@
*/
#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_NAND /* NAND flash suppport */
-
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 2
#define CONFIG_SYS_NAND_ONFI_DETECTION
@@ -167,7 +182,6 @@
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
/* USB */
-#define CONFIG_CMD_USB
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
@@ -216,7 +230,6 @@
"image_offset=0x00080000\0" \
"image_size=0x00f00000\0" \
"verify=n\0" \
- "autostart=yes\0" \
"norboot=run add_default_bootargs;" \
"bootm $image_offset\0" \
"nandboot=run add_default_bootargs;" \
@@ -225,10 +238,6 @@
"add_default_bootargs=setenv bootargs $bootargs" \
" console=ttyS0,$baudrate\0" \
-/* FIT support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
-
/* Open Firmware flat tree */
#define CONFIG_OF_LIBFDT
@@ -248,6 +257,13 @@
#define CONFIG_SYS_TEXT_BASE 0x84000000
+#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#define CONFIG_SPL_TEXT_BASE 0x00040000
+#endif
+#if defined(CONFIG_MACH_PH1_PRO4)
+#define CONFIG_SPL_TEXT_BASE 0x00100000
+#endif
+
#define CONFIG_BOARD_POSTCLK_INIT
#ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index c39c568..87b4fff 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -265,7 +265,7 @@
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 3da9fab..d2b665c 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -120,6 +120,9 @@
COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */
COMPAT_INTEL_MICROCODE, /* Intel microcode update */
COMPAT_MEMORY_SPD, /* Memory SPD information */
+ COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */
+ COMPAT_INTEL_MODEL_206AX, /* Intel Model 206AX CPU */
+ COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */
COMPAT_COUNT,
};
@@ -390,17 +393,6 @@
int *seqp);
/**
- * Get the offset of the given alias node
- *
- * This looks up an alias in /aliases then finds the offset of that node.
- *
- * @param blob Device tree blob (if NULL, then error is returned)
- * @param name Alias name, e.g. "console"
- * @return Node offset referred to by that alias, or -ve FDT_ERR_...
- */
-int fdtdec_get_alias_node(const void *blob, const char *name);
-
-/**
* Get the offset of the given chosen node
*
* This looks up a property in /chosen containing the path to another node,
diff --git a/include/linux/compat.h b/include/linux/compat.h
index 47b0889..b40133c 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -215,13 +215,11 @@
#define cond_resched() do { } while (0)
#define yield() do { } while (0)
-#define __user
#define __init
#define __exit
#define __devinit
#define __devinitdata
#define __devinitconst
-#define __iomem
#define kthread_create(...) __builtin_return_address(0)
#define kthread_stop(...) do { } while (0)
@@ -252,8 +250,6 @@
#define cdev_add(...) 0
#define cdev_del(...) do { } while (0)
-#define MAX_ERRNO 4095
-
#define prandom_u32(...) 0
typedef struct {
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index 89fcae0..0b61671 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -16,7 +16,9 @@
#define LLONG_MAX ((long long)(~0ULL>>1))
#define LLONG_MIN (-LLONG_MAX - 1)
#define ULLONG_MAX (~0ULL)
+#ifndef SIZE_MAX
#define SIZE_MAX (~(size_t)0)
+#endif
#define U8_MAX ((u8)~0U)
#define S8_MAX ((s8)(U8_MAX>>1))
diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h
index 82630ad..cb166e6 100644
--- a/include/linux/usb/xhci-omap.h
+++ b/include/linux/usb/xhci-omap.h
@@ -14,6 +14,10 @@
#define OMAP_XHCI_BASE 0x488d0000
#define OMAP_OCP1_SCP_BASE 0x4A081000
#define OMAP_OTG_WRAPPER_BASE 0x488c0000
+#elif defined CONFIG_AM57XX
+#define OMAP_XHCI_BASE 0x48890000
+#define OMAP_OCP1_SCP_BASE 0x4A084c00
+#define OMAP_OTG_WRAPPER_BASE 0x48880000
#elif defined CONFIG_AM43XX
#define OMAP_XHCI_BASE 0x483d0000
#define OMAP_OCP1_SCP_BASE 0x483E8000
diff --git a/include/mmc.h b/include/mmc.h
index d74a190..adffc35 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -385,6 +385,7 @@
int mmc_legacy_init(int verbose);
#endif
+void board_mmc_power_init(void);
int board_mmc_init(bd_t *bis);
int cpu_mmc_init(bd_t *bis);
int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
diff --git a/include/pci.h b/include/pci.h
index d211351..216f448 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -678,5 +678,28 @@
extern void pci_mpc85xx_init (struct pci_controller *hose);
#endif
+/**
+ * pci_write_bar32() - Write the address of a BAR including control bits
+ *
+ * This writes a raw address (with control bits) to a bar
+ *
+ * @hose: PCI hose to use
+ * @dev: PCI device to update
+ * @barnum: BAR number (0-5)
+ * @addr: BAR address with control bits
+ */
+void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
+ u32 addr_and_ctrl);
+
+/**
+ * pci_read_bar32() - read the address of a bar
+ *
+ * @hose: PCI hose to use
+ * @dev: PCI device to inspect
+ * @barnum: BAR number (0-5)
+ * @return address of the bar, masking out any control bits
+ * */
+u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
+
#endif /* __ASSEMBLY__ */
#endif /* _PCI_H */
diff --git a/include/pci_ids.h b/include/pci_ids.h
index f84c13a..ee98bee 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -526,7 +526,19 @@
#define PCI_DEVICE_ID_AMD_11H_NB_DRAM 0x1302
#define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303
#define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304
-#define PCI_DEVICE_ID_AMD_15H_NB_MISC 0x1603
+#define PCI_DEVICE_ID_AMD_15H_M10H_F3 0x1403
+#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F3 0x141d
+#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F4 0x141e
+#define PCI_DEVICE_ID_AMD_15H_NB_F0 0x1600
+#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
+#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
+#define PCI_DEVICE_ID_AMD_15H_NB_F3 0x1603
+#define PCI_DEVICE_ID_AMD_15H_NB_F4 0x1604
+#define PCI_DEVICE_ID_AMD_15H_NB_F5 0x1605
+#define PCI_DEVICE_ID_AMD_16H_NB_F3 0x1533
+#define PCI_DEVICE_ID_AMD_16H_NB_F4 0x1534
+#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583
+#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584
#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
#define PCI_DEVICE_ID_AMD_LANCE 0x2000
#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
@@ -569,8 +581,9 @@
#define PCI_DEVICE_ID_AMD_CS5536_IDE 0x209A
#define PCI_DEVICE_ID_AMD_LX_VIDEO 0x2081
#define PCI_DEVICE_ID_AMD_LX_AES 0x2082
-#define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c
#define PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE 0x7800
+#define PCI_DEVICE_ID_AMD_HUDSON2_SMBUS 0x780b
+#define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c
#define PCI_VENDOR_ID_TRIDENT 0x1023
#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
@@ -616,6 +629,8 @@
#define PCI_DEVICE_ID_MATROX_G550 0x2527
#define PCI_DEVICE_ID_MATROX_VIA 0x4536
+#define PCI_VENDOR_ID_MOBILITY_ELECTRONICS 0x14f2
+
#define PCI_VENDOR_ID_CT 0x102c
#define PCI_DEVICE_ID_CT_69000 0x00c0
#define PCI_DEVICE_ID_CT_65545 0x00d8
@@ -724,6 +739,7 @@
#define PCI_DEVICE_ID_SI_7018 0x7018
#define PCI_VENDOR_ID_HP 0x103c
+#define PCI_VENDOR_ID_HP_3PAR 0x1590
#define PCI_DEVICE_ID_HP_VISUALIZE_EG 0x1005
#define PCI_DEVICE_ID_HP_VISUALIZE_FX6 0x1006
#define PCI_DEVICE_ID_HP_VISUALIZE_FX4 0x1008
@@ -755,6 +771,8 @@
#define PCI_DEVICE_ID_HP_CISSD 0x3238
#define PCI_DEVICE_ID_HP_CISSE 0x323a
#define PCI_DEVICE_ID_HP_CISSF 0x323b
+#define PCI_DEVICE_ID_HP_CISSH 0x323c
+#define PCI_DEVICE_ID_HP_CISSI 0x3239
#define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031
#define PCI_VENDOR_ID_PCTECH 0x1042
@@ -779,6 +797,29 @@
#define PCI_DEVICE_ID_ELSA_QS3000 0x3000
#define PCI_VENDOR_ID_STMICRO 0x104A
+#define PCI_DEVICE_ID_STMICRO_USB_HOST 0xCC00
+#define PCI_DEVICE_ID_STMICRO_USB_OHCI 0xCC01
+#define PCI_DEVICE_ID_STMICRO_USB_OTG 0xCC02
+#define PCI_DEVICE_ID_STMICRO_UART_HWFC 0xCC03
+#define PCI_DEVICE_ID_STMICRO_UART_NO_HWFC 0xCC04
+#define PCI_DEVICE_ID_STMICRO_SOC_DMA 0xCC05
+#define PCI_DEVICE_ID_STMICRO_SATA 0xCC06
+#define PCI_DEVICE_ID_STMICRO_I2C 0xCC07
+#define PCI_DEVICE_ID_STMICRO_SPI_HS 0xCC08
+#define PCI_DEVICE_ID_STMICRO_MAC 0xCC09
+#define PCI_DEVICE_ID_STMICRO_SDIO_EMMC 0xCC0A
+#define PCI_DEVICE_ID_STMICRO_SDIO 0xCC0B
+#define PCI_DEVICE_ID_STMICRO_GPIO 0xCC0C
+#define PCI_DEVICE_ID_STMICRO_VIP 0xCC0D
+#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_DMA 0xCC0E
+#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_SRCS 0xCC0F
+#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_MSPS 0xCC10
+#define PCI_DEVICE_ID_STMICRO_CAN 0xCC11
+#define PCI_DEVICE_ID_STMICRO_MLB 0xCC12
+#define PCI_DEVICE_ID_STMICRO_DBP 0xCC13
+#define PCI_DEVICE_ID_STMICRO_SATA_PHY 0xCC14
+#define PCI_DEVICE_ID_STMICRO_ESRAM 0xCC15
+#define PCI_DEVICE_ID_STMICRO_VIC 0xCC16
#define PCI_VENDOR_ID_BUSLOGIC 0x104B
#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
@@ -1294,6 +1335,8 @@
#define PCI_VENDOR_ID_TUNDRA 0x10e3
#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000
+#define PCI_VENDOR_ID_AMCC 0x10e8
+
#define PCI_VENDOR_ID_INTERG 0x10ea
#define PCI_DEVICE_ID_INTERG_1682 0x1682
#define PCI_DEVICE_ID_INTERG_2000 0x2000
@@ -1322,6 +1365,7 @@
#define PCI_SUBDEVICE_ID_CREATIVE_SB08801 0x0041
#define PCI_SUBDEVICE_ID_CREATIVE_SB08802 0x0042
#define PCI_SUBDEVICE_ID_CREATIVE_SB08803 0x0043
+#define PCI_SUBDEVICE_ID_CREATIVE_SB1270 0x0062
#define PCI_SUBDEVICE_ID_CREATIVE_HENDRIX 0x6000
#define PCI_VENDOR_ID_ECTIVA 0x1102 /* duplicate: CREATIVE */
@@ -1411,6 +1455,7 @@
#define PCI_DEVICE_ID_VIA_CX700_IDE 0x0581
#define PCI_DEVICE_ID_VIA_VX800 0x8353
#define PCI_DEVICE_ID_VIA_VX855 0x8409
+#define PCI_DEVICE_ID_VIA_VX900 0x8410
#define PCI_DEVICE_ID_VIA_8371_1 0x8391
#define PCI_DEVICE_ID_VIA_82C598_1 0x8598
#define PCI_DEVICE_ID_VIA_838X_1 0xB188
@@ -1551,6 +1596,8 @@
#define PCI_DEVICE_ID_RICOH_RL5C476 0x0476
#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478
#define PCI_DEVICE_ID_RICOH_R5C822 0x0822
+#define PCI_DEVICE_ID_RICOH_R5CE822 0xe822
+#define PCI_DEVICE_ID_RICOH_R5CE823 0xe823
#define PCI_DEVICE_ID_RICOH_R5C832 0x0832
#define PCI_DEVICE_ID_RICOH_R5C843 0x0843
@@ -1586,6 +1633,7 @@
#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334
#define PCI_VENDOR_ID_MARVELL 0x11ab
+#define PCI_VENDOR_ID_MARVELL_EXT 0x1b4b
#define PCI_DEVICE_ID_MARVELL_GT64111 0x4146
#define PCI_DEVICE_ID_MARVELL_GT64260 0x6430
#define PCI_DEVICE_ID_MARVELL_MV64360 0x6460
@@ -1798,6 +1846,8 @@
#define PCI_VENDOR_ID_ESDGMBH 0x12fe
#define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
+#define PCI_VENDOR_ID_CB 0x1307 /* Measurement Computing */
+
#define PCI_VENDOR_ID_SIIG 0x131f
#define PCI_SUBVENDOR_ID_SIIG 0x131f
#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000
@@ -1860,8 +1910,23 @@
#define PCI_VENDOR_ID_QUATECH 0x135C
#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010
#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020
+#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030
+#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040
#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050
#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060
+#define PCI_DEVICE_ID_QUATECH_QSCP100 0x0120
+#define PCI_DEVICE_ID_QUATECH_DSCP100 0x0130
+#define PCI_DEVICE_ID_QUATECH_QSCP200 0x0140
+#define PCI_DEVICE_ID_QUATECH_DSCP200 0x0150
+#define PCI_DEVICE_ID_QUATECH_QSCLP100 0x0170
+#define PCI_DEVICE_ID_QUATECH_DSCLP100 0x0180
+#define PCI_DEVICE_ID_QUATECH_DSC100E 0x0181
+#define PCI_DEVICE_ID_QUATECH_SSCLP100 0x0190
+#define PCI_DEVICE_ID_QUATECH_QSCLP200 0x01A0
+#define PCI_DEVICE_ID_QUATECH_DSCLP200 0x01B0
+#define PCI_DEVICE_ID_QUATECH_DSC200E 0x01B1
+#define PCI_DEVICE_ID_QUATECH_SSCLP200 0x01C0
+#define PCI_DEVICE_ID_QUATECH_ESCLP100 0x01E0
#define PCI_DEVICE_ID_QUATECH_SPPXP_100 0x0278
#define PCI_VENDOR_ID_SEALEVEL 0x135e
@@ -1978,6 +2043,9 @@
#define PCI_DEVICE_ID_EXAR_XR17C152 0x0152
#define PCI_DEVICE_ID_EXAR_XR17C154 0x0154
#define PCI_DEVICE_ID_EXAR_XR17C158 0x0158
+#define PCI_DEVICE_ID_EXAR_XR17V352 0x0352
+#define PCI_DEVICE_ID_EXAR_XR17V354 0x0354
+#define PCI_DEVICE_ID_EXAR_XR17V358 0x0358
#define PCI_VENDOR_ID_MICROGATE 0x13c0
#define PCI_DEVICE_ID_MICROGATE_USC 0x0010
@@ -2002,6 +2070,10 @@
#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
+#define PCI_VENDOR_ID_ADVANTECH 0x13fe
+
+#define PCI_VENDOR_ID_MEILHAUS 0x1402
+
#define PCI_VENDOR_ID_LAVA 0x1407
#define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */
#define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */
@@ -2047,6 +2119,8 @@
#define PCI_VENDOR_ID_CHELSIO 0x1425
+#define PCI_VENDOR_ID_ADLINK 0x144a
+
#define PCI_VENDOR_ID_SAMSUNG 0x144d
#define PCI_VENDOR_ID_GIGABYTE 0x1458
@@ -2080,6 +2154,8 @@
#define PCI_DEVICE_ID_AFAVLAB_P030 0x2182
#define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150
+#define PCI_VENDOR_ID_AMPLICON 0x14dc
+
#define PCI_VENDOR_ID_BCM_GVC 0x14a4
#define PCI_VENDOR_ID_BROADCOM 0x14e4
#define PCI_DEVICE_ID_TIGON3_5752 0x1600
@@ -2100,19 +2176,25 @@
#define PCI_DEVICE_ID_NX2_57711E 0x1650
#define PCI_DEVICE_ID_TIGON3_5705 0x1653
#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654
+#define PCI_DEVICE_ID_TIGON3_5719 0x1657
#define PCI_DEVICE_ID_TIGON3_5721 0x1659
#define PCI_DEVICE_ID_TIGON3_5722 0x165a
#define PCI_DEVICE_ID_TIGON3_5723 0x165b
#define PCI_DEVICE_ID_TIGON3_5705M 0x165d
#define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e
+#define PCI_DEVICE_ID_NX2_57712 0x1662
+#define PCI_DEVICE_ID_NX2_57712E 0x1663
+#define PCI_DEVICE_ID_NX2_57712_MF 0x1663
#define PCI_DEVICE_ID_TIGON3_5714 0x1668
#define PCI_DEVICE_ID_TIGON3_5714S 0x1669
#define PCI_DEVICE_ID_TIGON3_5780 0x166a
#define PCI_DEVICE_ID_TIGON3_5780S 0x166b
#define PCI_DEVICE_ID_TIGON3_5705F 0x166e
+#define PCI_DEVICE_ID_NX2_57712_VF 0x166f
#define PCI_DEVICE_ID_TIGON3_5754M 0x1672
#define PCI_DEVICE_ID_TIGON3_5755M 0x1673
#define PCI_DEVICE_ID_TIGON3_5756 0x1674
+#define PCI_DEVICE_ID_TIGON3_5750 0x1676
#define PCI_DEVICE_ID_TIGON3_5751 0x1677
#define PCI_DEVICE_ID_TIGON3_5715 0x1678
#define PCI_DEVICE_ID_TIGON3_5715S 0x1679
@@ -2124,6 +2206,9 @@
#define PCI_DEVICE_ID_TIGON3_5761E 0x1680
#define PCI_DEVICE_ID_TIGON3_5761 0x1681
#define PCI_DEVICE_ID_TIGON3_5764 0x1684
+#define PCI_DEVICE_ID_NX2_57800 0x168a
+#define PCI_DEVICE_ID_NX2_57840 0x168d
+#define PCI_DEVICE_ID_NX2_57810 0x168e
#define PCI_DEVICE_ID_TIGON3_5787M 0x1693
#define PCI_DEVICE_ID_TIGON3_5782 0x1696
#define PCI_DEVICE_ID_TIGON3_5784 0x1698
@@ -2131,11 +2216,19 @@
#define PCI_DEVICE_ID_TIGON3_5787 0x169b
#define PCI_DEVICE_ID_TIGON3_5788 0x169c
#define PCI_DEVICE_ID_TIGON3_5789 0x169d
+#define PCI_DEVICE_ID_NX2_57840_4_10 0x16a1
+#define PCI_DEVICE_ID_NX2_57840_2_20 0x16a2
+#define PCI_DEVICE_ID_NX2_57840_MF 0x16a4
+#define PCI_DEVICE_ID_NX2_57800_MF 0x16a5
#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6
#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7
#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8
+#define PCI_DEVICE_ID_NX2_57800_VF 0x16a9
#define PCI_DEVICE_ID_NX2_5706S 0x16aa
#define PCI_DEVICE_ID_NX2_5708S 0x16ac
+#define PCI_DEVICE_ID_NX2_57840_VF 0x16ad
+#define PCI_DEVICE_ID_NX2_57810_MF 0x16ae
+#define PCI_DEVICE_ID_NX2_57810_VF 0x16af
#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6
#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7
#define PCI_DEVICE_ID_TIGON3_5781 0x16dd
@@ -2307,6 +2400,8 @@
#define PCI_VENDOR_ID_TOPSPIN 0x1867
+#define PCI_VENDOR_ID_COMMTECH 0x18f7
+
#define PCI_VENDOR_ID_SILAN 0x1904
#define PCI_VENDOR_ID_RENESAS 0x1912
@@ -2316,6 +2411,11 @@
#define PCI_DEVICE_ID_RENESAS_SH7785 0x0007
#define PCI_DEVICE_ID_RENESAS_SH7786 0x0010
+#define PCI_VENDOR_ID_SOLARFLARE 0x1924
+#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0 0x0703
+#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1 0x6703
+#define PCI_DEVICE_ID_SOLARFLARE_SFC4000B 0x0710
+
#define PCI_VENDOR_ID_TDI 0x192E
#define PCI_DEVICE_ID_TDI_EHCI 0x0101
@@ -2414,6 +2514,11 @@
#define PCI_VENDOR_ID_AZWAVE 0x1a3b
+#define PCI_VENDOR_ID_ASMEDIA 0x1b21
+
+#define PCI_VENDOR_ID_CIRCUITCO 0x1cc8
+#define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD 0x0001
+
#define PCI_VENDOR_ID_TEKRAM 0x1de1
#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29
@@ -2463,6 +2568,9 @@
#define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_DEVICE_ID_INTEL_EESSC 0x0008
+#define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100
+#define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154
+#define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00
#define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320
#define PCI_DEVICE_ID_INTEL_PXHD_1 0x0321
#define PCI_DEVICE_ID_INTEL_PXH_0 0x0329
@@ -2485,6 +2593,7 @@
#define PCI_DEVICE_ID_INTEL_MRST_SD2 0x084F
#define PCI_DEVICE_ID_INTEL_I960 0x0960
#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
+#define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60
#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
#define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c
#define PCI_DEVICE_ID_INTEL_82542 0x1000
@@ -2564,13 +2673,50 @@
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_HDA 0x1c20
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Z68 0x1c44
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_P67 0x1c46
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_UM67 0x1c47
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM65 0x1c49
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H67 0x1c4a
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM67 0x1c4b
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q65 0x1c4c
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QS67 0x1c4d
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q67 0x1c4e
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QM67 0x1c4f
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_B65 0x1c50
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C202 0x1c52
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C204 0x1c54
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C206 0x1c56
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H61 0x1c5c
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
-#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03
-#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA 0x1e20
-#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
-#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC 0x1d40
+#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0 0x1d40
+#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1 0x1d41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA 0x1e20
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI 0x1e31
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_B75 0x1e49
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_C216 0x1e53
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_H77 0x1e4A
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM70 0x1e5e
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM75 0x1e5d
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM76 0x1e59
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM77 0x1e57
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MBL_SAMPLE 0x1e42
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_NM70 0x1e5f
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Q75 0x1e48
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Q77 0x1e47
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_QM77 0x1e55
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_QS77 0x1e56
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_SFF_SAMPLE 0x1e43
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_UM77 0x1e58
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Z75 0x1e46
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Z77 0x1e44
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
+#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN 0x2310
+#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX 0x231f
#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410
#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411
#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413
@@ -2783,8 +2929,30 @@
#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN 0x3b00
#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX 0x3b1f
#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB0 0x3c20
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB1 0x3c21
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB2 0x3c22
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB3 0x3c23
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB4 0x3c24
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB5 0x3c25
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB6 0x3c26
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 0x3c27
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 0x3c2e
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 0x3c2f
+#define PCI_DEVICE_ID_INTEL_UNC_HA 0x3c46
+#define PCI_DEVICE_ID_INTEL_UNC_IMC0 0x3cb0
+#define PCI_DEVICE_ID_INTEL_UNC_IMC1 0x3cb1
+#define PCI_DEVICE_ID_INTEL_UNC_IMC2 0x3cb4
+#define PCI_DEVICE_ID_INTEL_UNC_IMC3 0x3cb5
+#define PCI_DEVICE_ID_INTEL_UNC_QPI0 0x3c41
+#define PCI_DEVICE_ID_INTEL_UNC_QPI1 0x3c42
+#define PCI_DEVICE_ID_INTEL_UNC_R2PCIE 0x3c43
+#define PCI_DEVICE_ID_INTEL_UNC_R3QPI0 0x3c44
+#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45
+#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0
#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f
#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
+#define PCI_DEVICE_ID_INTEL_5100_19 0x65f3
#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5
#define PCI_DEVICE_ID_INTEL_5100_22 0x65f6
#define PCI_DEVICE_ID_INTEL_5400_ERR 0x4030
@@ -2823,6 +2991,7 @@
#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601
#define PCI_DEVICE_ID_INTEL_SCH_LPC 0x8119
#define PCI_DEVICE_ID_INTEL_SCH_IDE 0x811a
+#define PCI_DEVICE_ID_INTEL_ITC_LPC 0x8186
#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4
#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5
#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca
@@ -2905,7 +3074,11 @@
#define PCI_DEVICE_ID_NETMOS_9845 0x9845
#define PCI_DEVICE_ID_NETMOS_9855 0x9855
#define PCI_DEVICE_ID_NETMOS_9865 0x9865
+#define PCI_DEVICE_ID_NETMOS_9900 0x9900
#define PCI_DEVICE_ID_NETMOS_9901 0x9901
+#define PCI_DEVICE_ID_NETMOS_9904 0x9904
+#define PCI_DEVICE_ID_NETMOS_9912 0x9912
+#define PCI_DEVICE_ID_NETMOS_9922 0x9922
#define PCI_VENDOR_ID_3COM_2 0xa727
@@ -2927,3 +3100,5 @@
#define PCI_VENDOR_ID_XEN 0x5853
#define PCI_DEVICE_ID_XEN_PLATFORM 0x0001
+
+#define PCI_VENDOR_ID_OCZ 0x1b85
diff --git a/include/pci_rom.h b/include/pci_rom.h
new file mode 100644
index 0000000..8b2674c
--- /dev/null
+++ b/include/pci_rom.h
@@ -0,0 +1,58 @@
+/*
+ * From coreboot file of same name
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PCI_ROM_H
+#define _PCI_ROM_H
+
+#define PCI_ROM_HDR 0xaa55
+#define PCI_VGA_RAM_IMAGE_START 0xc0000
+
+struct pci_rom_header {
+ uint16_t signature;
+ uint8_t size;
+ uint8_t init[3];
+ uint8_t reserved[0x12];
+ uint16_t data;
+};
+
+struct pci_rom_data {
+ uint32_t signature;
+ uint16_t vendor;
+ uint16_t device;
+ uint16_t reserved_1;
+ uint16_t dlen;
+ uint8_t drevision;
+ uint8_t class_lo;
+ uint16_t class_hi;
+ uint16_t ilen;
+ uint16_t irevision;
+ uint8_t type;
+ uint8_t indicator;
+ uint16_t reserved_2;
+};
+
+ /**
+ * pci_run_vga_bios() - Run the VGA BIOS in an x86 PC
+ *
+ * @dev: Video device containing the BIOS
+ * @int15_handler: Function to call to handle int 0x15
+ * @emulate: true to use the x86 emulator, false to run native
+ */
+int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate);
+
+/**
+ * board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects
+ *
+ * Some VGA option roms are used for several chipsets but they only have one
+ * PCI ID in their header. If we encounter such an option rom, we need to do
+ * the mapping ourselves.
+ *
+ * @vendev: Vendor and device for the video device
+ * @return standard vendor and device expected by the ROM
+ */
+uint32_t board_map_oprom_vendev(uint32_t vendev);
+
+#endif
diff --git a/include/rtc.h b/include/rtc.h
index c034966..d11aa8b 100644
--- a/include/rtc.h
+++ b/include/rtc.h
@@ -50,4 +50,9 @@
unsigned long mktime (unsigned int, unsigned int, unsigned int,
unsigned int, unsigned int, unsigned int);
+/**
+ * rtc_init() - Set up the real time clock ready for use
+ */
+void rtc_init(void);
+
#endif /* _RTC_H_ */
diff --git a/include/twl4030.h b/include/twl4030.h
index f33cd1e..50f8da8 100644
--- a/include/twl4030.h
+++ b/include/twl4030.h
@@ -651,7 +651,7 @@
/* For initializing power device */
void twl4030_power_init(void);
/* For initializing mmc power */
-void twl4030_power_mmc_init(void);
+void twl4030_power_mmc_init(int dev_index);
/*
* LED
diff --git a/include/vbe.h b/include/vbe.h
new file mode 100644
index 0000000..d405691
--- /dev/null
+++ b/include/vbe.h
@@ -0,0 +1,103 @@
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * Copyright (c) 2009 Pattrick Hueper <phueper@hueper.net>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+#ifndef _VBE_H
+#define _VBE_H
+
+/* these structs are for input from and output to OF */
+struct __packed screen_info {
+ u8 display_type; /* 0=NONE, 1= analog, 2=digital */
+ u16 screen_width;
+ u16 screen_height;
+ /* bytes per line in framebuffer, may be more than screen_width */
+ u16 screen_linebytes;
+ u8 color_depth; /* color depth in bits per pixel */
+ u32 framebuffer_address;
+ u8 edid_block_zero[128];
+};
+
+struct __packed screen_info_input {
+ u8 signature[4];
+ u16 size_reserved;
+ u8 monitor_number;
+ u16 max_screen_width;
+ u8 color_depth;
+};
+
+/* these structs only store the required a subset of the VBE-defined fields */
+struct __packed vbe_info {
+ char signature[4];
+ u16 version;
+ u8 *oem_string_ptr;
+ u32 capabilities;
+ u16 video_mode_list[256];
+ u16 total_memory;
+};
+
+struct __packed vesa_mode_info {
+ u16 mode_attributes; /* 00 */
+ u8 win_a_attributes; /* 02 */
+ u8 win_b_attributes; /* 03 */
+ u16 win_granularity; /* 04 */
+ u16 win_size; /* 06 */
+ u16 win_a_segment; /* 08 */
+ u16 win_b_segment; /* 0a */
+ u32 win_func_ptr; /* 0c */
+ u16 bytes_per_scanline; /* 10 */
+ u16 x_resolution; /* 12 */
+ u16 y_resolution; /* 14 */
+ u8 x_charsize; /* 16 */
+ u8 y_charsize; /* 17 */
+ u8 number_of_planes; /* 18 */
+ u8 bits_per_pixel; /* 19 */
+ u8 number_of_banks; /* 20 */
+ u8 memory_model; /* 21 */
+ u8 bank_size; /* 22 */
+ u8 number_of_image_pages; /* 23 */
+ u8 reserved_page;
+ u8 red_mask_size;
+ u8 red_mask_pos;
+ u8 green_mask_size;
+ u8 green_mask_pos;
+ u8 blue_mask_size;
+ u8 blue_mask_pos;
+ u8 reserved_mask_size;
+ u8 reserved_mask_pos;
+ u8 direct_color_mode_info;
+ u32 phys_base_ptr;
+ u32 offscreen_mem_offset;
+ u16 offscreen_mem_size;
+ u8 reserved[206];
+};
+
+struct vbe_mode_info {
+ u16 video_mode;
+ bool valid;
+ union {
+ struct vesa_mode_info vesa;
+ u8 mode_info_block[256];
+ };
+};
+
+struct vbe_ddc_info {
+ u8 port_number; /* i.e. monitor number */
+ u8 edid_transfer_time;
+ u8 ddc_level;
+ u8 edid_block_zero[128];
+};
+
+#define VESA_GET_INFO 0x4f00
+#define VESA_GET_MODE_INFO 0x4f01
+#define VESA_SET_MODE 0x4f02
+
+struct graphic_device;
+int vbe_get_video_info(struct graphic_device *gdev);
+
+#endif
diff --git a/include/video_fb.h b/include/video_fb.h
index 6cd4e37..55ec24d 100644
--- a/include/video_fb.h
+++ b/include/video_fb.h
@@ -40,7 +40,7 @@
/* Export Graphic Driver Control */
/******************************************************************************/
-typedef struct {
+typedef struct graphic_device {
unsigned int isaBase;
unsigned int pciBase;
unsigned int dprBase;
diff --git a/lib/Makefile b/lib/Makefile
index 320197a..3ceb697 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -11,14 +11,12 @@
obj-$(CONFIG_LZMA) += lzma/
obj-$(CONFIG_LZO) += lzo/
obj-$(CONFIG_ZLIB) += zlib/
+obj-$(CONFIG_BZIP2) += bzip2/
obj-$(CONFIG_TIZEN) += tizen/
+obj-$(CONFIG_OF_LIBFDT) += libfdt/
+obj-$(CONFIG_FIT) += libfdt/
obj-$(CONFIG_AES) += aes.o
-obj-$(CONFIG_BZIP2) += bzlib.o
-obj-$(CONFIG_BZIP2) += bzlib_crctable.o
-obj-$(CONFIG_BZIP2) += bzlib_decompress.o
-obj-$(CONFIG_BZIP2) += bzlib_randtable.o
-obj-$(CONFIG_BZIP2) += bzlib_huffman.o
obj-$(CONFIG_USB_TTY) += circbuf.o
obj-y += crc7.o
obj-y += crc8.o
diff --git a/lib/bzip2/Makefile b/lib/bzip2/Makefile
new file mode 100644
index 0000000..929c24e
--- /dev/null
+++ b/lib/bzip2/Makefile
@@ -0,0 +1,2 @@
+obj-y += bzlib.o bzlib_crctable.o bzlib_decompress.o \
+ bzlib_randtable.o bzlib_huffman.o
diff --git a/lib/bzlib.c b/lib/bzip2/bzlib.c
similarity index 100%
rename from lib/bzlib.c
rename to lib/bzip2/bzlib.c
diff --git a/lib/bzlib_crctable.c b/lib/bzip2/bzlib_crctable.c
similarity index 100%
rename from lib/bzlib_crctable.c
rename to lib/bzip2/bzlib_crctable.c
diff --git a/lib/bzlib_decompress.c b/lib/bzip2/bzlib_decompress.c
similarity index 100%
rename from lib/bzlib_decompress.c
rename to lib/bzip2/bzlib_decompress.c
diff --git a/lib/bzlib_huffman.c b/lib/bzip2/bzlib_huffman.c
similarity index 100%
rename from lib/bzlib_huffman.c
rename to lib/bzip2/bzlib_huffman.c
diff --git a/lib/bzlib_private.h b/lib/bzip2/bzlib_private.h
similarity index 100%
rename from lib/bzlib_private.h
rename to lib/bzip2/bzlib_private.h
diff --git a/lib/bzlib_randtable.c b/lib/bzip2/bzlib_randtable.c
similarity index 100%
rename from lib/bzlib_randtable.c
rename to lib/bzip2/bzlib_randtable.c
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 7c7e673..9d86dba 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -75,6 +75,9 @@
COMPAT(COMPAT_INTEL_LPC, "intel,lpc"),
COMPAT(INTEL_MICROCODE, "intel,microcode"),
COMPAT(MEMORY_SPD, "memory-spd"),
+ COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
+ COMPAT(INTEL_MODEL_206AX, "intel,model-206ax"),
+ COMPAT(INTEL_GMA, "intel,gma"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
@@ -370,21 +373,6 @@
return -ENOENT;
}
-int fdtdec_get_alias_node(const void *blob, const char *name)
-{
- const char *prop;
- int alias_node;
- int len;
-
- if (!blob)
- return -FDT_ERR_NOTFOUND;
- alias_node = fdt_path_offset(blob, "/aliases");
- prop = fdt_getprop(blob, alias_node, name, &len);
- if (!prop)
- return -FDT_ERR_NOTFOUND;
- return fdt_path_offset(blob, prop);
-}
-
int fdtdec_get_chosen_node(const void *blob, const char *name)
{
const char *prop;
diff --git a/lib/libfdt/Makefile b/lib/libfdt/Makefile
index 6fe79e0..2f5413f 100644
--- a/lib/libfdt/Makefile
+++ b/lib/libfdt/Makefile
@@ -5,8 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-COBJS-libfdt += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o \
+obj-y += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o \
fdt_empty_tree.o fdt_addresses.o
-
-obj-$(CONFIG_OF_LIBFDT) += $(COBJS-libfdt)
-obj-$(CONFIG_FIT) += $(COBJS-libfdt)
diff --git a/lib/zlib/zlib.h b/lib/zlib/zlib.h
index 556be32..af3703e 100644
--- a/lib/zlib/zlib.h
+++ b/lib/zlib/zlib.h
@@ -3,7 +3,7 @@
#define __GLUE_ZLIB_H__
#include <common.h>
-#include <compiler.h>
+#include <linux/compiler.h>
#include <asm/unaligned.h>
#include <watchdog.h>
#include "u-boot/zlib.h"
diff --git a/net/bootp.c b/net/bootp.c
index d4c86cf..8106601 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -145,8 +145,6 @@
if (tmp_ip != 0)
NetCopyIP(&NetServerIP, &bp->bp_siaddr);
memcpy(NetServerEther, ((struct ethernet_hdr *)NetRxPacket)->et_src, 6);
-#endif
- NetCopyIP(&NetOurIP, &bp->bp_yiaddr);
if (strlen(bp->bp_file) > 0)
copy_filename(BootFile, bp->bp_file, sizeof(BootFile));
@@ -158,6 +156,8 @@
*/
if (*BootFile)
setenv("bootfile", BootFile);
+#endif
+ NetCopyIP(&NetOurIP, &bp->bp_yiaddr);
}
static int truncate_sz(const char *name, int maxlen, int curlen)
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 9d1383a..13af604 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -260,11 +260,13 @@
cmd_dt_S_dtb= \
( \
echo '.section .dtb.init.rodata,"a"'; \
+ echo '.balign 16'; \
echo '.global __dtb_$(*F)_begin'; \
echo '__dtb_$(*F)_begin:'; \
echo '.incbin "$<" '; \
echo '__dtb_$(*F)_end:'; \
echo '.global __dtb_$(*F)_end'; \
+ echo '.balign 16'; \
) > $@
$(obj)/%.dtb.S: $(obj)/%.dtb
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 1905446..ecf3037 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -34,6 +34,7 @@
endif
include $(srctree)/config.mk
+include $(srctree)/arch/$(ARCH)/Makefile
# Enable garbage collection of un-used sections for SPL
KBUILD_CFLAGS += -ffunction-sections -fdata-sections
@@ -45,21 +46,6 @@
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n)
-ifdef CONFIG_SPL_START_S_PATH
-START_PATH := $(CONFIG_SPL_START_S_PATH:"%"=%)
-else
-START_PATH := $(CPUDIR)
-endif
-
-head-y := $(START_PATH)/start.o
-head-$(CONFIG_X86) += $(START_PATH)/start16.o $(START_PATH)/resetvec.o
-head-$(CONFIG_4xx) += $(START_PATH)/resetvec.o
-head-$(CONFIG_MPC85xx) += $(START_PATH)/resetvec.o
-
-libs-y += arch/$(ARCH)/lib/
-
-libs-y += $(CPUDIR)/
-
libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
@@ -94,13 +80,6 @@
libs-$(CONFIG_OMAP_USB_PHY) += drivers/usb/phy/
libs-$(CONFIG_SPL_SATA_SUPPORT) += drivers/block/
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
-libs-y += arch/$(ARCH)/imx-common/
-endif
-
-libs-$(CONFIG_ARM) += arch/arm/cpu/
-libs-$(CONFIG_PPC) += arch/powerpc/cpu/
-
head-y := $(addprefix $(obj)/,$(head-y))
libs-y := $(addprefix $(obj)/,$(libs-y))
u-boot-spl-dirs := $(patsubst %/,%,$(filter %/, $(libs-y)))
diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.pl
index 7717d68..368a20e 100755
--- a/scripts/get_maintainer.pl
+++ b/scripts/get_maintainer.pl
@@ -835,8 +835,7 @@
if ($lk_path ne "" && substr($lk_path,length($lk_path)-1,1) ne "/") {
$lk_path .= "/";
}
- if ( (-f "${lk_path}CREDITS")
- && (-f "${lk_path}Kbuild")
+ if ( (-f "${lk_path}Kbuild")
&& (-f "${lk_path}MAINTAINERS")
&& (-f "${lk_path}Makefile")
&& (-f "${lk_path}README")
diff --git a/scripts/kconfig/menu.c b/scripts/kconfig/menu.c
index a26cc5d..72c9dba 100644
--- a/scripts/kconfig/menu.c
+++ b/scripts/kconfig/menu.c
@@ -548,7 +548,7 @@
{
int i, j;
struct menu *submenu[8], *menu, *location = NULL;
- struct jump_key *jump;
+ struct jump_key *jump = NULL;
str_printf(r, _("Prompt: %s\n"), _(prop->text));
menu = prop->menu->parent;
@@ -586,7 +586,7 @@
str_printf(r, _(" Location:\n"));
for (j = 4; --i >= 0; j += 2) {
menu = submenu[i];
- if (head && location && menu == location)
+ if (jump && menu == location)
jump->offset = strlen(r->s);
str_printf(r, "%*c-> %s", j, ' ',
_(menu_get_prompt(menu)));
diff --git a/tools/.gitignore b/tools/.gitignore
index e7f0f8f..9bc9fec 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -4,6 +4,7 @@
/fit_check_sign
/fit_info
/gen_eth_addr
+/ifdtool
/img2srec
/kwboot
/dumpimage
diff --git a/tools/buildman/README b/tools/buildman/README
index 8ba19ec..bfb2f18 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -85,10 +85,10 @@
valid value, and all will be well. Otherwise buildman will perform random
actions. Use -n to check what the random actions might be.
-If you just want to build the current source tree, leave off the -b flag.
-This will display results and errors as they happen. You can still look
-at them later using -s. Note that buildman will assume that the source
-has changed, and will build all specified boards in this case.
+If you just want to build the current source tree, leave off the -b flag
+and add -e. This will display results and errors as they happen. You can
+still look at them later using -se. Note that buildman will assume that the
+source has changed, and will build all specified boards in this case.
Buildman is optimised for building many commits at once, for many boards.
On multi-core machines, Buildman is fast because it uses most of the
@@ -693,9 +693,9 @@
==================
If you have made changes and want to do a quick sanity check of the
-currently-checked-out source, run buildman without the -b flag. This will
-build the selected boards and display build status and errors as it runs
-(i.e. -v amd -e are enabled automatically).
+currently checked-out source, run buildman without the -b flag. This will
+build the selected boards and display build status as it runs (i.e. -v is
+enabled automatically). Use -e to see errors/warnings as well.
Other options
@@ -752,7 +752,7 @@
flag to see the full errors and -l to see which boards caused which errors.
If you really want to see build results as they happen, use -v when doing a
-build (-e will be enabled automatically).
+build (and -e to see the errors/warnings too).
You don't need to stick around on that branch while buildman is running. It
checks out its own copy of the source code, so you can change branches,
@@ -816,11 +816,10 @@
This has mostly be written in my spare time as a response to my difficulties
in testing large series of patches. Apart from tidying up there is quite a
-bit of scope for improvement. Things like better error diffs, easier access
-to log files, error display while building. Also it would be nice it buildman
-could 'hunt' for problems, perhaps by building a few boards for each arch,
-or checking commits for changed files and building only boards which use
-those files.
+bit of scope for improvement. Things like better error diffs and easier
+access to log files. Also it would be nice it buildman could 'hunt' for
+problems, perhaps by building a few boards for each arch, or checking
+commits for changed files and building only boards which use those files.
Credits
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index 8155c16..7002034 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -918,7 +918,8 @@
if self._list_error_boards:
names = []
for board in line_boards[line]:
- names.append(board.target)
+ if not board.target in names:
+ names.append(board.target)
names_str = '(%s) ' % ','.join(names)
else:
names_str = ''
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index a9cf68a..bc4541c 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -332,7 +332,7 @@
# Now write the actual build output
if keep_outputs:
- patterns = ['u-boot', '*.bin', 'u-boot.dtb', '*.map',
+ patterns = ['u-boot', '*.bin', 'u-boot.dtb', '*.map', '*.img',
'include/autoconf.mk', 'spl/u-boot-spl',
'spl/u-boot-spl.bin']
for pattern in patterns:
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 8b8c826..2c3ba8b 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -70,7 +70,7 @@
if commits:
for upto in range(0, len(series.commits), options.step):
commit = series.commits[upto]
- print ' ', col.Color(col.YELLOW, commit.hash, bright=False),
+ print ' ', col.Color(col.YELLOW, commit.hash[:8], bright=False),
print commit.subject
print
for arg in why_selected:
@@ -188,7 +188,6 @@
else:
series = None
options.verbose = True
- options.show_errors = True
# By default we have one thread per CPU. But if there are not enough jobs
# we can have fewer threads and use a high '-j' value for make.
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index d630157..da04883 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -248,8 +248,7 @@
# Detect the start of a new commit
elif commit_match:
self.CloseCommit()
- # TODO: We should store the whole hash, and just display a subset
- self.commit = commit.Commit(commit_match.group(1)[:8])
+ self.commit = commit.Commit(commit_match.group(1))
# Detect tags in the commit message
elif tag_match: