commit 235dd6e8d1696f85e6ff536bd64bf1e4240ae368
author Vitaly Andrianov <vitalya@ti.com> Sat Sep 19 16:26:43 2015 +0530
committer Tom Rini <trini@konsulko.com> Thu Oct 22 14:22:18 2015 -0400
tree 91905c3bffb3605b5d067aca857742c366e125b7
parent 0fba27b69033276b23711a3ea8c06ab65382b14b

ARM: k2g: Add ddr3 info

Add ddr3 related info

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

arch/arm/mach-keystone/ddr3.c

diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index dfb27b5..34606f4 100644
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -52,7 +52,8 @@
 	__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
 	__raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);
 	__raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);
-	__raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
+	if (!cpu_is_k2g())
+		__raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
 	__raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);
 	__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
 
@@ -64,6 +65,15 @@
 	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
 		;
 
+	/* Disable ECC for K2G */
+	if (cpu_is_k2g()) {
+		clrbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
+		clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
+		clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
+		clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
+		clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
+	}
+
 	__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
 	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
 		;