tree 2fbe9e0e90b289fe6073799180d31806f9fe6d7f
parent c27c8102e128827c684d8d3da7f0ce03d550b65a
author Sean Anderson <sean.anderson@seco.com> 1698440223 -0400
committer Jaehoon Chung <jh80.chung@samsung.com> 1698800470 +0900

mmc: sdhci: Rework SDHCI_QUIRK_BROKEN_R1B

As noted in commit 3a6383207be ("mmc: sdhci: add the quirk for broken
r1b response"), some MMC controllers don't always set the transfer
complete bit with R1b responses.

According to the SD Host Controller Simplified Specification v4.20,

> In the case of a command pairing with response-with-busy[, Transfer
> Complete] is set when busy is de-asserted. Refer to DAT Line Active
> and Command Inhibit (DAT) in the Present State register.

By polling the DAT Line Active bit in the present state register, we can
detect when we are no longer busy, without waiting for a long timeout.
This results in much faster reads/writes on buggy controllers.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Tested-by: Henrik Grimler <henrik@grimler.se>