riscv: lib: implement enable_caches for sifive cache
The enable_caches is a generic hook for architecture-implemented, we
define this function to enable composable cache of sifive platforms.
In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4b0c3df..ec651fe 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -179,6 +179,11 @@
The SiFive CLINT block holds memory-mapped control and status registers
associated with software and timer interrupts.
+config SIFIVE_CACHE
+ bool
+ help
+ This enables the operations to configure SiFive cache
+
config ANDES_PLIC
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE