commit 198cafbf2cab9851ee5dd8d24d268d0ccc0fe3bd
author Alison Wang <b18965@freescale.com> Mon Mar 26 21:49:08 2012 +0000
committer jason <jason@jason-ThinkPad-T61.(none)> Thu Sep 20 20:39:27 2012 +0800
tree a6fc11865887140e289ba28bc03f69f5388c8008
parent a4110eecf2944b2f8b47f38273cc3730ddd394a3

ColdFire: Clean up checkpatch warnings for MCF54451 and MCF54455

Signed-off-by: Alison Wang <b18965@freescale.com>

board/freescale/m54451evb/m54451evb.c

diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
index 088c8c4..32a9374 100644
--- a/board/freescale/m54451evb/m54451evb.c
+++ b/board/freescale/m54451evb/m54451evb.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <spi.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -51,14 +52,14 @@
 	 */
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 #else
-	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
-	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+	sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
 	u32 i;
 
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 
-	if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) &&
-	    (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2))
+	if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
+	    (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
 		return dramsize;
 
 	for (i = 0x13; i < 0x20; i++) {
@@ -67,32 +68,33 @@
 	}
 	i--;
 
-	gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+	out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
 
-	sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
 
-	sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
-	sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
 
 	udelay(200);
 
 	/* Issue PALL */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
 	__asm__("nop");
 
 	/* Perform two refresh cycles */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
 	__asm__("nop");
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
 	__asm__("nop");
 
 	/* Issue LEMR */
-	sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
 	__asm__("nop");
-	sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
 	__asm__("nop");
 
-	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000;
+	out_be32(&sdram->sdcr,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
 
 	udelay(100);
 #endif