| commit | 1673f199d917e0649098e0cb7ef5b375b96bd6cb | [log] [tgz] |
|---|---|---|
| author | Ajay Kumar <ajaykumar.rs@samsung.com> | Tue Jan 08 20:42:23 2013 +0000 |
| committer | Minkyu Kang <mk7.kang@samsung.com> | Thu Jan 10 10:19:47 2013 +0900 |
| tree | 827f9a574affebaab94e75ee1f909585f4c2357b | |
| parent | 9b572852c0547365b186651d27b3df5dcbe82be2 [diff] |
EXYNOS5: Change parent clock of FIMD to MPLL With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>